Clifford Wolf 752553d8e9

Merge pull request #946 from YosysHQ/clifford/specify ...

Add specify parser

2019-05-06 20:57:15 +02:00

..

ast.cc

Add $specrule cells for $setup/$hold/$skew specify rules

2019-04-23 21:36:59 +02:00

ast.h

New behavior for front-end handling of whiteboxes

2019-04-20 22:24:50 +02:00

dpicall.cc

Fixed trailing whitespaces

2015-07-02 11:14:30 +02:00

genrtlil.cc

Improve write_verilog specify support

2019-05-04 08:46:24 +02:00

Makefile.inc

Added Verilog/AST support for DPI functions (dpi_call() still unimplemented)

2014-08-21 12:43:51 +02:00

simplify.cc

Merge branch 'master' of github.com:YosysHQ/yosys into clifford/fix968

2019-05-06 15:41:13 +02:00