Clifford Wolf a61c88f122 Added $anyconst support to AIGER back-end

2016-12-11 13:48:18 +01:00

..

aiger

Added $anyconst support to AIGER back-end

2016-12-11 13:48:18 +01:00

blif

Added wire start_offset and upto handling BLIF back-end

2016-11-23 13:54:33 +01:00

btor

Added "yosys -D" feature

2016-04-21 23:28:37 +02:00

edif

Added "yosys -D" feature

2016-04-21 23:28:37 +02:00

firrtl

Bugfix: include assign to write-mask

2016-11-18 11:49:26 -08:00

ilang

Added avail params to ilang format, check module params in 'hierarchy -check'

2016-10-22 11:05:49 +02:00

intersynth

Added "yosys -D" feature

2016-04-21 23:28:37 +02:00

json

write_json: also write module attributes.

2016-07-12 06:32:04 +00:00

smt2

Improved yosys-smtbmc default -t/--assume-skipped for --cex and --aig

2016-12-03 12:37:20 +01:00

smv

Added "yosys -D" feature

2016-04-21 23:28:37 +02:00

spice

Also escape "=" in spice output

2016-05-20 16:43:13 +02:00

verilog

Cleanups and fixed in write_verilog regarding reg init

2016-11-16 12:00:39 +01:00