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f348ffa44d4ec00537499ffe79ce627beeeefe85
YosysHQ.yosys
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tests
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arch
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Eddie Hung
2e21aa59a2
Add DSP cascade tests
2019-12-23 14:58:06 -08:00
..
anlogic
Rename memory tests to lutram, add more xilinx tests
2019-12-12 17:44:37 -08:00
common
Merge pull request
#1574
from YosysHQ/eddie/xilinx_lutram
2019-12-16 21:48:21 -08:00
ecp5
Rename memory tests to lutram, add more xilinx tests
2019-12-12 17:44:37 -08:00
efinix
Rename memory tests to lutram, add more xilinx tests
2019-12-12 17:44:37 -08:00
gowin
Rename memory tests to lutram, add more xilinx tests
2019-12-12 17:44:37 -08:00
ice40
Rename memory tests to lutram, add more xilinx tests
2019-12-12 17:44:37 -08:00
xilinx
Add DSP cascade tests
2019-12-23 14:58:06 -08:00
run-test.sh
Add simcells.v, simlib.v, and some output
2019-06-27 11:13:49 -07:00
