Marcelina Kościelnicka 98003430d6 opt_merge: Use FfInitVals. ...

Partial #2920 fix.

2021-08-08 01:19:22 +02:00

..

aiger

switch argument order to work with macOS getopt

2020-09-23 12:48:26 +02:00

arch

opt_lut: Allow more than one -dlogic per cell type.

2021-07-29 17:30:07 +02:00

asicworld

Fix FIRRTL to Verilog process instance subfield assignment.

2019-02-25 16:18:13 -08:00

bind

Add support for parsing the SystemVerilog 'bind' construct

2021-07-16 09:31:39 -04:00

blif

tests/blif: Add missing gitignore

2021-05-20 12:49:51 +02:00

bram

tests/bram: Do not generate write address collisions.

2021-03-08 16:53:03 +01:00

errors

Rename the generic "Syntax error" message from the Verilog/SystemVerilog parser into unique,

2018-10-25 02:37:56 +03:00

fsm

tests: fsm to use a randomly-generated seed

2020-04-24 14:31:33 -07:00

hana

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liberty

dfflibmap: Refactor to use dfflegalize internally.

2020-07-09 18:51:03 +02:00

lut

Forgot to commit

2019-07-16 12:44:26 -07:00

memfile

Added 'set -e' into tests/memfile/run-test.sh

2020-02-06 10:45:40 -03:00

memories

tests: Parallelize

2020-09-21 15:07:02 +02:00

opt

opt_merge: Use FfInitVals.

2021-08-08 01:19:22 +02:00

opt_share

tests: Parallelize

2020-09-21 15:07:02 +02:00

proc

proc_rmdead: use explicit pattern set when there are no wildcards

2021-07-29 20:55:59 -04:00

realmath

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rpc

rpc test: make frontend listen before launching yosys & introduce safeguard if yosys errors

2020-03-06 15:29:01 +01:00

sat

assertpmux: Fix crash on unused $pmux output.

2021-02-22 23:30:28 +01:00

select

Merge pull request #1949 from YosysHQ/eddie/select_blackbox

2020-04-22 15:35:05 -07:00

share

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simple

proc_rmdead: use explicit pattern set when there are no wildcards

2021-07-29 20:55:59 -04:00

simple_abc9

abc9: fix SCC issues (#2694)

2021-03-29 22:01:57 -07:00

smv

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sva

Fix "verific -extnets" for more complex situations

2019-03-26 14:17:46 +01:00

svinterfaces

Add a test for interfaces on modules loaded on-demand

2021-07-14 22:54:50 -04:00

svtypes

verilog: check entire user type stack for type definition

2021-03-21 19:35:13 -04:00

techmap

Add tests for some common techmap files.

2021-02-24 01:07:34 +01:00

tools

memory_dff: Remove now-useless write port handling.

2021-03-08 20:16:29 +01:00

unit

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various

More deadname stuff

2021-06-09 12:40:33 +02:00

verilog

verilog: save and restore overwritten macro arguments

2021-07-28 21:52:16 -04:00

vloghtb

Use HTTPS for website links, gatecat email

2021-06-09 12:16:56 +02:00

gen-tests-makefile.sh

tests: Parallelize

2020-09-21 15:07:02 +02:00