Adam Izraelevitz 794cec0016 More progress on Firrtl backend. ...

Chisel -> Firrtl -> Verilog -> Firrtl -> Verilog is successful for a
simple rocket-chip design.

2017-02-13 11:17:53 -08:00

..

aiger

Added $anyconst support to AIGER back-end

2016-12-11 13:48:18 +01:00

blif

Added wire start_offset and upto handling BLIF back-end

2016-11-23 13:54:33 +01:00

btor

Added "yosys -D" feature

2016-04-21 23:28:37 +02:00

edif

Added "yosys -D" feature

2016-04-21 23:28:37 +02:00

firrtl

More progress on Firrtl backend.

2017-02-13 11:17:53 -08:00

ilang

Added avail params to ilang format, check module params in 'hierarchy -check'

2016-10-22 11:05:49 +02:00

intersynth

Added "yosys -D" feature

2016-04-21 23:28:37 +02:00

json

Improved write_json help message

2016-12-29 12:13:29 +01:00

smt2

Add assert check in "yosys-smtbmc -c"

2017-02-04 21:22:17 +01:00

smv

Added "yosys -D" feature

2016-04-21 23:28:37 +02:00

spice

Also escape "=" in spice output

2016-05-20 16:43:13 +02:00

verilog

Cleanups and fixed in write_verilog regarding reg init

2016-11-16 12:00:39 +01:00