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mirror of synced 2026-01-21 02:18:17 +00:00
Emil J. Tywoniak 36491569d2 Revert "verilog: add support for SystemVerilog string literals."
This reverts commit 5feb1a1752a7469fd5a02ec8afdb68794e55ef8f.
2025-08-11 13:34:10 +02:00
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