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YosysHQ.yosys/passes
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Marcelina Kościelnicka 28b9f49c94 fsm_extract: avoid calling log_signal to determine wire name 
log_signal can result in a string with spaces (when bit selection is
involved), which breaks the rule of IdString not containing whitespace.
Instead, remove the sigspec from the name entirely — given that the
resulting wire will have no users, it will be removed later anyway,
so its name doesn't really matter.

Fixes #2118
2020-06-08 03:49:58 +02:00
..
cmds
Merge pull request #2081 from YosysHQ/eddie/blackbox_ast
2020-05-30 08:59:20 -07:00
equiv
kernel: big fat patch to use more ID::*, otherwise ID(*)
2020-04-02 09:51:32 -07:00
fsm
fsm_extract: avoid calling log_signal to determine wire name
2020-06-08 03:49:58 +02:00
hierarchy
Fix small typos in documentation for hierarchy command
2020-05-28 11:39:44 +01:00
memory
Add flooring division operator
2020-05-28 22:59:04 +02:00
opt
Add flooring division operator
2020-05-28 22:59:04 +02:00
pmgen
xilinx: xilinx_dsp_cascade to check CREG for DSP48E1 only
2020-04-22 17:43:25 -07:00
proc
kernel: big fat patch to use more ID::*, otherwise ID(*)
2020-04-02 09:51:32 -07:00
sat
smtbmc and qbfsat: Add timeout option to set solver timeouts for Z3, Yices, and CVC4.
2020-05-25 20:39:30 +00:00
techmap
Merge pull request #2077 from YosysHQ/eddie/abc9_dff_improve
2020-06-04 08:15:25 -07:00
tests
Add flooring division operator
2020-05-28 22:59:04 +02:00