Clifford Wolf f6629b9c29 Optimize memory address port width in wreduce and memory_collect, not verilog front-end

2016-08-19 18:38:25 +02:00

..

Makefile.inc

Added memory_bram (not functional yet)

2014-12-31 16:53:53 +01:00

memory_bram.cc

Don't sign-extend memory bram initialization data

2016-05-15 00:05:30 +02:00

memory_collect.cc

Optimize memory address port width in wreduce and memory_collect, not verilog front-end

2016-08-19 18:38:25 +02:00

memory_dff.cc

Added "yosys -D" feature

2016-04-21 23:28:37 +02:00

memory_map.cc

Added "yosys -D" feature

2016-04-21 23:28:37 +02:00

memory_share.cc

Added "yosys -D" feature

2016-04-21 23:28:37 +02:00

memory_unpack.cc

Added "yosys -D" feature

2016-04-21 23:28:37 +02:00

memory.cc

Added "yosys -D" feature

2016-04-21 23:28:37 +02:00