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YosysHQ.yosys/tests
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David Shah f6b5e47e40 sv: Switch parser to glr, prep for typedef 
Signed-off-by: David Shah <dave@ds0.me>
2019-10-03 09:54:14 +01:00
..
aiger
tests: use optional ABCEXTERNAL when specified
2019-06-27 23:00:13 -04:00
arch
Add simcells.v, simlib.v, and some output
2019-06-27 11:13:49 -07:00
asicworld
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bram
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errors
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fsm
Speed up "make test" and related cleanups
2019-08-17 14:37:07 +02:00
hana
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ice40
Merge pull request #1359 from YosysHQ/xc7dsp
2019-09-29 11:26:22 -07:00
liberty
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lut
Forgot to commit
2019-07-16 12:44:26 -07:00
memories
memory_dff: Fix checking of feedback mux input when more than one mux
2019-07-02 13:35:50 +01:00
opt
Add missing -assert to equiv_opt
2019-09-06 22:51:44 -07:00
opt_share
Support various binary operators in opt_share
2019-08-04 19:06:38 +02:00
proc
proc_clean: fix order of switch insertion.
2019-08-19 16:44:23 +00:00
realmath
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rpc
rpc: new frontend.
2019-09-30 15:53:11 +00:00
sat
Revert to using clean
2019-08-27 09:24:32 -07:00
share
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simple
simple/peepopt.v tests to various/peepopt.ys with equiv_opt & select
2019-09-05 08:43:22 -07:00
simple_abc9
Revert "abc9 followed by clean otherwise netlist could be invalid for sim"
2019-09-05 08:25:09 -07:00
smv
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sva
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svinterfaces
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svtypes
sv: Switch parser to glr, prep for typedef
2019-10-03 09:54:14 +01:00
techmap
Extend test with renaming cells with prefix too
2019-10-02 12:43:18 -07:00
tools
autotest.sh to define _AUTOTB when test_autotb
2019-06-28 14:56:22 -07:00
unit
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various
Merge pull request #1355 from YosysHQ/eddie/peepopt_dffmuxext
2019-09-18 12:40:08 -07:00
vloghtb
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xilinx
Add latch test modified from #1363
2019-09-30 12:52:43 +02:00