github.com/YosysHQ.yosys
1
0
Fork 0
mirror of synced 2026-02-13 19:54:09 +00:00
Code Issues Releases Wiki Activity
Files
f88335a8a5284a8e69230ec20eeeca6c02b055bf
YosysHQ.yosys/tests/arch
History
Pepijn de Vos 8226f2db0b ALU sim tweaks
2019-10-24 13:39:43 +02:00
..
anlogic
Common memory test now shared
2019-10-18 12:33:35 +02:00
common
fixed error
2019-10-18 13:15:36 +02:00
ecp5
Common memory test now shared
2019-10-18 12:33:35 +02:00
efinix
Common memory test now shared
2019-10-18 12:33:35 +02:00
gowin
ALU sim tweaks
2019-10-24 13:39:43 +02:00
ice40
Common memory test now shared
2019-10-18 12:33:35 +02:00
xilinx
Common memory test now shared
2019-10-18 12:33:35 +02:00
run-test.sh
Add simcells.v, simlib.v, and some output
2019-06-27 11:13:49 -07:00