Clifford Wolf 2bec47a404 Use only module->addCell() and module->remove() to create and delete cells

2014-07-25 17:56:19 +02:00

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ast

Use only module->addCell() and module->remove() to create and delete cells

2014-07-25 17:56:19 +02:00

ilang

Use only module->addCell() and module->remove() to create and delete cells

2014-07-25 17:56:19 +02:00

liberty

Use only module->addCell() and module->remove() to create and delete cells

2014-07-25 17:56:19 +02:00

verific

Updated verific build/test instructions

2014-07-25 12:16:03 +02:00

verilog

Added "make PRETTY=1"

2014-07-24 17:15:01 +02:00

vhdl2verilog

Added passing of various options to vhdl2verilog

2014-07-12 10:02:39 +02:00