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faa2d6fc1c4bc10cda96c2dc3721df209d2d2117
YosysHQ.yosys
/
techlibs
/
xilinx
History
Eddie Hung
faa2d6fc1c
Constrain wreduce only if wide mux
2019-06-21 17:12:34 -07:00
..
tests
…
.gitignore
…
abc_xc7.box
Add $__XILINX_MUXF78 to preserve entire box
2019-06-21 15:47:42 -07:00
abc_xc7.lut
…
arith_map.v
…
brams_bb.v
…
brams_init.py
…
brams_map.v
…
brams.txt
…
cells_map.v
Fix spacing
2019-06-21 16:55:34 -07:00
cells_sim.v
Add $__XILINX_MUXF78 to preserve entire box
2019-06-21 15:47:42 -07:00
cells_xtra.sh
…
cells_xtra.v
…
drams_map.v
…
drams.txt
…
ff_map.v
…
lut_map.v
Really permute Xilinx LUT mappings as default LUT6.I5:A6
2019-06-18 11:48:48 -07:00
Makefile.inc
…
mux_map.v
Simplify and comment out mux_map.v
2019-06-21 17:06:30 -07:00
synth_xilinx.cc
Constrain wreduce only if wide mux
2019-06-21 17:12:34 -07:00
