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YosysHQ.yosys/tests/hana/test_simulation_shifter_left_4_test.v
Clifford Wolf 7764d0ba1d initial import
2013-01-05 11:13:26 +01:00

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Verilog

module test(input [3:0] IN, input [2:0] SHIFT, output [3:0] OUT);
assign OUT = IN << SHIFT;
endmodule