Eddie Hung 505557e93e Merge pull request #1576 from YosysHQ/eddie/opt_merge_init ...

opt_merge: discard \init of '$' cells with 'Q' port when merging

2020-02-05 14:56:26 -08:00

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aiger

Add testcases

2020-01-07 11:44:20 -08:00

arch

Merge pull request #1650 from YosysHQ/eddie/shiftx2mux

2020-02-05 14:55:57 -08:00

asicworld

Fix FIRRTL to Verilog process instance subfield assignment.

2019-02-25 16:18:13 -08:00

bram

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errors

Rename the generic "Syntax error" message from the Verilog/SystemVerilog parser into unique,

2018-10-25 02:37:56 +03:00

fsm

Speed up "make test" and related cleanups

2019-08-17 14:37:07 +02:00

hana

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liberty

Liberty file parser now accepts superfluous ;

2019-03-27 15:16:19 +01:00

lut

Forgot to commit

2019-07-16 12:44:26 -07:00

memories

memory_dff: Fix checking of feedback mux input when more than one mux

2019-07-02 13:35:50 +01:00

opt

Merge pull request #1576 from YosysHQ/eddie/opt_merge_init

2020-02-05 14:56:26 -08:00

opt_share

Support various binary operators in opt_share

2019-08-04 19:06:38 +02:00

proc

proc_clean: fix order of switch insertion.

2019-08-19 16:44:23 +00:00

realmath

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rpc

rpc: new frontend.

2019-09-30 15:53:11 +00:00

sat

Merge pull request #1638 from YosysHQ/eddie/fix1631

2020-02-05 19:31:18 +01:00

share

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simple

Make SV2017 compliant courtesy of @wsnyder

2019-12-12 07:34:07 -08:00

simple_abc9

simple_abc9 tests to discard whitebox before write for sim

2020-01-23 22:07:43 -08:00

smv

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sva

Fix "verific -extnets" for more complex situations

2019-03-26 14:17:46 +01:00

svinterfaces

Fix typo in tests/svinterfaces/runone.sh

2019-05-03 14:40:51 +02:00

svtypes

Use "(id)" instead of "id" for types as temporary hack

2019-10-14 05:24:31 +02:00

techmap

Merge remote-tracking branch 'origin/master' into eddie/shiftx2mux

2020-02-05 10:47:31 -08:00

tools

autotest.sh to define _AUTOTB when test_autotb

2019-06-28 14:56:22 -07:00

unit

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various

sv: More tests for wildcard port connections

2020-02-02 16:12:33 +00:00

vloghtb

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