Clifford Wolf df9d096a7d Ignoring more system task and functions

2015-01-15 13:08:19 +01:00

..

.gitignore

Updated .gitignore file for ilang and verilog frontends

2014-10-15 01:14:38 +02:00

const2ast.cc

Fixed two minor bugs in constant parsing

2014-11-24 14:39:24 +01:00

Makefile.inc

Enable bison to be customized

2015-01-08 09:56:20 -02:00

preproc.cc

Define YOSYS and SYNTHESIS in preproc

2015-01-02 17:11:54 +01:00

verilog_frontend.cc

Print "SystemVerilog" in "read_verilog -sv" log messages

2014-10-16 10:31:54 +02:00

verilog_frontend.h

Added warning for use of 'z' constants in HDL

2014-11-14 19:59:50 +01:00

verilog_lexer.l

Ignoring more system task and functions

2015-01-15 13:08:19 +01:00

verilog_parser.y

Fixed supply0/supply1 with many wires

2014-12-11 13:56:20 +01:00