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YosysHQ.yosys/manual/PRESENTATION_ExSyn
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Clifford Wolf b18fa95d2f Progress in presentation
2014-06-21 16:33:33 +02:00
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.gitignore
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abc_01_cells.lib
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abc_01_cells.v
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abc_01.v
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abc_01.ys
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Makefile
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memory_01.v
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memory_01.ys
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memory_02.v
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memory_02.ys
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opt_01.v
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opt_01.ys
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opt_02.v
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opt_02.ys
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opt_03.v
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opt_03.ys
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opt_04.v
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opt_04.ys
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proc_01.v
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proc_01.ys
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proc_02.v
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proc_02.ys
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proc_03.v
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proc_03.ys
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techmap_01_map.v
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techmap_01.v
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techmap_01.ys
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