Clifford Wolf fea11f0fa4 Added API for generic cell cost calculations

2014-10-09 13:59:26 +02:00

..

bitpattern.h

namespace Yosys

2014-09-27 16:17:53 +02:00

calc.cc

Removed $bu0 cell type

2014-09-04 02:07:52 +02:00

celltypes.h

Added $_BUF_ cell type

2014-10-03 10:12:28 +02:00

consteval.h

namespace Yosys

2014-09-27 16:17:53 +02:00

cost.h

Added API for generic cell cost calculations

2014-10-09 13:59:26 +02:00

driver.cc

No rusage on win32

2014-10-09 10:51:24 +02:00

log.cc

Removed compatbility.{h,cc}: Not using open_memstream/fmemopen anymore

2014-08-23 15:14:58 +02:00

log.h

No rusage on win32

2014-10-09 10:51:24 +02:00

macc.h

added resource sharing of $macc cells

2014-10-03 12:58:40 +02:00

modtools.h

Fixed build with gcc-4.6

2014-08-07 22:37:01 +02:00

register.cc

Corrected spelling mistakes found by lintian

2014-09-06 08:47:06 +02:00

register.h

Changed frontend-api from FILE to std::istream

2014-08-23 15:03:55 +02:00

rtlil.cc

Added $_BUF_ cell type

2014-10-03 10:12:28 +02:00

rtlil.h

Added support for "keep" on modules

2014-09-29 12:51:54 +02:00

satgen.h

satgen import sigbit api

2014-10-03 18:51:50 +02:00

sigtools.h

Added ModIndex helper class, some changes to RTLIL::Monitor

2014-08-01 17:14:32 +02:00

utils.h

namespace Yosys

2014-09-27 16:17:53 +02:00

yosys.cc

Create a default selection stack in RTLIL::Design::Design()

2014-09-02 22:49:24 +02:00

yosys.h

namespace Yosys

2014-09-27 16:17:53 +02:00