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YosysHQ.yosys/techlibs/common
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Marcelina Kościelnicka a3528649c8 memory_dff: Remove now-useless write port handling.
2021-03-08 20:16:29 +01:00
..
.gitignore
Added first help messages for cell types
2015-10-14 16:27:42 +02:00
abc9_map.v
techmap: Add support for [] wildcards in techmap_celltype.
2020-08-02 22:46:48 +02:00
abc9_model.v
abc9_ops/xaiger: further reducing Module::derive() calls by ...
2020-05-14 10:33:57 -07:00
abc9_unmap.v
abc9_ops: -reintegrate use SigMap to remove (* init *) from $_DFF_[NP]_
2020-05-29 17:17:40 -07:00
adff2dff.v
Fix syntax error in adff2dff.v
2021-02-24 01:07:34 +01:00
cellhelp.py
Progress on cell help messages
2015-10-17 02:35:19 +02:00
cells.lib
Added cells.lib
2015-01-16 15:50:42 +01:00
cmp2lcu.v
verilog: significant block scoping improvements
2021-01-31 09:42:09 -05:00
cmp2lut.v
verilog: significant block scoping improvements
2021-01-31 09:42:09 -05:00
dff2ff.v
Add force_downto and force_upto wire attributes.
2020-05-19 01:42:40 +02:00
gate2lut.v
Fix invalid verilog syntax
2020-03-14 14:33:44 +01:00
gen_fine_ffs.py
simcells: Fix reset polarity for $_DLATCH_???_ cells.
2020-06-30 15:32:06 +02:00
Makefile.inc
abc9: add flop boxes to basic $_DFF_P_ and $_DFF_N_ too
2020-05-14 10:33:56 -07:00
mul2dsp.v
verilog: significant block scoping improvements
2021-01-31 09:42:09 -05:00
pmux2mux.v
Added techlibs/common/pmux2mux.v
2014-01-17 20:06:15 +01:00
prep.cc
memory_dff: Remove now-useless write port handling.
2021-03-08 20:16:29 +01:00
simcells.v
simcells: Fix reset polarity for $_DLATCH_???_ cells.
2020-06-30 15:32:06 +02:00
simlib.v
Fix some trivial typos.
2021-01-03 23:52:59 -08:00
synth.cc
Replace opt_rmdff with opt_dff.
2020-08-07 13:21:03 +02:00
techmap.v
techmap/shift_shiftx: Remove the "shiftx2mux" special path.
2020-08-20 12:44:09 +02:00