github.com/YosysHQ.yosys
1
0
Fork 0
mirror of synced 2026-02-01 14:42:19 +00:00
Code Issues Releases Wiki Activity
Files
0.45
YosysHQ.yosys/backends/verilog
History
Catherine d9a4a42389 write_verilog: don't assign to a reg. 
Fixes #2035.
2024-04-03 13:06:45 +02:00
..
Makefile.inc
initial import
2013-01-05 11:13:26 +01:00
verilog_backend.cc
write_verilog: don't assign to a reg.
2024-04-03 13:06:45 +02:00