13 lines
145 B
Plaintext
13 lines
145 B
Plaintext
ram distributed $__TRELLIS_DPR16X4_ {
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abits 4;
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width 4;
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cost 4;
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init any;
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prune_rom;
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port sw "W" {
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clock anyedge;
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}
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port ar "R" {
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}
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}
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