38 lines
524 B
Verilog
38 lines
524 B
Verilog
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module test1(a, b, x, y);
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input [7:0] a, b;
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output [7:0] x, y;
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inc #(.step(3)) inc_a (.in(a), .out(x));
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inc #(.width(4), .step(7)) inc_b (b, y);
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endmodule
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// -----------------------------------
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module test2(a, b, x, y);
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input [7:0] a, b;
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output [7:0] x, y;
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inc #(5) inc_a (.in(a), .out(x));
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inc #(4, 7) inc_b (b, y);
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endmodule
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// -----------------------------------
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module inc(in, out);
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parameter width = 8;
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parameter step = 1;
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input [width-1:0] in;
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output [width-1:0] out;
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assign out = in + step;
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endmodule
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