Emil J. Tywoniak 6240aec433 test: restore verific handling, nicer naming

2024-12-13 10:24:47 +01:00

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.gitignore

Add test cases for co-simulation

2022-02-02 13:22:44 +01:00

alu.v

Add test cases for co-simulation

2022-02-02 13:22:44 +01:00

asserts_seq.v

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asserts_seq.ys

tests: Run async2sync before sat and/or sim to handle $check cells

2024-02-01 16:14:11 +01:00

asserts.v

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asserts.ys

tests: Run async2sync before sat and/or sim to handle $check cells

2024-02-01 16:14:11 +01:00

bug2595.ys

Remove references to ilang

2024-11-05 12:36:31 +13:00

clk2fflogic.ys

More rigorous test

2020-01-16 09:15:42 -08:00

counters-repeat.v

support repeat loops with constant repeat counts outside of constant functions

2019-04-09 12:28:32 -04:00

counters-repeat.ys

support repeat loops with constant repeat counts outside of constant functions

2019-04-09 12:28:32 -04:00

counters.v

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counters.ys

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dff.ys

satgen: Add support for dffe, sdff, sdffe, sdffce cells.

2020-07-24 03:19:21 +02:00

expose_dff.v

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expose_dff.ys

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grom_computer.v

Add test cases for co-simulation

2022-02-02 13:22:44 +01:00

grom_cpu.v

Proper example code

2022-03-14 15:39:11 +01:00

grom.ys

bug fix and cleanups

2022-02-04 10:01:06 +01:00

initval.v

Wire with init on FF part, 1'bx on non-FF part

2019-08-24 15:05:44 -07:00

initval.ys

tests: Run async2sync before sat and/or sim to handle $check cells

2024-02-01 16:14:11 +01:00

ram_memory.v

Proper example code

2022-03-14 15:39:11 +01:00

run-test.sh

test: restore verific handling, nicer naming

2024-12-13 10:24:47 +01:00

share.v

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share.ys

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sim_counter.ys

Add test cases for co-simulation

2022-02-02 13:22:44 +01:00

sizebits.sv

Add support for $dimensions and $unpacked_dimensions

2024-02-11 11:26:52 -05:00

sizebits.ys

tests: Run async2sync before sat and/or sim to handle $check cells

2024-02-01 16:14:11 +01:00

splice.v

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splice.ys

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