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YosysHQ.yosys/tests
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Eddie Hung 862631d657 Add ABC9 DSP cascade test
2023-05-25 18:42:08 +01:00
..
aiger
switch argument order to work with macOS getopt
2020-09-23 12:48:26 +02:00
arch
Add ABC9 DSP cascade test
2023-05-25 18:42:08 +01:00
asicworld
Fix FIRRTL to Verilog process instance subfield assignment.
2019-02-25 16:18:13 -08:00
bind
Add support for parsing the SystemVerilog 'bind' construct
2021-07-16 09:31:39 -04:00
blif
Adding check for BLIF names command input plane size.
2022-08-21 23:18:20 -05:00
bram
Fix the tests we just broke
2021-12-10 00:22:37 +01:00
errors
Rename the generic "Syntax error" message from the Verilog/SystemVerilog parser into unique,
2018-10-25 02:37:56 +03:00
fsm
tests: fsm to use a randomly-generated seed
2020-04-24 14:31:33 -07:00
hana
Add optional SEED=n command line option to Makefile, and -S n command line option to test scripts, for deterministic regression tests.
2016-09-22 11:49:29 -06:00
liberty
fix file rights
2023-05-17 13:39:57 +02:00
lut
Forgot to commit
2019-07-16 12:44:26 -07:00
memfile
Added 'set -e' into tests/memfile/run-test.sh
2020-02-06 10:45:40 -03:00
memlib
More tests in memlib/generate.py
2023-02-21 05:23:15 +13:00
memories
Fix the tests we just broke
2021-12-10 00:22:37 +01:00
opt
simplemap: Map $xnor to $_XNOR_ cells
2022-11-29 19:06:45 +01:00
opt_share
tests: Parallelize
2020-09-21 15:07:02 +02:00
proc
proc_rom: Add special handling of const-0 address bits.
2022-05-18 17:32:30 +02:00
realmath
Add optional SEED=n command line option to Makefile, and -S n command line option to test scripts, for deterministic regression tests.
2016-09-22 11:49:29 -06:00
rpc
rpc test: make frontend listen before launching yosys & introduce safeguard if yosys errors
2020-03-06 15:29:01 +01:00
sat
Proper example code
2022-03-14 15:39:11 +01:00
select
Merge pull request #1949 from YosysHQ/eddie/select_blackbox
2020-04-22 15:35:05 -07:00
share
Add optional SEED=n command line option to Makefile, and -S n command line option to test scripts, for deterministic regression tests.
2016-09-22 11:49:29 -06:00
sim
Replace GNU specific invocation of basename(1) with the equivalent
2022-10-23 11:02:18 +13:00
simple
verilog: Support module-scoped task/function calls
2022-10-29 15:14:11 -04:00
simple_abc9
abc9: fix SCC issues (#2694)
2021-03-29 22:01:57 -07:00
smv
Progress in SMV back-end
2015-06-19 14:08:46 +02:00
sva
verific: Use new value change logic also for $stable of wide signals.
2022-05-11 13:05:27 +02:00
svinterfaces
Resolve package types in interfaces (#3658)
2023-02-12 18:25:39 -05:00
svtypes
Cleaner tests for RTLIL cells in struct_dynamic_range.sv
2023-05-04 14:28:21 +02:00
techmap
add pmux option to bmuxmap for better fsm detection with verific frontend
2023-01-30 16:12:53 +01:00
tools
support file locations containing spaces
2022-08-08 20:30:50 +02:00
unit
Build hotfix in tests/unit/Makefile
2016-12-11 10:58:49 +01:00
various
Merge pull request #3646 from YosysHQ/lofty/fix-3591
2023-02-27 16:26:57 +01:00
verific
verific: Fix enum_values support and signed attribute values
2023-03-15 09:51:36 +01:00
verilog
Standard compliance for tests/verilog/block_labels.ys
2023-05-21 16:38:14 -04:00
vloghtb
Use HTTPS for website links, gatecat email
2021-06-09 12:16:56 +02:00
xprop
xprop tests: Make iverilog invocation more portable
2023-02-13 16:54:11 +01:00
gen-tests-makefile.sh
Out of bounds checking for struct/union members
2023-02-19 23:25:08 +01:00