From 14a82a7e610832ba5994ea2c15d8eb6752c7b9b7 Mon Sep 17 00:00:00 2001 From: aap Date: Sun, 13 Nov 2016 02:06:34 +0100 Subject: [PATCH] rewrote the verilog code --- verilog/Makefile | 4 +- verilog/apr.v | 1700 +++++++++++++++++++++++++++++++------------- verilog/core161c.v | 315 ++++++++ verilog/coremem.v | 255 ------- verilog/fast162.v | 234 ++++++ verilog/fastmem.v | 195 ----- verilog/modules.v | 362 +++++----- verilog/pdp6.v | 244 +++++++ verilog/test.gtkw | 491 ++++++------- verilog/test.v | 286 +++----- 10 files changed, 2520 insertions(+), 1566 deletions(-) create mode 100644 verilog/core161c.v delete mode 100644 verilog/coremem.v create mode 100644 verilog/fast162.v delete mode 100644 verilog/fastmem.v create mode 100644 verilog/pdp6.v diff --git a/verilog/Makefile b/verilog/Makefile index 650c709..5268f92 100644 --- a/verilog/Makefile +++ b/verilog/Makefile @@ -1,5 +1,5 @@ -a.out: test.v apr.v coremem.v fastmem.v modules.v - iverilog test.v apr.v coremem.v fastmem.v modules.v +a.out: test.v pdp6.v apr.v core161c.v fast162.v modules.v + iverilog test.v pdp6.v apr.v core161c.v fast162.v modules.v run: a.out vvp a.out diff --git a/verilog/apr.v b/verilog/apr.v index e8dfb99..5af48d7 100644 --- a/verilog/apr.v +++ b/verilog/apr.v @@ -1,448 +1,1212 @@ -//`default_nettype none +`default_nettype none -module ar_reg( - input clk, - input arlt_clr, - input arrt_clr, - input arlt_fm_mb0, - input arrt_fm_mb0, - input arlt_fm_mb1, - input arrt_fm_mb1, - input arlt_fm_datasw1, - input arrt_fm_datasw1, - input [0:35] mb, - input [0:35] datasw, - output [0:35] ar +module apr( + input wire clk, + input wire reset, + + // keys + input wire key_start, + input wire key_read_in, + input wire key_mem_cont, + input wire key_inst_cont, + input wire key_mem_stop, + input wire key_inst_stop, + input wire key_exec, + input wire key_io_reset, + input wire key_dep, + input wire key_dep_nxt, + input wire key_ex, + input wire key_ex_nxt, + + // switches + input wire sw_addr_stop, + input wire sw_mem_disable, + input wire sw_repeat, + input wire sw_power, + input wire [0:35] datasw, + input wire [18:35] mas, + + // maintenance switches + input wire sw_rim_maint, + input wire sw_repeat_bypass, + input wire sw_art3_maint, + input wire sw_sct_maint, + input wire sw_split_cyc, + + // lights + output [0:17] ir, + output [0:35] mi, + output [0:35] ar, + output [0:35] mb, + output [0:35] mq, + output [18:35] pc, + output [18:35] ma, + output [0:8] fe, + output [0:8] sc, + output run, + output mc_stop, + output pi_active, + output [1:7] pih, + output [1:7] pir, + output [1:7] pio, + output [18:25] pr, + output [18:25] rlr, + output [18:25] rla, + // TODO: all the flipflops? + + // membus + output wire membus_wr_rs, + output wire membus_rq_cyc, + output wire membus_rd_rq, + output wire membus_wr_rq, + output wire [21:35] membus_ma, + output wire [18:21] membus_sel, + output wire membus_fmc_select, + output wire [0:35] membus_mb_out, + input wire membus_addr_ack, + input wire membus_rd_rs, + input wire [0:35] membus_mb_in, + + // IO bus + output wire iobus_iob_poweron, + output wire iobus_iob_reset, + output wire iobus_datao_clear, + output wire iobus_datao_set, + output wire iobus_cono_clear, + output wire iobus_cono_set, + output wire iobus_iob_fm_datai, + output wire iobus_iob_fm_status, + output wire [3:9] iobus_ios, + output wire [0:35] iobus_iob_out, + input wire [1:7] iobus_pi_req, + input wire [0:35] iobus_iob_in ); - reg [0:17] arlt; - reg [18:35] arrt; - always @(posedge clk) begin: arctl - integer i; - if(arlt_clr) - arlt <= 0; - if(arrt_clr) - arrt <= 0; - for(i = 0; i < 18; i = i+1) begin - if(arlt_fm_mb0 & ~mb[i]) - arlt[i] <= 0; - if(arlt_fm_mb1 & mb[i]) - arlt[i] <= 1; - if(arrt_fm_mb0 & ~mb[i+18]) - arrt[i+18] <= 0; - if(arrt_fm_mb1 & mb[i+18]) - arrt[i+18] <= 1; - end - if(arlt_fm_datasw1) - arlt <= arlt | datasw[0:17]; - if(arlt_fm_datasw1) - arrt <= arrt | datasw[18:35]; + /* + * KEY + */ + reg run; + reg key_ex_st; + reg key_dep_st; + reg key_ex_sync; + reg key_dep_sync; + reg key_rim_sbr; + reg key_rdwr; + + wire key_clr_rim = ~key_read_in | + ~key_mem_cont & ~key_inst_cont; + wire key_ma_fm_mas = key_ex_sync | key_dep_sync | + key_start_OR_read_in; + wire key_execute = ~run & key_exec; + wire key_start_OR_read_in = key_start | key_read_in; + wire key_start_OR_cont_OR_read_in = key_inst_cont | + key_start_OR_read_in; + wire key_ex_OR_dep_nxt = key_ex_nxt | key_dep_nxt; + wire key_dp_OR_dp_nxt = key_dep_sync | key_dep_nxt; + wire key_run_AND_NOT_ex_OR_dep = run & ~key_ex_OR_dep_st; + wire key_ex_OR_ex_nxt = key_ex_sync | key_ex_nxt; + wire key_manual = key_ex | key_ex_nxt | + key_dep | key_dep_nxt | + key_start | key_inst_cont | key_mem_cont | + key_io_reset | key_execute | key_read_in; + wire key_ex_OR_dep_st = key_ex_st | key_dep_st; + wire key_run_AND_ex_OR_dep = run & key_ex_OR_dep_st; + wire key_execute_OR_dp_OR_dp_nxt = key_execute | key_dp_OR_dp_nxt; + wire run_clr; + wire mr_pwr_clr; + wire mr_start = kt1 & key_io_reset | mr_pwr_clr; + wire mr_clr = kt1 & key_manual & ~key_mem_cont | + mr_pwr_clr | uuo_t1 | iat0 | xct_t0 | it0; + wire kt0; + wire kt0a; + wire kt1; + wire kt2; + wire kt3; + wire kt4; + wire key_go; + wire key_rdwr_ret; + wire key_ma_clr = kt1 & key_ma_fm_mas; + wire key_ma_fm_masw1 = kt2 & key_ma_fm_mas; + wire key_ma_inc = kt1 & key_ex_OR_dep_nxt; + wire key_ar_clr = kt1 & key_execute_OR_dp_OR_dp_nxt; + wire key_ar_fm_datasw1 = kt2 & key_execute_OR_dp_OR_dp_nxt | + 0; // TODO: cpa & iob <- datai + wire key_rd = kt3 & key_ex_OR_ex_nxt; + wire key_wr = kt3 & key_dp_OR_dp_nxt; + + wire kt0a_D, kt1_D, kt2_D; + pg key_pg0(.clk(clk), .reset(reset), .in(key_inst_stop), .p(run_clr)); + pg key_pg1(.clk(clk), .reset(reset), .in(sw_power), .p(mr_pwr_clr)); + pg key_pg2(.clk(clk), .reset(reset), .in(key_manual), .p(kt0)); + pa key_pa0(.clk(clk), .reset(reset), .in(kt0), .p(kt0a)); + dly100ns key_dly0(.clk(clk), .reset(reset), .in(kt0a), .p(kt0a_D)); + pa key_pa1(.clk(clk), .reset(reset), + .in(kt0a_D & ~run | + kt0a & key_mem_cont | // TODO: check run? + st7 & run & key_ex_OR_dep_st), + .p(kt1)); + dly200ns key_dly1(.clk(clk), .reset(reset), .in(kt1), .p(kt1_D)); + pa key_pa2(.clk(clk), .reset(reset), .in(kt1_D), .p(kt2)); + dly200ns key_dly2(.clk(clk), .reset(reset), .in(kt2), .p(kt2_D)); + pa key_pa3(.clk(clk), .reset(reset), .in(kt2_D), .p(kt3)); + pa key_pa4(.clk(clk), .reset(reset), + .in(kt3 & key_execute | + key_rdwr_ret | + mc_stop_set & key_mem_cont | + st7 & key_start_OR_cont_OR_read_in), + .p(kt4)); + pa key_pa5(.clk(clk), .reset(reset), + .in(kt3 & key_start_OR_cont_OR_read_in | + key_run_AND_ex_OR_dep), + .p(key_go)); + pa key_pa6(.clk(clk), .reset(reset), + .in(key_rdwr & mc_rs_t1), + .p(key_rdwr_ret)); + + /* add to this as needed */ + always @(posedge reset) begin + run <= 0; + key_ex_st <= 0; + key_dep_st <= 0; end - assign ar = {arlt, arrt}; -endmodule + always @(posedge clk) begin + if(run_clr | + et0a & key_inst_stop | + et0a & ir_jrst & ir[10] & ~ex_user | + mr_pwr_clr) + run <= 0; + if(key_go) + run <= 1; -module mb_reg( - input clk, - input mblt_clr, - input mbrt_clr, - input mblt_fm_ar0, - input mbrt_fm_ar0, - input mblt_fm_ar1, - input mbrt_fm_ar1, - input mblt_fm_mbrtJ, - input mbrt_fm_mbltJ, - input [0:35] mbN_clr, - input [0:35] mbN_set, - input [0:35] ar, - output [0:35] mb -); - reg [0:17] mblt; - reg [18:35] mbrt; + if(kt0a | key_go) begin + key_ex_st <= 0; + key_dep_st <= 0; + key_ex_sync <= 0; + key_dep_sync <= 0; + end + if(et0a) begin + if(key_ex_sync) key_ex_st <= 1; + if(key_dep_sync) key_dep_st <= 1; + end + if(kt0a) begin + if(key_ex) key_ex_sync <= 1; + if(key_dep) key_dep_sync <= 1; + end - always @(posedge clk) begin: mbctl - integer i; - if(mblt_clr) - mblt <= 0; - if(mbrt_clr) - mbrt <= 0; - for(i = 0; i < 18; i = i+1) begin - if(mblt_fm_ar0 & ~ar[i]) - mblt[i] <= 0; - if(mblt_fm_ar1 & ar[i]) - mblt[i] <= 1; - if(mbrt_fm_ar0 & ~ar[i+18]) - mbrt[i+18] <= 0; - if(mbrt_fm_ar1 & ar[i+18]) - mbrt[i+18] <= 1; - end - for(i = 0; i < 18; i = i+1) begin - if(mbN_clr[i]) - mblt[i] <= 0; - if(mbN_clr[i+18]) - mbrt[i+18] <= 0; - if(mbN_set[i]) - mblt[i] <= 1; - if(mbN_set[i+18]) - mbrt[i+18] <= 1; - end - if(mblt_fm_mbrtJ) - mblt <= mbrt; - if(mbrt_fm_mbltJ) - mbrt <= mblt; + if(key_rd | key_wr) + key_rdwr <= 1; + if(mr_clr | key_rdwr_ret) + key_rdwr <= 0; + + if(kt1 & key_read_in | sw_rim_maint) + key_rim_sbr <= 1; + else if(kt1 & key_clr_rim | it1a & ~ma18_31_eq_0) + key_rim_sbr <= 0; end - assign mb = {mblt, mbrt}; -endmodule + /* + * I + */ + reg if1a; + wire at1_inh = 0; + wire ia_NOT_int = 0; + wire iat0 = 0; + wire it0 = 0; + wire it1 = 0; + wire it1a = 0; -module pc_reg( - input clk, - input pc_clr, - input pc_inc, - input pc_fm_ma1, - input [18:35] ma, - output [18:35] pc -); + /* + * A + */ + reg af0; + reg af3; + reg af3a; + wire at0 = 0; + wire at1 = 0; + wire at2 = 0; + wire at3 = 0; + wire at3a = 0; + wire at4 = 0; + wire at5 = 0; + + /* + * F + */ + reg f1a; + reg f4a; + reg f6a; + wire ft0 = 0; + wire ft1 = 0; + wire ft1a = 0; + wire ft3 = 0; + wire ft4 = 0; + wire ft4a = 0; + wire ft5 = 0; + wire ft6 = 0; + wire ft6a = 0; + wire ft7 = 0; + wire f_c_c_acrt = 0; + wire f_c_c_aclt = 0; + wire f_ac_2 = 0; + wire f_c_c_aclt_OR_rt = 0; + wire f_ac_inh = 0; + wire f_c_e = 0; + wire f_c_e_pse = 0; + wire f_c_e_OR_pse = 0; + + /* + * E + */ + reg et4_ar_pse; + wire et0a = 0; + wire et0 = 0; + wire et1 = 0; + wire et3 = 0; + wire et4 = 0; + wire et5 = 0; + wire et6 = 0; + wire et7 = 0; + wire et8 = 0; + wire et9 = 0; + wire et10 = 0; + wire et4_inh = 0; + wire et5_inh = 0; + wire e_long = 0; + + /* + * S + */ + reg sf3; + reg sf5a; + reg sf7; + wire st1 = 0; + wire st2 = 0; + wire st3 = 0; + wire st3a = 0; + wire st5 = 0; + wire st5a = 0; + wire st6 = 0; + wire st7 = 0; + wire s_c_e = 0; + wire s_ac_inh_if_ac_0 = 0; + wire s_ac_inh = 0; + wire s_ac_2 = 0; + wire s_ac_0 = 0; + + /* + * IR + */ + reg [0:17] ir; + wire ir0_12_clr = 0; + wire ir13_17_clr = 0; + wire ir0_12_fm_mb1 = 0; + wire ir13_17_fm_mb1 = 0; + + wire ir_uuo_a = 0; + wire ir_fpch = 0; + wire ir_2xx = 0; + wire ir_accp_OR_memac = 0; + wire ir_boole = 0; + wire ir_hwt = 0; + wire ir_acbm = 0; + wire ir_iot_a = 0; + + wire ir_130 = 0; + wire ir_131 = 0; + wire ir_fsc = 0; + wire ir_cao = 0; + wire ir_ldci = 0; + wire ir_ldc = 0; + wire ir_dpci = 0; + wire ir_dpc = 0; + + wire ir_fwt_mov_s = 0; + wire ir_fwt_movn_m = 0; + wire ir_fwt = 0; + wire ir_mul = 0; + wire ir_div = 0; + wire ir_sh = 0; + wire ir_25x = 0; + wire ir_jp = 0; + wire ir_as = 0; + + wire ir_ash = 0; + wire ir_rot = 0; + wire ir_lsh = 0; + wire ir_243 = 0; + wire ir_ashc = 0; + wire ir_rotc = 0; + wire ir_lshc = 0; + wire ir_247 = 0; + + wire ir_exch = 0; + wire ir_blt = 0; + wire ir_aobjp = 0; + wire ir_aobjn = 0; + wire ir_jrst_a = 0; + wire ir_jfcl = 0; + wire ir_xct = 0; + wire ir_257 = 0; + + wire ir_ash_OR_ashc = 0; + wire ir_md = 0; + wire ir_md_s_c_e = 0; + wire ir_md_f_c_e = 0; + wire ir_md_sac_inh = 0; + wire ir_254_7 = 0; + wire ir_md_f_ac_2 = 0; + wire ir_md_s_ac_2 = 0; + wire ir_iot = 0; + wire ir_jrst = 0; + wire ir_9_OR_10_1 = 0; + wire ir_fp = 0; + wire ir_fp_dir = 0; + wire ir_fp_rem = 0; + wire ir_fp_mem = 0; + wire ir_fp_both = 0; + wire ir_fad = 0; + wire ir_fsb = 0; + wire ir_fmp = 0; + wire ir_fdv = 0; + wire ir_14_17_0 = 0; + + /* ACCP V MEM AC */ + wire accp = 0; + wire memac_tst = 0; + wire memac_inc = 0; + wire memac_dec = 0; + wire memac = 0; + wire memac_mem = 0; + wire memac_ac = 0; + wire accp_etc_cond = 0; + wire accp_etal_test = 0; + wire accp_dir = 0; + + /* ACBM */ + wire acbm_swap = 0; + wire acbm_dir = 0; + wire acbm_cl = 0; + wire acbm_dn = 0; + wire acbm_com = 0; + wire acbm_set = 0; + + /* FWT */ + wire fwt_swap = 0; + wire fwt_negate = 0; + wire fwt_00 = 0; + wire fwt_01 = 0; + wire fwt_10 = 0; + wire fwt_11 = 0; + + /* HWT */ + wire hwt_lt_set = 0; + wire hwt_rt_set = 0; + wire hwt_lt = 0; + wire hwt_rt = 0; + wire hwt_swap = 0; + wire hwt_ar_clr = 0; + wire hwt_00 = 0; + wire hwt_01 = 0; + wire hwt_10 = 0; + wire hwt_11 = 0; + + /* BOOLE */ + wire boole_as_00 = 0; + wire boole_as_01 = 0; + wire boole_as_10 = 0; + wire boole_as_11 = 0; + wire boole_00 = 0; + wire boole_01 = 0; + wire boole_02 = 0; + wire boole_03 = 0; + wire boole_04 = 0; + wire boole_05 = 0; + wire boole_06 = 0; + wire boole_07 = 0; + wire boole_10 = 0; + wire boole_11 = 0; + wire boole_12 = 0; + wire boole_13 = 0; + wire boole_14 = 0; + wire boole_15 = 0; + wire boole_16 = 0; + wire boole_17 = 0; + + /* JUMP V PUSH */ + wire jp_flag_stor = 0; + wire jp_AND_NOT_jsr = 0; + wire jp_AND_ir6_0 = 0; + wire jp_jmp = 0; + wire jp_pushj = 0; + wire jp_push = 0; + wire jp_pop = 0; + wire jp_popj = 0; + wire jp_jsr = 0; + wire jp_jsp = 0; + wire jp_jsa = 0; + wire jp_jra = 0; + + /* AS */ + wire as_plus = 0; + wire as_minus = 0; + + /* XCT */ + wire xct_t0 = 0; + + /* + * UUO + */ + reg uuo_f1; + wire uuo_t1 = 0; + wire uuo_t2 = 0; + + /* + * PC + */ reg [18:35] pc; + wire pc_clr = et7 & pc_set | kt1 & key_start_OR_read_in; + wire pc_fm_ma1 = et8 & pc_set | kt3 & key_start_OR_read_in; + wire pc_inc = 0; + wire pc_set_OR_pc_inc = 0; + wire pc_set = 0; + wire pc_inc_et9 = 0; + wire pc_inc_inh_et0 = 0; + wire pc_inc_enable = 0; + wire pc_set_enable = 0; always @(posedge clk) begin if(pc_clr) pc <= 0; - if(pc_inc) - pc <= pc+1; if(pc_fm_ma1) pc <= pc | ma; end -endmodule -module ma_reg( - input clk, - input ma_clr, - input ma_inc, - input key_ma_fm_masw1, - input ma_fm_pc1, - input [18:35] mas, - input [18:35] pc, - output [18:35] ma -); + /* + * EX + */ + reg ex_user; + reg ex_mode_sync; + reg ex_uuo_sync; + reg ex_pi_sync; + reg ex_ill_op; + wire ex_clr; + wire ex_set = 0; + wire ex_ir_uuo = 0; + wire ex_inh_rel = ~ex_user | ex_pi_sync | ma18_31_eq_0 | ex_ill_op; + + pa ex_pa0(.clk(clk), .reset(reset), + .in(mr_start), // TODO + .p(ex_clr)); + + always @(posedge clk) begin + if(mr_start) begin + ex_ill_op <= 0; + ex_user <= 0; + end + if(mr_clr) begin + if(ex_mode_sync) + ex_user <= 1; + ex_mode_sync <= 0; + ex_uuo_sync <= 0; + ex_pi_sync <= 0; + end + end + + /* + * MB + */ + reg [0:35] mb; + wire mblt_clr = mb_clr; + wire mblt_fm_ar0 = mb_fm_arJ | mb_ar_swap | mb_fm_ar0 | cfac_mb_ar_swap; + wire mblt_fm_ar1 = mb_fm_arJ | mb_ar_swap | cfac_mb_ar_swap; + wire mblt_fm_mq0 = 0; + wire mblt_fm_mq1 = 0; + wire mblt_fm_mbrtJ = 0; + wire mb_fm_ir1 = 0; + wire mbrt_clr = mb_clr; + wire mbrt_fm_ar0 = mb_fm_arJ | mb_ar_swap | mb_fm_ar0 | cfac_mb_ar_swap; + wire mbrt_fm_ar1 = mb_fm_arJ | mb_ar_swap | cfac_mb_ar_swap; + wire mbrt_fm_mq0 = 0; + wire mbrt_fm_mq1 = 0; + wire mbrt_fm_mbltJ = 0; + wire mb_fm_pc1 = 0; + + wire mb_clr = et1 & ex_ir_uuo | + et5 & mb_pc_sto | + mc_mb_clr_D; + wire mblt_mbrt_swap = 0; + wire mblt_mbrt_swap_et0 = 0; + wire mblt_mbrt_swap_et1 = 0; + wire mb_fm_misc_bits1 = 0; + wire mb_fm_ar0 = 0; + wire mb_fm_ar0_et1 = 0; + wire mb_fm_arJ = at3a | st5 | key_wr | dst1 | mst1 | + et0a & mb_fm_arJ_et0 | + et10 & mb_fm_arJ_et10 | + kt3 & key_execute; + wire mb_fm_arJ_et0 = 0; + wire mb_fm_arJ_et10 = 0; + wire mb_fm_arJ_inh_et10 = 0; + wire mb_ar_swap = 0; + wire mb_ar_swap_et0 = 0; + wire mb_ar_swap_et4 = 0; + wire mb_ar_swap_et9 = 0; + wire mb_ar_swap_et10 = 0; + wire mb_fm_mqJ = 0; + wire mb_fm_mqJ_et0 = 0; + wire mb1_8_clr = 0; + wire mb1_8_set = 0; + wire mblt_fm_ir1_uuo_t0 = 0; + wire mblt_fm_pc1_init = 0; + wire mb_pc_sto = 0; + wire mb_fm_pc1_et6 = 0; + + wire mc_mb_clr_D; + dly100ns mb_dly0(.clk(clk), .reset(reset), .in(mc_mb_clr), .p(mc_mb_clr_D)); + + wire membus_mb_pulse; + pg mb_pg0(.clk(clk), .reset(reset), .in(| membus_mb_in), .p(membus_mb_pulse)); + + + always @(posedge clk) begin: mbctl + integer i; + if(mblt_clr) + mb[0:17] <= 0; + if(mbrt_clr) + mb[18:35] <= 0; + for(i = 0; i < 18; i = i+1) begin + if(mblt_fm_ar0 & ~ar[i]) + mb[i] <= 0; + if(mblt_fm_ar1 & ar[i]) + mb[i] <= 1; + if(mbrt_fm_ar0 & ~ar[i+18]) + mb[i+18] <= 0; + if(mbrt_fm_ar1 & ar[i+18]) + mb[i+18] <= 1; + end + if(membus_mb_pulse & mc_mb_membus_enable) + mb <= mb | membus_mb_in; + end + + /* + * AR + */ + reg [0:35] ar; + reg ar_com_cont; + reg ar_pc_chg_flg; + reg ar_ov_flag; + reg ar_cry0_flag; + reg ar_cry1_flag; + reg ar_cry0; + reg ar_cry1; + wire arlt_clr = ar_clr | at4 | blt_t2 | key_ar_clr; + wire arlt_cry_initiate = 0; + wire arlt_com = 0; + wire arlt_fm_mb_xor = 0; + wire arlt_fm_mblt0 = 0; + wire arlt_fm_mblt1 = 0; + wire arlt_shlt = 0; + wire arlt_shrt = 0; + wire arlt_fm_datasw1 = key_ar_fm_datasw1; + wire arlt_fm_iob1 = 0; + wire arrt_clr = ar_clr | key_ar_clr; + wire arrt_cry_initiate = 0; + wire arrt_com = 0; + wire arrt_fm_mb_xor = 0; + wire arrt_fm_mbrt0 = 0; + wire arrt_fm_mbrt1 = 0; + wire arrt_shlt = 0; + wire arrt_shrt = 0; + wire arrt_fm_datasw1 = key_ar_fm_datasw1; + wire arrt_iob1 = 0; + wire ar0_shl_inp = 0; + wire ar0_shr_inp = 0; + wire ar35_shl_inp = 0; + + wire shc_ashc = 0; + wire shc_lshc_OR_div = 0; + wire shc_div = 0; + + wire ar_clr = dst2 | fat6 | et0a & ar_clr_et0 | et1 & ar_clr_et1 | + 0; // TODO: MST1 50ns delay + wire ar_clr_et0 = 0; + wire ar_clr_et1 = 0; + wire ar_com = 0; + wire ar_com_et0 = 0; + wire ar_com_et4 = 0; + wire ar_com_et5 = 0; + wire ar_com_et7 = 0; + wire ar_fm_mb0 = 0; + wire ar_fm_mb0_et1 = 0; + wire ar_fm_mb0_et6 = 0; + wire ar_fm_mb1 = 0; + wire ar_fm_mb1_et1 = 0; + wire ar_fm_mb_xor = 0; + wire ar_fm_mb_xor_et1 = 0; + wire ar_fm_mbJ = 0; + wire ar_fm_mbJ_et0 = 0; + wire ar_fm_mbltJ_et4 = 0; + wire ar_fm_mbrtJ_et4 = 0; + + wire ar1_8_clr = 0; + wire ar1_8_set = 0; + wire ar_add = 0; + wire ar_sub = 0; + wire ar_inc = 0; + wire ar_incdec_lt_rt = 0; + wire ar_dec = 0; + wire ar_sbr = 0; + wire ar_cry_comp = 0; + wire ar_fm_sc1_8J = 0; + wire ar0_5_fm_sc3_8J = 0; + wire ar_incdec_t0 = 0; + wire ar_negate_t0 = 0; + wire ar_incdec_t1 = 0; + wire ar_17_cry_in = 0; + wire ar_as_t0 = 0; + wire ar_as_t1 = 0; + wire ar_as_t2 = 0; + wire ar_eq_fp_half = 0; + wire ar_eq_0 = 0; + wire ar0_xor_ar1 = 0; + wire ar_ov_set = 0; + wire ar_cry0_xor_cry1 = 0; + wire ar0_xor_ar_ov = 0; + wire ar0_xor_mb0 = 0; + wire ar0_eq_sc0 = 0; + wire ar_flag_clr = 0; + wire ar_flag_set = 0; + wire ar_jfcl_clr = 0; + + always @(posedge clk) begin + if(arlt_clr) + ar[0:17] <= 0; + if(arrt_clr) + ar[18:35] <= 0; + if(arlt_fm_datasw1) + ar[0:17] <= ar[0:17] | datasw[0:17]; + if(arrt_fm_datasw1) + ar[18:35] <= ar[18:35] | datasw[18:35]; + end + + /* + * MQ + */ + reg [0:35] mq; + reg mq36; + wire mqlt_clr = 0; + wire mqlt_fm_mb0 = 0; + wire mqlt_fm_mb1 = 0; + wire mqrt_clr = 0; + wire mqrt_fm_mb0 = 0; + wire mqrt_fm_mb1 = 0; + wire mq_shl = 0; + wire mq_shr = 0; + + wire mq0_shl_inp = 0; + wire mq0_shr_inp = 0; + wire mq1_shr_inp = 0; + wire mq35_shl_inp = 0; + + wire mq0_clr = 0; + wire mq0_set = 0; + wire mq_fm_mbJ = 0; + wire mq35_xor_mb0 = 0; + wire mq35_eq_mq36 = 0; + + /* + * FE, SC + */ + reg [0:8] fe; + wire fe_clr = 0; + wire fe_fm_sc1 = 0; + wire fe_fm_mb0_5_1 = 0; + + reg [0:8] sc; + wire sc_clr = 0; + wire sc_inc = 0; + wire sc_com = 0; + wire sc_pad = 0; + wire sc_cry = 0; + wire sc_fm_fe1 = 0; + wire sc_fm_mb18_28_35_0 = 0; + wire sc_mb0_5_0_enable = 0; + wire sc_mb6_11_1_enable = 0; + wire sc_ar0_8_1_enable = 0; + wire sc_mb0_8_1_enable = 0; + // TODO: figure out what's going on here... + wire sc_eq_777 = 0; + wire sc0_2_eq_7 = 0; + + wire sat0 = 0; + wire sat1 = 0; + wire sat2 = 0; + wire sat21 = 0; + wire sat3 = 0; + + wire sct0 = 0; + wire sct1 = 0; + wire sct2 = 0; + + /* + * CFAC + */ + wire cfac_ar_negate = 0; + wire cfac_ar_add = 0; + wire cfac_ar_sub = 0; + wire cfac_mb_fm_mqJ = 0; + wire cfac_mb_mq_swap = 0; + wire cfac_mb_ar_swap = 0; + wire cfac_ar_com = 0; + wire cfac_overflow = 0; + wire cfac_ar_sh_lt = 0; + wire cfac_mq_sh_lt = 0; + wire cfac_ar_sh_rt = 0; + wire cfac_mq_sh_rt = 0; + + /* + * BLT + */ + reg blt_f0a; + reg blt_f3a; + reg blt_f5a; + wire blt_done = 0; + wire blt_last = 0; + + wire blt_t0 = 0; + wire blt_t0a = 0; + wire blt_t1 = 0; + wire blt_t2 = 0; + wire blt_t3 = 0; + wire blt_t3a = 0; + wire blt_t4 = 0; + wire blt_t5 = 0; + wire blt_t5a = 0; + wire blt_t6 = 0; + + /* + * FS + */ + reg fsf1; + wire fsc = 0; + wire fst0 = 0; + wire fst0a = 0; + wire fst1 = 0; + + /* + * CH + */ + reg chf1; + reg chf2; + reg chf3; + reg chf4; + reg chf5; + reg chf6; + reg chf7; + wire ch_inc_op = 0; + wire ch_NOT_inc_op = 0; + + wire cht1 = 0; + wire cht2 = 0; + wire cht3 = 0; + wire cht3a = 0; + wire cht4 = 0; + wire cht4a = 0; + wire cht5 = 0; + wire cht6 = 0; + wire cht7 = 0; + wire cht8 = 0; + wire cht8a = 0; + wire cht8b = 0; + wire cht9 = 0; + + /* + * LC + */ + reg lcf1; + + wire lct0 = 0; + wire lct0a = 0; + + /* + * DC + */ + reg dcf1; + wire ch_dep = 0; + + wire dct0 = 0; + wire dct0a = 0; + wire dct0b = 0; + wire dct1 = 0; + wire dct2 = 0; + wire dct3 = 0; + + /* + * SH + */ + reg shf1; + wire shift_op = 0; + wire sh_ac_2 = 0; + + wire sht0 = 0; + wire sht1 = 0; + wire sht1a = 0; + + /* + * MP + */ + reg mpf1; + wire mp_clr = 0; + + wire mpt0 = 0; + wire mpt0a = 0; + wire mpt1 = 0; + wire mpt2 = 0; + + /* + * FA + */ + reg faf1; + reg faf2; + reg faf3; + reg faf4; + + wire fat0 = 0; + wire fat1 = 0; + wire fat1a = 0; + wire fat1b = 0; + wire fat2 = 0; + wire fat3 = 0; + wire fat4 = 0; + wire fat5 = 0; + wire fat5a = 0; + wire fat6 = 0; + wire fat7 = 0; + wire fat8 = 0; + wire fat8a = 0; + wire fat9 = 0; + wire fat10 = 0; + + /* + * FM + */ + reg fmf1; + reg fmf2; + + wire fmt0 = 0; + wire fmt0a = 0; + wire fmt0b = 0; + + /* + * FD + */ + reg fdf1; + reg fdf2; + + wire fdt0 = 0; + wire fdt0a = 0; + wire fdt0b = 0; + wire fdt1 = 0; + + /* + * FP + */ + reg fpf1; + reg fpf2; + wire fp_ar0_xor_fmf1 = 0; + wire fp_ar0_xor_mb0_xor_fmf1 = 0; + wire fp_mb0_eq_fmf1 = 0; + + wire fpt0 = 0; + wire fpt01 = 0; + wire fpt1 = 0; + wire fpt1a = 0; + wire fpt1aa = 0; + wire fpt1b = 0; + wire fpt2 = 0; + wire fpt3 = 0; + wire fpt4 = 0; + + /* + * MS + */ + reg msf1; + wire ms_mult = 0; + + wire mst1 = 0; + wire mst2 = 0; + wire mst3 = 0; + wire mst3a = 0; + wire mst4 = 0; + wire mst5 = 0; + wire mst6 = 0; + + /* + * DS + */ + reg dsf1; + reg dsf2; + reg dsf3; + reg dsf4; + reg dsf5; + reg dsf6; + reg dsf7; + reg dsf8; + reg dsf9; + wire ds_div = 0; + wire ds_divi = 0; + wire ds_clr = 0; + wire dsf7_xor_mq0 = 0; + + wire dst0 = 0; + wire dst0a = 0; + wire dst1 = 0; + wire dst2 = 0; + wire dst3 = 0; + wire dst4 = 0; + wire dst5 = 0; + wire dst6 = 0; + wire dst7 = 0; + wire dst8 = 0; + wire dst9 = 0; + wire dst10 = 0; + wire dst10a = 0; + wire dst10b = 0; + wire dst11 = 0; + wire dst11a = 0; + wire dst12 = 0; + wire dst13 = 0; + wire dst14 = 0; + wire dst14a = 0; + wire dst14b = 0; + wire dst15 = 0; + wire dst16 = 0; + wire dst17 = 0; + wire dst17a = 0; + wire dst18 = 0; + wire dst19 = 0; + wire dst20 = 0; + wire dst21 = 0; + wire dst21a = 0; + + wire ds_div_t0 = 0; + + /* + * NR + */ + reg nrf1; + reg nrf2; + reg nrf3; + wire nr_ar9_eq_ar0 = 0; + wire nr_round = 0; + wire nr_ar_eq_0_AND_mq1_0; + + wire nrt05 = 0; + wire nrt0 = 0; + wire nrt01 = 0; + wire nrt1 = 0; + wire nrt2 = 0; + wire nrt3 = 0; + wire nrt31 = 0; + wire nrt4 = 0; + wire nrt5 = 0; + wire nrt5a = 0; + wire nrt6 = 0; + + /* + * MA + */ reg [18:35] ma; - reg en_cry; reg ma32_cry_out; + wire ma_clr = it0 | at0 | at3 | ft4a | key_ma_clr | iot_t0a | + et1 & ma_clr_et1 | + et9 & ma_reset_et9 | + st3 & ~s_ac_inh | + ft1a & ~f_ac_2; + wire ma_inc = st6 | key_ma_inc | uuo_t1 | + ft1a & f_ac_2 | + it1 & pi_ov; + wire ma_fm_mbrt1 = 0; + wire ma_fm_pc1 = 0; + wire ma31_cry_in_en = ~s_ac_2 & ~f_ac_2; - initial - en_cry = 0; + wire ma_eq_mas = ma == mas; + wire ma18_31_eq_0 = ma[18:31] == 0; + wire ma_fmc_select = ~key_rim_sbr & ma18_31_eq_0; + wire ma_fm_mbrt_et3 = 0; + wire ma_clr_et1 = 0; + wire ma_reset_et9 = 0; + wire ma_fm_14_17 = 0; + wire ma_fm_9_12 = 0; + wire ma_fm_pich = 0; always @(posedge clk) begin if(ma_clr) ma <= 0; if(ma_inc) begin {ma32_cry_out, ma[32:35]} = ma[32:35]+1; - ma[18:31] = ma[18:31] + (ma32_cry_out & en_cry); + ma[18:31] = ma[18:31] + (ma32_cry_out & ma31_cry_in_en); end if(key_ma_fm_masw1) ma <= ma | mas; end -endmodule -module apr( - input clk, - input key_start, - input key_read_in, - input key_inst_cont, - input key_mem_cont, - input key_inst_stop, - input key_mem_stop, - input key_exec, - input key_ioreset, - input key_dep, - input key_dep_nxt, - input key_ex, - input key_ex_nxt, - input sw_addr_stop, - input sw_mem_disable, - input sw_repeat, - input sw_power, - input sw_rim_maint, - output [0:35] mi, - input [18:35] mas, - input [0:35] datasw, + /* + * PR + */ + reg [18:25] pr; + wire pr18_ok = ma[18:25] <= pr; + wire pr_rel_AND_ma_ok = ~ex_inh_rel & pr18_ok; + wire pr_rel_AND_NOT_ma_ok = ~ex_inh_rel & ~pr18_ok; - output membus_mc_wr_rs, - output membus_mc_rq_cyc, - output membus_mc_rd_rq, - output membus_mc_wr_rq, - output [21:35] membus_ma, - output [18:21] membus_sel, - output membus_fmc_select, - output [0:35] membus_mb_out, - - input membus_mai_cmc_addr_ack, - input membus_mai_cmc_rd_rs, - input [0:35] membus_mb_in -); - - reg run; - reg [0:35] mi; - wire [18:35] ma; - wire [18:35] pc; - wire [0:35] ar; - wire [0:35] mb; - wire [0:35] mbN_clr; - wire [0:35] mbN_set; - - // TMP - assign st7 = 0; - - /****** - * MA * - ******/ - - ma_reg ma_reg( - .clk(clk), - .ma_clr(ma_clr), - .ma_inc(ma_inc), - .key_ma_fm_masw1(key_ma_fm_masw1), - .mas(mas), - .pc(pc), - .ma(ma)); - assign ma_inc = key_ma_inc; - assign ma_clr = key_ma_clr; - - /****** - * PC * - ******/ - - pc_reg pc_reg( - .clk(clk), - .pc_clr(pc_clr), - .pc_inc(pc_inc), - .pc_fm_ma1(pc_fm_ma1), - .ma(ma), - .pc(pc)); - assign pc_clr = kt1 & key_start_OR_read_in; - assign pc_fm_ma1 = kt3 & key_start_OR_read_in; - - /****** - * AR * - ******/ - - ar_reg ar_reg( - .clk(clk), - .arlt_clr(arlt_clr), - .arrt_clr(arrt_clr), - .arlt_fm_mb0(arlt_fm_mb0), - .arrt_fm_mb0(arrt_fm_mb0), - .arlt_fm_mb1(arlt_fm_mb1), - .arrt_fm_mb1(arrt_fm_mb1), - .arlt_fm_datasw1(arlt_fm_datasw1), - .arrt_fm_datasw1(arrt_fm_datasw1), - .mb(mb), - .datasw(datasw), - .ar(ar)); - assign arlt_clr = key_ar_clr; - assign arrt_clr = key_ar_clr; - assign arlt_fm_mb0 = ar_fm_mbJ; - assign arrt_fm_mb0 = ar_fm_mbJ; - assign arlt_fm_mb1 = ar_fm_mbJ; - assign arrt_fm_mb1 = ar_fm_mbJ; - assign arlt_fm_datasw1 = key_ar_fm_datasw1; - assign arrt_fm_datasw1 = key_ar_fm_datasw1; - assign ar_fm_mbJ = mbJ_swap_arJ; - - /****** - * MB * - ******/ - - mb_reg mb_reg( - .clk(clk), - .mblt_clr(mblt_clr), - .mbrt_clr(mbrt_clr), - .mblt_fm_ar0(mblt_fm_ar0), - .mbrt_fm_ar0(mbrt_fm_ar0), - .mblt_fm_ar1(mblt_fm_ar1), - .mbrt_fm_ar1(mbrt_fm_ar1), - .mblt_fm_mbrtJ(mblt_fm_mbrtJ), - .mbrt_fm_mbltJ(mbrt_fm_mbltJ), - .mbN_clr(mbN_clr), - .mbN_set(mbN_set), - .ar(ar), - .mb(mb)); - dly100ns mbdly1(.clk(clk), .in(mc_mb_clr), .out(mc_mb_clr_dly)); - assign mb_clr = mc_mb_clr_dly; - assign mblt_clr = mb_clr; - assign mbrt_clr = mb_clr; - assign mblt_fm_ar0 = mb_fm_arJ; - assign mbrt_fm_ar0 = mb_fm_arJ; - assign mblt_fm_ar1 = mb_fm_arJ; - assign mbrt_fm_ar1 = mb_fm_arJ; - assign mbN_set = membus_mb_in & {36{mc_mb_membus_enable}}; - - assign mblt_fm_mbrtJ = 0; - assign mbrt_fm_mbltJ = 0; - assign mb_fm_arJ = key_wr; - assign mbJ_swap_arJ = 0; - - /****** - * MI * - ******/ - - assign mi_clr = (mai_rd_rs | mc_wr_rs) & ma == mas | - mc_rs_t1 & key_ex_OR_dep_nxt; - dly100ns midly0(.clk(clk), .in(mi_clr), .out(mi_fm_mb1)); - always @(posedge clk) begin - if(mi_clr) - mi <= 0; - if(mi_fm_mb1) - mi <= mi | mb; - end - - /******* - * KEY * - *******/ - - reg key_ex_st, key_dep_st, key_ex_sync, key_dep_sync; - reg key_rim_sbr; - - // KEY-1 - assign key_clr_rim = ~(key_read_in | key_mem_cont | key_inst_cont); - assign key_ma_fm_mas = key_ex_sync | key_dep_sync | - key_start_OR_read_in; - assign key_execute = key_exec & ~run; - assign key_start_OR_read_in = key_start | key_read_in; - assign key_start_OR_cont_OR_read_in = key_start_OR_read_in | - key_inst_cont; - assign key_ex_OR_dep_nxt = key_ex_nxt | key_dep_nxt; - assign key_dp_OR_dp_nxt = key_dep_sync | key_dep_nxt; - assign key_ex_OR_ex_nxt = key_ex_sync | key_ex_nxt; - assign key_ex_OR_dep_st = key_ex_st | key_dep_st; - assign key_run1_AND_NOT_ex_OR_dep = run & ~key_ex_OR_dep_st; - assign key_manual = key_ex | key_ex_nxt | key_dep | key_dep_nxt | - key_start | key_inst_cont | key_mem_cont | key_ioreset | - key_execute | key_read_in; - assign key_run_AND_ex_OR_dep = run & key_ex_OR_dep_st; - assign key_execute_OR_dp_OR_dp_nxt = key_execute | key_dp_OR_dp_nxt; - - syncpulse keysync1(clk, sw_power, mr_pwr_clr); - syncpulse keysync2(clk, key_inst_stop, run_clr); + /* + * RLR, RLA + */ + reg [18:25] rlr; + wire [18:25] rla = ma[18:25] + (ex_inh_rel ? 0 : rlr); always @(posedge clk) begin - if(mr_pwr_clr | run_clr) - run <= 0; - if(kt0a | key_go) begin - key_ex_st <= 0; - key_dep_st <= 0; - end - if(kt0a) begin - key_ex_sync <= key_ex; - key_dep_sync <= key_dep; - end - if(key_go) begin - key_ex_sync <= 0; - key_dep_sync <= 0; - run <= 1; + if(ex_clr) begin + pr <= 0; + rlr <= 0; end end + /* + * MI + */ + reg [0:35] mi; + wire milt_clr = 0; + wire milt_fm_mblt1 = 0; + wire mirt_clr = 0; + wire mirt_fm_mbrt1 = 0; - // KEY-2 - assign mr_start = mr_pwr_clr | kt1 & key_ioreset; - assign mr_clr = kt1 & key_manual & ~key_mem_cont | - mr_pwr_clr; // TODO: more - assign key_ma_clr = kt1 & key_ma_fm_mas; - assign key_ma_fm_masw1 = kt2 & key_ma_fm_mas; - assign key_ma_inc = kt1 & key_ex_OR_dep_nxt; - assign key_ar_clr = kt1 & key_execute_OR_dp_OR_dp_nxt; - assign key_ar_fm_datasw1 = kt2 & key_execute_OR_dp_OR_dp_nxt | - 0; // TODO: more - assign key_rd = kt3 & key_ex_OR_ex_nxt; - assign key_wr = kt3 & key_dp_OR_dp_nxt; + /* + * MC + */ + reg mc_rd; + reg mc_wr; + reg mc_rq; + reg mc_stop; + reg mc_stop_sync; + reg mc_split_cyc_sync; + wire mc_rd_rq_pulse; + wire mc_wr_rq_pulse; + wire mc_rdwr_rq_pulse; + wire mc_rq_pulse; + wire mc_rdwr_rs_pulse; + wire mc_split_rd_rq; + wire mc_split_wr_rq; + wire mc_mb_clr; + wire mc_rs_t0; + wire mc_rs_t1; + wire mc_wr_rs; + wire mai_addr_ack; + wire mai_rd_rs; + wire mc_addr_ack; + wire mc_non_exist_mem; + wire mc_non_exist_mem_rst; + wire mc_non_exist_rd; + wire mc_illeg_address; + wire mc_rq_set; + wire mc_stop_set = mc_rq_pulse_D2 & + (key_mem_stop | sw_addr_stop & ma_eq_mas); - syncpulse keysync3(clk, key_manual, kt0); + wire mc_membus_fm_mb1; + wire mc_mb_membus_enable = mc_rd; - assign kt0a = kt0; - dly100ns keydly1(.clk(clk), .in(kt0a), .out(key_tmp1)); - assign kt1 = kt0a & key_mem_cont | - key_tmp1 & ~run & ~key_mem_cont; // no key_mem_cont in the real hardware, why? - dly200ns keydly2(.clk(clk), .in(kt1 & ~run), .out(kt2)); - dly200ns keydly3(.clk(clk), .in(kt2), .out(kt3)); - assign kt4 = kt3 & key_execute | - key_rdwr_ret | - mc_stop_set & key_mem_cont | - st7 & key_start_OR_cont_OR_read_in; - assign key_go = kt3 & key_start_OR_cont_OR_read_in | - kt4 & key_run1_AND_NOT_ex_OR_dep; + pg mc_pg0(.clk(clk), .reset(reset), + .in(membus_addr_ack), .p(mai_addr_ack)); + pg mc_pg1(.clk(clk), .reset(reset), + .in(membus_rd_rs), .p(mai_rd_rs)); - always @(posedge clk) begin - if(kt1 & key_clr_rim) - key_rim_sbr <= 0; - if(kt1 & key_read_in | sw_rim_maint) - key_rim_sbr <= 1; - end + pa mc_pa0(.clk(clk), .reset(reset), + .in(it1 | at2 | at5 | + ft1 | ft4 | ft6 | + key_rd | uuo_t2 | mc_split_rd_rq), + .p(mc_rd_rq_pulse)); + pa mc_pa1(.clk(clk), .reset(reset), + .in(st1 | st5 | st6 | key_wr | + mblt_fm_ir1_uuo_t0 | mc_split_wr_rq | blt_t0), + .p(mc_wr_rq_pulse)); + pa mc_pa2(.clk(clk), .reset(reset), + .in(ft7 & ~mc_split_cyc_sync), + .p(mc_rdwr_rq_pulse)); + pa mc_pa3(.clk(clk), .reset(reset), + .in(mc_rdwr_rq_pulse | mc_rd_rq_pulse | mc_wr_rq_pulse), + .p(mc_rq_pulse)); + pa mc_pa4(.clk(clk), .reset(reset), + .in(st2 | iot_t0 | cht8), + .p(mc_rdwr_rs_pulse)); + pa mc_pa5(.clk(clk), .reset(reset), + .in(ft7 & mc_split_cyc_sync), + .p(mc_split_rd_rq)); + pa mc_pa6(.clk(clk), .reset(reset), + .in(mc_rdwr_rs_pulse & mc_split_cyc_sync), + .p(mc_split_wr_rq)); + pa mc_pa7(.clk(clk), .reset(reset), + .in(mc_rd_rq_pulse | mc_rdwr_rq_pulse), + .p(mc_mb_clr)); + pa mc_pa8(.clk(clk), .reset(reset), + .in(mc_rq_pulse_D3 & mc_rq & ~mc_stop), + .p(mc_non_exist_mem)); + pa mc_pa9(.clk(clk), .reset(reset), + .in(mc_non_exist_mem & ~sw_mem_disable), + .p(mc_non_exist_mem_rst)); + pa mc_pa10(.clk(clk), .reset(reset), + .in(mc_non_exist_mem_rst & mc_rd), + .p(mc_non_exist_rd)); + pa mc_pa11(.clk(clk), .reset(reset), + .in(mc_rq_pulse_D0 & ex_inh_rel | + mc_rq_pulse_D1 & pr_rel_AND_ma_ok), + .p(mc_rq_set)); + pa mc_pa12(.clk(clk), .reset(reset), + .in(mc_rq_pulse_D1 & pr_rel_AND_NOT_ma_ok), + .p(mc_illeg_address)); + pa mc_pa13(.clk(clk), .reset(reset), + .in(mai_addr_ack | mc_non_exist_mem_rst), + .p(mc_addr_ack)); + pa mc_pa14(.clk(clk), .reset(reset), + .in(mc_addr_ack & ~mc_rd & mc_wr | + mc_rdwr_rs_pulse_D & ~mc_split_cyc_sync | + kt1 & key_manual & mc_stop & mc_stop_sync & ~key_mem_cont), + .p(mc_wr_rs)); + pa mc_pa15(.clk(clk), .reset(reset), + .in(kt1 & key_mem_cont & mc_stop | + ~mc_stop & (mc_wr_rs | mai_rd_rs | mc_non_exist_rd)), + .p(mc_rs_t0)); + pa mc_pa16(.clk(clk), .reset(reset), .in(mc_rs_t0_D), .p(mc_rs_t1)); - sbr key_rdwr( - .clk(clk), - .clr(mr_clr), - .set(key_rd | key_wr), - .from(mc_rs_t1), - .ret(key_rdwr_ret)); + bd mc_bd0(.clk(clk), .reset(reset), .in(mc_wr_rs), .p(membus_wr_rs)); + bd2 mb_bd1(.clk(clk), .reset(reset), .in(mc_wr_rs), .p(mc_membus_fm_mb1)); + wire mc_rdwr_rs_pulse_D, mc_rs_t0_D; + wire mc_rq_pulse_D0, mc_rq_pulse_D1, mc_rq_pulse_D2, mc_rq_pulse_D3; + dly100ns mc_dly0(.clk(clk), .reset(reset), + .in(mc_rdwr_rs_pulse), + .p(mc_rdwr_rs_pulse_D)); + dly50ns mc_dly1(.clk(clk), .reset(reset), + .in(mc_rq_pulse), + .p(mc_rq_pulse_D0)); + dly150ns mc_dly2(.clk(clk), .reset(reset), + .in(mc_rq_pulse), + .p(mc_rq_pulse_D1)); + dly200ns mc_dly3(.clk(clk), .reset(reset), + .in(mc_rq_pulse), + .p(mc_rq_pulse_D2)); + dly100us mc_dly4(.clk(clk), .reset(reset), .in(mc_rq_pulse), + .p(mc_rq_pulse_D3)); + dly50ns mc_dly5(.clk(clk), .reset(reset), .in(mc_rs_t0), + .p(mc_rs_t0_D)); - /****** - * MC * - ******/ - - reg mc_rd, mc_wr, mc_rq, mc_stop, mc_stop_sync, mc_split_cyc_sync; - - assign mc_mb_membus_enable = mc_rd; - assign membus_mc_rq_cyc = mc_rq & (mc_rd | mc_wr); - assign membus_mc_rd_rq = mc_rd; - assign membus_mc_wr_rq = mc_wr; - assign membus_ma = {rla[21:25], ma[26:35]}; - assign membus_sel = rla[18:21]; - assign membus_fmc_select = ~key_rim_sbr & ma[18:31] == 0; - assign membus_mc_wr_rs = mc_wr_rs; - assign membus_mb_out = mc_wr_rs_b ? mb : 0; - - // pulses - assign mc_mb_clr = mc_rd_rq_pulse | - mc_rdwr_rq_pulse; - assign mc_rd_rq_pulse = key_rd; // TODO - assign mc_wr_rq_pulse = key_wr | - mc_rdwr_rs_pulse & mc_split_cyc_sync; // TODO - assign mc_split_rd_rq = 0; - assign mc_rdwr_rq_pulse = 0;//key_rd; // TODO - assign mc_rdwr_rs_pulse = 0;//key_wr; - assign mc_split_wr_rq = 0; - assign mc_rq_pulse = mc_rd_rq_pulse | - mc_wr_rq_pulse | - mc_rdwr_rq_pulse; - - dly100us mcdly1(.clk(clk), .in(mc_rq_pulse), .out(mc_tmp3)); - assign mc_non_exist_mem = mc_tmp3 & mc_rq & ~mc_stop; - assign mc_non_exist_mem_rst = mc_non_exist_mem & ~sw_mem_disable; - assign mc_non_exist_rd = mc_non_exist_mem_rst & mc_rd; - syncpulse syncmc1(.clk(clk), .in(membus_mai_cmc_addr_ack), .out(mai_addr_ack)); - assign mc_addr_ack = mai_addr_ack | mc_non_exist_mem_rst; - syncpulse syncmc2(.clk(clk), .in(membus_mai_cmc_rd_rs), .out(mai_rd_rs)); - assign mc_rs_t0 = kt1 & key_mem_cont & mc_stop | - (mc_wr_rs | mc_non_exist_rd | mai_rd_rs) & ~mc_stop; - dly50ns mcdly2(.clk(clk), .in(mc_rs_t0), .out(mc_rs_t1)); - syncpulse syncmc3(.clk(clk), .in(| membus_mb_in), .out(mb_pulse)); - assign mc_wr_rs = - kt1 & key_manual & mc_stop & mc_stop_sync & ~key_mem_cont | - mc_addr_ack & mc_wr & ~mc_rd | - mc_tmp1 & ~mc_split_cyc_sync; - pa100ns mcpa0(.clk(clk), .in(mc_wr_rs), .out(mc_wr_rs_b)); - dly100ns mcdly3(.clk(clk), .in(mc_rdwr_rs_pulse), .out(mc_tmp1)); - dly200ns mcdly4(.clk(clk), .in(mc_rq_pulse), .out(mc_tmp2)); - assign mc_stop_set = mc_tmp2 & - (key_mem_stop | ma == mas & sw_addr_stop); - dly50ns mcdly5(.clk(clk), .in(mc_rq_pulse), .out(mc_tmp4)); - dly150ns mcdly6(.clk(clk), .in(mc_rq_pulse), .out(mc_tmp5)); - assign mc_rq_set = mc_tmp4 & ex_inh_rel | - mc_tmp5 & pr_rel_AND_ma_ok; - assign mc_illeg_address = mc_tmp5 & pr_rel_AND_NOT_ma_ok; - // TODO: 100ns -> ST7 + assign membus_rq_cyc = mc_rq & (mc_rd | mc_wr); + assign membus_wr_rq = mc_wr; + assign membus_rd_rq = mc_rd; + assign membus_ma = { rla[21:25], ma[26:35] }; + assign membus_sel = rla[18:21]; + assign membus_fmc_select = ma_fmc_select; + assign membus_mb_out = mc_membus_fm_mb1 ? mb : 0; always @(posedge clk) begin if(mr_clr) begin @@ -469,97 +1233,79 @@ module apr( mc_stop <= 0; if(mc_stop_set) mc_stop <= 1; - if(mc_rdwr_rq_pulse) - mc_stop_sync <= 1; - // TODO: set mc_split_cyc_sync end /* - * Memory relocation + * IOT */ + reg iot_go; + reg iot_f0a; - reg [18:25] pr; - reg [18:25] rlr; - wire [18:25] rla; + wire iot_blki = 0; + wire iot_datai = 0; + wire iot_blko = 0; + wire iot_datao = 0; + wire iot_cono = 0; + wire iot_coni = 0; + wire iot_consz = 0; + wire iot_conso = 0; - assign rla = ma[18:25] + (ex_inh_rel ? 0 : rlr); - assign pr18ok = ma[18:25] <= pr; - assign pr_rel_AND_ma_ok = pr18ok & ~ex_inh_rel; - assign pr_rel_AND_NOT_ma_ok = ~pr18ok & ~ex_inh_rel; + wire iot_blk = 0; + wire iot_outgoing = 0; + wire iot_status = 0; + wire iot_datai_o = 0; + wire iot_init_setup = 0; + wire iot_final_setup = 0; - /****** - * EX * - ******/ + wire iot_t0 = 0; + wire iot_t0a = 0; + wire iot_t2 = 0; + wire iot_t3 = 0; + wire iot_t3a = 0; + wire iot_t4 = 0; - reg ex_user, ex_mode_sync, ex_uuo_sync, ex_pi_sync, ex_ill_op; + /* + * PIH, PIR, PIO + */ + reg [1:7] pih; + wire pih_clr = 0; + wire pih_fm_pi_ch_rq = 0; + wire pih0_fm_pi_ok1 = 0; - assign ex_inh_rel = ~ex_user | ex_pi_sync | (ma[18:31] == 0) | ex_ill_op; - assign ex_clr = mr_start | - 0; // TODO + reg [1:7] pir; + wire pir_clr = 0; + wire pir_fm_iob1 = 0; + wire pir_stb = 0; - always @(posedge clk) begin - if(mr_clr) begin - if(ex_mode_sync) - ex_user <= 1; - ex_mode_sync <= 0; - ex_uuo_sync <= 0; - if(~pi_cyc) - ex_pi_sync <= 0; - end - if(mr_start) begin - ex_user <= 0; - ex_ill_op <= 0; - end - if(ex_clr) begin - pr <= 0; - rlr <= 0; - end - end + reg [1:7] pio; + wire pi_reset = 0; + wire pio_fm_iob1 = 0; + wire pio0_fm_iob1 = 0; - /****** - * PI * - ******/ + /* + * PI + */ + reg pi_ov; + reg pi_cyc; + reg pi_active; + wire pi_sync = 0; + wire pi_rq = 0; + wire pi_enc_32 = 0; + wire pi_enc_33 = 0; + wire pi_enc_34 = 0; - reg pi_ov, pi_cyc, pi_active; - - assign pi_reset = mr_start | - 0; // TODO - - always @(posedge clk) begin - if(mr_start) begin - pi_ov <= 0; - pi_cyc <= 0; - end - if(pi_reset) - pi_active <= 0; - end - - /******* - * CPA * - *******/ - - reg cpa_iot_user, cpa_illeg_op, cpa_non_exist_mem; - reg cpa_clock_enable, cpa_clock_flag; - reg cpa_pc_chg_enable, cpa_pdl_ov; + /* + * CPA + */ + reg cpa_iot_user; + reg cpa_illeg_op; + reg cpa_non_exist_mem; + reg cpa_clock_enable; + reg cpa_clock_flag; + reg cpa_pc_chg_enable; + reg cpa_pdl_ov; reg cpa_arov_enable; reg [33:35] cpa_pia; - - always @(posedge clk) begin - if(mr_start) begin - cpa_iot_user <= 0; - cpa_illeg_op <= 0; - cpa_non_exist_mem <= 0; - cpa_clock_enable <= 0; - cpa_clock_flag <= 0; - cpa_pc_chg_enable <= 0; - cpa_pdl_ov <= 0; - cpa_arov_enable <= 0; - cpa_pia <= 0; - end - if(mc_illeg_address) - cpa_illeg_op <= 1; - if(mc_non_exist_mem) - cpa_non_exist_mem <= 1; - end + wire cpa_cono_set = 0; endmodule diff --git a/verilog/core161c.v b/verilog/core161c.v new file mode 100644 index 0000000..4136e5e --- /dev/null +++ b/verilog/core161c.v @@ -0,0 +1,315 @@ +module core161c( + input wire clk, + input wire reset, + input wire power, + input wire sw_single_step, + input wire sw_restart, + + input wire membus_wr_rs_p0, + input wire membus_rq_cyc_p0, + input wire membus_rd_rq_p0, + input wire membus_wr_rq_p0, + input wire [21:35] membus_ma_p0, + input wire [18:21] membus_sel_p0, + input wire membus_fmc_select_p0, + input wire [0:35] membus_mb_in_p0, + output wire membus_addr_ack_p0, + output wire membus_rd_rs_p0, + output wire [0:35] membus_mb_out_p0, + + input wire membus_wr_rs_p1, + input wire membus_rq_cyc_p1, + input wire membus_rd_rq_p1, + input wire membus_wr_rq_p1, + input wire [21:35] membus_ma_p1, + input wire [18:21] membus_sel_p1, + input wire membus_fmc_select_p1, + input wire [0:35] membus_mb_in_p1, + output wire membus_addr_ack_p1, + output wire membus_rd_rs_p1, + output wire [0:35] membus_mb_out_p1, + + input wire membus_wr_rs_p2, + input wire membus_rq_cyc_p2, + input wire membus_rd_rq_p2, + input wire membus_wr_rq_p2, + input wire [21:35] membus_ma_p2, + input wire [18:21] membus_sel_p2, + input wire membus_fmc_select_p2, + input wire [0:35] membus_mb_in_p2, + output wire membus_addr_ack_p2, + output wire membus_rd_rs_p2, + output wire [0:35] membus_mb_out_p2, + + input wire membus_wr_rs_p3, + input wire membus_rq_cyc_p3, + input wire membus_rd_rq_p3, + input wire membus_wr_rq_p3, + input wire [21:35] membus_ma_p3, + input wire [18:21] membus_sel_p3, + input wire membus_fmc_select_p3, + input wire [0:35] membus_mb_in_p3, + output wire membus_addr_ack_p3, + output wire membus_rd_rs_p3, + output wire [0:35] membus_mb_out_p3 +); + + /* Jumpers */ + reg [0:3] memsel_p0; + reg [0:3] memsel_p1; + reg [0:3] memsel_p2; + reg [0:3] memsel_p3; + + reg [22:35] cma; + reg cma_rd_rq; + reg cma_wr_rq; + + reg [0:35] cmb; + + reg cmc_p0_act, cmc_p1_act, cmc_p2_act, cmc_p3_act; + reg cmc_last_proc; + reg cmc_rd; + reg cmc_inhibit; + reg cmc_wr; + reg cmc_await_rq; + reg cmc_proc_rs; + reg cmc_pse_sync; + reg cmc_stop; + + reg [0:36] core[0:040000]; + + wire cyc_rq_p0 = memsel_p0 == membus_sel_p0 & + ~membus_fmc_select_p0 & membus_rq_cyc_p0; + wire cyc_rq_p1 = memsel_p1 == membus_sel_p1 & + ~membus_fmc_select_p1 & membus_rq_cyc_p1; + wire cyc_rq_p2 = memsel_p2 == membus_sel_p2 & + ~membus_fmc_select_p2 & membus_rq_cyc_p2; + wire cyc_rq_p3 = memsel_p3 == membus_sel_p3 & + ~membus_fmc_select_p3 & membus_rq_cyc_p3; + wire cmpc_p0_rq = cyc_rq_p0 & cmc_await_rq; + wire cmpc_p1_rq = cyc_rq_p1 & cmc_await_rq; + wire cmpc_p2_rq = cyc_rq_p2 & cmc_await_rq; + wire cmpc_p3_rq = cyc_rq_p3 & cmc_await_rq; + + wire wr_rs = cmc_p0_act ? membus_wr_rs_p0 : + cmc_p1_act ? membus_wr_rs_p1 : + cmc_p2_act ? membus_wr_rs_p2 : + cmc_p3_act ? membus_wr_rs_p3 : 0; + wire rq_cyc = cmc_p0_act ? membus_rq_cyc_p0 : + cmc_p1_act ? membus_rq_cyc_p1 : + cmc_p2_act ? membus_rq_cyc_p2 : + cmc_p3_act ? membus_rq_cyc_p3 : 0; + wire rd_rq = cmc_p0_act ? membus_rd_rq_p0 : + cmc_p1_act ? membus_rd_rq_p1 : + cmc_p2_act ? membus_rd_rq_p2 : + cmc_p3_act ? membus_rd_rq_p3 : 0; + wire wr_rq = cmc_p0_act ? membus_wr_rq_p0 : + cmc_p1_act ? membus_wr_rq_p1 : + cmc_p2_act ? membus_wr_rq_p2 : + cmc_p3_act ? membus_wr_rq_p3 : 0; + wire [21:35] ma = cmc_p0_act ? membus_ma_p0 : + cmc_p1_act ? membus_ma_p1 : + cmc_p2_act ? membus_ma_p2 : + cmc_p3_act ? membus_ma_p3 : 0; + wire [0:35] mb_in = cmc_p0_act ? membus_mb_in_p0 : + cmc_p1_act ? membus_mb_in_p1 : + cmc_p2_act ? membus_mb_in_p2 : + cmc_p3_act ? membus_mb_in_p3 : 0; + assign membus_addr_ack_p0 = cmc_addr_ack & cmc_p0_act; + assign membus_rd_rs_p0 = cmc_rd_rs & cmc_p0_act; + assign membus_mb_out_p0 = cmc_p0_act ? mb_out : 0; + assign membus_addr_ack_p1 = cmc_addr_ack & cmc_p1_act; + assign membus_rd_rs_p1 = cmc_rd_rs & cmc_p1_act; + assign membus_mb_out_p1 = cmc_p1_act ? mb_out : 0; + assign membus_addr_ack_p2 = cmc_addr_ack & cmc_p2_act; + assign membus_rd_rs_p2 = cmc_rd_rs & cmc_p2_act; + assign membus_mb_out_p2 = cmc_p2_act ? mb_out : 0; + assign membus_addr_ack_p3 = cmc_addr_ack & cmc_p3_act; + assign membus_rd_rs_p3 = cmc_rd_rs & cmc_p3_act; + assign membus_mb_out_p3 = cmc_p3_act ? mb_out : 0; + + wire cmc_addr_ack; + wire cmc_rd_rs; + wire [0:35] mb_out = mb_pulse_out ? core[cma] : 0; + wire cmpc_rs_strb; + + wire cmc_pwr_clr; + wire cmc_pwr_start; + wire cmc_key_restart; + wire cmc_state_clr; + wire cmc_cmb_clr; + wire cmc_strb_sa; + wire cmc_proc_rs_P; + wire mb_pulse_out; + wire mb_pulse_in; + wire cmc_wr_rs; + wire cmc_t0; + wire cmc_t1; + wire cmc_t2; + wire cmc_t4; + wire cmc_t5; + wire cmc_t6; + wire cmc_t7; + wire cmc_t8; + wire cmc_t9; + wire cmc_t9a; + wire cmc_t10; + wire cmc_t11; + wire cmc_t12; + + // power-on timing is totally wrong + + pg cmc_pg0(.clk(clk), .reset(reset), .in(power), .p(cmc_pwr_clr)); + pg cmc_pg1(.clk(clk), .reset(reset), + .in(sw_restart & cmc_stop), .p(cmc_key_restart)); + pg cmc_pg2(.clk(clk), .reset(reset), + .in(cmpc_p0_rq | cmpc_p1_rq | cmpc_p2_rq | cmpc_p3_rq), + .p(cmc_t0)); + pg cmc_pg3(.clk(clk), .reset(reset), .in(| mb_in), .p(mb_pulse_in)); + pg cmc_pg4(.clk(clk), .reset(reset), .in(wr_rs), .p(cmpc_rs_strb)); + pg cmc_pg5(.clk(clk), .reset(reset), .in(cmc_proc_rs), .p(cmc_proc_rs_P)); + pg cmc_pg6(.clk(clk), .reset(reset), .in(cmc_pse_sync & cmc_proc_rs), .p(cmc_wr_rs)); + + + pa cmc_pa0(.clk(clk), .reset(reset), .in(cmc_pwr_clr | cmc_t9a_D), .p(cmc_t12)); + pa cmc_pa1(.clk(clk), .reset(reset), .in(cmc_pwr_clr_D), .p(cmc_pwr_start)); + pa cmc_pa2(.clk(clk), .reset(reset), + .in(cmc_t9a & ~cmc_stop | cmc_pwr_start | cmc_key_restart), + .p(cmc_t10)); + pa cmc_pa3(.clk(clk), .reset(reset), .in(cmc_t10_D), .p(cmc_t11)); + pa cmc_pa4(.clk(clk), .reset(reset), + .in(cmc_t10 | ~cma_wr_rq & cmc_strb_sa_D1 | cmc_proc_rs_P), + .p(cmc_state_clr)); + pa cmc_pa5(.clk(clk), .reset(reset), + .in(cmc_t0 | cmc_strb_sa_D2 & cma_wr_rq), + .p(cmc_cmb_clr)); + pa cmc_pa6(.clk(clk), .reset(reset), .in(cmc_t0_D), .p(cmc_t1)); + pa cmc_pa7(.clk(clk), .reset(reset), .in(cmc_t1_D), .p(cmc_t2)); + pa cmc_pa8(.clk(clk), .reset(reset), .in(cmc_t2_D0), .p(cmc_t4)); + pa cmc_pa9(.clk(clk), .reset(reset), .in(cmc_t4_D), .p(cmc_t5)); + pa cmc_pa10(.clk(clk), .reset(reset), + .in(cmc_t5 & ~cma_wr_rq | cmc_wr_rs), + .p(cmc_t6)); + pa cmc_pa11(.clk(clk), .reset(reset), .in(cmc_t6_D), .p(cmc_t7)); + pa cmc_pa12(.clk(clk), .reset(reset), .in(cmc_t7_D), .p(cmc_t8)); + pa cmc_pa13(.clk(clk), .reset(reset), .in(cmc_t8_D), .p(cmc_t9)); + pa cmc_pa14(.clk(clk), .reset(reset), .in(cmc_t9_D), .p(cmc_t9a)); + pa cmc_pa15(.clk(clk), .reset(reset), + .in(cmc_t2_D1 & cma_rd_rq), + .p(cmc_strb_sa)); + + // not on schematics + bd cmc_bd0(.clk(clk), .reset(reset), .in(cmc_t1), .p(cmc_addr_ack)); + bd cmc_bd1(.clk(clk), .reset(reset), .in(cmc_strb_sa_D0), .p(cmc_rd_rs)); + bd2 cmc_bd2(.clk(clk), .reset(reset), .in(cmc_strb_sa), .p(mb_pulse_out)); + + wire cmc_pwr_clr_D; + wire cmc_t0_D, cmc_t1_D, cmc_t2_D0, cmc_t2_D1, cmc_t4_D; + wire cmc_t6_D, cmc_t7_D, cmc_t8_D, cmc_t9_D, cmc_t9a_D, cmc_t10_D; + wire cmc_strb_sa_D0, cmc_strb_sa_D1, cmc_strb_sa_D2; + dly100ns cmc_dly0(.clk(clk), .reset(reset), .in(cmc_pwr_clr), .p(cmc_pwr_clr_D)); + dly100ns cmc_dly1(.clk(clk), .reset(reset), .in(cmc_t10), .p(cmc_t10_D)); + dly200ns cmc_dly2(.clk(clk), .reset(reset), .in(cmc_t0), .p(cmc_t0_D)); + dly1us cmc_dly3(.clk(clk), .reset(reset), .in(cmc_t1), .p(cmc_t1_D)); + dly1us cmc_dly4(.clk(clk), .reset(reset), .in(cmc_t2), .p(cmc_t2_D0)); + dly200ns cmc_dly5(.clk(clk), .reset(reset), .in(cmc_t4), .p(cmc_t4_D)); + dly200ns cmc_dly6(.clk(clk), .reset(reset), .in(cmc_t6), .p(cmc_t6_D)); + dly200ns cmc_dly7(.clk(clk), .reset(reset), .in(cmc_t7), .p(cmc_t7_D)); + dly1us cmc_dly8(.clk(clk), .reset(reset), .in(cmc_t8), .p(cmc_t8_D)); + dly400ns cmc_dly9(.clk(clk), .reset(reset), .in(cmc_t9), .p(cmc_t9_D)); + dly200ns cmc_dly10(.clk(clk), .reset(reset), .in(cmc_t9a), .p(cmc_t9a_D)); + dly800ns cmc_dly11(.clk(clk), .reset(reset), .in(cmc_t2), .p(cmc_t2_D1)); + dly100ns cmc_dly12(.clk(clk), .reset(reset), + .in(cmc_strb_sa), .p(cmc_strb_sa_D0)); + dly200ns cmc_dly13(.clk(clk), .reset(reset), + .in(cmc_strb_sa), .p(cmc_strb_sa_D1)); + dly250ns cmc_dly14(.clk(clk), .reset(reset), + .in(cmc_strb_sa), .p(cmc_strb_sa_D2)); + + always @(posedge reset) begin + cmc_await_rq <= 0; + cmc_last_proc <= 0; + cmc_proc_rs <= 0; + end + + wire [0:35] corescope = core[cma]; + + always @(posedge clk) begin + if(cmc_state_clr) begin + cmc_p0_act <= 0; + cmc_p1_act <= 0; + cmc_p2_act <= 0; + cmc_p3_act <= 0; + end + if(cmc_cmb_clr) + cmb <= 0; + if(cmc_strb_sa) + cmb <= cmb | core[cma]; + if(mb_pulse_in) + cmb <= cmb | mb_in; + if(cmpc_rs_strb) + cmc_proc_rs <= 1; + if(cmc_t0) begin + cmc_await_rq <= 0; + cmc_proc_rs <= 0; + cmc_pse_sync <= 0; + cmc_stop <= 0; + cma <= 0; + cma_rd_rq <= 0; + cma_wr_rq <= 0; + + // this happens between t0 and t1 */ + if(cmpc_p0_rq) + cmc_p0_act <= 1; + else if(cmpc_p1_rq) + cmc_p1_act <= 1; + else if(cmpc_p2_rq) begin + if(~cmpc_p3_rq | cmc_last_proc) + cmc_p2_act <= 1; + end else if(cmpc_p3_rq) begin + if(~cmpc_p2_rq | ~cmc_last_proc) + cmc_p3_act <= 1; + end + end + if(cmc_t1) begin // this seems to be missing from the schematics + cma <= cma | ma; + if(rd_rq) + cma_rd_rq <= 1; + if(wr_rq) + cma_wr_rq <= 1; + end + if(cmc_t2) begin + cmc_rd <= 1; + if(cmc_p2_act) + cmc_last_proc <= 0; + if(cmc_p3_act) + cmc_last_proc <= 1; + end + if(cmc_t4) + /* As a hack zero core here */ + core[cma] <= 0; + if(cmc_t5) begin + cmc_rd <= 0; + cmc_pse_sync <= 1; + end + if(cmc_t7) begin + cmc_inhibit <= 1; + if(sw_single_step) + cmc_stop <= 1; + end + if(cmc_t8) + cmc_wr <= 1; + if(cmc_t9 & cmc_wr) + /* again a hack. core is written some time after t8. + * (cmc_wr is always set here) */ + core[cma] <= core[cma] | cmb; + if(cmc_t11) + cmc_await_rq <= 1; + if(cmc_t12) begin + cmc_rd <= 0; + cmc_inhibit <= 0; + cmc_wr <= 0; + end + end + +endmodule diff --git a/verilog/coremem.v b/verilog/coremem.v deleted file mode 100644 index 9cc4254..0000000 --- a/verilog/coremem.v +++ /dev/null @@ -1,255 +0,0 @@ -module coremem16k( - input clk, - - input mc_wr_rs_p0, - input mc_rq_cyc_p0, - input mc_rd_rq_p0, - input mc_wr_rq_p0, - input [21:35] ma_p0, - input [18:21] sel_p0, - input fmc_select_p0, - input [0:35] mb_in_p0, - output cmc_addr_ack_p0, - output cmc_rd_rs_p0, - output [0:35] mb_out_p0, - - input mc_wr_rs_p1, - input mc_rq_cyc_p1, - input mc_rd_rq_p1, - input mc_wr_rq_p1, - input [21:35] ma_p1, - input [18:21] sel_p1, - input fmc_select_p1, - input [0:35] mb_in_p1, - output cmc_addr_ack_p1, - output cmc_rd_rs_p1, - output [0:35] mb_out_p1, - - input mc_wr_rs_p2, - input mc_rq_cyc_p2, - input mc_rd_rq_p2, - input mc_wr_rq_p2, - input [21:35] ma_p2, - input [18:21] sel_p2, - input fmc_select_p2, - input [0:35] mb_in_p2, - output cmc_addr_ack_p2, - output cmc_rd_rs_p2, - output [0:35] mb_out_p2, - - input mc_wr_rs_p3, - input mc_rq_cyc_p3, - input mc_rd_rq_p3, - input mc_wr_rq_p3, - input [21:35] ma_p3, - input [18:21] sel_p3, - input fmc_select_p3, - input [0:35] mb_in_p3, - output cmc_addr_ack_p3, - output cmc_rd_rs_p3, - output [0:35] mb_out_p3 -); - - wire [21:35] ma; - wire [0:35] mb_out; - wire [0:35] mb_in; - wire cmc_power_start; - - reg power; - reg single_step_sw; - reg restart_sw; - reg [0:3] memsel_p0; - reg [0:3] memsel_p1; - reg [0:3] memsel_p2; - reg [0:3] memsel_p3; - - reg cmc_p0_act, cmc_p1_act, cmc_p2_act, cmc_p3_act; - reg cmc_last_proc; - reg cmc_aw_rq, cmc_proc_rs, cmc_pse_sync, cmc_stop; - reg cmc_rd, cmc_wr, cmc_inhibit; - reg [0:35] cmb; - reg [22:35] cma; - reg cma_rd_rq, cma_wr_rq; - reg [0:36] core[0:040000]; - - assign cyc_rq_p0 = memsel_p0 == sel_p0 & ~fmc_select_p0 & mc_rq_cyc_p0; - assign cyc_rq_p1 = memsel_p1 == sel_p1 & ~fmc_select_p1 & mc_rq_cyc_p1; - assign cyc_rq_p2 = memsel_p2 == sel_p2 & ~fmc_select_p2 & mc_rq_cyc_p2; - assign cyc_rq_p3 = memsel_p3 == sel_p3 & ~fmc_select_p3 & mc_rq_cyc_p3; - assign cmpc_p0_rq = cyc_rq_p0 & cmc_aw_rq; - assign cmpc_p1_rq = cyc_rq_p1 & cmc_aw_rq; - assign cmpc_p2_rq = cyc_rq_p2 & cmc_aw_rq; - assign cmpc_p3_rq = cyc_rq_p3 & cmc_aw_rq; - - // simulate power on - initial begin - power = 0; - cmc_aw_rq = 0; - cmc_rd = 0; - cmc_wr = 0; - single_step_sw = 0; - restart_sw = 0; - - cmc_proc_rs = 0; - cmc_pse_sync = 0; - cmc_last_proc = 0; - #500; - power = 1; - end - - // there has to be a better way.... - // from proc to mem - assign mc_wr_rs = cmc_p0_act ? mc_wr_rs_p0 : - cmc_p1_act ? mc_wr_rs_p1 : - cmc_p2_act ? mc_wr_rs_p2 : - cmc_p3_act ? mc_wr_rs_p3 : 0; - assign mc_rq_cyc = cmc_p0_act ? mc_rq_cyc_p0 : - cmc_p1_act ? mc_rq_cyc_p1 : - cmc_p2_act ? mc_rq_cyc_p2 : - cmc_p3_act ? mc_rq_cyc_p3 : 0; - assign mc_rd_rq = cmc_p0_act ? mc_rd_rq_p0 : - cmc_p1_act ? mc_rd_rq_p1 : - cmc_p2_act ? mc_rd_rq_p2 : - cmc_p3_act ? mc_rd_rq_p3 : 0; - assign mc_wr_rq = cmc_p0_act ? mc_wr_rq_p0 : - cmc_p1_act ? mc_wr_rq_p1 : - cmc_p2_act ? mc_wr_rq_p2 : - cmc_p3_act ? mc_wr_rq_p3 : 0; - assign ma = cmc_p0_act ? ma_p0 : - cmc_p1_act ? ma_p1 : - cmc_p2_act ? ma_p2 : - cmc_p3_act ? ma_p3 : 0; - assign mb_in = cmc_p0_act ? mb_in_p0 : - cmc_p1_act ? mb_in_p1 : - cmc_p2_act ? mb_in_p2 : - cmc_p3_act ? mb_in_p3 : 0; - - // from mem to proc - assign cmc_addr_ack_p0 = cmc_addr_ack & cmc_p0_act; - assign cmc_rd_rs_p0 = cmc_rd_rs & cmc_p0_act; - assign mb_out_p0 = cmc_p0_act ? mb_out : 0; - assign cmc_addr_ack_p1 = cmc_addr_ack & cmc_p1_act; - assign cmc_rd_rs_p1 = cmc_rd_rs & cmc_p1_act; - assign mb_out_p1 = cmc_p1_act ? mb_out : 0; - assign cmc_addr_ack_p2 = cmc_addr_ack & cmc_p2_act; - assign cmc_rd_rs_p2 = cmc_rd_rs & cmc_p2_act; - assign mb_out_p2 = cmc_p2_act ? mb_out : 0; - assign cmc_addr_ack_p3 = cmc_addr_ack & cmc_p3_act; - assign cmc_rd_rs_p3 = cmc_rd_rs & cmc_p3_act; - assign mb_out_p3 = cmc_p3_act ? mb_out : 0; - - syncpulse synccmc0(.clk(clk), .in(cmc_aw_rq & mc_rq_cyc), .out(cmc_t0)); - syncpulse synccmc2(.clk(clk), .in(mc_wr_rs), .out(mc_wr_rs_S)); - - dly200ns cmcdly1(.clk(clk), .in(cmc_t0), .out(cmc_t1)); - assign cmc_addr_ack = cmc_t1; - dly1000ns cmcdly2(.clk(clk), .in(cmc_t1), .out(cmc_t2)); - dly1000ns cmcdly3(.clk(clk), .in(cmc_t2), .out(cmc_t4)); - dly200ns cmcdly4(.clk(clk), .in(cmc_t4), .out(cmc_t5)); - assign cmc_t6 = cmc_t5 & ~cma_wr_rq | cmc_tmp4; - dly200ns cmcdly9(.clk(clk), .in(cmc_t6), .out(cmc_t7)); - dly200ns cmcdly10(.clk(clk), .in(cmc_t7), .out(cmc_t8)); - dly1000ns cmcdly11(.clk(clk), .in(cmc_t8), .out(cmc_t9)); - dly400ns cmcdly12(.clk(clk), .in(cmc_t9), .out(cmc_t9a)); - assign cmc_t10 = cmc_t9a & ~cmc_stop | cmc_pwr_start; - dly100ns cmcdly13(.clk(clk), .in(cmc_t10), .out(cmc_t11)); - dly200ns cmcdly14(.clk(clk), .in(cmc_t9a), .out(cmc_t12)); - dly800ns cmcdly5(.clk(clk), .in(cmc_t2), .out(cmc_tmp1)); - assign cmc_strb_sa = cmc_tmp1 & cma_rd_rq; - dly100ns cmcdly6(.clk(clk), .in(cmc_strb_sa), .out(cmc_rd_rs)); - dly250ns cmcdly7(.clk(clk), .in(cmc_strb_sa), .out(cmc_tmp2)); - dly200ns cmcdly8(.clk(clk), .in(cmc_strb_sa), .out(cmc_tmp3)); - assign cmc_cmb_clr = cmc_t0 | cmc_tmp2 & cma_wr_rq; - assign cmc_state_clr = cmc_tmp3 & ~cma_wr_rq | cmc_t10 | cmc_proc_rs1; - syncpulse synccmc1(.clk(clk), .in(| mb_in), .out(mb_pulse)); - syncpulse synccmc3(.clk(clk), .in(cmc_proc_rs & cmc_pse_sync), .out(cmc_tmp4)); - syncpulse synccmc4(.clk(clk), .in(cmc_proc_rs), .out(cmc_proc_rs1)); - syncpulse synccmc5(.clk(clk), .in(power), .out(cmc_pwr_start)); - - // generate a longer pulse so processor has time to read - pa100ns cmcpa0(.clk(clk), .in(cmc_strb_sa), .out(cmc_strb_sa_b)); - assign mb_out = cmc_strb_sa_b ? core[cma] : 0; - - wire [0:35] corescope; - assign corescope = core[cma]; - - always @(posedge clk) begin - if(cmc_power_start) - cmc_aw_rq <= 1; - if(cmc_aw_rq) begin - if(cmpc_p0_rq) - cmc_p0_act <= 1; - else if(cmpc_p1_rq) - cmc_p1_act <= 1; - else if(cmpc_p2_rq) begin - if(~cmpc_p3_rq | cmc_last_proc) - cmc_p2_act <= 1; - end else if(cmpc_p3_rq) begin - if(~cmpc_p2_rq | ~cmc_last_proc) - cmc_p3_act <= 1; - end - end - if(cmc_state_clr) begin - cmc_p0_act <= 0; - cmc_p1_act <= 0; - cmc_p2_act <= 0; - cmc_p3_act <= 0; - end - if(cmc_t0) begin - cmc_aw_rq <= 0; - cmc_proc_rs <= 0; - cmc_pse_sync <= 0; - cmc_stop <= 0; - cma <= 0; - cma_rd_rq <= 0; - cma_wr_rq <= 0; - end - if(cmc_t1) begin - cma <= cma | ma_p0[22:35]; - if(mc_rd_rq) - cma_rd_rq <= 1; - if(mc_wr_rq) - cma_wr_rq <= 1; - end - if(cmc_t2) begin - cmc_rd <= 1; - if(cmc_p2_act) - cmc_last_proc <= 0; - if(cmc_p3_act) - cmc_last_proc <= 1; - end - if(cmc_t5) begin - // this is hack, normally core should be cleared - // roughly at the time of cmc_strb_sa, which is - // however does not happen on a write - core[cma] <= 0; - cmc_rd <= 0; - cmc_pse_sync <= 1; - end - if(cmc_t7) - cmc_inhibit <= 1; // totally useless - if(cmc_t8) - cmc_wr <= 1; - if(cmc_t9 & cmc_wr) - // again a hack, core is written some time after T8 - // ...and we know cmc_wr is set then anway. - core[cma] <= core[cma] | cmb; - if(cmc_t11) - cmc_aw_rq <= 1; - if(cmc_t12) begin - cmc_rd <= 0; - cmc_wr <= 0; - cmc_inhibit <= 0; - end - if(mc_wr_rs_S) - cmc_proc_rs <= 1; - if(cmc_strb_sa) begin - cmb <= mb_out; - end - if(cmc_cmb_clr) - cmb <= 0; - if(mb_pulse) - cmb <= cmb | mb_in; - end - -endmodule diff --git a/verilog/fast162.v b/verilog/fast162.v new file mode 100644 index 0000000..8df571b --- /dev/null +++ b/verilog/fast162.v @@ -0,0 +1,234 @@ +module fast162( + input wire clk, + input wire reset, + input wire power, + input wire sw_single_step, + input wire sw_restart, + + input wire membus_wr_rs_p0, + input wire membus_rq_cyc_p0, + input wire membus_rd_rq_p0, + input wire membus_wr_rq_p0, + input wire [21:35] membus_ma_p0, + input wire [18:21] membus_sel_p0, + input wire membus_fmc_select_p0, + input wire [0:35] membus_mb_in_p0, + output wire membus_addr_ack_p0, + output wire membus_rd_rs_p0, + output wire [0:35] membus_mb_out_p0, + + input wire membus_wr_rs_p1, + input wire membus_rq_cyc_p1, + input wire membus_rd_rq_p1, + input wire membus_wr_rq_p1, + input wire [21:35] membus_ma_p1, + input wire [18:21] membus_sel_p1, + input wire membus_fmc_select_p1, + input wire [0:35] membus_mb_in_p1, + output wire membus_addr_ack_p1, + output wire membus_rd_rs_p1, + output wire [0:35] membus_mb_out_p1, + + input wire membus_wr_rs_p2, + input wire membus_rq_cyc_p2, + input wire membus_rd_rq_p2, + input wire membus_wr_rq_p2, + input wire [21:35] membus_ma_p2, + input wire [18:21] membus_sel_p2, + input wire membus_fmc_select_p2, + input wire [0:35] membus_mb_in_p2, + output wire membus_addr_ack_p2, + output wire membus_rd_rs_p2, + output wire [0:35] membus_mb_out_p2, + + input wire membus_wr_rs_p3, + input wire membus_rq_cyc_p3, + input wire membus_rd_rq_p3, + input wire membus_wr_rq_p3, + input wire [21:35] membus_ma_p3, + input wire [18:21] membus_sel_p3, + input wire membus_fmc_select_p3, + input wire [0:35] membus_mb_in_p3, + output wire membus_addr_ack_p3, + output wire membus_rd_rs_p3, + output wire [0:35] membus_mb_out_p3 +); + + /* Jumpers */ + reg [0:3] memsel_p0; + reg [0:3] memsel_p1; + reg [0:3] memsel_p2; + reg [0:3] memsel_p3; + reg fmc_p0_sel; + reg fmc_p1_sel; + reg fmc_p2_sel; + reg fmc_p3_sel; + + reg fmc_act; + reg fmc_rd0; + reg fmc_rs; + reg fmc_stop; + reg fmc_wr; + wire [0:35] fm_out = (fma != 0 | fmc_rd0) ? ff[fma] : 0; + reg [0:35] ff[0:16]; + + wire wr_rs = fmc_p0_sel ? membus_wr_rs_p0 : + fmc_p1_sel ? membus_wr_rs_p1 : + fmc_p2_sel ? membus_wr_rs_p2 : + fmc_p3_sel ? membus_wr_rs_p3 : 0; + wire rq_cyc = fmc_p0_sel ? membus_rq_cyc_p0 : + fmc_p1_sel ? membus_rq_cyc_p1 : + fmc_p2_sel ? membus_rq_cyc_p2 : + fmc_p3_sel ? membus_rq_cyc_p3 : 0; + wire fma_rd_rq = fmc_p0_sel ? membus_rd_rq_p0 : + fmc_p1_sel ? membus_rd_rq_p1 : + fmc_p2_sel ? membus_rd_rq_p2 : + fmc_p3_sel ? membus_rd_rq_p3 : 0; + wire fma_wr_rq = fmc_p0_sel ? membus_wr_rq_p0 : + fmc_p1_sel ? membus_wr_rq_p1 : + fmc_p2_sel ? membus_wr_rq_p2 : + fmc_p3_sel ? membus_wr_rq_p3 : 0; + wire [21:35] fma = fmc_p0_sel ? membus_ma_p0[32:35] : + fmc_p1_sel ? membus_ma_p1[32:35] : + fmc_p2_sel ? membus_ma_p2[32:35] : + fmc_p3_sel ? membus_ma_p3[32:35] : 0; + wire [0:35] mb_in = fmc_p0_sel ? membus_mb_in_p0 : + fmc_p1_sel ? membus_mb_in_p1 : + fmc_p2_sel ? membus_mb_in_p2 : + fmc_p3_sel ? membus_mb_in_p3 : 0; + assign membus_addr_ack_p0 = fmc_addr_ack & fmc_p0_sel; + assign membus_rd_rs_p0 = fmc_rd_rs & fmc_p0_sel; + assign membus_mb_out_p0 = fmc_p0_sel ? mb_out : 0; + assign membus_addr_ack_p1 = fmc_addr_ack & fmc_p1_sel; + assign membus_rd_rs_p1 = fmc_rd_rs & fmc_p1_sel; + assign membus_mb_out_p1 = fmc_p1_sel ? mb_out : 0; + assign membus_addr_ack_p2 = fmc_addr_ack & fmc_p2_sel; + assign membus_rd_rs_p2 = fmc_rd_rs & fmc_p2_sel; + assign membus_mb_out_p2 = fmc_p2_sel ? mb_out : 0; + assign membus_addr_ack_p3 = fmc_addr_ack & fmc_p3_sel; + assign membus_rd_rs_p3 = fmc_rd_rs & fmc_p3_sel; + assign membus_mb_out_p3 = fmc_p3_sel ? mb_out : 0; + + wire fmc_addr_ack; + wire fmc_rd_rs; + wire [0:35] mb_out = fmc_rd_strb ? fm_out : 0; + + wire fmc_p0_sel1 = fmc_p0_sel & ~fmc_stop; + wire fmc_p1_sel1 = fmc_p1_sel & ~fmc_stop; + wire fmc_p2_sel1 = fmc_p2_sel & ~fmc_stop; + wire fmc_p3_sel1 = fmc_p3_sel & ~fmc_stop; + wire fmc_p0_wr_sel = fmc_p0_sel & fmc_act & ~fma_rd_rq; + wire fmc_p1_wr_sel = fmc_p1_sel & fmc_act & ~fma_rd_rq; + wire fmc_p2_wr_sel = fmc_p2_sel & fmc_act & ~fma_rd_rq; + wire fmc_p3_wr_sel = fmc_p3_sel & fmc_act & ~fma_rd_rq; + wire fmpc_p0_rq = fmc_p0_sel1 & memsel_p0 == membus_sel_p0 & + membus_fmc_select_p0 & membus_rq_cyc_p0; + wire fmpc_p1_rq = fmc_p1_sel1 & memsel_p1 == membus_sel_p1 & + membus_fmc_select_p1 & membus_rq_cyc_p1; + wire fmpc_p2_rq = fmc_p2_sel1 & memsel_p2 == membus_sel_p2 & + membus_fmc_select_p2 & membus_rq_cyc_p2; + wire fmpc_p3_rq = fmc_p3_sel1 & memsel_p3 == membus_sel_p3 & + membus_fmc_select_p3 & membus_rq_cyc_p3; + + wire fmc_pwr_on; + wire fmc_restart; + wire fmc_start; + wire fmc_rd_strb; + wire fmct0; + wire fmct1; + wire fmct3; + wire fmct4; + wire fmct5; + + wire fm_clr; + wire fmc_wr_set; + wire fmc_wr_rs; + wire fma_rd_rq_P, fma_rd_rq_D, fmc_rd0_set; + wire fmct1_D, fmct3_D; + wire mb_pulse_in; + + pg fmc_pg0(.clk(clk), .reset(reset), .in(power), .p(fmc_pwr_on)); + pg fmc_pg1(.clk(clk), .reset(reset), .in(sw_restart & fmc_stop), + .p(fmc_restart)); + pg fmc_pg2(.clk(clk), .reset(reset), .in(fmc_act), .p(fmct0)); + pg fmc_pg3(.clk(clk), .reset(reset), .in(fma_rd_rq), .p(fma_rd_rq_P)); + pg cmc_pg4(.clk(clk), .reset(reset), .in(| mb_in), .p(mb_pulse_in)); + pg cmc_pg5(.clk(clk), .reset(reset), .in(wr_rs), .p(fmc_wr_rs)); + + pa fmc_pa0(.clk(clk), .reset(reset), + .in(fmc_start | fmct4 & ~fmc_stop), + .p(fmct5)); + pa fmc_pa1(.clk(clk), .reset(reset), + .in(fmct0 & fma_rd_rq), + .p(fmct1)); + pa fmc_pa2(.clk(clk), .reset(reset), + .in(fma_rd_rq_D), + .p(fmc_rd0_set)); + pa fmc_pa3(.clk(clk), .reset(reset), + .in(fmct3), + .p(fm_clr)); + pa fmc_pa4(.clk(clk), .reset(reset), + .in(fmct3_D), + .p(fmc_wr_set)); + pg fmc_pg5(.clk(clk), .reset(reset), + .in(fmct0 & ~fma_rd_rq & fma_wr_rq | + fmct1_D & fma_wr_rq), + .p(fmct3)); + pa fmc_pa6(.clk(clk), .reset(reset), + .in(fmct1_D & ~fma_wr_rq | fmc_wr_rs), + .p(fmct4)); + + dly200ns fmc_dly0(.clk(clk), .reset(reset), + .in(fmc_restart | fmc_pwr_on), + .p(fmc_start)); + dly50ns fmc_dly1(.clk(clk), .reset(reset), + .in(fma_rd_rq_P), + .p(fma_rd_rq_D)); + dly100ns fmc_dly3(.clk(clk), .reset(reset), + .in(fmct1), + .p(fmct1_D)); + dly50ns fmc_dly4(.clk(clk), .reset(reset), + .in(fmct3), + .p(fmct3_D)); + + bd fmc_bd0(.clk(clk), .reset(reset), .in(fmct0), .p(fmc_addr_ack)); + bd fmc_bd1(.clk(clk), .reset(reset), .in(fmct1), .p(fmc_rd_rs)); + bd2 fmc_bd2(.clk(clk), .reset(reset), .in(fmct1), .p(fmc_rd_strb)); + + always @(posedge reset) begin + fmc_act <= 0; + end + + always @(posedge clk) begin + if(fmc_restart | fmc_pwr_on) begin + fmc_act <= 0; + fmc_stop <= 1; + end + if(fmpc_p0_rq | fmpc_p1_rq | fmpc_p2_rq | fmpc_p3_rq) + fmc_act <= 1; + if(fmc_wr_rs) + fmc_rs <= 1; + if(~fma_rd_rq) + fmc_rd0 <= 0; + if(fmc_rd0_set) + fmc_rd0 <= 1; + if(fmc_wr_set) + fmc_wr <= 1; + if(fm_clr) + ff[fma] <= 0; + if(mb_pulse_in & fmc_wr) + ff[fma] <= ff[fma] | mb_in; + if(fmct0) begin + fmc_rs <= 0; + fmc_stop <= sw_single_step; + end + if(fmct4) begin + fmc_act <= 0; + fmc_rd0 <= 0; + end + if(fmct5) begin + fmc_stop <= 0; + fmc_wr <= 0; + end + end +endmodule diff --git a/verilog/fastmem.v b/verilog/fastmem.v deleted file mode 100644 index 278cd49..0000000 --- a/verilog/fastmem.v +++ /dev/null @@ -1,195 +0,0 @@ -module fastmem( - input clk, - - input mc_wr_rs_p0, - input mc_rq_cyc_p0, - input mc_rd_rq_p0, - input mc_wr_rq_p0, - input [21:35] ma_p0, - input [18:21] sel_p0, - input fmc_select_p0, - input [0:35] mb_in_p0, - output cmc_addr_ack_p0, - output cmc_rd_rs_p0, - output [0:35] mb_out_p0, - - input mc_wr_rs_p1, - input mc_rq_cyc_p1, - input mc_rd_rq_p1, - input mc_wr_rq_p1, - input [21:35] ma_p1, - input [18:21] sel_p1, - input fmc_select_p1, - input [0:35] mb_in_p1, - output cmc_addr_ack_p1, - output cmc_rd_rs_p1, - output [0:35] mb_out_p1, - - input mc_wr_rs_p2, - input mc_rq_cyc_p2, - input mc_rd_rq_p2, - input mc_wr_rq_p2, - input [21:35] ma_p2, - input [18:21] sel_p2, - input fmc_select_p2, - input [0:35] mb_in_p2, - output cmc_addr_ack_p2, - output cmc_rd_rs_p2, - output [0:35] mb_out_p2, - - input mc_wr_rs_p3, - input mc_rq_cyc_p3, - input mc_rd_rq_p3, - input mc_wr_rq_p3, - input [21:35] ma_p3, - input [18:21] sel_p3, - input fmc_select_p3, - input [0:35] mb_in_p3, - output cmc_addr_ack_p3, - output cmc_rd_rs_p3, - output [0:35] mb_out_p3 -); - wire [0:35] mb_out; - wire [0:35] mb_in; - - reg power; - reg single_step_sw; - reg restart_sw; - reg [0:3] memsel_p0; - reg [0:3] memsel_p1; - reg [0:3] memsel_p2; - reg [0:3] memsel_p3; - reg fmc_p0_sel; - reg fmc_p1_sel; - reg fmc_p2_sel; - reg fmc_p3_sel; - - reg fmc_act, fmc_rd0, fmc_rs, fmc_stop, fmc_wr; - reg [0:35] ff[0:16]; - wire [32:35] fma; - wire fma_rd_rq, fma_wr_rq; - wire [0:35] fm_out; - - // simulate power on - initial begin - power = 0; - single_step_sw = 0; - restart_sw = 0; - #500 power = 1; - end - - assign fma = fmc_p0_sel ? ma_p0[32:35] : - fmc_p1_sel ? ma_p1[32:35] : - fmc_p2_sel ? ma_p2[32:35] : - fmc_p3_sel ? ma_p3[32:35] : 0; - assign mb_in = fmc_p0_sel ? mb_in_p0 : - fmc_p1_sel ? mb_in_p1 : - fmc_p2_sel ? mb_in_p2 : - fmc_p3_sel ? mb_in_p3 : 0; - assign fmc_wr_rs = fmc_p0_sel ? mc_wr_rs_p0 : - fmc_p1_sel ? mc_wr_rs_p1 : - fmc_p2_sel ? mc_wr_rs_p2 : - fmc_p3_sel ? mc_wr_rs_p3 : 0; - assign fma_rd_rq = fmc_p0_sel ? mc_rd_rq_p0 : - fmc_p1_sel ? mc_rd_rq_p1 : - fmc_p2_sel ? mc_rd_rq_p2 : - fmc_p3_sel ? mc_rd_rq_p3 : 0; - assign fma_wr_rq = fmc_p0_sel ? mc_wr_rq_p0 : - fmc_p1_sel ? mc_wr_rq_p1 : - fmc_p2_sel ? mc_wr_rq_p2 : - fmc_p3_sel ? mc_wr_rq_p3 : 0; - assign cmc_addr_ack_p0 = fmc_addr_ack & fmc_p0_sel; - assign cmc_rd_rs_p0 = fmc_rd_rs & fmc_p0_sel; - assign mb_out_p0 = fmc_p0_sel ? mb_out : 0; - assign cmc_addr_ack_p1 = fmc_addr_ack & fmc_p1_sel; - assign cmc_rd_rs_p1 = fmc_rd_rs & fmc_p1_sel; - assign mb_out_p1 = fmc_p1_sel ? mb_out : 0; - assign cmc_addr_ack_p2 = fmc_addr_ack & fmc_p2_sel; - assign cmc_rd_rs_p2 = fmc_rd_rs & fmc_p2_sel; - assign mb_out_p2 = fmc_p2_sel ? mb_out : 0; - assign cmc_addr_ack_p3 = fmc_addr_ack & fmc_p3_sel; - assign cmc_rd_rs_p3 = fmc_rd_rs & fmc_p3_sel; - assign mb_out_p3 = fmc_p3_sel ? mb_out : 0; - - assign fmc_addr_ack = fmc_t0; - assign fmc_rd_rs = fmc_t1; - assign mb_out = fmc_rd_strb ? fm_out : 0; - assign fm_out = fma > 0 | fmc_rd0 ? ff[fma] : 0; - - assign fmc_p0_sel1 = fmc_p0_sel & ~fmc_stop; - assign fmc_p1_sel1 = fmc_p1_sel & ~fmc_stop; - assign fmc_p2_sel1 = fmc_p2_sel & ~fmc_stop; - assign fmc_p3_sel1 = fmc_p3_sel & ~fmc_stop; - assign fmc_p0_wr_sel = fmc_p0_sel & fmc_act & ~fma_rd_rq; - assign fmc_p1_wr_sel = fmc_p1_sel & fmc_act & ~fma_rd_rq; - assign fmc_p2_wr_sel = fmc_p2_sel & fmc_act & ~fma_rd_rq; - assign fmc_p3_wr_sel = fmc_p3_sel & fmc_act & ~fma_rd_rq; - assign fmpc_p0_rq = fmc_p0_sel1 & memsel_p0 == sel_p0 & - fmc_select_p0 & mc_rq_cyc_p0; - assign fmpc_p1_rq = fmc_p1_sel1 & memsel_p1 == sel_p1 & - fmc_select_p1 & mc_rq_cyc_p1; - assign fmpc_p2_rq = fmc_p2_sel1 & memsel_p2 == sel_p2 & - fmc_select_p2 & mc_rq_cyc_p2; - assign fmpc_p3_rq = fmc_p3_sel1 & memsel_p3 == sel_p3 & - fmc_select_p3 & mc_rq_cyc_p3; - - // Pulses - // the delays here aren't accurate, but gate delays accumulate - syncpulse syncfmc0(.clk(clk), .in(power), .out(fmc_pwr_start)); - syncpulse syncfmc1(.clk(clk), .in(fma_rd_rq), .out(fma_rd_rqD)); - dly50ns fmcdly0(.clk(clk), .in(fma_rd_rqD), .out(fmc_rd0_set)); - syncpulse syncfmc2(.clk(clk), .in(fmc_act), .out(fmc_t0)); - dly50ns fmcdly1(.clk(clk), .in(fmc_t0), .out(fmc_t0D)); - assign fmc_t1 = fmc_t0D & fma_rd_rq; - // generate a longer pulse so processor has time to read - pa100ns fmcpa0(.clk(clk), .in(fmc_t1), .out(fmc_rd_strb)); - dly100ns fmcdly2(.clk(clk), .in(fmc_t1), .out(fmc_t1D)); - assign fmc_t3 = fmc_t0D & ~fma_rd_rq & fma_wr_rq | - fmc_t1D & fma_wr_rq; - assign fmc_restart = fmc_pwr_start; - dly200ns fmcdly3(.clk(clk), .in(fmc_restart), .out(fmc_start), .level(fmc_clr)); - assign fmc_t4 = fmc_wr_rsD | fmc_t1D & ~fma_wr_rq; - dly50ns fmcdly4(.clk(clk), .in(fmc_t4), .out(fmc_t4D)); - assign fmc_t5 = fmc_start | fmc_t4D & ~fmc_stop; - - syncpulse syncfmc3(.clk(clk), .in(| mb_in), .out(fmb_in)); - syncpulse syncfmc4(.clk(clk), .in(fmc_wr_rs), .out(fmc_wr_rsS)); - dly50ns fmcdly5(.clk(clk), .in(fmc_wr_rsS), .out(fmc_wr_rsD)); - - wire [0:35] wordn; - assign wordn = ff[fma]; - - always @(posedge clk) begin - if(fmc_clr) begin - fmc_act <= 0; - fmc_stop <= 1; - end - if(fmpc_p0_rq | fmpc_p1_rq | fmpc_p2_rq | fmpc_p3_rq) - fmc_act <= 1; - if(fmc_rd0_set) - fmc_rd0 <= 1; - if(~fma_rd_rq) - fmc_rd0 <= 0; - if(fmc_t0) begin - fmc_rs <= 0; - fmc_stop <= single_step_sw; - end - if(fmc_t3) begin - fmc_wr <= 1; - ff[fma] <= 0; - end - if(fmc_t4) begin - fmc_rd0 <= 0; - fmc_act <= 0; - end - if(fmc_t5) begin - fmc_stop <= 0; - fmc_wr <= 0; - end - if(fmb_in & fmc_wr) - ff[fma] <= ff[fma] | mb_in; - if(fmc_wr_rsS) - fmc_rs <= 1; - end - -endmodule diff --git a/verilog/modules.v b/verilog/modules.v index cecc5b0..ccd9abe 100644 --- a/verilog/modules.v +++ b/verilog/modules.v @@ -1,173 +1,209 @@ -module syncpulse( +module pg( input clk, + input reset, input in, - output out + output p ); - reg x0, x1; - initial begin - x0 <= 0; - x1 <= 0; - end - always @(posedge clk) begin - x0 <= in; - x1 <= x0; - end - assign out = x0 && !x1; + reg [1:0] x; + always @(posedge clk or posedge reset) + if(reset) + x <= 0; + else + x <= { x[0], in }; + assign p = x[0] & !x[1]; endmodule -module sbr( - input clk, - input clr, - input set, - input from, - output ret -); - reg ff; - always @(posedge clk) begin - if(clr | from) - ff <= 0; - if(set) - ff <= 1; - end - assign ret = ff & from; +module pa(input clk, input reset, input in, output p); + reg p; + always @(posedge clk or posedge reset) + if(reset) + p <= 0; + else + p <= in; endmodule -module pa100ns( - input clk, - input in, - output out -); - reg [1:0] r; - initial - r <= 0; - always @(posedge clk) begin - r = r << 1; - if(in) - r = 4'b11; - end - assign out = r[1]; -endmodule - -module dly50ns( - input clk, - input in, - output out -); - reg r; - initial - r <= 0; - always @(posedge clk) - r <= {r, in}; - assign out = r; -endmodule - -module dly100ns( - input clk, - input in, - output out -); - reg [1:0] r; - initial - r <= 0; - always @(posedge clk) - r <= {r, in}; - assign out = r[1]; -endmodule - -module dly150ns( - input clk, - input in, - output out -); - reg [2:0] r; - initial - r <= 0; - always @(posedge clk) - r <= {r, in}; - assign out = r[2]; -endmodule - -module dly200ns( - input clk, - input in, - output out, - output level -); +/* +module pa100ns(input clk, input reset, input in, output p); reg [3:0] r; - initial - r <= 0; - always @(posedge clk) - r <= {r, in}; - assign out = r[3]; - assign level = (|r[2:0]); -endmodule - -module dly250ns( - input clk, - input in, - output out -); - reg [4:0] r; - initial - r <= 0; - always @(posedge clk) - r <= {r, in}; - assign out = r[4]; -endmodule - -module dly400ns( - input clk, - input in, - output out -); - reg [7:0] r; - initial - r <= 0; - always @(posedge clk) - r <= {r, in}; - assign out = r[7]; -endmodule - -module dly800ns( - input clk, - input in, - output out -); - reg [15:0] r; - initial - r <= 0; - always @(posedge clk) - r <= {r, in}; - assign out = r[15]; -endmodule - - -module dly1000ns( - input clk, - input in, - output out -); - reg [19:0] r; - initial - r <= 0; - always @(posedge clk) - r <= {r, in}; - assign out = r[19]; -endmodule - -module dly100us( - input clk, - input in, - output out -); - reg [15:0] r; - initial - r <= 0; - always @(posedge clk) begin - if(r) - r = r + 1; - if(in) - r = 1; + always @(posedge clk or posedge reset) begin + if(reset) + r <= 0; + else begin + if(r) + r <= r + 1; + if(in) + r <= 1; + end end - assign out = r == 2000; + assign p = r && r <= 10; +endmodule +*/ + +/* "bus driver", 40ns delayed pulse */ +module bd(input clk, input reset, input in, output p); + reg [2:0] r; + always @(posedge clk or posedge reset) begin + if(reset) + r <= 0; + else begin + if(r) + r <= r + 1; + if(in) + r <= 1; + end + end + assign p = r == 4; +endmodule + +/* Same as above but with longer pulse. Used to pulse mb + * because one more clock cycle is needed to get the data + * after the pulse has been synchronizes. */ +module bd2(input clk, input reset, input in, output p); + reg [2:0] r; + always @(posedge clk or posedge reset) begin + if(reset) + r <= 0; + else begin + if(r) + r <= r + 1; + if(in) + r <= 1; + end + end + assign p = r == 4 || r == 5; +endmodule + +module dly50ns(input clk, input reset, input in, output p); + reg [2:0] r; + always @(posedge clk or posedge reset) begin + if(reset) + r <= 0; + else begin + if(r) + r <= r + 1; + if(in) + r <= 1; + end + end + assign p = r == 7; +endmodule + +module dly100ns(input clk, input reset, input in, output p); + reg [3:0] r; + always @(posedge clk or posedge reset) begin + if(reset) + r <= 0; + else begin + if(r) + r <= r + 1; + if(in) + r <= 1; + end + end + assign p = r == 12; +endmodule + +module dly150ns(input clk, input reset, input in, output p); + reg [4:0] r; + always @(posedge clk or posedge reset) begin + if(reset) + r <= 0; + else begin + if(r) + r <= r + 1; + if(in) + r <= 1; + end + end + assign p = r == 17; +endmodule + +module dly200ns(input clk, input reset, input in, output p); + reg [4:0] r; + always @(posedge clk or posedge reset) begin + if(reset) + r <= 0; + else begin + if(r) + r <= r + 1; + if(in) + r <= 1; + end + end + assign p = r == 22; +endmodule + +module dly250ns(input clk, input reset, input in, output p); + reg [4:0] r; + always @(posedge clk or posedge reset) begin + if(reset) + r <= 0; + else begin + if(r) + r <= r + 1; + if(in) + r <= 1; + end + end + assign p = r == 27; +endmodule + +module dly400ns(input clk, input reset, input in, output p); + reg [5:0] r; + always @(posedge clk or posedge reset) begin + if(reset) + r <= 0; + else begin + if(r) + r <= r + 1; + if(in) + r <= 1; + end + end + assign p = r == 42; +endmodule + +module dly800ns(input clk, input reset, input in, output p); + reg [6:0] r; + always @(posedge clk or posedge reset) begin + if(reset) + r <= 0; + else begin + if(r) + r <= r + 1; + if(in) + r <= 1; + end + end + assign p = r == 82; +endmodule + +module dly1us(input clk, input reset, input in, output p); + reg [6:0] r; + always @(posedge clk or posedge reset) begin + if(reset) + r <= 0; + else begin + if(r) + r <= r + 1; + if(in) + r <= 1; + end + end + assign p = r == 102; +endmodule + +module dly100us(input clk, input reset, input in, output p); + reg [15:0] r; + always @(posedge clk or posedge reset) begin + if(reset) + r <= 0; + else begin + if(r) + r <= r + 1; + if(in) + r <= 1; + end + end + assign p = r == 10002; endmodule diff --git a/verilog/pdp6.v b/verilog/pdp6.v new file mode 100644 index 0000000..20fa7e8 --- /dev/null +++ b/verilog/pdp6.v @@ -0,0 +1,244 @@ +`default_nettype none + +module pdp6( + input wire clk, + input wire reset +); + // keys + reg key_start; + reg key_read_in; + reg key_mem_cont; + reg key_inst_cont; + reg key_mem_stop; + reg key_inst_stop; + reg key_exec; + reg key_io_reset; + reg key_dep; + reg key_dep_nxt; + reg key_ex; + reg key_ex_nxt; + + // switches + reg sw_addr_stop; + reg sw_mem_disable; + reg sw_repeat; + reg sw_power; + reg [0:35] datasw; + reg [18:35] mas; + + // maintenance switches + reg sw_rim_maint; + reg sw_repeat_bypass; + reg sw_art3_maint; + reg sw_sct_maint; + reg sw_split_cyc; + + // lights + wire [0:17] ir; + wire [0:35] mi; + wire [0:35] ar; + wire [0:35] mb; + wire [0:35] mq; + wire [18:35] pc; + wire [18:35] ma; + wire [0:8] fe; + wire [0:8] sc; + wire run; + wire mc_stop; + wire pi_active; + wire [1:7] pih; + wire [1:7] pir; + wire [1:7] pio; + wire [18:25] pr; + wire [18:25] rlr; + wire [18:25] rla; + + + /* Mem bus */ + wire membus_wr_rs_p0; + wire membus_rq_cyc_p0; + wire membus_rd_rq_p0; + wire membus_wr_rq_p0; + wire [21:35] membus_ma_p0; + wire [18:21] membus_sel_p0; + wire membus_fmc_select_p0; + wire membus_addr_ack_p0; + wire membus_rd_rs_p0; + wire [0:35] membus_mb_in_p0; + + /* Out of apr0 */ + wire [0:35] membus_mb_out_p0_p; + + /* Out of fmem0 */ + wire [0:35] membus_mb_out_p0_0; + wire membus_addr_ack_p0_0; + wire membus_rd_rs_p0_0; + + /* Out of mem0 */ + wire [0:35] membus_mb_out_p0_1; + wire membus_addr_ack_p0_1; + wire membus_rd_rs_p0_1; + + /* IO bus */ + wire iobus_iob_poweron; + wire iobus_iob_reset; + wire iobus_datao_clear; + wire iobus_datao_set; + wire iobus_cono_clear; + wire iobus_cono_set; + wire iobus_iob_fm_datai; + wire iobus_iob_fm_status; + wire [3:9] iobus_ios; + wire [0:35] iobus_iob_out; + wire [1:7] iobus_pi_req; + wire [0:35] iobus_iob_in; + + + assign membus_mb_in_p0 = membus_mb_out_p0_p | membus_mb_out_p0_0 | membus_mb_out_p0_1; + assign membus_addr_ack_p0 = membus_addr_ack_p0_0 | membus_addr_ack_p0_1; + assign membus_rd_rs_p0 = membus_rd_rs_p0_0 | membus_rd_rs_p0_1; + + + apr apr0( + .clk(clk), + .reset(reset), + + .key_start(key_start), + .key_read_in(key_read_in), + .key_mem_cont(key_mem_cont), + .key_inst_cont(key_inst_cont), + .key_mem_stop(key_mem_stop), + .key_inst_stop(key_inst_stop), + .key_exec(key_exec), + .key_io_reset(key_io_reset), + .key_dep(key_dep), + .key_dep_nxt(key_dep_nxt), + .key_ex(key_ex), + .key_ex_nxt(key_ex_nxt), + + .sw_addr_stop(sw_addr_stop), + .sw_mem_disable(sw_mem_disable), + .sw_repeat(sw_repeat), + .sw_power(sw_power), + .datasw(datasw), + .mas(mas), + + .sw_rim_maint(sw_rim_maint), + .sw_repeat_bypass(sw_repeat_bypass), + .sw_art3_maint(sw_art3_maint), + .sw_sct_maint(sw_sct_maint), + .sw_split_cyc(sw_split_cyc), + + .ir(ir), + .mi(mi), + .ar(ar), + .mb(mb), + .mq(mq), + .pc(pc), + .ma(ma), + .fe(fe), + .sc(sc), + .run(run), + .mc_stop(mc_stop), + .pi_active(pi_active), + .pih(pih), + .pir(pir), + .pio(pio), + .pr(pr), + .rlr(rlr), + .rla(rla), + + .membus_wr_rs(membus_wr_rs_p0), + .membus_rq_cyc(membus_rq_cyc_p0), + .membus_rd_rq(membus_rd_rq_p0), + .membus_wr_rq(membus_wr_rq_p0), + .membus_ma(membus_ma_p0), + .membus_sel(membus_sel_p0), + .membus_fmc_select(membus_fmc_select_p0), + .membus_mb_out(membus_mb_out_p0_p), + .membus_addr_ack(membus_addr_ack_p0), + .membus_rd_rs(membus_rd_rs_p0), + .membus_mb_in(membus_mb_in_p0), + + .iobus_iob_poweron(iobus_iob_poweron), + .iobus_iob_reset(iobus_iob_reset), + .iobus_datao_clear(iobus_datao_clear), + .iobus_datao_set(iobus_datao_set), + .iobus_cono_clear(iobus_cono_clear), + .iobus_cono_set(iobus_cono_set), + .iobus_iob_fm_datai(iobus_iob_fm_datai), + .iobus_iob_fm_status(iobus_iob_fm_status), + .iobus_ios(iobus_ios), + .iobus_iob_out(iobus_iob_out), + .iobus_pi_req(iobus_pi_req), + .iobus_iob_in(iobus_iob_in) + ); + + reg mem0_sw_single_step; + reg mem0_sw_restart; + + fast162 fmem0( + .clk(clk), + .reset(reset), + .power(sw_power), + .sw_single_step(mem0_sw_single_step), + .sw_restart(mem0_sw_restart), + + .membus_wr_rs_p0(membus_wr_rs_p0), + .membus_rq_cyc_p0(membus_rq_cyc_p0), + .membus_rd_rq_p0(membus_rd_rq_p0), + .membus_wr_rq_p0(membus_wr_rq_p0), + .membus_ma_p0(membus_ma_p0), + .membus_sel_p0(membus_sel_p0), + .membus_fmc_select_p0(membus_fmc_select_p0), + .membus_mb_in_p0(membus_mb_in_p0), + .membus_addr_ack_p0(membus_addr_ack_p0_0), + .membus_rd_rs_p0(membus_rd_rs_p0_0), + .membus_mb_out_p0(membus_mb_out_p0_0), + + .membus_rq_cyc_p1(1'b0), + .membus_sel_p1(4'b0), + .membus_fmc_select_p1(1'b0), + + .membus_rq_cyc_p2(1'b0), + .membus_sel_p2(4'b0), + .membus_fmc_select_p2(1'b0), + + .membus_rq_cyc_p3(1'b0), + .membus_sel_p3(4'b0), + .membus_fmc_select_p3(1'b0) + ); + + core161c mem0( + .clk(clk), + .reset(reset), + .power(sw_power), + .sw_single_step(mem0_sw_single_step), + .sw_restart(mem0_sw_restart), + + .membus_wr_rs_p0(membus_wr_rs_p0), + .membus_rq_cyc_p0(membus_rq_cyc_p0), + .membus_rd_rq_p0(membus_rd_rq_p0), + .membus_wr_rq_p0(membus_wr_rq_p0), + .membus_ma_p0(membus_ma_p0), + .membus_sel_p0(membus_sel_p0), + .membus_fmc_select_p0(membus_fmc_select_p0), + .membus_mb_in_p0(membus_mb_in_p0), + .membus_addr_ack_p0(membus_addr_ack_p0_1), + .membus_rd_rs_p0(membus_rd_rs_p0_1), + .membus_mb_out_p0(membus_mb_out_p0_1), + + .membus_rq_cyc_p1(1'b0), + .membus_sel_p1(4'b0), + .membus_fmc_select_p1(1'b0), + + .membus_rq_cyc_p2(1'b0), + .membus_sel_p2(4'b0), + .membus_fmc_select_p2(1'b0), + + .membus_rq_cyc_p3(1'b0), + .membus_sel_p3(4'b0), + .membus_fmc_select_p3(1'b0) + ); + +endmodule diff --git a/verilog/test.gtkw b/verilog/test.gtkw index e7c77db..593b9ec 100644 --- a/verilog/test.gtkw +++ b/verilog/test.gtkw @@ -1,303 +1,230 @@ [*] [*] GTKWave Analyzer v3.3.76 (w)1999-2016 BSI -[*] Tue Nov 8 22:00:50 2016 +[*] Sat Nov 12 18:37:06 2016 [*] -[dumpfile] "/home/aap/src/verilog/dump.vcd" -[dumpfile_mtime] "Tue Nov 8 19:25:18 2016" -[dumpfile_size] 49349 -[savefile] "/home/aap/src/verilog/test.gtkw" -[timestart] 6847 -[size] 1916 1071 +[dumpfile] "/home/aap/src/pdp6/verilog/new/dump.vcd" +[dumpfile_mtime] "Sat Nov 12 18:36:40 2016" +[dumpfile_size] 98790 +[savefile] "/home/aap/src/pdp6/verilog/new/test.gtkw" +[timestart] 0 +[size] 1920 1080 [pos] -1 -1 -*-9.999172 8463 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +*-9.650465 1200 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 [treeopen] test. -[treeopen] test.fmem0. -[sst_width] 240 -[signals_width] 293 +[treeopen] test.pdp6. +[treeopen] test.pdp6.mem0. +[sst_width] 337 +[signals_width] 442 [sst_expanded] 1 -[sst_vpaned_height] 286 +[sst_vpaned_height] 319 @28 ->-2 -test.apr.clk -@800200 ->0 --regs -@30 -test.apr.ar[0:35] -test.apr.mb[0:35] -test.apr.pc[18:35] -test.apr.ma[18:35] -test.apr.mas[18:35] -test.apr.datasw[0:35] -test.apr.mi[0:35] -test.apr.rlr[18:25] -test.apr.rla[18:25] -@28 -test.apr.pr18ok -test.apr.pr_rel_AND_ma_ok -test.apr.pr_rel_AND_NOT_ma_ok -@1000200 --regs -@800200 --general -@28 -test.apr.run -test.apr.mr_clr -test.apr.mr_start -@1000200 --general +test.clk +test.reset @c00200 --ma +-sw @28 -test.apr.ma_reg.key_ma_fm_masw1 -test.apr.ma_reg.ma_clr -test.apr.ma_reg.ma_fm_pc1 -test.apr.ma_reg.ma_inc +test.pdp6.apr0.sw_power +test.pdp6.apr0.sw_repeat +test.pdp6.apr0.sw_addr_stop +test.pdp6.apr0.sw_mem_disable +test.pdp6.apr0.sw_rim_maint +test.pdp6.apr0.sw_split_cyc +test.pdp6.apr0.sw_repeat_bypass +test.pdp6.apr0.sw_art3_maint +test.pdp6.apr0.sw_sct_maint @1401200 --ma -@c00200 --pc -@28 -test.apr.pc_clr -test.apr.pc_fm_ma1 -test.apr.pc_inc -@1401200 --pc -@c00200 --mb -@28 -test.apr.mblt_clr -test.apr.mbrt_clr -test.apr.mblt_fm_ar0 -test.apr.mbrt_fm_ar0 -test.apr.mblt_fm_ar1 -test.apr.mbrt_fm_ar1 -test.apr.mblt_fm_mbrtJ -test.apr.mbrt_fm_mbltJ -@1401200 --mb -@c00200 --ar -@28 -test.apr.arlt_clr -test.apr.arrt_clr -test.apr.arlt_fm_mb0 -test.apr.arrt_fm_mb0 -test.apr.arlt_fm_mb1 -test.apr.arrt_fm_mb1 -test.apr.arlt_fm_datasw1 -test.apr.arrt_fm_datasw1 -@1401200 --ar +-sw @c00200 -keys @28 -test.apr.key_start -test.apr.key_read_in -test.apr.key_mem_cont -test.apr.key_inst_cont -test.apr.key_mem_stop -test.apr.key_inst_stop -test.apr.key_exec -test.apr.key_ioreset -test.apr.key_dep -test.apr.key_dep_nxt -test.apr.key_ex -test.apr.key_ex_nxt +test.pdp6.key_start +test.pdp6.key_read_in +test.pdp6.key_mem_cont +test.pdp6.key_inst_cont +test.pdp6.key_mem_stop +test.pdp6.key_inst_stop +test.pdp6.key_exec +test.pdp6.key_io_reset +test.pdp6.key_dep +test.pdp6.key_dep_nxt +test.pdp6.key_ex +test.pdp6.key_ex_nxt @1401200 -keys -@c00200 --keytime -@28 -test.apr.kt0 -test.apr.kt0a -test.apr.key_tmp1 -test.apr.kt1 -test.apr.kt2 -test.apr.kt3 -test.apr.kt4 -test.apr.key_wr -test.apr.key_rd -test.apr.key_rdwr_ret -test.apr.key_go -@1401200 --keytime @800200 --EX -@28 -test.apr.ex_user -test.apr.ex_mode_sync -test.apr.ex_uuo_sync -test.apr.ex_pi_sync -test.apr.ex_ill_op -test.apr.ex_inh_rel -test.apr.ex_clr -@1000200 --EX -@800200 --MC -@28 -test.apr.mc_rd_rq_pulse -test.apr.mc_wr_rq_pulse -test.apr.mc_rdwr_rq_pulse -test.apr.mc_rdwr_rs_pulse -test.apr.mc_rq_pulse -test.apr.mc_tmp4 -test.apr.mc_tmp5 -test.apr.mc_illeg_address -test.apr.mc_non_exist_mem -test.apr.mc_non_exist_mem_rst -test.apr.mc_non_exist_rd -test.apr.mc_addr_ack -test.apr.mc_wr_rs -test.apr.mc_rs_t0 -test.apr.mc_rs_t1 -test.apr.mc_rd -test.apr.mc_mb_membus_enable -test.apr.mc_wr -test.apr.mc_rq -test.apr.mc_stop -test.apr.mc_stop_sync -test.apr.mc_split_cyc_sync -test.apr.mc_mb_clr -@1000200 --MC -@800200 --membus +-regs @30 -test.apr.membus_ma[21:35] -test.apr.membus_sel[18:21] -@28 -test.apr.membus_fmc_select -test.apr.membus_mc_rq_cyc -test.apr.membus_mc_rd_rq -test.apr.membus_mc_wr_rq -test.apr.mc_mb_membus_enable -test.apr.membus_mai_cmc_addr_ack -test.apr.membus_mai_cmc_rd_rs -test.apr.membus_mc_wr_rs -@30 -test.apr.membus_mb_in[0:35] -test.apr.membus_mb_out[0:35] -@1000200 --membus -@c00200 --mem0 -@c00030 -test.mem0.ma[21:35] -@28 -(0)test.mem0.ma[21:35] -(1)test.mem0.ma[21:35] -(2)test.mem0.ma[21:35] -(3)test.mem0.ma[21:35] -(4)test.mem0.ma[21:35] -(5)test.mem0.ma[21:35] -(6)test.mem0.ma[21:35] -(7)test.mem0.ma[21:35] -(8)test.mem0.ma[21:35] -(9)test.mem0.ma[21:35] -(10)test.mem0.ma[21:35] -(11)test.mem0.ma[21:35] -(12)test.mem0.ma[21:35] -(13)test.mem0.ma[21:35] -(14)test.mem0.ma[21:35] -@1401200 --group_end -@30 -test.mem0.mb_in[0:35] -test.mem0.mc_rq_cyc -test.mem0.mc_rd_rq -test.mem0.mc_wr_rq -test.mem0.mc_wr_rs -test.mem0.mb_out[0:35] -@28 -test.mem0.cmc_addr_ack -test.mem0.cmc_rd_rs -@30 -test.mem0.cma[22:35] -test.mem0.cma_rd_rq -test.mem0.cma_wr_rq -test.mem0.cmb[0:35] -@28 -test.mem0.cmc_p0_act -test.mem0.cmc_p1_act -test.mem0.cmc_p2_act -test.mem0.cmc_p3_act -test.mem0.cmc_last_proc -test.mem0.cmc_aw_rq -test.mem0.cmc_rd -test.mem0.cmc_wr -test.mem0.cmc_inhibit -test.mem0.cmc_pse_sync -test.mem0.cmc_proc_rs -test.mem0.cmc_pwr_start -test.mem0.mc_wr_rs -test.mem0.cmc_t0 -test.mem0.cmc_t1 -test.mem0.cmc_t2 -test.mem0.cmc_t4 -test.mem0.cmc_t5 -test.mem0.cmc_t6 -test.mem0.cmc_t7 -test.mem0.cmc_t8 -test.mem0.cmc_t9 -test.mem0.cmc_t9a -test.mem0.cmc_t10 -test.mem0.cmc_t11 -test.mem0.cmc_t12 -test.mem0.cmc_strb_sa -test.mem0.cmc_state_clr -test.mem0.cyc_rq_p0 -test.mem0.cyc_rq_p1 -test.mem0.cyc_rq_p2 -test.mem0.cyc_rq_p3 -test.mem0.cmpc_p0_rq -test.mem0.cmpc_p1_rq -test.mem0.cmpc_p2_rq -test.mem0.cmpc_p3_rq -@30 -test.mem0.corescope[0:35] -@1401200 --mem0 -@800200 --fmem0 -@28 -test.fmem0.fmc_wr_rsS -@22 -test.fmem0.fma[32:35] -@28 -test.fmem0.fma_rd_rq -test.fmem0.fma_wr_rq -test.fmem0.fmc_p0_wr_sel -test.fmem0.fmc_clr -test.fmem0.fmc_rd0 -test.fmem0.fmc_t0 -test.fmem0.fmc_t1 -test.fmem0.fmc_rd_strb -test.fmem0.fmc_t3 -test.fmem0.fmc_t4 -test.fmem0.fmc_t5 -test.fmem0.fmc_wr_rs -test.fmem0.fmc_pwr_start -test.fmem0.fmc_restart -test.fmem0.fmc_start -test.fmem0.fmc_act -test.fmem0.fmc_rd0 -test.fmem0.fmc_rs -test.fmem0.fmc_stop -test.fmem0.fmc_wr -test.fmem0.fmpc_p0_rq -test.fmem0.fmpc_p1_rq -test.fmem0.fmpc_p2_rq -test.fmem0.fmpc_p3_rq +test.pdp6.apr0.ma[18:35] +test.pdp6.apr0.pc[18:35] +test.pdp6.apr0.ir[0:17] +test.pdp6.apr0.mb[0:35] +test.pdp6.apr0.ar[0:35] +test.pdp6.apr0.mq[0:35] @31 -test.fmem0.fm_out[0:35] -@28 -test.fmem0.fmb_in -@30 -test.fmem0.mb_in[0:35] -test.fmem0.wordn[0:35] +test.pdp6.apr0.datasw[0:35] +test.pdp6.apr0.mas[18:35] @1000200 --fmem0 +-regs +@c00200 +-ex +@28 +test.pdp6.apr0.ex_clr +test.pdp6.apr0.ex_user +test.pdp6.apr0.ex_inh_rel +@1401200 +-ex +@c00200 +-key +@28 +test.pdp6.apr0.run +test.pdp6.apr0.key_rim_sbr +test.pdp6.apr0.key_rdwr +test.pdp6.apr0.mr_pwr_clr +test.pdp6.apr0.mr_start +test.pdp6.apr0.mr_clr +test.pdp6.apr0.key_dep_st +test.pdp6.apr0.key_ex_st +test.pdp6.apr0.key_ex_sync +test.pdp6.apr0.key_dep_sync +@200 +- +@28 +test.pdp6.apr0.key_ma_clr +test.pdp6.apr0.key_ma_fm_masw1 +test.pdp6.apr0.key_ma_inc +test.pdp6.apr0.key_ar_clr +test.pdp6.apr0.key_ar_fm_datasw1 +test.pdp6.apr0.key_rd +test.pdp6.apr0.key_wr +test.pdp6.apr0.kt0 +test.pdp6.apr0.kt0a +test.pdp6.apr0.kt1 +test.pdp6.apr0.kt2 +test.pdp6.apr0.kt3 +test.pdp6.apr0.kt4 +test.pdp6.apr0.key_go +test.pdp6.apr0.key_rd +test.pdp6.apr0.key_wr +test.pdp6.apr0.key_rdwr_ret +@1401200 +-key +@800200 +-mc +@28 +test.pdp6.apr0.mc_rd_rq_pulse +test.pdp6.apr0.mc_rdwr_rq_pulse +test.pdp6.apr0.mc_rdwr_rs_pulse +test.pdp6.apr0.mc_wr_rq_pulse +test.pdp6.apr0.mc_rq_pulse +test.pdp6.apr0.mc_mb_clr +test.pdp6.apr0.mc_rq_set +test.pdp6.apr0.mc_addr_ack +test.pdp6.apr0.mai_rd_rs +test.pdp6.apr0.mc_wr_rs +test.pdp6.apr0.mc_rs_t0 +test.pdp6.apr0.mc_rs_t1 +test.pdp6.apr0.mc_illeg_address +test.pdp6.apr0.mc_membus_fm_mb1 +@200 +- +@30 +test.pdp6.apr0.rlr[18:25] +test.pdp6.apr0.rla[18:25] +test.pdp6.apr0.pr[18:25] +@28 +test.pdp6.apr0.pr18_ok +@200 +- +@28 +test.pdp6.apr0.mc_rd +test.pdp6.apr0.mc_wr +test.pdp6.apr0.mc_rq +test.pdp6.apr0.mc_stop +test.pdp6.apr0.mc_stop_sync +test.pdp6.apr0.mc_split_cyc_sync +test.pdp6.apr0.mc_mb_membus_enable +@1000200 +-mc +@c00200 +-membus +@28 +test.pdp6.apr0.membus_rq_cyc +test.pdp6.apr0.membus_rd_rq +test.pdp6.apr0.membus_wr_rq +test.pdp6.apr0.membus_wr_rs +@30 +test.pdp6.apr0.membus_sel[18:21] +test.pdp6.apr0.membus_ma[21:35] +test.pdp6.apr0.membus_fmc_select +test.pdp6.apr0.membus_mb_out[0:35] +test.pdp6.apr0.membus_rd_rs +test.pdp6.apr0.membus_addr_ack +test.pdp6.apr0.membus_mb_in[0:35] +test.pdp6.apr0.mc_non_exist_mem +test.pdp6.apr0.mc_non_exist_mem_rst +test.pdp6.apr0.mc_non_exist_rd +@1401200 +-membus +@c00200 +-mem0 +@28 +test.pdp6.mem0.sw_single_step +test.pdp6.mem0.sw_restart +test.pdp6.mem0.cmc_key_restart +@200 +- +@28 +test.pdp6.mem0.cmc_await_rq +test.pdp6.mem0.cmc_rd +test.pdp6.mem0.cmc_inhibit +test.pdp6.mem0.cmc_wr +test.pdp6.mem0.cyc_rq_p0 +test.pdp6.mem0.cyc_rq_p1 +test.pdp6.mem0.cyc_rq_p2 +test.pdp6.mem0.cyc_rq_p3 +test.pdp6.mem0.cmc_p0_act +test.pdp6.mem0.cmc_p1_act +test.pdp6.mem0.cmc_p2_act +test.pdp6.mem0.cmc_p3_act +@30 +test.pdp6.mem0.cmb[0:35] +@28 +test.pdp6.apr0.membus_mb_pulse +@200 +- +@30 +test.pdp6.mem0.corescope[0:35] +test.pdp6.mem0.ma[21:35] +test.pdp6.mem0.cma[22:35] +@28 +test.pdp6.mem0.cma_rd_rq +test.pdp6.mem0.cma_wr_rq +test.pdp6.mem0.cmc_pse_sync +test.pdp6.mem0.cmc_proc_rs +test.pdp6.mem0.cmc_proc_rs_P +@200 +- +@28 +test.pdp6.mem0.cmc_pwr_clr +test.pdp6.mem0.cmc_pwr_start +test.pdp6.mem0.cmc_state_clr +test.pdp6.mem0.cmc_cmb_clr +test.pdp6.mem0.cmc_strb_sa +test.pdp6.mem0.cmc_rd_rs +test.pdp6.mem0.cmc_t0 +test.pdp6.mem0.cmc_t1 +test.pdp6.mem0.cmc_t2 +test.pdp6.mem0.cmc_t4 +test.pdp6.mem0.cmc_t5 +test.pdp6.mem0.cmc_t6 +test.pdp6.mem0.cmc_t7 +test.pdp6.mem0.cmc_t8 +test.pdp6.mem0.cmc_t9 +test.pdp6.mem0.cmc_t9a +test.pdp6.mem0.cmc_t10 +test.pdp6.mem0.cmc_t11 +test.pdp6.mem0.cmc_t12 +@1401200 +-mem0 [pattern_trace] 1 [pattern_trace] 0 diff --git a/verilog/test.v b/verilog/test.v index 39011ce..3a4695c 100644 --- a/verilog/test.v +++ b/verilog/test.v @@ -1,219 +1,121 @@ `timescale 1ns/1ns -module clock( - output clk -); - reg clk; +module clock(output reg clk); initial clk = 0; always - #25 clk = ~clk; - initial - #20000 $finish; -// #150000 $finish; - + #5 clk = ~clk; endmodule -//`define TESTKEY key_start -//`define TESTKEY key_read_in -//`define TESTKEY key_ex_nxt -`define TESTKEY key_ex -//`define TESTKEY key_dep -//`define TESTKEY key_mem_cont +//`define TESTKEY pdp6.key_inst_stop +//`define TESTKEY pdp6.key_read_in +//`define TESTKEY pdp6.key_start +//`define TESTKEY pdp6.key_exec +`define TESTKEY pdp6.key_ex +//`define TESTKEY pdp6.key_dep +//`define TESTKEY pdp6.key_mem_cont module test; - reg key_start, key_read_in; - reg key_inst_cont, key_mem_cont; - reg key_inst_stop, key_mem_stop; - reg key_exec, key_ioreset; - reg key_dep, key_dep_nxt; - reg key_ex, key_ex_nxt; - reg sw_addr_stop; - reg sw_mem_disable; - reg sw_repeat; - reg sw_power; - reg [18:35] mas; - reg [0:35] datasw; - reg sw_rim_maint; + wire clk; + reg reset; - wire [0:35] mi; - wire [21:35] ma_p0; - wire [18:21] sel_p0; - wire [0:35] mb_in_p0; - wire [0:35] mb_out_p0_p; - wire [0:35] mb_out_p0_0; - wire [0:35] mb_out_p0_1; + clock clock0(clk); + pdp6 pdp6(.clk(clk), .reset(reset)); - clock clock(.clk(clk)); - apr apr( - .clk(clk), - .key_start(key_start), - .key_read_in(key_read_in), - .key_inst_cont(key_inst_cont), - .key_mem_cont(key_mem_cont), - .key_inst_stop(key_inst_stop), - .key_mem_stop (key_mem_stop), - .key_exec(key_exec), - .key_ioreset(key_ioreset), - .key_dep(key_dep), - .key_dep_nxt(key_dep_nxt), - .key_ex(key_ex), - .key_ex_nxt(key_ex_nxt), - .sw_addr_stop(sw_addr_stop), - .sw_mem_disable(sw_mem_disable), - .sw_repeat(sw_repeat), - .sw_power(sw_power), - .sw_rim_maint(sw_rim_maint), - .mas(mas), - .datasw(datasw), - .mi(mi), - - .membus_mc_wr_rs(mc_wr_rs_p0), - .membus_mc_rq_cyc(mc_rq_cyc_p0), - .membus_mc_rd_rq(mc_rd_rq_p0), - .membus_mc_wr_rq(mc_wr_rq_p0), - .membus_ma(ma_p0), - .membus_sel(sel_p0), - .membus_fmc_select(fmc_select_p0), - .membus_mb_out(mb_out_p0_p), - - .membus_mai_cmc_addr_ack(cmc_addr_ack_p0), - .membus_mai_cmc_rd_rs(cmc_rd_rs_p0), - .membus_mb_in(mb_in_p0) - ); - - assign cmc_addr_ack_p0 = cmc_addr_ack_p0_0 | cmc_addr_ack_p0_1; - assign cmc_rd_rs_p0 = cmc_rd_rs_p0_0 | cmc_rd_rs_p0_1; - assign mb_in_p0 = mb_out_p0_p | mb_out_p0_0 | mb_out_p0_1; - - fastmem fmem0( - .clk(clk), - - .mc_wr_rs_p0(mc_wr_rs_p0), - .mc_rq_cyc_p0(mc_rq_cyc_p0), - .mc_rd_rq_p0(mc_rd_rq_p0), - .mc_wr_rq_p0(mc_wr_rq_p0), - .ma_p0(ma_p0), - .sel_p0(sel_p0), - .fmc_select_p0(fmc_select_p0), - .mb_in_p0(mb_in_p0), - - .cmc_addr_ack_p0(cmc_addr_ack_p0_0), - .cmc_rd_rs_p0(cmc_rd_rs_p0_0), - .mb_out_p0(mb_out_p0_0), - - .mc_rq_cyc_p1(1'b1), - .sel_p1(4'b0000), - .fmc_select_p1(1'b1), - - .mc_rq_cyc_p2(1'b1), - .sel_p2(4'b0000), - .fmc_select_p2(1'b1), - - .mc_rq_cyc_p3(1'b1), - .sel_p3(4'b0000), - .fmc_select_p3(1'b1) - ); - - coremem16k mem0( - .clk(clk), - - .mc_wr_rs_p0(mc_wr_rs_p0), - .mc_rq_cyc_p0(mc_rq_cyc_p0), - .mc_rd_rq_p0(mc_rd_rq_p0), - .mc_wr_rq_p0(mc_wr_rq_p0), - .ma_p0(ma_p0), - .sel_p0(sel_p0), - .fmc_select_p0(fmc_select_p0), - .mb_in_p0(mb_in_p0), - - .cmc_addr_ack_p0(cmc_addr_ack_p0_1), - .cmc_rd_rs_p0(cmc_rd_rs_p0_1), - .mb_out_p0(mb_out_p0_1), - - .mc_rq_cyc_p1(1'b0), - .sel_p1(4'b0000), - .fmc_select_p1(1'b0), - - .mc_rq_cyc_p2(1'b0), - .sel_p2(4'b0000), - .fmc_select_p2(1'b0), - - .mc_rq_cyc_p3(1'b0), - .sel_p3(4'b0000), - .fmc_select_p3(1'b0) - ); + initial +// #110000 $finish; + #10000 $finish; initial begin -// #1000 apr.rlr = 8'o201; -// apr.ex_user = 1; + #100 `TESTKEY = 1; + #1000 `TESTKEY = 0; + + // #3000 pdp6.key_dep = 1; + // #1000 pdp6.key_dep = 0; end - integer i; +/* initial begin + #100; + pdp6.mem0_sw_single_step = 1; + #6000; + pdp6.mem0_sw_restart = 1; + end*/ + initial begin - mem0.memsel_p0 = 0; - mem0.memsel_p1 = 0; - mem0.memsel_p2 = 0; - mem0.memsel_p3 = 0; - - fmem0.memsel_p0 = 0; - fmem0.memsel_p1 = 0; - fmem0.memsel_p2 = 0; - fmem0.memsel_p3 = 0; - fmem0.fmc_p0_sel = 1; - fmem0.fmc_p1_sel = 0; - fmem0.fmc_p2_sel = 0; - fmem0.fmc_p3_sel = 0; - - for(i = 0; i < 040000; i = i+1) - mem0.core[i] = 0; - mem0.core[4] = 36'o222333111666; - mem0.core['o20] = 36'o123234345456; - - for(i = 0; i < 16; i = i + 1) - fmem0.ff[i] = i+1 | 36'o50000; - - key_start <= 0; - key_read_in <= 0; - key_inst_cont <= 0; - key_mem_cont <= 0; - key_inst_stop <= 0; - key_mem_stop <= 0; - key_exec <= 0; - key_ioreset <= 0; - key_dep <= 0; - key_dep_nxt <= 0; - key_ex <= 0; - key_ex_nxt <= 0; - sw_addr_stop <= 0; - sw_mem_disable <= 0; - sw_repeat <= 0; - sw_power <= 0; - sw_rim_maint <= 0; -// mas <= 18'o777777; -// mas <= 18'o000000; - mas <= 18'o000004; -// mas <= 18'o000020; -// mas <= 18'o000104; -// mas <= 18'o300004; - datasw <= 36'o123456654321; - $dumpfile("dump.vcd"); $dumpvars(); + + reset = 0; + + pdp6.key_start = 0; + pdp6.key_read_in = 0; + pdp6.key_mem_cont = 0; + pdp6.key_inst_cont = 0; + pdp6.key_mem_stop = 0; + pdp6.key_inst_stop = 0; + pdp6.key_exec = 0; + pdp6.key_io_reset = 0; + pdp6.key_dep = 0; + pdp6.key_dep_nxt = 0; + pdp6.key_ex = 0; + pdp6.key_ex_nxt = 0; + + pdp6.sw_power = 0; + pdp6.sw_addr_stop = 0; + pdp6.sw_mem_disable = 0; + pdp6.sw_repeat = 0; + pdp6.sw_power = 0; + pdp6.datasw = 0; + pdp6.mas = 0; + + pdp6.sw_rim_maint = 0; + pdp6.sw_repeat_bypass = 0; + pdp6.sw_art3_maint = 0; + pdp6.sw_sct_maint = 0; + pdp6.sw_split_cyc = 0; + + pdp6.mem0_sw_single_step = 0; + pdp6.mem0_sw_restart = 0; + pdp6.fmem0.memsel_p0 = 0; + pdp6.fmem0.memsel_p1 = 0; + pdp6.fmem0.memsel_p2 = 0; + pdp6.fmem0.memsel_p3 = 0; + pdp6.fmem0.fmc_p0_sel = 1; + pdp6.fmem0.fmc_p1_sel = 0; + pdp6.fmem0.fmc_p2_sel = 0; + pdp6.fmem0.fmc_p3_sel = 0; + pdp6.mem0.memsel_p0 = 0; + pdp6.mem0.memsel_p1 = 0; + pdp6.mem0.memsel_p2 = 0; + pdp6.mem0.memsel_p3 = 0; + end initial begin - #10 sw_power = 1; + #80 pdp6.apr0.pr = 8'o003; + pdp6.apr0.rlr = 8'o002; + //pdp6.apr0.ex_user = 1; end initial begin - #400 `TESTKEY = 1; - #1000 `TESTKEY = 0; + #1 reset = 1; + #20 reset = 0; + + pdp6.datasw = 36'o111777222666; +// pdp6.mas = 18'o010100; +// pdp6.mas = 18'o000004; + pdp6.mas = 18'o000020; + //pdp6.mas = 18'o777777; + + pdp6.fmem0.ff['o0] = 36'o000000010000; + pdp6.fmem0.ff['o4] = 36'o000000010004; + pdp6.mem0.core['o4] = 36'o222333111666; + pdp6.mem0.core['o20] = 36'o777000777000; + end + + initial begin + #25 pdp6.sw_power = 1; + #25 pdp6.sw_power = 0; end -// initial begin -// #7000; -// #400 key_dep = 1; -// #1000 key_dep = 0; -// end endmodule