From 45bd177a73f54f21c43966fd32b95ccb8e40669b Mon Sep 17 00:00:00 2001 From: aap Date: Thu, 24 Nov 2016 16:13:49 +0100 Subject: [PATCH] verilog character instructions --- src/apr.c | 5 +- verilog/apr.v | 298 +++++++++++++++++++++++++++++++++++++++------- verilog/test.gtkw | 121 ++++++++++--------- verilog/test.v | 16 ++- 4 files changed, 335 insertions(+), 105 deletions(-) diff --git a/src/apr.c b/src/apr.c index ebbaa6b..e8c45ef 100644 --- a/src/apr.c +++ b/src/apr.c @@ -1111,9 +1111,12 @@ pulse(dct1){ } pulse(dct0a){ + word mb; trace("DCT0A\n"); apr->dcf1 = 0; // 6-20 - swap(&apr->mb, &apr->mq); // 6-17, 6-13 (dct0b) + mb = apr->mq; // 6-13 + apr->mq |= apr->mb; // 6-17 dct0b + apr->mb = mb; apr->ar = ~apr->ar & FW; // 6-17 nextpulse(apr, dct1); // 6-20 } diff --git a/verilog/apr.v b/verilog/apr.v index fb87245..2b7548d 100644 --- a/verilog/apr.v +++ b/verilog/apr.v @@ -1368,9 +1368,9 @@ module apr( * FE, SC */ reg [0:8] fe; - wire fe_clr = 0; - wire fe_fm_sc1 = 0; - wire fe_fm_mb0_5_1 = 0; + wire fe_clr = mr_clr; + wire fe_fm_sc1 = fpt3; + wire fe_fm_mb0_5_1 = cht8b; reg [0:8] sc; wire sc_clr = mr_clr | cht4 | cht8a | @@ -1387,23 +1387,60 @@ module apr( fpt1b & fp_mb0_eq_fmf1 | fat7 & mb[0] | nrt3 & (~ar[0] | nr_round); - wire sc_pad = 0; - wire sc_cry = 0; - wire sc_fm_fe1 = 0; + wire sc_pad = cht2 | cht7 | sat1 | fat8 | fat1; + wire sc_cry = sat21; + wire sc_fm_fe1 = cht9 | fmt0b | fdt0b; wire sc_fm_mb18_28_35_0 = et0a & (fsc | shift_op); - wire sc_mb0_5_0_enable = 0; - wire sc_mb6_11_1_enable = 0; - wire sc_ar0_8_1_enable = 0; - wire sc_mb0_8_1_enable = 0; + wire sc_mb0_5_0_enable = chf1; + wire sc_mb6_11_1_enable = chf2; + wire sc_ar0_8_1_enable = fsf1 | fpf1 | faf2; + wire sc_mb0_8_1_enable = fpf2 | faf1; // TODO: what the hell is sc8b? wire sc_eq_777 = sc == 9'o777; wire sc0_2_eq_7 = sc[0:2] == 3'o7; - wire sat0 = 0; - wire sat1 = 0; - wire sat2 = 0; - wire sat21 = 0; - wire sat3 = 0; + wire [0:8] sc_data = + {9{sc_mb0_5_0_enable}} & ~{ 3'b0, mb[0:5] } | + {9{sc_mb6_11_1_enable}} & { 2'b0, mb[6:11] } | + {9{sc_ar0_8_1_enable}} & ar[0:8] | + {9{sc_mb0_8_1_enable}} & mb[0:8]; + wire [0:8] scN_cry = ~sc & sc_data; + + wire sat0; + wire sat1; + wire sat2; + wire sat21; + wire sat3; + + pa sa_pa0(.clk(clk), .reset(reset), + .in(cht3 | fst0 | fat1 | fpt1 | fpt1aa), + .p(sat0)); + pa sa_pa1(.clk(clk), .reset(reset), + .in(sat0_D), + .p(sat1)); + pa sa_pa2(.clk(clk), .reset(reset), + .in(sat1_D), + .p(sat2)); + pa sa_pa3(.clk(clk), .reset(reset), + .in(sat2_D), + .p(sat21)); + pa sa_pa4(.clk(clk), .reset(reset), + .in(sat21_D), + .p(sat3)); + + wire sat0_D, sat1_D, sat2_D, sat21_D; + dly150ns sa_dly0(.clk(clk), .reset(reset), + .in(sat0), + .p(sat0_D)); + dly200ns sa_dly1(.clk(clk), .reset(reset), + .in(sat1), + .p(sat1_D)); + dly50ns sa_dly2(.clk(clk), .reset(reset), + .in(sat2), + .p(sat2_D)); + dly100ns sa_dly3(.clk(clk), .reset(reset), + .in(sat21), + .p(sat21_D)); wire sct0; wire sct1; @@ -1443,7 +1480,10 @@ module apr( sc <= sc + 1; if(sc_com) sc <= ~sc; - // TODO: sc_pad, sc_cry + if(sc_pad) + sc <= sc ^ sc_data; + if(sc_cry) + sc <= sc + { scN_cry[1:8], 1'b0 }; if(sc_fm_fe1) sc <= sc | fe; if(sc_fm_mb18_28_35_0) @@ -1454,16 +1494,23 @@ module apr( /* * CFAC */ - wire cfac_ar_negate = 0; - wire cfac_ar_add = 0; - wire cfac_ar_sub = 0; - wire cfac_mb_fm_mqJ = 0; + wire cfac_ar_negate = dst0 | dst5 | dst9 | dst19 | dst21; + wire cfac_ar_add = dst11 | dst15 | dst17 | mst3 | fat9; + wire cfac_ar_sub = dst12 | dst14 | dst18 | mst4; + wire cfac_mb_fm_mqJ = mpt1 | lct0 | dct0a | dct1; wire cfac_mb_mq_swap = dst2 | dst3 | dst7 | dst9 | dst19a | dst21a | blt_t0 | blt_t3a | blt_t5; - wire cfac_mb_ar_swap = 0; - wire cfac_ar_com = 0; - wire cfac_overflow = 0; + wire cfac_mb_ar_swap = dst4 | dst6 | dst8 | dst20 | + ch_inc_op & cht7 | + fat1a & ar0_eq_sc0; + wire cfac_ar_com = dst7 | dct0a | dct2 | + mpt0a & ~ir[6] & ar[0]; + wire cfac_overflow = mpt0a & mpf2 & ar[0] | + mpt1 & ~ar_eq_0 | + nrt3 & ~sc[0] | + dst0a & ~ar0_eq_sc0 | + dst13; wire cfac_ar_sh_lt = dst14a | nrt2 | sct1 & (dcf1 | shift_op & ~mb[18]); wire cfac_mq_sh_lt = dst14a | nrt2 | dst10b | @@ -1567,11 +1614,18 @@ module apr( * FS */ reg fsf1; - wire fsc = 0; + wire fsc = ir_fsc; wire fst0 = 0; wire fst0a = 0; wire fst1 = 0; + always @(posedge clk) begin + if(ds_clr | fst0a) + fsf1 <= 0; + if(fst0) + fsf1 <= 1; + end + /* * CH */ @@ -1587,19 +1641,116 @@ module apr( wire ch_NOT_inc_op = (ir_ldc | ir_dpc) & ~chf5 | ch_inc & chf7; - wire cht1 = 0; - wire cht2 = 0; - wire cht3 = 0; - wire cht3a = 0; - wire cht4 = 0; - wire cht4a = 0; - wire cht5 = 0; - wire cht6 = 0; - wire cht7 = 0; - wire cht8 = 0; - wire cht8a = 0; - wire cht8b = 0; - wire cht9 = 0; + wire cht1; + wire cht2; + wire cht3; + wire cht3a; + wire cht4; + wire cht4a; + wire cht5; + wire cht6; + wire cht7; + wire cht8; + wire cht8a; + wire cht8b; + wire cht9; + + pa ch_pa0(.clk(clk), .reset(reset), + .in(et0 & ch_inc_op), + .p(cht1)); + pa ch_pa1(.clk(clk), .reset(reset), + .in(cht1_D), + .p(cht2)); + pa ch_pa2(.clk(clk), .reset(reset), + .in(cht2 | cht4a), + .p(cht3)); + pa ch_pa3(.clk(clk), .reset(reset), + .in(sat3 & chf2), + .p(cht3a)); + pa ch_pa4(.clk(clk), .reset(reset), + .in(cht4a & ~sc[0]), + .p(cht4)); + pa ch_pa5(.clk(clk), .reset(reset), + .in(ar_t3 & ~chf3), + .p(cht4a)); + pa ch_pa6(.clk(clk), .reset(reset), + .in(cht3a & sc[0]), + .p(cht5)); + pa ch_pa7(.clk(clk), .reset(reset), + .in(et0 & ch_NOT_inc_op | cht5_D), + .p(cht6)); + pa ch_pa8(.clk(clk), .reset(reset), + .in(cht6_D), + .p(cht7)); + pa ch_pa9(.clk(clk), .reset(reset), + .in(cht7_D & ch_inc_op), + .p(cht8)); + pa ch_pa10(.clk(clk), .reset(reset), + .in(cht7_D & ch_NOT_inc_op | + mc_rs_t1 & chf6), + .p(cht8b)); + pa ch_pa11(.clk(clk), .reset(reset), + .in(sct2 & chf4), + .p(cht8a)); + pa ch_pa12(.clk(clk), .reset(reset), + .in(cht8a), + .p(cht9)); + + wire cht1_D, cht5_D, cht6_D, cht7_D, cht8a_D; + dly100ns ch_dly0(.clk(clk), .reset(reset), + .in(cht1), + .p(cht1_D)); + dly100ns ch_dly1(.clk(clk), .reset(reset), + .in(cht5), + .p(cht5_D)); + dly150ns ch_dly2(.clk(clk), .reset(reset), + .in(cht6), + .p(cht6_D)); + dly100ns ch_dly3(.clk(clk), .reset(reset), + .in(cht7), + .p(cht7_D)); + dly100ns ch_dly4(.clk(clk), .reset(reset), + .in(cht8a), + .p(cht8a_D)); + + always @(posedge clk) begin + if(mp_clr | sat0) + chf1 <= 0; + if(cht1) + chf1 <= 1; + + if(mp_clr | cht3a | cht8b) + chf2 <= 0; + if(cht3 | cht6) + chf2 <= 1; + + if(mp_clr | cht4a) + chf3 <= 0; + if(cht4) + chf3 <= 1; + + if(mp_clr | cht8a) + chf4 <= 0; + if(cht8b & ~ir_cao) + chf4 <= 1; + + if(mp_clr) + chf5 <= 0; + if(cht9) + chf5 <= 1; + + if(mp_clr | cht8b) + chf6 <= 0; + if(cht8) + chf6 <= 1; + + if(ar_flag_clr | dct3 | lct0a | + et9 & jp_jsr) + chf7 <= 0; + if(cht9 | + ar_flag_set & mb[4]) + chf7 <= 1; + end /* * LC @@ -1607,8 +1758,22 @@ module apr( reg lcf1; wire ch_load = (ir_ldc | ir_ldci) & chf5; - wire lct0 = 0; - wire lct0a = 0; + wire lct0; + wire lct0a; + + pa lc_pa0(.clk(clk), .reset(reset), + .in(et0 & ch_load), + .p(lct0)); + pa lc_pa1(.clk(clk), .reset(reset), + .in(sct2 & lcf1), + .p(lct0a)); + + always @(posedge clk) begin + if(mp_clr | lct0a) + lcf1 <= 0; + if(lct0) + lcf1 <= 1; + end /* * DC @@ -1616,12 +1781,46 @@ module apr( reg dcf1; wire ch_dep = (ir_dpc | ir_dpci) & chf5; - wire dct0 = 0; - wire dct0a = 0; - wire dct0b = 0; - wire dct1 = 0; - wire dct2 = 0; - wire dct3 = 0; + wire dct0; + wire dct0a; + wire dct0b = dct0a; // otherwise we get timing problems + wire dct1; + wire dct2; + wire dct3; + + pa dc_pa0(.clk(clk), .reset(reset), + .in(et0 & ch_dep), + .p(dct0)); + pa dc_pa1(.clk(clk), .reset(reset), + .in(sct2 & dcf1), + .p(dct0a)); + pa dc_pa2(.clk(clk), .reset(reset), + .in(dct0a_D), + .p(dct1)); + pa dc_pa3(.clk(clk), .reset(reset), + .in(dct1_D), + .p(dct2)); + pa dc_pa4(.clk(clk), .reset(reset), + .in(dct2_D), + .p(dct3)); + + wire dct0a_D, dct1_D, dct2_D; + dly150ns dc_dly0(.clk(clk), .reset(reset), + .in(dct0a), + .p(dct0a_D)); + dly100ns dc_dly1(.clk(clk), .reset(reset), + .in(dct1), + .p(dct1_D)); + dly100ns dc_dly2(.clk(clk), .reset(reset), + .in(dct2), + .p(dct2_D)); + + always @(posedge clk) begin + if(mr_clr | dct0a) + dcf1 <= 0; + if(dct0) + dcf1 <= 1; + end /* * SH @@ -1662,6 +1861,7 @@ module apr( * MP */ reg mpf1; + reg mpf2; wire mp_clr = mr_clr; wire mpt0 = 0; @@ -1672,6 +1872,8 @@ module apr( always @(posedge clk) begin if(mp_clr | mpt0a) mpf1 <= 0; + if(mp_clr) + mpf2 <= 0; end /* @@ -1803,7 +2005,7 @@ module apr( reg dsf9; wire ds_div = 0; wire ds_divi = 0; - wire ds_clr = 0; + wire ds_clr; wire dsf7_xor_mq0 = 0; wire dst0 = 0; @@ -1841,6 +2043,10 @@ module apr( wire ds_div_t0 = 0; + pa ds_pa0(.clk(clk), .reset(reset), + .in(mr_clr), + .p(ds_clr)); + always @(posedge clk) begin if(ds_clr | dst0a) dsf1 <= 0; diff --git a/verilog/test.gtkw b/verilog/test.gtkw index b1cff61..2423ed2 100644 --- a/verilog/test.gtkw +++ b/verilog/test.gtkw @@ -1,15 +1,15 @@ [*] [*] GTKWave Analyzer v3.3.76 (w)1999-2016 BSI -[*] Thu Nov 24 10:04:34 2016 +[*] Thu Nov 24 15:13:00 2016 [*] [dumpfile] "/home/aap/src/pdp6/verilog/dump.vcd" -[dumpfile_mtime] "Thu Nov 24 09:54:12 2016" -[dumpfile_size] 223600 +[dumpfile_mtime] "Thu Nov 24 15:10:54 2016" +[dumpfile_size] 251956 [savefile] "/home/aap/src/pdp6/verilog/test.gtkw" -[timestart] 4587 +[timestart] 0 [size] 1920 1080 [pos] -1 -1 -*-10.555068 11855 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +*-11.555068 8970 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 [treeopen] test. [treeopen] test.pdp6. [treeopen] test.pdp6.fmem0. @@ -217,14 +217,12 @@ test.pdp6.apr0.et9 test.pdp6.apr0.et10 @1401200 -E -@800200 +@c00200 -S @28 test.pdp6.apr0.s_ac_0 test.pdp6.apr0.s_ac_2 -@29 test.pdp6.apr0.s_ac_inh -@28 test.pdp6.apr0.s_ac_inh_if_ac_0 test.pdp6.apr0.st1 test.pdp6.apr0.st2 @@ -236,7 +234,7 @@ test.pdp6.apr0.st5a test.pdp6.apr0.st6 test.pdp6.apr0.sf7 test.pdp6.apr0.st7 -@1000200 +@1401200 -S @c00200 -iobus @@ -278,49 +276,6 @@ test.pdp6.apr0.mc_non_exist_mem_rst test.pdp6.apr0.mc_non_exist_rd @1401200 -membus -@c00030 -test.fmem0scope[0:35] -@28 -(0)test.fmem0scope[0:35] -(1)test.fmem0scope[0:35] -(2)test.fmem0scope[0:35] -(3)test.fmem0scope[0:35] -(4)test.fmem0scope[0:35] -(5)test.fmem0scope[0:35] -(6)test.fmem0scope[0:35] -(7)test.fmem0scope[0:35] -(8)test.fmem0scope[0:35] -(9)test.fmem0scope[0:35] -(10)test.fmem0scope[0:35] -(11)test.fmem0scope[0:35] -(12)test.fmem0scope[0:35] -(13)test.fmem0scope[0:35] -(14)test.fmem0scope[0:35] -(15)test.fmem0scope[0:35] -(16)test.fmem0scope[0:35] -(17)test.fmem0scope[0:35] -(18)test.fmem0scope[0:35] -(19)test.fmem0scope[0:35] -(20)test.fmem0scope[0:35] -(21)test.fmem0scope[0:35] -(22)test.fmem0scope[0:35] -(23)test.fmem0scope[0:35] -(24)test.fmem0scope[0:35] -(25)test.fmem0scope[0:35] -(26)test.fmem0scope[0:35] -(27)test.fmem0scope[0:35] -(28)test.fmem0scope[0:35] -(29)test.fmem0scope[0:35] -(30)test.fmem0scope[0:35] -(31)test.fmem0scope[0:35] -(32)test.fmem0scope[0:35] -(33)test.fmem0scope[0:35] -(34)test.fmem0scope[0:35] -(35)test.fmem0scope[0:35] -@1401200 --group_end -@30 -test.mem0scope[0:35] @c00200 -mem0 @28 @@ -399,6 +354,7 @@ test.pdp6.fmem0.fmct5 -fmem0 @28 test.pdp6.apr0.at1_inh +@29 test.pdp6.apr0.ia_NOT_int @c00200 -PI @@ -517,9 +473,17 @@ test.pdp6.apr0.sht1a test.pdp6.apr0.sct0 test.pdp6.apr0.sct1 test.pdp6.apr0.sct2 +@200 +- +@28 +test.pdp6.apr0.sat0 +test.pdp6.apr0.sat1 +test.pdp6.apr0.sat2 +test.pdp6.apr0.sat21 +test.pdp6.apr0.sat3 @1401200 -shift -@800200 +@c00200 -BLT @28 test.pdp6.apr0.blt_last @@ -537,7 +501,56 @@ test.pdp6.apr0.blt_t5 test.pdp6.apr0.blt_f5a test.pdp6.apr0.blt_t5a test.pdp6.apr0.blt_t6 -@1000200 +@1401200 -BLT +@c00200 +-CH +@28 +test.pdp6.apr0.ch_inc_op +test.pdp6.apr0.ch_NOT_inc_op +test.pdp6.apr0.ch_load +test.pdp6.apr0.ch_dep +test.pdp6.apr0.cht1 +test.pdp6.apr0.chf1 +test.pdp6.apr0.cht2 +test.pdp6.apr0.chf2 +test.pdp6.apr0.cht3 +test.pdp6.apr0.cht3a +test.pdp6.apr0.cht4 +test.pdp6.apr0.chf3 +test.pdp6.apr0.cht4a +test.pdp6.apr0.cht5 +test.pdp6.apr0.cht6 +test.pdp6.apr0.cht7 +test.pdp6.apr0.cht8 +test.pdp6.apr0.chf6 +test.pdp6.apr0.cht8a +test.pdp6.apr0.cht8b +test.pdp6.apr0.cht9 +test.pdp6.apr0.chf7 +test.pdp6.apr0.chf4 +test.pdp6.apr0.chf5 +@1401200 +-CH +@c00200 +-LC +@28 +test.pdp6.apr0.lct0 +test.pdp6.apr0.lcf1 +test.pdp6.apr0.lct0a +@1401200 +-LC +@c00200 +-DC +@28 +test.pdp6.apr0.dct0 +test.pdp6.apr0.dcf1 +test.pdp6.apr0.dct0a +test.pdp6.apr0.dct0b +test.pdp6.apr0.dct1 +test.pdp6.apr0.dct2 +test.pdp6.apr0.dct3 +@1401200 +-DC [pattern_trace] 1 [pattern_trace] 0 diff --git a/verilog/test.v b/verilog/test.v index 9cc9027..ee7e916 100644 --- a/verilog/test.v +++ b/verilog/test.v @@ -26,7 +26,7 @@ module test; initial begin stop = 0; // #110000 stop = 1; - #50000 stop = 1; + #20000 stop = 1; end always @(pdp6.apr0.st7) if(pdp6.apr0.st7) @@ -36,7 +36,7 @@ module test; always @(stop) if(stop) begin: fin integer i; - #1000; + #4000; for(i = 0; i < 'o20; i = i + 1) $display("%o %o %o", i, pdp6.mem0.core[i], pdp6.fmem0.ff[i]); for(i = 'o1000; i < 'o1010; i = i + 1) @@ -161,7 +161,7 @@ module test; #20 reset = 0; pdp6.datasw = 36'o111777222666; - pdp6.mas = 18'o000060; + pdp6.mas = 18'o000067; for(i = 0; i < 'o40000; i = i + 1) pdp6.mem0.core[i] = 0; @@ -176,7 +176,10 @@ module test; pdp6.fmem0.ff['o5] = 36'o377777_777777; pdp6.fmem0.ff['o6] = 36'o444000_222000; pdp6.fmem0.ff['o7] = 36'o777776_000010; // BLK ptr - pdp6.fmem0.ff['o10] = 36'o000002_001000; // BLT ptr + pdp6.fmem0.ff['o10] = 36'o000002_001000; // BLT ptr + pdp6.fmem0.ff['o11] = 36'o440600_001000; // char ptr + pdp6.fmem0.ff['o12] = 36'o300600_001000; // char ptr + pdp6.fmem0.ff['o13] = 36'o000000_005555; // char pdp6.fmem0.ff['o17] = 36'o777000_001000; // PDL ptr // pdp6.fmem0.ff['o17] = 36'o777000_777777; // PDL ptr pdp6.mem0.core['o20] = 36'o200_064_000104; // MOVE 1,@104(4) FAC_INH @@ -200,7 +203,12 @@ module test; pdp6.mem0.core['o56] = 36'o244_100_000001; // ASHC 2,1 pdp6.mem0.core['o60] = 36'o251_400_001001; // BLT 10,1007 + pdp6.mem0.core['o64] = 36'o133_000_000011; // IBP 11 + pdp6.mem0.core['o65] = 36'o135_000_000012; // LBP 0,12 + pdp6.mem0.core['o66] = 36'o134_000_000012; // ILBP 0,12 + pdp6.mem0.core['o67] = 36'o137_540_000012; // DBP 13,12 + pdp6.mem0.core['o1000] = 36'o50_45_54_54_57_00; pdp6.mem0.core['o10410] = 36'o000_000_000333; end