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added quartus project files

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aap 2016-12-10 00:00:16 +01:00
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244
verilog/quartus/apr_test.v Normal file
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// UNUSED
module apr(
input wire clk,
input wire reset,
input wire key_start,
input wire key_read_in,
input wire key_inst_cont,
input wire key_mem_cont,
input wire key_inst_stop,
input wire key_mem_stop,
input wire key_io_reset,
input wire key_exec,
input wire key_dep,
input wire key_dep_nxt,
input wire key_ex,
input wire key_ex_nxt,
input wire sw_repeat,
input wire sw_addr_stop,
input wire sw_power,
input wire sw_mem_disable,
input wire [0:35] datasw,
input wire [18:35] mas,
input wire sw_rim_maint,
input wire sw_repeat_bypass,
input wire sw_art3_maint,
input wire sw_sct_maint,
input wire sw_split_cyc,
output reg [0:17] ir,
output reg [0:35] mi,
output reg [0:35] ar,
output reg [0:35] mb,
output reg [0:35] mq,
output reg [18:35] pc,
output reg [18:35] ma,
output reg run,
output reg mc_stop,
output reg pi_active,
output reg [1:7] pih,
output reg [1:7] pir,
output reg [1:7] pio,
output reg [18:25] pr,
output reg [18:25] rlr,
output reg [18:25] rla,
output wire [0:7] ff0,
output wire [0:7] ff1,
output wire [0:7] ff2,
output wire [0:7] ff3,
output wire [0:7] ff4,
output wire [0:7] ff5,
output wire [0:7] ff6,
output wire [0:7] ff7,
output wire [0:7] ff8,
output wire [0:7] ff9,
output wire [0:7] ff10,
output wire [0:7] ff11,
output wire [0:7] ff12,
output wire [0:7] ff13,
// membus
output wire membus_wr_rs,
output wire membus_rq_cyc,
output wire membus_rd_rq,
output wire membus_wr_rq,
output wire [21:35] membus_ma,
output wire [18:21] membus_sel,
output wire membus_fmc_select,
output wire [0:35] membus_mb_out,
input wire membus_addr_ack,
input wire membus_rd_rs,
input wire [0:35] membus_mb_in,
// IO bus
output wire iobus_iob_poweron,
output wire iobus_iob_reset,
output wire iobus_datao_clear,
output wire iobus_datao_set,
output wire iobus_cono_clear,
output wire iobus_cono_set,
output wire iobus_iob_fm_datai,
output wire iobus_iob_fm_status,
output wire [3:9] iobus_ios,
output wire [0:35] iobus_iob_out,
input wire [1:7] iobus_pi_req,
input wire [0:35] iobus_iob_in
);
wire key_any = key_start | key_read_in | key_inst_cont | key_mem_cont | key_inst_stop | key_mem_stop | key_ex | key_ex_nxt | key_dep | key_dep_nxt;
wire key_pulse;
pg pg0(.clk(clk), .reset(reset),
.in(key_any),
.p(key_pulse));
assign ff1 = 2;
assign ff2 = 3;
assign ff3 = 4;
assign ff4 = 5;
assign ff5 = 6;
assign ff6 = 7;
assign ff7 = 8;
assign ff8 = 9;
assign ff9 = 10;
assign ff10 = 11;
assign ff11 = 12;
assign ff12 = 13;
assign ff13 = 14;
//initial begin
// mb <= 36'o111111111111;
// ar <= 36'o222222222222;
// mq <= 36'o333333333333;
// mi <= 36'o444444444444;
// ir <= 18'o555555;
// ma <= 18'o666666;
// pc <= 18'o777777;
//end
wire kt0, kt1, kt2;
wire key_rd, key_wr;
pa key_pa0(.clk(clk), .reset(reset),
.in(key_pulse),
.p(kt0));
pa key_pa1(.clk(clk), .reset(reset),
.in(mc_rs_t1 & key_rdwr),
.p(kt2));
dly200ns dly0(.clk(clk), .reset(reset),
.in(kt0),
.p(kt1));
dly200ns dly1(.clk(clk), .reset(reset),
.in(kt1 & (key_ex | key_ex_nxt)),
.p(key_rd));
dly200ns dly2(.clk(clk), .reset(reset),
.in(kt1 & (key_dep | key_dep_nxt)),
.p(key_wr));
always @(posedge clk) begin
if(kt0 & (key_ex | key_dep))
ma <= 0;
if(kt0 & (key_ex_nxt | key_dep_nxt))
ma <= ma + 18'b1;
if(kt0 & (key_dep | key_dep_nxt))
ar <= 0;
if(kt1 & (key_ex | key_dep))
ma <= ma | mas;
if(kt1 & (key_dep | key_dep_nxt))
ar <= ar | datasw;
if(key_rd | key_wr)
key_rdwr <= 1;
if(kt2)
key_rdwr <= 0;
end
assign membus_rq_cyc = mc_rq & (mc_rd | mc_wr);
assign membus_rd_rq = mc_rd;
assign membus_wr_rq = mc_wr;
assign membus_ma = ma[21:35];
assign membus_sel = 0;
assign membus_fmc_select = sw_rim_maint;
assign membus_mb_out = mc_membus_fm_mb1 ? mb : 0;
wire mai_addr_ack, mai_rd_rs;
wire mb_pulse;
pg mc_pg0(.clk(clk), .reset(reset),
.in(membus_addr_ack), .p(mai_addr_ack));
pg mc_pg1(.clk(clk), .reset(reset),
.in(membus_rd_rs), .p(mai_rd_rs));
pg mc_pg2(.clk(clk), .reset(reset),
.in(| membus_mb_in),
.p(mb_pulse));
wire mc_wr_rs, mc_membus_fm_mb1;
bd mc_bd0(.clk(clk), .reset(reset), .in(mc_wr_rs), .p(membus_wr_rs));
bd2 mb_bd1(.clk(clk), .reset(reset), .in(mc_wr_rs), .p(mc_membus_fm_mb1));
reg key_rdwr = 0;
reg mc_rd = 0, mc_wr = 0, mc_rq = 0;
wire mc_addr_ack;
wire mc_rd_rq_pulse, mc_wr_rq_pulse, mc_rq_pulse;
wire mc_rs_t0, mc_rs_t1;
pa mc_pa1(.clk(clk), .reset(reset),
.in(key_rd),
.p(mc_rd_rq_pulse));
pa mc_pa2(.clk(clk), .reset(reset),
.in(key_wr),
.p(mc_wr_rq_pulse));
pa mc_pa3(.clk(clk), .reset(reset),
.in(mc_rd_rq_pulse | mc_wr_rq_pulse),
.p(mc_rq_pulse));
pa mc_pa4(.clk(clk), .reset(reset),
.in(mai_rd_rs | mc_wr_rs),
.p(mc_rs_t0));
pa mc_pa5(.clk(clk), .reset(reset),
.in(mc_rs_t0),
.p(mc_rs_t1));
pa mc_pa6(.clk(clk), .reset(reset),
.in(mai_addr_ack),
.p(mc_addr_ack));
pa mc_pa7(.clk(clk), .reset(reset),
.in(mc_addr_ack & ~mc_rd & mc_wr),
.p(mc_wr_rs));
reg f0 = 0;
reg f1 = 0;
always @(posedge clk) begin
if(mc_rd_rq_pulse) begin
mc_rd <= 1;
mc_wr <= 0;
mb <= 0;
end
if(mc_wr_rq_pulse) begin
mc_rd <= 0;
mc_wr <= 1;
end
if(mc_rq_pulse)
mc_rq <= 1;
if(mc_addr_ack)
mc_rq <= 0;
if(mai_rd_rs)
f1 <= 1;
if(mb_pulse & mc_rd)
mb <= mb | membus_mb_in;
if(mc_rs_t1)
mc_rd <= 0;
if(key_wr)
mb <= ar;
end
assign ff0 = { 2'b0, f0, f1, key_rdwr, mc_rd, mc_wr, mc_rq };
endmodule

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verilog/quartus/fpdpga6.cdf Normal file
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/* Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition */
JedecChain;
FileRevision(JESD32A);
DefaultMfr(6E);
P ActionCode(Cfg)
Device PartName(5CGXFC5C6F27) Path("C:/Users/aap/src/pdp6/verilog/quartus/output_files/") File("fpdpga6.sof") MfrSpec(OpMask(1));
ChainEnd;
AlteraBegin;
ChainType(JTAG);
AlteraEnd;

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verilog/quartus/fpdpga6.qpf Normal file
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 2016 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel MegaCore Function License Agreement, or other
# applicable license agreement, including, without limitation,
# that your use is for the sole purpose of programming logic
# devices manufactured by Intel and sold by Intel or its
# authorized distributors. Please refer to the applicable
# agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
# Date created = 10:24:53 December 02, 2016
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "16.1"
DATE = "10:24:53 December 02, 2016"
# Revisions
PROJECT_REVISION = "fpdpga6"

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verilog/quartus/fpdpga6.qsf Normal file
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 2016 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel MegaCore Function License Agreement, or other
# applicable license agreement, including, without limitation,
# that your use is for the sole purpose of programming logic
# devices manufactured by Intel and sold by Intel or its
# authorized distributors. Please refer to the applicable
# agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
# Date created = 10:24:53 December 02, 2016
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# fpdpga6_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus Prime software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "Cyclone V"
set_global_assignment -name DEVICE 5CGXFC5C6F27C7
set_global_assignment -name TOP_LEVEL_ENTITY fpdpga6
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:24:53 DECEMBER 02, 2016"
set_global_assignment -name LAST_QUARTUS_VERSION "16.1.0 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
set_global_assignment -name VERILOG_FILE fpdpga6.v
set_global_assignment -name VERILOG_FILE i2c.v
set_global_assignment -name VERILOG_FILE i2c_core.v
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_location_assignment PIN_P11 -to key[0]
set_location_assignment PIN_P12 -to key[1]
set_location_assignment PIN_Y15 -to key[2]
set_location_assignment PIN_Y16 -to key[3]
set_location_assignment PIN_AB24 -to key[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to key[4]
set_instance_assignment -name IO_STANDARD "1.2 V" -to key[3]
set_instance_assignment -name IO_STANDARD "1.2 V" -to key[2]
set_instance_assignment -name IO_STANDARD "1.2 V" -to key[1]
set_instance_assignment -name IO_STANDARD "1.2 V" -to key[0]
set_location_assignment PIN_R20 -to clk
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to clk
set_location_assignment PIN_B25 -to sram_a[0]
set_location_assignment PIN_B26 -to sram_a[1]
set_location_assignment PIN_H19 -to sram_a[2]
set_location_assignment PIN_H20 -to sram_a[3]
set_location_assignment PIN_D25 -to sram_a[4]
set_location_assignment PIN_C25 -to sram_a[5]
set_location_assignment PIN_J20 -to sram_a[6]
set_location_assignment PIN_J21 -to sram_a[7]
set_location_assignment PIN_D22 -to sram_a[8]
set_location_assignment PIN_E23 -to sram_a[9]
set_location_assignment PIN_G20 -to sram_a[10]
set_location_assignment PIN_F21 -to sram_a[11]
set_location_assignment PIN_E21 -to sram_a[12]
set_location_assignment PIN_F22 -to sram_a[13]
set_location_assignment PIN_J25 -to sram_a[14]
set_location_assignment PIN_J26 -to sram_a[15]
set_location_assignment PIN_N24 -to sram_a[16]
set_location_assignment PIN_M24 -to sram_a[17]
set_location_assignment PIN_E24 -to sram_d[0]
set_location_assignment PIN_E25 -to sram_d[1]
set_location_assignment PIN_K24 -to sram_d[2]
set_location_assignment PIN_K23 -to sram_d[3]
set_location_assignment PIN_F24 -to sram_d[4]
set_location_assignment PIN_G24 -to sram_d[5]
set_location_assignment PIN_L23 -to sram_d[6]
set_location_assignment PIN_L24 -to sram_d[7]
set_location_assignment PIN_H23 -to sram_d[8]
set_location_assignment PIN_H24 -to sram_d[9]
set_location_assignment PIN_H22 -to sram_d[10]
set_location_assignment PIN_J23 -to sram_d[11]
set_location_assignment PIN_F23 -to sram_d[12]
set_location_assignment PIN_G22 -to sram_d[13]
set_location_assignment PIN_L22 -to sram_d[14]
set_location_assignment PIN_K21 -to sram_d[15]
set_location_assignment PIN_N23 -to sram_ce
set_location_assignment PIN_H25 -to sram_lb
set_location_assignment PIN_G25 -to sram_we
set_location_assignment PIN_M25 -to sram_ub
set_location_assignment PIN_M22 -to sram_oe
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_a[17]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_a[16]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_a[15]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_a[14]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_a[13]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_a[12]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_a[11]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_a[10]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_a[9]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_a[8]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_we
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_ub
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_oe
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_lb
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_d[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_d[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_d[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_d[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_d[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_d[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_d[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_d[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_d[8]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_d[9]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_d[10]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_d[11]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_d[12]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_d[13]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_d[14]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_d[15]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_d
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_ce
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_a[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_a[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_a[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_a[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_a[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_a[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_a[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_a[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_a
set_location_assignment PIN_AC9 -to sw[0]
set_location_assignment PIN_AE10 -to sw[1]
set_location_assignment PIN_AD13 -to sw[2]
set_location_assignment PIN_AC8 -to sw[3]
set_location_assignment PIN_W11 -to sw[4]
set_location_assignment PIN_AB10 -to sw[5]
set_location_assignment PIN_V10 -to sw[6]
set_location_assignment PIN_AC10 -to sw[7]
set_location_assignment PIN_Y11 -to sw[8]
set_location_assignment PIN_AE19 -to sw[9]
set_instance_assignment -name IO_STANDARD "1.2 V" -to sw[9]
set_instance_assignment -name IO_STANDARD "1.2 V" -to sw[0]
set_instance_assignment -name IO_STANDARD "1.2 V" -to sw[1]
set_instance_assignment -name IO_STANDARD "1.2 V" -to sw[2]
set_instance_assignment -name IO_STANDARD "1.2 V" -to sw[3]
set_instance_assignment -name IO_STANDARD "1.2 V" -to sw[4]
set_instance_assignment -name IO_STANDARD "1.2 V" -to sw[5]
set_instance_assignment -name IO_STANDARD "1.2 V" -to sw[6]
set_instance_assignment -name IO_STANDARD "1.2 V" -to sw[7]
set_instance_assignment -name IO_STANDARD "1.2 V" -to sw[8]
set_instance_assignment -name IO_STANDARD "1.2 V" -to sw
set_location_assignment PIN_F7 -to ledr[0]
set_location_assignment PIN_F6 -to ledr[1]
set_location_assignment PIN_G6 -to ledr[2]
set_location_assignment PIN_G7 -to ledr[3]
set_location_assignment PIN_J8 -to ledr[4]
set_location_assignment PIN_J7 -to ledr[5]
set_location_assignment PIN_K10 -to ledr[6]
set_location_assignment PIN_K8 -to ledr[7]
set_location_assignment PIN_H7 -to ledr[8]
set_location_assignment PIN_J10 -to ledr[9]
set_location_assignment PIN_L7 -to ledg[0]
set_location_assignment PIN_K6 -to ledg[1]
set_location_assignment PIN_D8 -to ledg[2]
set_location_assignment PIN_E9 -to ledg[3]
set_location_assignment PIN_A5 -to ledg[4]
set_location_assignment PIN_B6 -to ledg[5]
set_location_assignment PIN_H8 -to ledg[6]
set_location_assignment PIN_H9 -to ledg[7]
set_location_assignment PIN_K25 -to scl
set_location_assignment PIN_E26 -to sda
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to scl
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sda
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
set_global_assignment -name NUM_PARALLEL_PROCESSORS 2
set_global_assignment -name CDF_FILE output_files/fpdpga6.cdf
set_global_assignment -name ENABLE_SIGNALTAP ON
set_global_assignment -name USE_SIGNALTAP_FILE output_files/test.stp
set_global_assignment -name SIGNALTAP_FILE output_files/test.stp
set_global_assignment -name VERILOG_FILE uart.v
set_location_assignment PIN_K26 -to rx
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to rx
set_location_assignment PIN_M26 -to tx
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to tx
set_global_assignment -name VERILOG_FILE ../apr.v
set_global_assignment -name VERILOG_FILE ../core161c.v
set_global_assignment -name VERILOG_FILE ../fast162.v
set_global_assignment -name VERILOG_FILE ../modules.v
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

116
verilog/quartus/fpdpga6.sdc Normal file
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## Generated SDC file "fpdpga6.sdc"
## Copyright (C) 2016 Intel Corporation. All rights reserved.
## Your use of Intel Corporation's design tools, logic functions
## and other software and tools, and its AMPP partner logic
## functions, and any output files from any of the foregoing
## (including device programming or simulation files), and any
## associated documentation or information are expressly subject
## to the terms and conditions of the Intel Program License
## Subscription Agreement, the Intel Quartus Prime License Agreement,
## the Intel MegaCore Function License Agreement, or other
## applicable license agreement, including, without limitation,
## that your use is for the sole purpose of programming logic
## devices manufactured by Intel and sold by Intel or its
## authorized distributors. Please refer to the applicable
## agreement for further details.
## VENDOR "Altera"
## PROGRAM "Quartus Prime"
## VERSION "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition"
## DATE "Fri Dec 02 10:55:33 2016"
##
## DEVICE "5CGXFC5C6F27C7"
##
#**************************************************************
# Time Information
#**************************************************************
set_time_format -unit ns -decimal_places 3
#**************************************************************
# Create Clock
#**************************************************************
create_clock -name {clk} -period 20.000 -waveform { 0.000 10.000 } [get_ports {clk}]
#**************************************************************
# Create Generated Clock
#**************************************************************
#**************************************************************
# Set Clock Latency
#**************************************************************
#**************************************************************
# Set Clock Uncertainty
#**************************************************************
set_clock_uncertainty -rise_from [get_clocks {clk}] -rise_to [get_clocks {clk}] -setup 0.100
set_clock_uncertainty -rise_from [get_clocks {clk}] -rise_to [get_clocks {clk}] -hold 0.060
set_clock_uncertainty -rise_from [get_clocks {clk}] -fall_to [get_clocks {clk}] -setup 0.100
set_clock_uncertainty -rise_from [get_clocks {clk}] -fall_to [get_clocks {clk}] -hold 0.060
set_clock_uncertainty -fall_from [get_clocks {clk}] -rise_to [get_clocks {clk}] -setup 0.100
set_clock_uncertainty -fall_from [get_clocks {clk}] -rise_to [get_clocks {clk}] -hold 0.060
set_clock_uncertainty -fall_from [get_clocks {clk}] -fall_to [get_clocks {clk}] -setup 0.100
set_clock_uncertainty -fall_from [get_clocks {clk}] -fall_to [get_clocks {clk}] -hold 0.060
#**************************************************************
# Set Input Delay
#**************************************************************
#**************************************************************
# Set Output Delay
#**************************************************************
#**************************************************************
# Set Clock Groups
#**************************************************************
#**************************************************************
# Set False Path
#**************************************************************
#**************************************************************
# Set Multicycle Path
#**************************************************************
#**************************************************************
# Set Maximum Delay
#**************************************************************
#**************************************************************
# Set Minimum Delay
#**************************************************************
#**************************************************************
# Set Input Transition
#**************************************************************

535
verilog/quartus/fpdpga6.v Normal file
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@ -0,0 +1,535 @@
`default_nettype none
`define synthesis
module fpdpga6(
input wire clk,
input wire [9:0] sw,
input wire [4:0] key,
output wire [7:0] ledg,
output wire [9:0] ledr,
input wire rx,
output wire tx,
output wire [17:0] sram_a,
inout wire [15:0] sram_d,
output wire sram_ce,
output wire sram_oe,
output wire sram_we,
output wire sram_lb,
output wire sram_ub,
input wire scl,
inout wire sda
);
// TODO: figure out what to do with this
wire reset = ~key[0];
wire ack;
reg ack0;
wire done = ~ack0 & ack;
wire [6:0] dev;
wire [7:0] in;
wire dir;
wire start, stop;
// hardcoded devices:
wire ok = panelok | coreok;
wire [7:0] out = panelok ? panelout :
coreok ? coreout : 8'b0;
i2cslv slv(.clk(clk), .reset(reset),
.scl(scl), .sda(sda),
.dev(dev), .ok(ok),
.ack(ack), .dir(dir),
.in(in), .out(out),
.start(start), .stop(stop));
always @(posedge clk)
ack0 <= ack;
wire [17:0] core_sram_a;
wire core_sram_ce;
wire core_sram_oe;
wire core_sram_we;
wire core_sram_lb;
wire core_sram_ub;
wire [17:0] i2c_sram_a;
wire i2c_sram_ce;
wire i2c_sram_oe;
wire i2c_sram_we;
wire i2c_sram_lb;
wire i2c_sram_ub;
assign sram_a = core_sram_a | i2c_sram_a;
assign sram_ce = core_sram_ce & i2c_sram_ce;
assign sram_oe = core_sram_oe & i2c_sram_oe;
assign sram_we = core_sram_we & i2c_sram_we;
assign sram_lb = core_sram_lb & i2c_sram_lb;
assign sram_ub = core_sram_ub & i2c_sram_ub;
// i2cdev core
wire coreok = dev == 7'h21;
wire [7:0] coreout;
i2c_core i2c_core0(.clk(clk), .reset(reset),
.start(start), .stop(stop),
.dir(dir),
.ok(coreok),
.done(done),
.in(in),
.out(coreout),
.sram_a(i2c_sram_a),
.sram_d(sram_d),
.sram_ce(i2c_sram_ce),
.sram_oe(i2c_sram_oe),
.sram_we(i2c_sram_we),
.sram_lb(i2c_sram_lb),
.sram_ub(i2c_sram_ub));
// i2cdev panel
wire panelok = dev == 7'h26;
reg [1:0] state;
reg [7:0] addr;
reg [7:0] panelout;
always @(posedge clk) if(panelok) begin
if(start)
state <= 0;
if(stop && dir == 1)
addr <= addr - 8'b1; // needed for consecutive reads
if(dir == 0) begin // WRITE
if(done) begin
case(state)
0: begin // got device address
state <= 1;
end
1: begin // got write address
state <= 2;
addr <= in;
end
2: begin
case(addr)
'h0: mas[18:25] <= in;
'h1: mas[26:33] <= in;
'h2: mas[34:35] <= in[7:6];
'h3: datasw[0:7] <= in;
'h4: datasw[8:15] <= in;
'h5: datasw[16:23] <= in;
'h6: datasw[24:31] <= in;
'h7: datasw[32:35] <= in[7:4];
'h8: { sw_repeat, sw_addr_stop,
sw_power, sw_mem_disable } <= in[7:4];
'h9: { sw_rim_maint, sw_repeat_bypass, sw_art3_maint,
sw_sct_maint, sw_split_cyc } <= in[7:3];
'hA: { key_start,
key_inst_cont,
key_inst_stop,
key_io_reset,
key_dep,
key_ex,
key_reader_off,
key_punch_feed } <= in;
'hB: { key_read_in,
key_mem_cont,
key_mem_stop,
key_exec,
key_dep_nxt,
key_ex_nxt,
key_reader_on,
key_reader_feed } <= in;
endcase
addr <= addr + 8'b1;
end
endcase
end
end else if(dir == 1) begin
if(done) begin
if(sw_power)
case(addr)
8'h0: panelout <= ir[0:7];
8'h1: panelout <= ir[8:15];
8'h2: panelout <= { ir[16:17], 6'b0 };
8'h3: panelout <= pc[18:25];
8'h4: panelout <= pc[26:33];
8'h5: panelout <= { pc[34:35], 6'b0 };
8'h6: panelout <= mi[0:7];
8'h7: panelout <= mi[8:15];
8'h8: panelout <= mi[16:23];
8'h9: panelout <= mi[24:31];
8'hA: panelout <= { mi[32:35], 4'b0 };
8'hB: panelout <= ma[18:25];
8'hC: panelout <= ma[26:33];
8'hD: panelout <= { ma[34:35], 6'b0 };
8'hE: panelout <= { run, pih };
8'hF: panelout <= { mc_stop, pir };
8'h10: panelout <= { pi_active, pio };
8'h11: panelout <= { sw_repeat, sw_addr_stop,
sw_power, sw_mem_disable, 4'b0 };
8'h12: panelout <= mb[0:7];
8'h13: panelout <= mb[8:15];
8'h14: panelout <= mb[16:23];
8'h15: panelout <= mb[24:31];
8'h16: panelout <= { mb[32:35], 4'b0 };
8'h17: panelout <= ar[0:7];
8'h18: panelout <= ar[8:15];
8'h19: panelout <= ar[16:23];
8'h1A: panelout <= ar[24:31];
8'h1B: panelout <= { ar[32:35], 4'b0 };
8'h1C: panelout <= mq[0:7];
8'h1D: panelout <= mq[8:15];
8'h1E: panelout <= mq[16:23];
8'h1F: panelout <= mq[24:31];
8'h20: panelout <= { mq[32:35], 4'b0 };
8'h21: panelout <= ff[0];
8'h22: panelout <= ff[1];
8'h23: panelout <= ff[2];
8'h24: panelout <= ff[3];
8'h25: panelout <= ff[4];
8'h26: panelout <= ff[5];
8'h27: panelout <= ff[6];
8'h28: panelout <= ff[7];
8'h29: panelout <= ff[8];
8'h2A: panelout <= ff[9];
8'h2B: panelout <= ff[10];
8'h2C: panelout <= ff[11];
8'h2D: panelout <= ff[12];
8'h2E: panelout <= ff[13];
8'h2F: panelout <= pr;
8'h30: panelout <= rlr;
8'h31: panelout <= rla;
8'h32: panelout <= { 1'b0, tty_ind };
8'h33: panelout <= tti_ind;
default: panelout <= 8'hFF;
endcase
else
panelout <= 8'b0;
addr <= addr + 8'b1;
end
end
end
// front panel
reg [0:35] datasw;
reg [18:35] mas;
reg sw_repeat, sw_addr_stop;
reg sw_power, sw_mem_disable;
reg sw_rim_maint, sw_repeat_bypass;
reg sw_art3_maint, sw_sct_maint, sw_split_cyc;
reg key_start, key_read_in;
reg key_inst_cont, key_mem_cont;
reg key_inst_stop, key_mem_stop;
reg key_io_reset, key_exec;
reg key_dep, key_dep_nxt;
reg key_ex, key_ex_nxt;
reg key_reader_off, key_reader_on;
reg key_punch_feed, key_reader_feed;
wire [0:17] ir;
wire [0:35] mi;
wire [0:35] ar;
wire [0:35] mb;
wire [0:35] mq;
wire [18:35] pc;
wire [18:35] ma;
wire run;
wire mc_stop;
wire pi_active;
wire [1:7] pih;
wire [1:7] pir;
wire [1:7] pio;
wire [18:25] pr;
wire [18:25] rlr;
wire [18:25] rla;
wire [0:7] ff[13:0];
/* Mem bus */
wire membus_wr_rs_p0;
wire membus_rq_cyc_p0;
wire membus_rd_rq_p0;
wire membus_wr_rq_p0;
wire [21:35] membus_ma_p0;
wire [18:21] membus_sel_p0;
wire membus_fmc_select_p0;
wire membus_addr_ack_p0;
wire membus_rd_rs_p0;
wire [0:35] membus_mb_in_p0;
/* Out of apr0 */
wire [0:35] membus_mb_out_p0_p;
/* Out of fmem0 */
wire [0:35] membus_mb_out_p0_0;
wire membus_addr_ack_p0_0;
wire membus_rd_rs_p0_0;
/* Out of mem0 */
wire [0:35] membus_mb_out_p0_1;
wire membus_addr_ack_p0_1;
wire membus_rd_rs_p0_1;
/* IO bus */
wire iobus_iob_poweron;
wire iobus_iob_reset;
wire iobus_datao_clear;
wire iobus_datao_set;
wire iobus_cono_clear;
wire iobus_cono_set;
wire iobus_iob_fm_datai;
wire iobus_iob_fm_status;
wire [3:9] iobus_ios;
wire [1:7] iobus_pi_req = tty_pi_req;
wire [0:35] iobus_iob_in = apr_iob_out | tty_iob_out;
wire [0:35] apr_iob_out;
assign membus_mb_in_p0 = membus_mb_out_p0_p | membus_mb_out_p0_0 | membus_mb_out_p0_1;
assign membus_addr_ack_p0 = membus_addr_ack_p0_0 | membus_addr_ack_p0_1;
assign membus_rd_rs_p0 = membus_rd_rs_p0_0 | membus_rd_rs_p0_1;
apr apr0(
.clk(clk),
.reset(reset),
.key_start(key_start),
.key_read_in(key_read_in),
.key_inst_cont(key_inst_cont),
.key_mem_cont(key_mem_cont),
.key_inst_stop(key_inst_stop),
.key_mem_stop(key_mem_stop),
.key_io_reset(key_io_reset),
.key_exec(key_exec),
.key_dep(key_dep),
.key_dep_nxt(key_dep_nxt),
.key_ex(key_ex),
.key_ex_nxt(key_ex_nxt),
.sw_repeat(sw_repeat),
.sw_addr_stop(sw_addr_stop),
.sw_power(sw_power),
.sw_mem_disable(sw_mem_disable),
.datasw(datasw),
.mas(mas),
.sw_rim_maint(sw_rim_maint),
.sw_repeat_bypass(sw_repeat_bypass),
.sw_art3_maint(sw_art3_maint),
.sw_sct_maint(sw_sct_maint),
.sw_split_cyc(sw_split_cyc),
.ir(ir),
.mi(mi),
.ar(ar),
.mb(mb),
.mq(mq),
.pc(pc),
.ma(ma),
.run(run),
.mc_stop(mc_stop),
.pi_active(pi_active),
.pih(pih),
.pir(pir),
.pio(pio),
.pr(pr),
.rlr(rlr),
.rla(rla),
.ff0(ff[0]),
.ff1(ff[1]),
.ff2(ff[2]),
.ff3(ff[3]),
.ff4(ff[4]),
.ff5(ff[5]),
.ff6(ff[6]),
.ff7(ff[7]),
.ff8(ff[8]),
.ff9(ff[9]),
.ff10(ff[10]),
.ff11(ff[11]),
.ff12(ff[12]),
.ff13(ff[13]),
.membus_wr_rs(membus_wr_rs_p0),
.membus_rq_cyc(membus_rq_cyc_p0),
.membus_rd_rq(membus_rd_rq_p0),
.membus_wr_rq(membus_wr_rq_p0),
.membus_ma(membus_ma_p0),
.membus_sel(membus_sel_p0),
.membus_fmc_select(membus_fmc_select_p0),
.membus_mb_out(membus_mb_out_p0_p),
.membus_addr_ack(membus_addr_ack_p0),
.membus_rd_rs(membus_rd_rs_p0),
.membus_mb_in(membus_mb_in_p0),
.iobus_iob_poweron(iobus_iob_poweron),
.iobus_iob_reset(iobus_iob_reset),
.iobus_datao_clear(iobus_datao_clear),
.iobus_datao_set(iobus_datao_set),
.iobus_cono_clear(iobus_cono_clear),
.iobus_cono_set(iobus_cono_set),
.iobus_iob_fm_datai(iobus_iob_fm_datai),
.iobus_iob_fm_status(iobus_iob_fm_status),
.iobus_ios(iobus_ios),
.iobus_iob_out(apr_iob_out),
.iobus_pi_req(iobus_pi_req),
.iobus_iob_in(iobus_iob_in)
);
reg mem0_sw_single_step = 0;
reg mem0_sw_restart = 0;
fast162 fmem0(
.clk(clk),
.reset(reset),
.power(sw_power),
.sw_single_step(mem0_sw_single_step),
.sw_restart(mem0_sw_restart),
.membus_wr_rs_p0(membus_wr_rs_p0),
.membus_rq_cyc_p0(membus_rq_cyc_p0),
.membus_rd_rq_p0(membus_rd_rq_p0),
.membus_wr_rq_p0(membus_wr_rq_p0),
.membus_ma_p0(membus_ma_p0),
.membus_sel_p0(membus_sel_p0),
.membus_fmc_select_p0(membus_fmc_select_p0),
.membus_mb_in_p0(membus_mb_in_p0),
.membus_addr_ack_p0(membus_addr_ack_p0_0),
.membus_rd_rs_p0(membus_rd_rs_p0_0),
.membus_mb_out_p0(membus_mb_out_p0_0),
.membus_rq_cyc_p1(1'b0),
.membus_sel_p1(4'b0),
.membus_fmc_select_p1(1'b0),
.membus_rq_cyc_p2(1'b0),
.membus_sel_p2(4'b0),
.membus_fmc_select_p2(1'b0),
.membus_rq_cyc_p3(1'b0),
.membus_sel_p3(4'b0),
.membus_fmc_select_p3(1'b0)
);
core161c mem0(
.clk(clk),
.reset(reset),
.power(sw_power),
.sw_single_step(mem0_sw_single_step),
.sw_restart(mem0_sw_restart),
.membus_wr_rs_p0(membus_wr_rs_p0),
.membus_rq_cyc_p0(membus_rq_cyc_p0),
.membus_rd_rq_p0(membus_rd_rq_p0),
.membus_wr_rq_p0(membus_wr_rq_p0),
.membus_ma_p0(membus_ma_p0),
.membus_sel_p0(membus_sel_p0),
.membus_fmc_select_p0(membus_fmc_select_p0),
.membus_mb_in_p0(membus_mb_in_p0),
.membus_addr_ack_p0(membus_addr_ack_p0_1),
.membus_rd_rs_p0(membus_rd_rs_p0_1),
.membus_mb_out_p0(membus_mb_out_p0_1),
.membus_rq_cyc_p1(1'b0),
.membus_sel_p1(4'b0),
.membus_fmc_select_p1(1'b0),
.membus_rq_cyc_p2(1'b0),
.membus_sel_p2(4'b0),
.membus_fmc_select_p2(1'b0),
.membus_rq_cyc_p3(1'b0),
.membus_sel_p3(4'b0),
.membus_fmc_select_p3(1'b0),
.sram_a(core_sram_a),
.sram_d(sram_d),
.sram_ce(core_sram_ce),
.sram_oe(core_sram_oe),
.sram_we(core_sram_we),
.sram_lb(core_sram_lb),
.sram_ub(core_sram_ub)
);
wire [7:0] tti_ind;
wire [6:0] tty_ind;
wire [1:7] tty_pi_req;
wire [0:35] tty_iob_out;
tty tty0(
.clk(clk),
.rx(rx),
.tx(tx),
.tti_ind(tti_ind),
.status_ind(tty_ind),
.iobus_iob_poweron(iobus_iob_poweron),
.iobus_iob_reset(iobus_iob_reset),
.iobus_datao_clear(iobus_datao_clear),
.iobus_datao_set(iobus_datao_set),
.iobus_cono_clear(iobus_cono_clear),
.iobus_cono_set(iobus_cono_set),
.iobus_iob_fm_datai(iobus_iob_fm_datai),
.iobus_iob_fm_status(iobus_iob_fm_status),
.iobus_ios(iobus_ios),
.iobus_iob_in(iobus_iob_in),
.iobus_pi_req(tty_pi_req),
.iobus_iob_out(tty_iob_out)
);
assign ledr = { run, 1'b0, tti_ind };
assign ledg = { 1'b0, tty_ind };
/*
assign ledr[7:0] = sw == 0 ? datasw[0:5] :
sw == 1 ? datasw[6:11] :
sw == 2 ? datasw[12:17] :
sw == 3 ? datasw[18:23] :
sw == 4 ? datasw[24:29] :
sw == 5 ? datasw[30:35] :
sw == 6 ? { 4'b0, sw_repeat, sw_addr_stop, sw_power, sw_mem_disable } :
sw == 7 ? { key_start, key_inst_cont, key_inst_stop, key_io_reset, key_dep, key_ex, key_reader_off, key_punch_feed } :
6'b0;
assign ledg[7:0] = sw == 3 ? { 2'b0, mas[18:23] } :
sw == 4 ? { 2'b0, mas[24:29] } :
sw == 5 ? { 2'b0, mas[30:35] } :
sw == 6 ? { 3'b0, sw_rim_maint, sw_repeat_bypass, sw_art3_maint, sw_sct_maint, sw_split_cyc } :
sw == 7 ? { key_read_in, key_mem_cont, key_mem_stop, key_exec, key_dep_nxt, key_ex_nxt, key_reader_on, key_reader_feed } :
6'b0;
assign ledr[9:8] = 2'b0;
assign ledr[5:0] = sw == 0 ? mb[0:5] :
sw == 1 ? mb[6:11] :
sw == 2 ? mb[12:17] :
sw == 3 ? mb[18:23] :
sw == 4 ? mb[24:29] :
sw == 5 ? mb[30:35] :
sw == 6 ? ar[0:5] :
sw == 7 ? ar[6:11] :
sw == 8 ? ar[12:17] :
sw == 9 ? ar[18:23] :
sw == 10 ? ar[24:29] :
sw == 11 ? ar[30:35] :
sw == 12 ? mq[0:5] :
sw == 13 ? mq[6:11] :
sw == 14 ? mq[12:17] :
sw == 15 ? mq[18:23] :
sw == 16 ? mq[24:29] :
sw == 17 ? mq[30:35] : 0;
assign ledr[9:6] = 0;
assign ledg = 0;
*/
endmodule

113
verilog/quartus/i2c.v Normal file
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@ -0,0 +1,113 @@
`default_nettype none
module i2cslv(
input wire clk,
input wire reset,
input wire scl,
inout reg sda,
output wire ack,
output reg dir,
output reg [6:0] dev,
input wire ok,
output wire [7:0] in,
input wire [7:0] out,
output wire start,
output wire stop
);
localparam IDLE = 0;
localparam ADDR = 1;
localparam RECV = 2;
localparam SENDACK = 3;
localparam SEND = 4;
localparam RECVACK = 5;
localparam WRITE = 0;
localparam READ = 1;
reg [2:0] state;
reg [2:0] n;
reg [7:0] b;
reg sda0, sda1, scl0, scl1;
assign in = b;
assign ack = state == SENDACK || state == RECVACK;
assign start = scl1 & scl0 & sda1 & ~sda0;
assign stop = scl1 & scl0 & ~sda1 & sda0;
wire scl_rise = ~scl1 & scl0;
wire scl_fall = scl1 & ~scl0;
always @(posedge clk) begin
{ sda1, sda0 } <= { sda0, sda };
{ scl1, scl0 } <= { scl0, scl };
if(scl_rise)
n <= n + 3'b1;
if(start) begin
state <= ADDR;
n <= 0;
end
if(stop)
state <= IDLE;
case(state)
ADDR: begin
if(scl_rise) begin
if(n == 7) begin
dir <= sda;
if(ok)
state <= SENDACK;
else
state <= IDLE;
end else
dev <= { dev[5:0], sda };
end
end
RECV: begin
if(scl_fall)
sda <= 1'bz;
if(scl_rise) begin
if(n == 7)
state <= SENDACK;
b <= { b[6:0], sda };
end
end
SENDACK: begin
if(scl_fall)
sda <= 1'b0;
if(scl_rise) begin
if(dir == WRITE)
state <= RECV;
else begin
b <= out;
state <= SEND;
end
n <= 0;
end
end
SEND: begin
if(scl_fall) begin
if(b[7])
sda <= 1'bz;
else
sda <= 1'b0;
b <= b << 1;
end
if(scl_rise & n == 7)
state <= RECVACK;
end
RECVACK: begin
if(scl_fall)
sda <= 1'bz;
if(scl_rise) begin
b <= out;
if(sda)
state <= IDLE;
else
state <= SEND;
n <= 0;
end
end
endcase
end
endmodule

159
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module i2c_core(
input wire clk,
input wire reset,
input wire start,
input wire stop,
input wire dir,
input wire ok,
input wire done,
input wire [7:0] in,
output reg [7:0] out,
output reg [17:0] sram_a,
inout reg [15:0] sram_d,
output reg sram_ce,
output reg sram_oe,
output reg sram_we,
output reg sram_lb,
output reg sram_ub
);
localparam DEV = 0;
localparam ADDR = 1;
localparam DATA = 2;
reg [17:0] caddr; // core address
reg [11:0] d; // a third of a word
reg [1:0] state; // major state
reg [1:0] n; // minor state
// memory controller
reg [1:0] memstate;
reg memdir; // 0: read, 1: write
reg memdone;
initial begin
memstate <= 0;
memdone <= 0;
sram_a <= 0;
sram_d <= 16'bz;
sram_ce <= 1;
sram_oe <= 1;
sram_we <= 1;
sram_lb <= 1;
sram_ub <= 1;
end
always @(posedge clk) if(ok) begin
if(memdone)
memdone <= 0;
if(start) begin
state <= DEV;
n <= 0;
end
if(stop)
sram_a <= 0;
if(dir == 0 && done) // WRITE
case(state)
DEV: state <= ADDR;
ADDR: begin
caddr <= { caddr[11:0], in[5:0] };
if(n == 2) begin
state <= DATA;
n <= 0;
end else
n <= n + 2'b1;
end
DATA: begin
d <= { d[5:0], in[5:0] };
case(n)
0: begin // first 6 bits, came from ADDR
sram_a <= (caddr << 1) + caddr;
n <= 2;
end
1: n <= 2; // first 6 bits, else
2: begin // read second 6 bits
n <= 1;
// start write
memdir <= 1;
memstate <= 1;
end
endcase
end
endcase
else if(done) // READ
case(state)
DEV: begin
state <= DATA;
sram_a <= (caddr << 1) + caddr;
// two dummy bytes
out <= 8'b0;
d <= 12'b0000;
end
DATA: begin
case(n)
0: begin
out <= { 2'b0, d[5:0] };
n <= 1;
// get a new 16 bit word
memdir <= 0;
memstate <= 1;
end
1: begin
out <= { 2'b0, d[11:6] };
n <= 0;
end
endcase
end
endcase
// Talk to SRAM
if(memdir == 0) // read
case(memstate)
1: begin
sram_ce <= 0;
sram_oe <= 0;
sram_lb <= 0;
sram_ub <= 0;
memstate <= 2;
end
2: memstate <= 3;
3: begin
sram_a <= sram_a + 18'b1;
d <= sram_d[15:4];
sram_ce <= 1;
sram_oe <= 1;
sram_lb <= 1;
sram_ub <= 1;
memstate <= 0;
memdone <= 1;
end
endcase
else // write
case(memstate)
1: begin
sram_d <= { d, 4'b0 };
sram_ce <= 0;
sram_we <= 1;
sram_lb <= 0;
sram_ub <= 0;
memstate <= 2;
end
2: begin
sram_we <= 0;
memstate <= 3;
end
3: begin
sram_a <= sram_a + 18'b1;
sram_d <= 16'bz;
sram_ce <= 1;
sram_we <= 1;
sram_lb <= 1;
sram_ub <= 1;
memstate <= 0;
memdone <= 1;
end
endcase
end
endmodule

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module tto(input wire clk,
input wire tto_clock,
input wire [8:1] iob,
input wire tty_data_clr,
input wire tty_data_set,
output wire tx,
output reg tto_done = 0
);
reg [8:1] tto;
reg tto_out_line;
reg tto_enable = 0;
reg tto_active = 0;
reg tto_active0;
reg tto_div2 = 0;
reg tto_div20;
wire tto_4count;
wire tto_shift = tto_div20 & ~tto_div2;
count4 c(.clk(clk),
.reset(tto_active0 & ~tto_active),
.enable(tto_clock),
.out(tto_4count));
always @(posedge clk) begin
tto_active0 <= tto_active;
tto_div20 <= tto_div2;
if(tty_data_clr) begin
tto_done <= 0;
end
if(tty_data_set) begin
tto <= iob;
tto_enable <= 1;
end
if(tto_clock) begin
if(tto_active)
tto_div2 <= ~tto_div2;
if(tto_4count & tto_enable)
tto_active <= 1;
end
if(tto_shift) begin
tto_enable <= 0;
{ tto, tto_out_line } <= { tto_enable, tto };
if(~tto_enable & tto[8:2] == 0) begin
tto_active <= 0;
tto_done <= 1;
end
end
if(~tto_active)
tto_out_line <= 1;
else
if(~tto_active0)
tto_out_line <= 0;
end
assign tx = tto_out_line;
endmodule
module tti(input wire clk,
input wire tti_clock,
input wire rx,
output wire [8:1] iob,
output reg tti_active = 0,
output reg tti_done = 0,
output reg [8:1] tti = 0
);
assign iob = tti;
wire tti_shift = tti_4count_rise & ~tti_last_unit;
reg tti_last_unit = 0;
reg tti_active0;
wire tti_4count;
reg tti_4count0;
wire tti_space = ~rx;
wire tti_4count_rise = ~tti_4count0 & tti_4count;
wire tti_set = ~tti_active0 & tti_active;
div8 d(.clk(clk),
.reset(tti_set),
.enable(tti_clock & tti_active),
.out(tti_4count));
always @(posedge clk) begin
tti_4count0 <= tti_4count;
tti_active0 <= tti_active;
if(tti_set) begin
tti <= 8'o377;
tti_last_unit <= 0;
end
if(tti_4count_rise & tti_last_unit)
tti_active <= 0;
if(tti_shift) begin
tti <= { rx, tti[8:2] };
if(~tti[1]) begin
tti_last_unit <= 1;
tti_done <= 1;
end
if(tti[1])
tti_done <= 0;
if(~tti_space & (& tti))
tti_active <= 0;
end
if(tti_clock)
if(~tti_active & tti_space)
tti_active <= 1;
end
endmodule
module tty(
input wire clk,
input wire rx,
output wire tx,
output wire [7:0] tti_ind,
output wire [6:0] status_ind,
input wire iobus_iob_poweron,
input wire iobus_iob_reset,
input wire iobus_datao_clear,
input wire iobus_datao_set,
input wire iobus_cono_clear,
input wire iobus_cono_set,
input wire iobus_iob_fm_datai,
input wire iobus_iob_fm_status,
input wire [3:9] iobus_ios,
input wire [0:35] iobus_iob_in,
output wire [1:7] iobus_pi_req,
output wire [0:35] iobus_iob_out
);
wire clk2;
clk14khz clock2(.inclk(clk),
.outclk(clk2));
wire tti_clock, tto_clock;
clk16div ttidiv(.clk(clk),
.inclk(clk2),
.outclk(tti_clock));
clk4div ttodiv(.clk(clk),
.inclk(tti_clock),
.outclk(tto_clock));
wire tty_sel = iobus_ios == 7'b001_010_0;
wire tty_data_clr;
wire tty_data_set;
wire tty_ic_clr;
wire tty_ic_set;
wire tty_reset;
wire tty_datai = tty_sel & iobus_iob_fm_datai;
wire tty_status = tty_sel & iobus_iob_fm_status;
pg tty_pg0(.clk(clk), .reset(0),
.in(tty_sel & iobus_datao_clear),
.p(tty_data_clr));
pg tty_pg1(.clk(clk), .reset(0),
.in(tty_sel & iobus_datao_set),
.p(tty_data_set));
pg tty_pg2(.clk(clk), .reset(0),
.in(tty_sel & iobus_cono_clear),
.p(tty_ic_clr));
pg tty_pg3(.clk(clk), .reset(0),
.in(tty_sel & iobus_cono_set),
.p(tty_ic_set));
pg tty_pg4(.clk(clk), .reset(0),
.in(iobus_iob_reset),
.p(tty_reset));
assign iobus_iob_out =
tty_datai ? { 28'b0, tti_ind } :
tty_status ? { 29'b0, tti_busy, tti_flag, tto_busy, tto_flag, tty_pia } :
36'b0;
wire [0:7] tty_req = { tti_flag | tto_flag, 7'b0 } >> tty_pia;
assign iobus_pi_req = tty_req[1:7];
reg [33:35] tty_pia = 0;
reg tti_busy = 0;
reg tti_flag = 0;
reg tto_busy = 0;
reg tto_flag = 0;
wire tto_done;
reg tto_done0;
wire tti_done;
reg tti_done0;
wire tti_active;
reg tti_active0;
assign status_ind = { tti_busy, tti_flag, tto_busy, tto_flag, tty_pia };
always @(posedge clk) begin
tti_done0 <= tti_done;
tto_done0 <= tto_done;
tti_active0 <= tti_active;
if(tty_ic_clr | tty_reset)
tty_pia <= 0;
if(tty_reset) begin
tto_busy <= 0;
tto_flag <= 0;
tti_busy <= 0;
tti_flag <= 0;
end
if(tty_ic_set) begin
tty_pia <= iobus_iob_in[33:35];
if(iobus_iob_in[25])
tti_busy <= 0;
if(iobus_iob_in[26])
tti_flag <= 0;
if(iobus_iob_in[27])
tto_busy <= 0;
if(iobus_iob_in[28])
tto_flag <= 0;
if(iobus_iob_in[29])
tti_busy <= 1;
if(iobus_iob_in[30])
tti_flag <= 1;
if(iobus_iob_in[31])
tto_busy <= 1;
if(iobus_iob_in[32])
tto_flag <= 1;
end
if(tty_data_clr) begin
tto_flag <= 0;
tto_busy <= 1;
end
if(~tto_done0 & tto_done) begin
tto_flag <= 1;
tto_busy <= 0;
end
if(tty_datai)
tti_flag <= 0;
if(~tti_active0 & tti_active)
tti_busy <= 1;
if(~tti_done0 & tti_done) begin
tti_flag <= 1;
tti_busy <= 0;
end
end
wire [8:1] iob;
tti tti0(.clk(clk),
.tti_clock(tti_clock),
.rx(rx),
.iob(iob),
.tti_active(tti_active),
.tti_done(tti_done),
.tti(tti_ind));
tto tto0(.clk(clk),
.tto_clock(tto_clock),
.iob(iobus_iob_in[28:35]),
.tty_data_clr(tty_data_clr),
.tty_data_set(tty_data_set),
.tx(tx),
.tto_done(tto_done));
endmodule
module clk14khz(input wire inclk,
output wire outclk);
reg [11:0] cnt = 0;
assign outclk = cnt == 3551;
always @(posedge inclk)
if(outclk)
cnt <= 0;
else
cnt <= cnt + 12'b1;
endmodule
module clk16div(input wire clk,
input wire inclk,
output wire outclk
);
reg [4:0] cnt = 0;
assign outclk = cnt == 16;
always @(posedge clk)
if(outclk)
cnt <= 0;
else if(inclk)
cnt <= cnt + 5'b1;
endmodule
module div8(
input wire clk,
input wire reset,
input wire enable,
output wire out
);
reg [2:0] cnt = 4;
always @(posedge clk)
if(reset)
cnt <= 0;
else if(enable)
cnt <= cnt + 3'b1;
assign out = cnt[2];
endmodule
module count4(
input wire clk,
input wire reset,
input wire enable,
output wire out
);
reg [1:0] cnt = 0;
always @(posedge clk)
if(reset)
cnt <= 0;
else if(enable && cnt != 3)
cnt <= cnt + 2'b1;
assign out = cnt == 3;
endmodule
module clk4div(input wire clk,
input wire inclk,
output wire outclk
);
reg [2:0] cnt = 0;
assign outclk = cnt == 4;
always @(posedge clk)
if(outclk)
cnt <= 0;
else if(inclk)
cnt <= cnt + 3'b1;
endmodule