From 69613da23e2fd0a2ed92bb3580d4be5bc76d5a7b Mon Sep 17 00:00:00 2001 From: aap Date: Fri, 9 Dec 2016 23:31:27 +0100 Subject: [PATCH] changed verilog code for synthesis --- verilog/apr.v | 199 +++++++++++++++++++++++++++++---------------- verilog/core161c.v | 175 ++++++++++++++++++++++++++++++++------- verilog/fast162.v | 51 ++++++------ verilog/modules.v | 60 +++++--------- verilog/pdp6.v | 16 ++-- verilog/test.v | 23 ++---- 6 files changed, 337 insertions(+), 187 deletions(-) diff --git a/verilog/apr.v b/verilog/apr.v index 2b7548d..40bf77a 100644 --- a/verilog/apr.v +++ b/verilog/apr.v @@ -1,5 +1,3 @@ -`default_nettype none - module apr( input wire clk, input wire reset, @@ -34,25 +32,36 @@ module apr( input wire sw_split_cyc, // lights - output [0:17] ir, - output [0:35] mi, - output [0:35] ar, - output [0:35] mb, - output [0:35] mq, - output [18:35] pc, - output [18:35] ma, - output [0:8] fe, - output [0:8] sc, - output run, - output mc_stop, - output pi_active, - output [1:7] pih, - output [1:7] pir, - output [1:7] pio, - output [18:25] pr, - output [18:25] rlr, - output [18:25] rla, - // TODO: all the flipflops? + output reg [0:17] ir, + output reg [0:35] mi, + output reg [0:35] ar, + output reg [0:35] mb, + output reg [0:35] mq, + output reg [18:35] pc, + output reg [18:35] ma, + output reg run, + output reg mc_stop, + output reg pi_active, + output reg [1:7] pih, + output reg [1:7] pir, + output reg [1:7] pio, + output reg [18:25] pr, + output reg [18:25] rlr, + output wire [18:25] rla, + output wire [0:7] ff0, + output wire [0:7] ff1, + output wire [0:7] ff2, + output wire [0:7] ff3, + output wire [0:7] ff4, + output wire [0:7] ff5, + output wire [0:7] ff6, + output wire [0:7] ff7, + output wire [0:7] ff8, + output wire [0:7] ff9, + output wire [0:7] ff10, + output wire [0:7] ff11, + output wire [0:7] ff12, + output wire [0:7] ff13, // membus output wire membus_wr_rs, @@ -82,10 +91,28 @@ module apr( input wire [0:35] iobus_iob_in ); + assign ff0 = { key_ex_st, key_ex_sync, key_dep_st, key_dep_sync, key_rdwr, mc_rd, mc_wr, mc_rq }; + assign ff1 = { if1a, af0, af3, af3a, et4_ar_pse, f1a, f4a, f6a }; + assign ff2 = { sf3, sf5a, sf7, ar_com, blt_f0a, blt_f3a, blt_f5a, iot_f0a }; + assign ff3 = { fpf1, fpf2, faf1, faf2, faf3, faf4, fmf1, fmf2 }; + assign ff4 = { fdf1, fdf2, nr_round, nrf1, nrf2, nrf3, fsf1, chf7 }; + assign ff5 = { dsf1, dsf2, dsf3, dsf4, dsf5, dsf6, dsf7, dsf8 }; + assign ff6 = { dsf9, msf1, mpf1, mpf2, mc_split_cyc_sync, mc_stop_sync, shf1, sc_eq_777 }; + assign ff7 = { chf1, chf2, chf3, chf4, chf5, chf6, lcf1, dcf1 }; + assign ff8 = { pi_ov, pi_cyc, pi_rq, iot_go, a_long, ma_eq_mas, uuo_f1, cpa_pdl_ov }; + assign ff9 = fe[1:8]; + assign ff10 = sc[1:8]; + assign ff11 = { ~ex_user, cpa_illeg_op, ex_ill_op, ex_uuo_sync, ex_pi_sync, mq36, sc[0], fe[0] }; + assign ff12 = { key_rim_sbr, ar_cry0_xor_cry1, ar_cry0, ar_cry1, ar_ov_flag, ar_cry0_flag, ar_cry1_flag, ar_pc_chg_flag }; + assign ff13 = { cpa_non_exist_mem, cpa_clock_enable, cpa_clock_flag, cpa_pc_chg_enable, cpa_arov_enable, cpa_pia[33:35] }; + + // TODO: + reg a_long = 1'b0; + /* * KEY */ - reg run; + // reg run; reg key_ex_st; reg key_dep_st; reg key_ex_sync; @@ -133,7 +160,7 @@ module apr( wire key_rd = kt3 & key_ex_OR_ex_nxt; wire key_wr = kt3 & key_dp_OR_dp_nxt; - wire kt0a_D, kt1_D, kt2_D; + wire kt0a_D, kt1_D, kt2_D, kt3_D; pg key_pg0(.clk(clk), .reset(reset), .in(key_inst_stop), .p(run_clr)); pg key_pg1(.clk(clk), .reset(reset), .in(sw_power), .p(mr_pwr_clr)); pg key_pg2(.clk(clk), .reset(reset), .in(key_manual), .p(kt0)); @@ -167,7 +194,9 @@ module apr( dly100ns key_dly0(.clk(clk), .reset(reset), .in(kt0a), .p(kt0a_D)); dly200ns key_dly1(.clk(clk), .reset(reset), .in(kt1), .p(kt1_D)); dly200ns key_dly2(.clk(clk), .reset(reset), .in(kt2), .p(kt2_D)); + dly100ns key_dly3(.clk(clk), .reset(reset), .in(kt3), .p(kt3_D)); +`ifdef simulation /* add to this as needed */ always @(posedge reset) begin run <= 0; @@ -177,6 +206,7 @@ module apr( mb <= 0; mq <= 0; end +`endif always @(posedge clk) begin if(run_clr | @@ -236,7 +266,9 @@ module apr( pi_sync_D & if1a & ia_NOT_int), .p(it1)); pa i_pa3(.clk(clk), .reset(reset), - .in(mc_rs_t1 & if1a), + .in(mc_rs_t1 & if1a | + kt3_D & key_execute | + xct_t0_D), .p(it1a)); wire it0_D, iat0_D0, iat0_D1; @@ -600,7 +632,7 @@ module apr( /* * IR */ - reg [0:17] ir; + // reg [0:17] ir; assign iobus_ios = ir[3:9]; wire ir0_12_clr = mr_clr; wire ir13_17_clr = mr_clr | at5_D | cht8a; @@ -775,6 +807,11 @@ module apr( .in(et3 & ir_xct), .p(xct_t0)); + wire xct_t0_D; + dly200ns xct_dly0(.clk(clk), .reset(reset), + .in(xct_t0), + .p(xct_t0_D)); + /* * UUO */ @@ -804,7 +841,7 @@ module apr( /* * PC */ - reg [18:35] pc; + // reg [18:35] pc; wire pc_clr = et7 & pc_set | kt1 & key_start_OR_read_in; wire pc_fm_ma1 = et8 & pc_set | kt3 & key_start_OR_read_in; wire pc_inc = et0 & ~pc_inc_inh_et0 | @@ -835,7 +872,7 @@ module apr( if(pc_clr) pc <= 0; if(pc_inc) - pc <= pc + 1; + pc <= pc + 18'b1; if(pc_fm_ma1) pc <= pc | ma; end @@ -881,7 +918,7 @@ module apr( /* * MB */ - reg [0:35] mb; + // reg [0:35] mb; wire mblt_clr = et1 & ex_ir_uuo | mb_clr; wire mblt_fm_ar0 = mb_fm_arJ | mb_ar_swap | mb_fm_ar0 | cfac_mb_ar_swap; wire mblt_fm_ar1 = mb_fm_arJ | mb_ar_swap | cfac_mb_ar_swap; @@ -998,7 +1035,7 @@ module apr( /* * AR */ - reg [0:35] ar; + // reg [0:35] ar; reg ar_com_cont; reg ar_pc_chg_flag; reg ar_ov_flag; @@ -1035,13 +1072,13 @@ module apr( ir_rot ? ar[35] : (ir_ash | shc_ashc | ms_mult | ir_fdv) ? ar[0] : ir_div ? ~mq[35] : - ch_load | ir_lsh | ir_lshc ? 0 : - 0; // shouldn't happen + ch_load | ir_lsh | ir_lshc ? 1'b0 : + 1'b0; // shouldn't happen wire ar35_shl_inp = ir_rot ? ar[0] : shc_ashc ? mq[1] : ir_rotc | shc_lshc_OR_div ? mq[0] : - ch_dep | ir_lsh | ir_ash ? 0 : - 0; // shouldn't happen + ch_dep | ir_lsh | ir_ash ? 1'b0 : + 1'b0; // shouldn't happen wire shc_ashc = ir_ashc | nrf2 | faf3; wire shc_lshc_OR_div = ir_lshc | shc_div; @@ -1173,12 +1210,6 @@ module apr( dly100ns ar_dly4(.clk(clk), .reset(reset), .in(ar_cry_comp), .p(ar_cry_comp_D)); - dly100ns ar_dly5(.clk(clk), .reset(reset), - .in(ar_incdec_t0), - .p(ar_incdec_t0_D)); - dly100ns ar_dly6(.clk(clk), .reset(reset), - .in(ar_negate_t0), - .p(ar_negate_t0_D)); wire mst1_D; dly50ns ar_dly7(.clk(clk), .reset(reset), @@ -1186,11 +1217,11 @@ module apr( .p(mst1_D)); wire [0:35] ar_mb_cry = mb & ~ar; - wire [0:35] ar_cry_in = ar_cry_initiate ? { mb&~ar, 1'b0 } : + wire [0:35] ar_cry_in = ar_cry_initiate ? { mb[1:35]&~ar[1:35], 1'b0 } : ar35_cry_in & ar17_cry_in ? 36'o000001000001 : ar35_cry_in ? 36'o000000000001 : ar17_cry_in ? 36'o000001000000 : - 0; + 36'b0; // hold the cry out temporarily reg cry0, cry1; @@ -1240,7 +1271,7 @@ module apr( if(ar1_8_set) ar[1:8] <= 8'o377; if(ar_fm_sc1_8J) - ar[1:8] <= sc; + ar[1:8] <= sc[1:8]; if(ar0_5_fm_sc3_8J) ar[0:5] <= sc[3:8]; @@ -1270,7 +1301,7 @@ module apr( set_flags_et10 & ar_ov_set | cfac_overflow | et10 & ir_fwt & ~ar_cry0 & ar_cry1 | - sct1 & ~mb[18] & ir_ash_OR_ashc | ar0_xor_ar1) + sct1 & ~mb[18] & ir_ash_OR_ashc & ar0_xor_ar1) ar_ov_flag <= 1; if(ar_jfcl_clr & ir[10]) @@ -1306,7 +1337,7 @@ module apr( /* * MQ */ - reg [0:35] mq; + // reg [0:35] mq; reg mq36; wire mqlt_clr = mr_clr; wire mqlt_fm_mb0 = mq_fm_mbJ | cfac_mb_mq_swap; @@ -1325,9 +1356,9 @@ module apr( wire mq1_shr_inp = shc_ashc ? ar[35] : mq[0]; wire mq35_shl_inp = ir_rotc ? ar[0] : shc_div ? ~ar[0] : - ch_inc_op | ch_NOT_inc_op ? 1 : - ir_lshc | shc_ashc | ch_dep ? 0 : - 0; // shouldn't happen + ch_inc_op | ch_NOT_inc_op ? 1'b1 : + ir_lshc | shc_ashc | ch_dep ? 1'b0 : + 1'b0; // shouldn't happen wire mq_fm_mbJ = ft4 | ft4a | dst1 | mst1; wire mq35_xor_mb0 = mq[35] ^ mb[0]; @@ -1477,7 +1508,7 @@ module apr( if(sc_clr) sc <= 0; if(sc_inc) - sc <= sc + 1; + sc <= sc + 9'b1; if(sc_com) sc <= ~sc; if(sc_pad) @@ -1488,7 +1519,22 @@ module apr( sc <= sc | fe; if(sc_fm_mb18_28_35_0) sc <= sc | ~{ mb[18], mb[28:35] }; - // TODO: single bits + if(cht4a | fmt0a | fdt0a | mpt0 | ds_div_t0) + sc[0] <= 1; + if(fpt01 | fmt0a | fdt0a | mpt0 | ds_div_t0) + sc[1] <= 1; + if(fmt0a | fdt0a | mpt0 | ds_div_t0) + sc[2] <= 1; + if(fmt0a | fdt0a) + sc[3] <= 1; + if(cht4a | mpt0 | ds_div_t0) + sc[4:5] <= 2'b11; + if(fmt0a | mpt0) + sc[6] <= 1; + if(cht4a | ds_div_t0) + sc[7] <= 1; + if(cht4a | fdt0a | ds_div_t0) + sc[8] <= 1; end /* @@ -1668,10 +1714,10 @@ module apr( .in(sat3 & chf2), .p(cht3a)); pa ch_pa4(.clk(clk), .reset(reset), - .in(cht4a & ~sc[0]), + .in(cht3a & ~sc[0]), .p(cht4)); pa ch_pa5(.clk(clk), .reset(reset), - .in(ar_t3 & ~chf3), + .in(ar_t3 & chf3), .p(cht4a)); pa ch_pa6(.clk(clk), .reset(reset), .in(cht3a & sc[0]), @@ -2102,7 +2148,7 @@ module apr( /* * MA */ - reg [18:35] ma; + // reg [18:35] ma; reg ma32_cry_out; wire ma_clr = it0 | at0 | at3 | ft4a | key_ma_clr | iot_t0a | et1 & ma_clr_et1 | @@ -2149,9 +2195,12 @@ module apr( integer i; if(ma_clr) ma <= 0; - if(ma_inc) begin - {ma32_cry_out, ma[32:35]} = ma[32:35]+1; - ma[18:31] = ma[18:31] + (ma32_cry_out & ma31_cry_in_en); + if(ma_inc) + {ma32_cry_out, ma[32:35]} <= ma[32:35] + 4'b1; + if(ma32_cry_out) begin + if(ma31_cry_in_en) + ma[18:31] <= ma[18:31] + 14'b1; + ma32_cry_out <= 1'b0; end if(ma_fm_mbrt1) ma <= ma | mb[18:35]; @@ -2166,7 +2215,7 @@ module apr( /* * PR */ - reg [18:25] pr; + // reg [18:25] pr; wire pr18_ok = ma[18:25] <= pr; wire pr_rel_AND_ma_ok = ~ex_inh_rel & pr18_ok; wire pr_rel_AND_NOT_ma_ok = ~ex_inh_rel & ~pr18_ok; @@ -2174,8 +2223,9 @@ module apr( /* * RLR, RLA */ - reg [18:25] rlr; - wire [18:25] rla = ma[18:25] + (ex_inh_rel ? 0 : rlr); + // reg [18:25] rlr; + // wire [18:25] rla = ma[18:25] + (ex_inh_rel ? 0 : rlr); + assign rla = ma[18:25] + (ex_inh_rel ? 8'b0 : rlr); always @(posedge clk) begin if(ex_clr) begin @@ -2191,7 +2241,7 @@ module apr( /* * MI */ - reg [0:35] mi; + // reg [0:35] mi; wire milt_clr = mi_clr; wire milt_fm_mblt1 = mi_fm_mb1; wire mirt_clr = mi_clr; @@ -2231,7 +2281,7 @@ module apr( reg mc_rd; reg mc_wr; reg mc_rq; - reg mc_stop; + // reg mc_stop; reg mc_stop_sync; reg mc_split_cyc_sync; wire mc_sw_stop = key_mem_stop | sw_addr_stop; @@ -2491,19 +2541,19 @@ module apr( */ // pih contains the currently serviced pi reqs. // lower channels override higher ones. - reg [1:7] pih; + // reg [1:7] pih; wire pih_clr = pi_reset; wire pih_fm_pi_ch_rq = et0a & pi_hold; wire pih0_fm_pi_ok1 = et1 & pi_rst; // pir contains all current and allowed pi reqs. - reg [1:7] pir; + // reg [1:7] pir; wire pir_clr = pi_reset; wire pir_fm_iob1 = pi_cono_set & iob[24]; wire pir_stb; // pio is a mask of which pi reqs are allowed. - reg [1:7] pio; + // reg [1:7] pio; wire pio_fm_iob1 = pi_cono_set & iob[25]; wire pio0_fm_iob1 = pi_cono_set & iob[26]; @@ -2515,12 +2565,14 @@ module apr( // requests coming from the bus wire [1:7] iob_pi_req = iobus_pi_req | cpa_req; - genvar i; assign pi_ok[1] = pi_active; - for(i = 1; i <= 7; i = i + 1) begin - assign pi_req[i] = pi_ok[i] & ~pih[i] & pir[i]; - assign pi_ok[i+1] = pi_ok[i] & ~pih[i] & ~pir[i]; - end + genvar i; + generate + for(i = 1; i <= 7; i = i + 1) begin: pi_reg_gen + assign pi_req[i] = pi_ok[i] & ~pih[i] & pir[i]; + assign pi_ok[i+1] = pi_ok[i] & ~pih[i] & ~pir[i]; + end + endgenerate always @(posedge clk) begin: pirctl integer i; @@ -2529,7 +2581,7 @@ module apr( if(pih_fm_pi_ch_rq) pih <= pih | pi_req; if(pih0_fm_pi_ok1) - pih <= pih & ~pi_ok; + pih <= pih & ~pi_ok[1:7]; if(pir_clr) pir <= 0; @@ -2556,7 +2608,7 @@ module apr( */ reg pi_ov; reg pi_cyc; - reg pi_active; + // reg pi_active; wire pi_select = iobus_ios == 1; wire pi_status = pi_select & iobus_iob_fm_status; wire pi_cono_set = pi_select & iobus_cono_set; @@ -2627,8 +2679,11 @@ module apr( cpa_arov_enable & ar_ov_flag; wire [1:7] cpa_req; genvar j; - for(j = 1; j <= 7; j = j + 1) - assign cpa_req[j] = cpa_req_enable & (cpa_pia == j); + generate + for(j = 1; j <= 7; j = j + 1) begin: cpa_req_gen + assign cpa_req[j] = cpa_req_enable & (cpa_pia == j); + end + endgenerate wire [0:35] cpa_iob = { 18'b0, 1'b0, cpa_pdl_ov, cpa_iot_user, ex_user, diff --git a/verilog/core161c.v b/verilog/core161c.v index 3efbd1d..c2f5f54 100644 --- a/verilog/core161c.v +++ b/verilog/core161c.v @@ -52,13 +52,25 @@ module core161c( output wire membus_addr_ack_p3, output wire membus_rd_rs_p3, output wire [0:35] membus_mb_out_p3 + +`ifdef synthesis + , + output reg [17:0] sram_a, + inout reg [15:0] sram_d, + output reg sram_ce, + output reg sram_oe, + output reg sram_we, + output reg sram_lb, + output reg sram_ub +`endif ); /* Jumpers */ - reg [0:3] memsel_p0; - reg [0:3] memsel_p1; - reg [0:3] memsel_p2; - reg [0:3] memsel_p3; + parameter memsel_p0 = 4'b0; + parameter memsel_p1 = 4'b0; + parameter memsel_p2 = 4'b0; + parameter memsel_p3 = 4'b0; + reg [22:35] cma; reg cma_rd_rq; @@ -69,14 +81,16 @@ module core161c( reg cmc_p0_act, cmc_p1_act, cmc_p2_act, cmc_p3_act; reg cmc_last_proc; reg cmc_rd; - reg cmc_inhibit; + reg cmc_inhibit; // not really used reg cmc_wr; - reg cmc_await_rq; - reg cmc_proc_rs; + reg cmc_await_rq = 0; + reg cmc_proc_rs = 0; reg cmc_pse_sync; reg cmc_stop; - reg [0:35] core[0:040000]; +`ifdef simulation + reg [0:35] core[0:'o40000]; +`endif wire cyc_rq_p0 = memsel_p0 == membus_sel_p0 & ~membus_fmc_select_p0 & membus_rq_cyc_p0; @@ -94,43 +108,39 @@ module core161c( wire wr_rs = cmc_p0_act ? membus_wr_rs_p0 : cmc_p1_act ? membus_wr_rs_p1 : cmc_p2_act ? membus_wr_rs_p2 : - cmc_p3_act ? membus_wr_rs_p3 : 0; - wire rq_cyc = cmc_p0_act ? membus_rq_cyc_p0 : - cmc_p1_act ? membus_rq_cyc_p1 : - cmc_p2_act ? membus_rq_cyc_p2 : - cmc_p3_act ? membus_rq_cyc_p3 : 0; + cmc_p3_act ? membus_wr_rs_p3 : 1'b0; wire rd_rq = cmc_p0_act ? membus_rd_rq_p0 : cmc_p1_act ? membus_rd_rq_p1 : cmc_p2_act ? membus_rd_rq_p2 : - cmc_p3_act ? membus_rd_rq_p3 : 0; + cmc_p3_act ? membus_rd_rq_p3 : 1'b0; wire wr_rq = cmc_p0_act ? membus_wr_rq_p0 : cmc_p1_act ? membus_wr_rq_p1 : cmc_p2_act ? membus_wr_rq_p2 : - cmc_p3_act ? membus_wr_rq_p3 : 0; + cmc_p3_act ? membus_wr_rq_p3 : 1'b0; wire [21:35] ma = cmc_p0_act ? membus_ma_p0 : cmc_p1_act ? membus_ma_p1 : cmc_p2_act ? membus_ma_p2 : - cmc_p3_act ? membus_ma_p3 : 0; + cmc_p3_act ? membus_ma_p3 : 15'b0; wire [0:35] mb_in = cmc_p0_act ? membus_mb_in_p0 : cmc_p1_act ? membus_mb_in_p1 : cmc_p2_act ? membus_mb_in_p2 : - cmc_p3_act ? membus_mb_in_p3 : 0; + cmc_p3_act ? membus_mb_in_p3 : 36'b0; assign membus_addr_ack_p0 = cmc_addr_ack & cmc_p0_act; assign membus_rd_rs_p0 = cmc_rd_rs & cmc_p0_act; - assign membus_mb_out_p0 = cmc_p0_act ? mb_out : 0; + assign membus_mb_out_p0 = cmc_p0_act ? mb_out : 36'b0; assign membus_addr_ack_p1 = cmc_addr_ack & cmc_p1_act; assign membus_rd_rs_p1 = cmc_rd_rs & cmc_p1_act; - assign membus_mb_out_p1 = cmc_p1_act ? mb_out : 0; + assign membus_mb_out_p1 = cmc_p1_act ? mb_out : 36'b0; assign membus_addr_ack_p2 = cmc_addr_ack & cmc_p2_act; assign membus_rd_rs_p2 = cmc_rd_rs & cmc_p2_act; - assign membus_mb_out_p2 = cmc_p2_act ? mb_out : 0; + assign membus_mb_out_p2 = cmc_p2_act ? mb_out : 36'b0; assign membus_addr_ack_p3 = cmc_addr_ack & cmc_p3_act; assign membus_rd_rs_p3 = cmc_rd_rs & cmc_p3_act; - assign membus_mb_out_p3 = cmc_p3_act ? mb_out : 0; + assign membus_mb_out_p3 = cmc_p3_act ? mb_out : 36'b0; wire cmc_addr_ack; wire cmc_rd_rs; - wire [0:35] mb_out = mb_pulse_out ? core[cma] : 0; + wire [0:35] mb_out = mb_pulse_out ? sa : 36'b0; wire cmpc_rs_strb; wire cmc_pwr_clr; @@ -226,13 +236,28 @@ module core161c( dly250ns cmc_dly14(.clk(clk), .reset(reset), .in(cmc_strb_sa), .p(cmc_strb_sa_D2)); +`ifdef synthesis + reg [2:0] memstate; + reg [0:35] sa; // "sense amplifiers" + initial begin + sram_a <= 0; + sram_d <= 16'bz; + sram_ce <= 1; + sram_oe <= 1; + sram_we <= 1; + sram_lb <= 1; + sram_ub <= 1; + memstate <= 0; + end +`endif +`ifdef simulation + wire [0:35] sa = core[cma]; // "sense amplifiers" always @(posedge reset) begin cmc_await_rq <= 0; cmc_last_proc <= 0; cmc_proc_rs <= 0; end - - wire [0:35] corescope = core[cma]; +`endif always @(posedge clk) begin if(cmc_state_clr) begin @@ -244,7 +269,7 @@ module core161c( if(cmc_cmb_clr) cmb <= 0; if(cmc_strb_sa) - cmb <= cmb | core[cma]; + cmb <= cmb | sa; if(mb_pulse_in) cmb <= cmb | mb_in; if(cmpc_rs_strb) @@ -272,7 +297,7 @@ module core161c( end end if(cmc_t1) begin // this seems to be missing from the schematics - cma <= cma | ma; + cma <= cma | ma[22:35]; if(rd_rq) cma_rd_rq <= 1; if(wr_rq) @@ -284,10 +309,15 @@ module core161c( cmc_last_proc <= 0; if(cmc_p3_act) cmc_last_proc <= 1; +`ifdef synthesis + memstate <= 1; // start SRAM read +`endif end +`ifdef simulation if(cmc_t4) /* As a hack zero core here */ - core[cma] <= 0; + core[cma[32:35]] <= 0; +`endif if(cmc_t5) begin cmc_rd <= 0; cmc_pse_sync <= 1; @@ -297,12 +327,18 @@ module core161c( if(sw_single_step) cmc_stop <= 1; end - if(cmc_t8) + if(cmc_t8) begin cmc_wr <= 1; +`ifdef synthesis + memstate <= 1; // start SRAM write +`endif + end +`ifdef simulation if(cmc_t9 & cmc_wr) /* again a hack. core is written some time after t8. * (cmc_wr is always set here) */ - core[cma] <= core[cma] | cmb; + core[cma[32:35]] <= core[cma[32:35]] | cmb; +`endif if(cmc_t11) cmc_await_rq <= 1; if(cmc_t12) begin @@ -310,6 +346,87 @@ module core161c( cmc_inhibit <= 0; cmc_wr <= 0; end + +`ifdef synthesis + if(cmc_rd) + case(memstate) + 1: begin + sram_a <= (cma << 1) + cma; + sram_ce <= 0; + sram_oe <= 0; + sram_lb <= 0; + sram_ub <= 0; + memstate <= 2; + end + 2: memstate <= 3; + 3: begin + sram_a <= sram_a + 18'b1; + sa[0:11] <= sram_d[15:4]; + memstate <= 4; + end + 4: memstate <= 5; + 5: begin + sram_a <= sram_a + 18'b1; + sa[12:23] <= sram_d[15:4]; + memstate <= 6; + end + 6: memstate <= 7; + 7: begin + sram_a <= 0; + sa[24:35] <= sram_d[15:4]; + sram_ce <= 1; + sram_oe <= 1; + sram_lb <= 1; + sram_ub <= 1; + memstate <= 0; + end + endcase + if(cmc_wr) // write + case(memstate) + 1: begin + sram_a <= (cma << 1) + cma; + sram_d <= { cmb[0:11], 4'b0 }; + sram_ce <= 0; + sram_we <= 1; + sram_lb <= 0; + sram_ub <= 0; + memstate <= 2; + end + 2: begin + sram_we <= 0; + memstate <= 3; + end + 3: begin + sram_a <= sram_a + 18'b1; + sram_d <= { cmb[12:23], 4'b0 }; + sram_we <= 1; + memstate <= 4; + end + 4: begin + sram_we <= 0; + memstate <= 5; + end + 5: begin + sram_a <= sram_a + 18'b1; + sram_d <= { cmb[24:35], 4'b0 }; + sram_we <= 1; + memstate <= 6; + end + 6: begin + sram_we <= 0; + memstate <= 7; + end + 7: begin + sram_a <= 0; + sram_d <= 16'bz; + sram_ce <= 1; + sram_we <= 1; + sram_lb <= 1; + sram_ub <= 1; + memstate <= 0; + end + endcase +`endif end endmodule diff --git a/verilog/fast162.v b/verilog/fast162.v index 8df571b..a74aa22 100644 --- a/verilog/fast162.v +++ b/verilog/fast162.v @@ -55,18 +55,19 @@ module fast162( ); /* Jumpers */ - reg [0:3] memsel_p0; - reg [0:3] memsel_p1; - reg [0:3] memsel_p2; - reg [0:3] memsel_p3; - reg fmc_p0_sel; - reg fmc_p1_sel; - reg fmc_p2_sel; - reg fmc_p3_sel; + parameter memsel_p0 = 4'b0; + parameter memsel_p1 = 4'b0; + parameter memsel_p2 = 4'b0; + parameter memsel_p3 = 4'b0; + parameter fmc_p0_sel = 1'b1; + parameter fmc_p1_sel = 1'b0; + parameter fmc_p2_sel = 1'b0; + parameter fmc_p3_sel = 1'b0; + reg fmc_act; reg fmc_rd0; - reg fmc_rs; + reg fmc_rs; // not used, what is this? reg fmc_stop; reg fmc_wr; wire [0:35] fm_out = (fma != 0 | fmc_rd0) ? ff[fma] : 0; @@ -75,43 +76,39 @@ module fast162( wire wr_rs = fmc_p0_sel ? membus_wr_rs_p0 : fmc_p1_sel ? membus_wr_rs_p1 : fmc_p2_sel ? membus_wr_rs_p2 : - fmc_p3_sel ? membus_wr_rs_p3 : 0; - wire rq_cyc = fmc_p0_sel ? membus_rq_cyc_p0 : - fmc_p1_sel ? membus_rq_cyc_p1 : - fmc_p2_sel ? membus_rq_cyc_p2 : - fmc_p3_sel ? membus_rq_cyc_p3 : 0; + fmc_p3_sel ? membus_wr_rs_p3 : 1'b0; wire fma_rd_rq = fmc_p0_sel ? membus_rd_rq_p0 : fmc_p1_sel ? membus_rd_rq_p1 : fmc_p2_sel ? membus_rd_rq_p2 : - fmc_p3_sel ? membus_rd_rq_p3 : 0; + fmc_p3_sel ? membus_rd_rq_p3 : 1'b0; wire fma_wr_rq = fmc_p0_sel ? membus_wr_rq_p0 : fmc_p1_sel ? membus_wr_rq_p1 : fmc_p2_sel ? membus_wr_rq_p2 : - fmc_p3_sel ? membus_wr_rq_p3 : 0; + fmc_p3_sel ? membus_wr_rq_p3 : 1'b0; wire [21:35] fma = fmc_p0_sel ? membus_ma_p0[32:35] : fmc_p1_sel ? membus_ma_p1[32:35] : fmc_p2_sel ? membus_ma_p2[32:35] : - fmc_p3_sel ? membus_ma_p3[32:35] : 0; - wire [0:35] mb_in = fmc_p0_sel ? membus_mb_in_p0 : - fmc_p1_sel ? membus_mb_in_p1 : - fmc_p2_sel ? membus_mb_in_p2 : - fmc_p3_sel ? membus_mb_in_p3 : 0; + fmc_p3_sel ? membus_ma_p3[32:35] : 1'b0; + wire [0:35] mb_in = fmc_p0_wr_sel ? membus_mb_in_p0 : + fmc_p1_wr_sel ? membus_mb_in_p1 : + fmc_p2_wr_sel ? membus_mb_in_p2 : + fmc_p3_wr_sel ? membus_mb_in_p3 : 1'b0; assign membus_addr_ack_p0 = fmc_addr_ack & fmc_p0_sel; assign membus_rd_rs_p0 = fmc_rd_rs & fmc_p0_sel; - assign membus_mb_out_p0 = fmc_p0_sel ? mb_out : 0; + assign membus_mb_out_p0 = fmc_p0_sel ? mb_out : 1'b0; assign membus_addr_ack_p1 = fmc_addr_ack & fmc_p1_sel; assign membus_rd_rs_p1 = fmc_rd_rs & fmc_p1_sel; - assign membus_mb_out_p1 = fmc_p1_sel ? mb_out : 0; + assign membus_mb_out_p1 = fmc_p1_sel ? mb_out : 1'b0; assign membus_addr_ack_p2 = fmc_addr_ack & fmc_p2_sel; assign membus_rd_rs_p2 = fmc_rd_rs & fmc_p2_sel; - assign membus_mb_out_p2 = fmc_p2_sel ? mb_out : 0; + assign membus_mb_out_p2 = fmc_p2_sel ? mb_out : 1'b0; assign membus_addr_ack_p3 = fmc_addr_ack & fmc_p3_sel; assign membus_rd_rs_p3 = fmc_rd_rs & fmc_p3_sel; - assign membus_mb_out_p3 = fmc_p3_sel ? mb_out : 0; + assign membus_mb_out_p3 = fmc_p3_sel ? mb_out : 1'b0; wire fmc_addr_ack; wire fmc_rd_rs; - wire [0:35] mb_out = fmc_rd_strb ? fm_out : 0; + wire [0:35] mb_out = fmc_rd_strb ? fm_out : 36'b0; wire fmc_p0_sel1 = fmc_p0_sel & ~fmc_stop; wire fmc_p1_sel1 = fmc_p1_sel & ~fmc_stop; @@ -195,9 +192,11 @@ module fast162( bd fmc_bd1(.clk(clk), .reset(reset), .in(fmct1), .p(fmc_rd_rs)); bd2 fmc_bd2(.clk(clk), .reset(reset), .in(fmct1), .p(fmc_rd_strb)); +`ifdef simulation always @(posedge reset) begin fmc_act <= 0; end +`endif always @(posedge clk) begin if(fmc_restart | fmc_pwr_on) begin diff --git a/verilog/modules.v b/verilog/modules.v index 29b89a7..a5f1462 100644 --- a/verilog/modules.v +++ b/verilog/modules.v @@ -1,15 +1,3 @@ -/*module pireq( - input wire piok_in, - input wire pih, - input wire pir, - output wire pireq, - output wire piok_out -); - wire a = piok_in & ~pih; - assign pireq = a & pir; - assign piok_out = a & ~pir; -endmodule*/ - module pg( input clk, input reset, @@ -25,8 +13,7 @@ module pg( assign p = x[0] & !x[1]; endmodule -module pa(input clk, input reset, input in, output p); - reg p; +module pa(input clk, input reset, input in, output reg p); always @(posedge clk or posedge reset) if(reset) p <= 0; @@ -42,7 +29,7 @@ module bd(input clk, input reset, input in, output p); r <= 0; else begin if(r) - r <= r + 1; + r <= r + 3'b1; if(in) r <= 1; end @@ -52,7 +39,7 @@ endmodule /* Same as above but with longer pulse. Used to pulse mb * because one more clock cycle is needed to get the data - * after the pulse has been synchronizes. */ + * after the pulse has been synchronized. */ module bd2(input clk, input reset, input in, output p); reg [2:0] r; always @(posedge clk or posedge reset) begin @@ -60,12 +47,12 @@ module bd2(input clk, input reset, input in, output p); r <= 0; else begin if(r) - r <= r + 1; + r <= r + 3'b1; if(in) r <= 1; end end - assign p = r == 4 || r == 5; + assign p = r == 4 || r == 5 || r == 6 || r == 7; endmodule module dly50ns(input clk, input reset, input in, output p); @@ -75,7 +62,7 @@ module dly50ns(input clk, input reset, input in, output p); r <= 0; else begin if(r) - r <= r + 1; + r <= r + 3'b1; if(in) r <= 1; end @@ -90,7 +77,7 @@ module dly70ns(input clk, input reset, input in, output p); r <= 0; else begin if(r) - r <= r + 1; + r <= r + 4'b1; if(in) r <= 1; end @@ -105,7 +92,7 @@ module dly100ns(input clk, input reset, input in, output p); r <= 0; else begin if(r) - r <= r + 1; + r <= r + 4'b1; if(in) r <= 1; end @@ -120,7 +107,7 @@ module dly150ns(input clk, input reset, input in, output p); r <= 0; else begin if(r) - r <= r + 1; + r <= r + 5'b1; if(in) r <= 1; end @@ -135,7 +122,7 @@ module dly200ns(input clk, input reset, input in, output p); r <= 0; else begin if(r) - r <= r + 1; + r <= r + 5'b1; if(in) r <= 1; end @@ -150,7 +137,7 @@ module dly250ns(input clk, input reset, input in, output p); r <= 0; else begin if(r) - r <= r + 1; + r <= r + 5'b1; if(in) r <= 1; end @@ -165,7 +152,7 @@ module dly400ns(input clk, input reset, input in, output p); r <= 0; else begin if(r) - r <= r + 1; + r <= r + 6'b1; if(in) r <= 1; end @@ -180,7 +167,7 @@ module dly800ns(input clk, input reset, input in, output p); r <= 0; else begin if(r) - r <= r + 1; + r <= r + 7'b1; if(in) r <= 1; end @@ -195,7 +182,7 @@ module dly1us(input clk, input reset, input in, output p); r <= 0; else begin if(r) - r <= r + 1; + r <= r + 7'b1; if(in) r <= 1; end @@ -203,16 +190,15 @@ module dly1us(input clk, input reset, input in, output p); assign p = r == 102; endmodule -module ldly1us(input clk, input reset, input in, output p, output l); +module ldly1us(input clk, input reset, input in, output p, output reg l); reg [6:0] r; - reg l; always @(posedge clk or posedge reset) begin if(reset) begin l <= 0; r <= 0; end else begin if(r) - r <= r + 1; + r <= r + 7'b1; if(in) begin l <= 1; r <= 1; @@ -226,16 +212,15 @@ module ldly1us(input clk, input reset, input in, output p, output l); assign p = r == 102; endmodule -module ldly1_5us(input clk, input reset, input in, output p, output l); +module ldly1_5us(input clk, input reset, input in, output p, output reg l); reg [7:0] r; - reg l; always @(posedge clk or posedge reset) begin if(reset) begin l <= 0; r <= 0; end else begin if(r) - r <= r + 1; + r <= r + 8'b1; if(in) begin l <= 1; r <= 1; @@ -249,16 +234,15 @@ module ldly1_5us(input clk, input reset, input in, output p, output l); assign p = r == 152; endmodule -module ldly2us(input clk, input reset, input in, output p, output l); +module ldly2us(input clk, input reset, input in, output p, output reg l); reg [7:0] r; - reg l; always @(posedge clk or posedge reset) begin if(reset) begin l <= 0; r <= 0; end else begin if(r) - r <= r + 1; + r <= r + 8'b1; if(in) begin l <= 1; r <= 1; @@ -279,7 +263,7 @@ module dly100us(input clk, input reset, input in, output p); r <= 0; else begin if(r) - r <= r + 1; + r <= r + 16'b1; if(in) r <= 1; end @@ -294,7 +278,7 @@ module ldly100us(input clk, input reset, input in, output p, output l); r <= 0; else begin if(r) - r <= r + 1; + r <= r + 16'b1; if(in) r <= 1; end diff --git a/verilog/pdp6.v b/verilog/pdp6.v index 58a95bc..1ebecf0 100644 --- a/verilog/pdp6.v +++ b/verilog/pdp6.v @@ -41,8 +41,6 @@ module pdp6( wire [0:35] mq; wire [18:35] pc; wire [18:35] ma; - wire [0:8] fe; - wire [0:8] sc; wire run; wire mc_stop; wire pi_active; @@ -136,8 +134,6 @@ module pdp6( .mq(mq), .pc(pc), .ma(ma), - .fe(fe), - .sc(sc), .run(run), .mc_stop(mc_stop), .pi_active(pi_active), @@ -177,7 +173,12 @@ module pdp6( reg mem0_sw_single_step; reg mem0_sw_restart; - fast162 fmem0( + fast162 + #(.memsel_p0(4'b0), .memsel_p1(4'b0), + .memsel_p2(4'b0), .memsel_p3(4'b0), + .fmc_p0_sel(1'b1), .fmc_p1_sel(1'b0), + .fmc_p2_sel(1'b0), .fmc_p3_sel(1'b0)) + fmem0( .clk(clk), .reset(reset), .power(sw_power), @@ -209,7 +210,10 @@ module pdp6( .membus_fmc_select_p3(1'b0) ); - core161c mem0( + core161c + #(.memsel_p0(4'b0), .memsel_p1(4'b0), + .memsel_p2(4'b0), .memsel_p3(4'b0)) + mem0( .clk(clk), .reset(reset), .power(sw_power), diff --git a/verilog/test.v b/verilog/test.v index ee7e916..ec48a3a 100644 --- a/verilog/test.v +++ b/verilog/test.v @@ -1,4 +1,5 @@ `timescale 1ns/1ns +`define simulation module clock(output reg clk); initial @@ -8,8 +9,8 @@ module clock(output reg clk); endmodule //`define TESTKEY pdp6.key_inst_stop -`define TESTKEY pdp6.key_read_in -//`define TESTKEY pdp6.key_start +//`define TESTKEY pdp6.key_read_in +`define TESTKEY pdp6.key_start //`define TESTKEY pdp6.key_exec //`define TESTKEY pdp6.key_ex //`define TESTKEY pdp6.key_dep @@ -132,19 +133,6 @@ module test; pdp6.mem0_sw_single_step = 0; pdp6.mem0_sw_restart = 0; - pdp6.fmem0.memsel_p0 = 0; - pdp6.fmem0.memsel_p1 = 0; - pdp6.fmem0.memsel_p2 = 0; - pdp6.fmem0.memsel_p3 = 0; - pdp6.fmem0.fmc_p0_sel = 1; - pdp6.fmem0.fmc_p1_sel = 0; - pdp6.fmem0.fmc_p2_sel = 0; - pdp6.fmem0.fmc_p3_sel = 0; - pdp6.mem0.memsel_p0 = 0; - pdp6.mem0.memsel_p1 = 0; - pdp6.mem0.memsel_p2 = 0; - pdp6.mem0.memsel_p3 = 0; - end /* @@ -161,7 +149,7 @@ module test; #20 reset = 0; pdp6.datasw = 36'o111777222666; - pdp6.mas = 18'o000067; + pdp6.mas = 18'o000070; for(i = 0; i < 'o40000; i = i + 1) pdp6.mem0.core[i] = 0; @@ -180,8 +168,10 @@ module test; pdp6.fmem0.ff['o11] = 36'o440600_001000; // char ptr pdp6.fmem0.ff['o12] = 36'o300600_001000; // char ptr pdp6.fmem0.ff['o13] = 36'o000000_005555; // char + pdp6.fmem0.ff['o14] = 36'o010700_001017; pdp6.fmem0.ff['o17] = 36'o777000_001000; // PDL ptr // pdp6.fmem0.ff['o17] = 36'o777000_777777; // PDL ptr + pdp6.mem0.core['o20] = 36'o200_064_000104; // MOVE 1,@104(4) FAC_INH pdp6.mem0.core['o21] = 36'o202_064_000104; // MOVEM 1,@104(4) pdp6.mem0.core['o22] = 36'o245_100_000003; // ROTC 2,3 @@ -207,6 +197,7 @@ module test; pdp6.mem0.core['o65] = 36'o135_000_000012; // LBP 0,12 pdp6.mem0.core['o66] = 36'o134_000_000012; // ILBP 0,12 pdp6.mem0.core['o67] = 36'o137_540_000012; // DBP 13,12 + pdp6.mem0.core['o70] = 36'o134_000_000014; // ILBP 0,14 pdp6.mem0.core['o1000] = 36'o50_45_54_54_57_00; pdp6.mem0.core['o10410] = 36'o000_000_000333;