From 77c02726f50172ee814c55675bf2e241e2b4373d Mon Sep 17 00:00:00 2001
From: aap <aap@papnet.eu>
Date: Tue, 29 Oct 2019 18:17:32 +0100
Subject: [PATCH] verilog: passing diags part5

---
 verilog/apr.v       |  4 ++--
 verilog/tb/tb_apr.v | 15 +++++----------
 2 files changed, 7 insertions(+), 12 deletions(-)

diff --git a/verilog/apr.v b/verilog/apr.v
index c1f5923..9a9b5fb 100644
--- a/verilog/apr.v
+++ b/verilog/apr.v
@@ -1067,7 +1067,7 @@ module apr(
 		if(mb1_8_clr)
 			mb[1:8] <= 0;
 		if(mb1_8_set)
-			mb[1:8] <= 1;
+			mb[1:8] <= 8'o377;
 		if(mb_fm_misc_bits1) begin
 			if(ar_ov_flag) mb[0] <= 1;
 			if(ar_cry0_flag) mb[1] <= 1;
@@ -1607,7 +1607,7 @@ module apr(
 	wire cfac_overflow = mpt0a & mpf2 & ar[0] |
 		mpt1 & ~ar_eq_0 |
 		nrt3 & ~sc[0] |
-		dst0a & ~ar0_eq_sc0 |
+		fst0a & ~ar0_eq_sc0 |
 		dst13;
 	wire cfac_ar_sh_lt = dst14a | nrt2 |
 		sct1 & (dcf1 | shift_op & ~mb[18]);
diff --git a/verilog/tb/tb_apr.v b/verilog/tb/tb_apr.v
index 38c941d..aa699ad 100644
--- a/verilog/tb/tb_apr.v
+++ b/verilog/tb/tb_apr.v
@@ -231,15 +231,12 @@ module tb_apr();
 		cmem.core['o52] <= 36'o334000_000000;
 		cmem.core['o53] <= 36'o000000_000000;
 
-		cmem.core['o1733] <= 36'o300000_000000;
-		cmem.core['o1734] <= 36'o254400001736;	// jrst 10,1736
-		cmem.core['o1735] <= 36'o254200000000;
-		cmem.core['o1736] <= 36'o254200000001;
-		cmem.core['o1737] <= 36'o254200000002;
+		cmem.core['o100] <= 36'o173040000000;
+		cmem.core['o101] <= 36'o254200000000;
 
-		fmem.ff[0] <= 36'o0;
-		fmem.ff[1] <= 36'o0;
-		mas <= 'o1733;
+		fmem.ff[0] <= 36'o611042323251;
+		fmem.ff[1] <= 36'o472340710317;
+		mas <= 'o100;
 
 		#200;
 		sw_power <= 1;
@@ -247,8 +244,6 @@ module tb_apr();
 		#200;
 //		key_mem_stop <= 1;
 
-		apr.pir <= 'o177;
-		apr.pi_active <= 1;
 		key_start <= 1;
 		#1000;
 		key_start <= 0;