From 844810b24991947550bf300de1f3726700df3f49 Mon Sep 17 00:00:00 2001 From: aap Date: Thu, 24 Nov 2016 11:04:41 +0100 Subject: [PATCH] verilog BLT --- verilog/apr.v | 99 +++++++++++++++++++++++++++++++++++------- verilog/core161c.v | 2 +- verilog/test.gtkw | 106 ++++++++++++++++++++++++++++++++++++++++----- verilog/test.v | 30 +++++++++---- 4 files changed, 200 insertions(+), 37 deletions(-) diff --git a/verilog/apr.v b/verilog/apr.v index 956a889..fb87245 100644 --- a/verilog/apr.v +++ b/verilog/apr.v @@ -335,8 +335,8 @@ module apr( wire ft6; wire ft6a; wire ft7; - wire f_c_c_aclt = jp_pop | jp_popj; - wire f_c_c_acrt = jp_jra | ir_blt; + wire f_c_c_aclt = jp_jra | ir_blt; + wire f_c_c_acrt = jp_pop | jp_popj; wire f_ac_2 = sh_ac_2 | ir_md_f_ac_2; wire f_c_c_aclt_OR_rt = f_c_c_aclt | f_c_c_acrt; wire f_ac_2_etc = f_c_c_aclt_OR_rt | f_ac_2; @@ -1458,7 +1458,9 @@ module apr( wire cfac_ar_add = 0; wire cfac_ar_sub = 0; wire cfac_mb_fm_mqJ = 0; - wire cfac_mb_mq_swap = 0; + wire cfac_mb_mq_swap = dst2 | dst3 | dst7 | + dst9 | dst19a | dst21a | + blt_t0 | blt_t3a | blt_t5; wire cfac_mb_ar_swap = 0; wire cfac_ar_com = 0; wire cfac_overflow = 0; @@ -1477,25 +1479,90 @@ module apr( reg blt_f0a; reg blt_f3a; reg blt_f5a; - wire blt_done = 0; - wire blt_last = 0; + wire blt_done = ~mq[0] | pi_rq; + wire blt_last = ir_blt & ~mq[0]; - wire blt_t0 = 0; - wire blt_t0a = 0; - wire blt_t1 = 0; - wire blt_t2 = 0; - wire blt_t3 = 0; - wire blt_t3a = 0; - wire blt_t4 = 0; - wire blt_t5 = 0; - wire blt_t5a = 0; - wire blt_t6 = 0; + wire blt_t0; + wire blt_t0a; + wire blt_t1; + wire blt_t2; + wire blt_t3; + wire blt_t3a; + wire blt_t4; + wire blt_t5; + wire blt_t5a; + wire blt_t6; - wire blt_t6_D; + pa blt_pa0(.clk(clk), .reset(reset), + .in(et3 & ir_blt), + .p(blt_t0)); + pa blt_pa1(.clk(clk), .reset(reset), + .in(mc_rs_t1 & blt_f0a), + .p(blt_t0a)); + pa blt_pa2(.clk(clk), .reset(reset), + .in(blt_t0a_D), + .p(blt_t1)); + pa blt_pa3(.clk(clk), .reset(reset), + .in(blt_t1_D), + .p(blt_t2)); + pa blt_pa4(.clk(clk), .reset(reset), + .in(blt_t2_D), + .p(blt_t3)); + pa blt_pa5(.clk(clk), .reset(reset), + .in(ar_t3 & blt_f3a), + .p(blt_t3a)); + pa blt_pa6(.clk(clk), .reset(reset), + .in(blt_t3a_D), + .p(blt_t4)); + pa blt_pa7(.clk(clk), .reset(reset), + .in(blt_t4_D), + .p(blt_t5)); + pa blt_pa8(.clk(clk), .reset(reset), + .in(ar_t3 & blt_f5a), + .p(blt_t5a)); + pa blt_pa9(.clk(clk), .reset(reset), + .in(blt_t5a & ~blt_done), + .p(blt_t6)); + + wire blt_t0a_D, blt_t1_D; + wire blt_t2_D, blt_t3a_D; + wire blt_t4_D, blt_t6_D; dly100ns blt_dly0(.clk(clk), .reset(reset), + .in(blt_t0a), + .p(blt_t0a_D)); + dly100ns blt_dly1(.clk(clk), .reset(reset), + .in(blt_t1), + .p(blt_t1_D)); + dly100ns blt_dly2(.clk(clk), .reset(reset), + .in(blt_t2), + .p(blt_t2_D)); + dly100ns blt_dly3(.clk(clk), .reset(reset), + .in(blt_t3a), + .p(blt_t3a_D)); + dly100ns blt_dly4(.clk(clk), .reset(reset), + .in(blt_t4), + .p(blt_t4_D)); + dly100ns blt_dly5(.clk(clk), .reset(reset), .in(blt_t6), .p(blt_t6_D)); + always @(posedge clk) begin + if(mr_clr | blt_t0a) + blt_f0a <= 0; + if(blt_t0) + blt_f0a <= 1; + + if(mr_clr | blt_t3a) + blt_f3a <= 0; + if(blt_t3) + blt_f3a <= 1; + + if(mr_clr | blt_t5a) + blt_f5a <= 0; + if(blt_t5) + blt_f5a <= 1; + end + /* * FS */ diff --git a/verilog/core161c.v b/verilog/core161c.v index 4136e5e..3efbd1d 100644 --- a/verilog/core161c.v +++ b/verilog/core161c.v @@ -76,7 +76,7 @@ module core161c( reg cmc_pse_sync; reg cmc_stop; - reg [0:36] core[0:040000]; + reg [0:35] core[0:040000]; wire cyc_rq_p0 = memsel_p0 == membus_sel_p0 & ~membus_fmc_select_p0 & membus_rq_cyc_p0; diff --git a/verilog/test.gtkw b/verilog/test.gtkw index cce817e..b1cff61 100644 --- a/verilog/test.gtkw +++ b/verilog/test.gtkw @@ -1,18 +1,18 @@ [*] [*] GTKWave Analyzer v3.3.76 (w)1999-2016 BSI -[*] Mon Nov 21 10:43:37 2016 +[*] Thu Nov 24 10:04:34 2016 [*] [dumpfile] "/home/aap/src/pdp6/verilog/dump.vcd" -[dumpfile_mtime] "Mon Nov 21 10:38:44 2016" -[dumpfile_size] 250577 +[dumpfile_mtime] "Thu Nov 24 09:54:12 2016" +[dumpfile_size] 223600 [savefile] "/home/aap/src/pdp6/verilog/test.gtkw" -[timestart] 4906 +[timestart] 4587 [size] 1920 1080 [pos] -1 -1 -*-7.734977 5505 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +*-10.555068 11855 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 [treeopen] test. [treeopen] test.pdp6. -[treeopen] test.pdp6.mem0. +[treeopen] test.pdp6.fmem0. [sst_width] 337 [signals_width] 442 [sst_expanded] 1 @@ -181,6 +181,9 @@ test.pdp6.apr0.f_c_c_aclt test.pdp6.apr0.f_c_c_acrt test.pdp6.apr0.f_ac_2 test.pdp6.apr0.f_ac_2_etc +@200 +- +@28 test.pdp6.apr0.ft0 test.pdp6.apr0.ft1 test.pdp6.apr0.f1a @@ -203,7 +206,9 @@ test.pdp6.apr0.et0a test.pdp6.apr0.et0 test.pdp6.apr0.et1 test.pdp6.apr0.et3 +test.pdp6.apr0.et4_inh test.pdp6.apr0.et4 +test.pdp6.apr0.et5_inh test.pdp6.apr0.et5 test.pdp6.apr0.et6 test.pdp6.apr0.et7 @@ -212,12 +217,14 @@ test.pdp6.apr0.et9 test.pdp6.apr0.et10 @1401200 -E -@c00200 +@800200 -S @28 test.pdp6.apr0.s_ac_0 test.pdp6.apr0.s_ac_2 +@29 test.pdp6.apr0.s_ac_inh +@28 test.pdp6.apr0.s_ac_inh_if_ac_0 test.pdp6.apr0.st1 test.pdp6.apr0.st2 @@ -229,7 +236,7 @@ test.pdp6.apr0.st5a test.pdp6.apr0.st6 test.pdp6.apr0.sf7 test.pdp6.apr0.st7 -@1401200 +@1000200 -S @c00200 -iobus @@ -271,6 +278,49 @@ test.pdp6.apr0.mc_non_exist_mem_rst test.pdp6.apr0.mc_non_exist_rd @1401200 -membus +@c00030 +test.fmem0scope[0:35] +@28 +(0)test.fmem0scope[0:35] +(1)test.fmem0scope[0:35] +(2)test.fmem0scope[0:35] +(3)test.fmem0scope[0:35] +(4)test.fmem0scope[0:35] +(5)test.fmem0scope[0:35] +(6)test.fmem0scope[0:35] +(7)test.fmem0scope[0:35] +(8)test.fmem0scope[0:35] +(9)test.fmem0scope[0:35] +(10)test.fmem0scope[0:35] +(11)test.fmem0scope[0:35] +(12)test.fmem0scope[0:35] +(13)test.fmem0scope[0:35] +(14)test.fmem0scope[0:35] +(15)test.fmem0scope[0:35] +(16)test.fmem0scope[0:35] +(17)test.fmem0scope[0:35] +(18)test.fmem0scope[0:35] +(19)test.fmem0scope[0:35] +(20)test.fmem0scope[0:35] +(21)test.fmem0scope[0:35] +(22)test.fmem0scope[0:35] +(23)test.fmem0scope[0:35] +(24)test.fmem0scope[0:35] +(25)test.fmem0scope[0:35] +(26)test.fmem0scope[0:35] +(27)test.fmem0scope[0:35] +(28)test.fmem0scope[0:35] +(29)test.fmem0scope[0:35] +(30)test.fmem0scope[0:35] +(31)test.fmem0scope[0:35] +(32)test.fmem0scope[0:35] +(33)test.fmem0scope[0:35] +(34)test.fmem0scope[0:35] +(35)test.fmem0scope[0:35] +@1401200 +-group_end +@30 +test.mem0scope[0:35] @c00200 -mem0 @28 @@ -332,6 +382,21 @@ test.pdp6.mem0.cmc_t11 test.pdp6.mem0.cmc_t12 @1401200 -mem0 +@c00200 +-fmem0 +@28 +test.pdp6.fmem0.fma_rd_rq +test.pdp6.fmem0.fma_wr_rq +@200 +- +@28 +test.pdp6.fmem0.fmct0 +test.pdp6.fmem0.fmct1 +test.pdp6.fmem0.fmct3 +test.pdp6.fmem0.fmct4 +test.pdp6.fmem0.fmct5 +@1401200 +-fmem0 @28 test.pdp6.apr0.at1_inh test.pdp6.apr0.ia_NOT_int @@ -439,13 +504,12 @@ test.pdp6.apr0.iobus_pi_req[1:7] test.pdp6.apr0.cpa_req[1:7] @1401200 -cpa -@800200 +@c00200 -shift @28 test.pdp6.apr0.sht0 test.pdp6.apr0.sht1 test.pdp6.apr0.shf1 -@29 test.pdp6.apr0.sht1a @200 - @@ -453,7 +517,27 @@ test.pdp6.apr0.sht1a test.pdp6.apr0.sct0 test.pdp6.apr0.sct1 test.pdp6.apr0.sct2 -@1000200 +@1401200 -shift +@800200 +-BLT +@28 +test.pdp6.apr0.blt_last +test.pdp6.apr0.blt_done +test.pdp6.apr0.blt_t0 +test.pdp6.apr0.blt_f0a +test.pdp6.apr0.blt_t0a +test.pdp6.apr0.blt_t1 +test.pdp6.apr0.blt_t2 +test.pdp6.apr0.blt_t3 +test.pdp6.apr0.blt_f3a +test.pdp6.apr0.blt_t3a +test.pdp6.apr0.blt_t4 +test.pdp6.apr0.blt_t5 +test.pdp6.apr0.blt_f5a +test.pdp6.apr0.blt_t5a +test.pdp6.apr0.blt_t6 +@1000200 +-BLT [pattern_trace] 1 [pattern_trace] 0 diff --git a/verilog/test.v b/verilog/test.v index b050acf..9cc9027 100644 --- a/verilog/test.v +++ b/verilog/test.v @@ -26,7 +26,7 @@ module test; initial begin stop = 0; // #110000 stop = 1; - #20000 stop = 1; + #50000 stop = 1; end always @(pdp6.apr0.st7) if(pdp6.apr0.st7) @@ -36,11 +36,11 @@ module test; always @(stop) if(stop) begin: fin integer i; - for(i = 0; i < 'o50; i = i + 1) - if(i < 'o20) - $display("%o %o %o", i, pdp6.mem0.core[i], pdp6.fmem0.ff[i]); - else - $display("%o %o", i, pdp6.mem0.core[i]); + #1000; + for(i = 0; i < 'o20; i = i + 1) + $display("%o %o %o", i, pdp6.mem0.core[i], pdp6.fmem0.ff[i]); + for(i = 'o1000; i < 'o1010; i = i + 1) + $display("%o %o", i, pdp6.mem0.core[i]); $finish; end @@ -155,12 +155,18 @@ module test; end */ - initial begin + initial begin: meminit + integer i; #1 reset = 1; #20 reset = 0; pdp6.datasw = 36'o111777222666; - pdp6.mas = 18'o000030; + pdp6.mas = 18'o000060; + + for(i = 0; i < 'o40000; i = i + 1) + pdp6.mem0.core[i] = 0; + for(i = 0; i < 'o20; i = i + 1) + pdp6.fmem0.ff[i] = 0; pdp6.fmem0.ff['o0] = 36'o000000_010000; pdp6.fmem0.ff['o1] = 36'o000000_010222; @@ -169,7 +175,8 @@ module test; pdp6.fmem0.ff['o4] = 36'o000000_010304; pdp6.fmem0.ff['o5] = 36'o377777_777777; pdp6.fmem0.ff['o6] = 36'o444000_222000; - pdp6.fmem0.ff['o7] = 36'o777776_000010; + pdp6.fmem0.ff['o7] = 36'o777776_000010; // BLK ptr + pdp6.fmem0.ff['o10] = 36'o000002_001000; // BLT ptr pdp6.fmem0.ff['o17] = 36'o777000_001000; // PDL ptr // pdp6.fmem0.ff['o17] = 36'o777000_777777; // PDL ptr pdp6.mem0.core['o20] = 36'o200_064_000104; // MOVE 1,@104(4) FAC_INH @@ -192,9 +199,14 @@ module test; pdp6.mem0.core['o55] = 36'o245_100_777775; // ROTC 2,-3 pdp6.mem0.core['o56] = 36'o244_100_000001; // ASHC 2,1 + pdp6.mem0.core['o60] = 36'o251_400_001001; // BLT 10,1007 + pdp6.mem0.core['o10410] = 36'o000_000_000333; end + wire [0:35] mem0scope = pdp6.mem0.core['o1000]; + wire [0:35] fmem0scope = pdp6.fmem0.ff[2]; + initial begin #25 pdp6.sw_power = 1; end