diff --git a/verilog/apr.v b/verilog/apr.v
index efd2db6..1322c4d 100644
--- a/verilog/apr.v
+++ b/verilog/apr.v
@@ -693,8 +693,7 @@ module apr(
 	wire memac_ac = memac & ~ir[5];
 	wire accp_etc_cond = ir_accp_OR_memac & ir[8] & ar0_xor_ar_ov |
 		ir[7] & ar_eq_0;
-	// simplifies to: accp_etc_cond != ir[6]
-	wire accp_etal_test = (accp_etc_cond | ir[6]) & (~accp_etc_cond | ~ir[6]);
+	wire accp_etal_test = accp_etc_cond ^ ir[6];
 	wire accp_dir = accp & ir[5];
 
 	/* ACBM */
@@ -1074,17 +1073,21 @@ module apr(
 	wire ar_as_t1;
 	wire ar_as_t2;
 	wire ar_t3;
-	wire ar_eq_fp_half = 0;
-	wire ar_eq_0 = ar == 0;
-	wire ar0_xor_ar1 = 0;
-	wire ar_ov_set = 0;
-	wire ar_cry0_xor_cry1 = 0;
-	wire ar0_xor_ar_ov = 0;
-	wire ar0_xor_mb0 = 0;
-	wire ar0_eq_sc0 = 0;
 	wire ar_flag_clr = mr_start | et0 & ir_jrst & ir[11];
-	wire ar_flag_set = 0;
-	wire ar_jfcl_clr = 0;
+	wire ar_jrst_AND_ir11 = ir_jrst & ir[11];
+	wire ar_flag_set = et1 & ar_jrst_AND_ir11;
+	wire ar_jfcl_clr = et10 & ir_jfcl;
+
+	wire ar_eq_fp_half = ar == 36'o000400000000;
+	wire ar_eq_0 = ar == 0;
+	wire ar0_xor_ar1 = ar[0] ^ ar[1];
+	wire ar_ov_set = ar_cry0 ^ ar_cry1;
+	wire ar_cry0_xor_cry1 = ar_ov_set & ~memac;
+	wire ar0_xor_ar_ov = ar[0] ^ ar_cry0_xor_cry1;
+	wire ar0_xor_mb0 = ar[0] ^ mb[0];
+	wire ar0_eq_sc0 = ar[0] == sc[0];
+
+	wire set_flags_et10 = et10 & (memac | ir_as);
 
 	pa ar_pa0();	// AR+-1 T0
 	pa ar_pa1();	// AR NEGATE T0
@@ -1125,6 +1128,8 @@ module apr(
 		.p(ar_cry_comp_D));
 
 	wire [0:35] ar_mb_cry = mb & ~ar;
+	// hold the cry out temporarily
+	reg cry0, cry1;
 
 	always @(posedge clk) begin: arctl
 		integer i;
@@ -1132,8 +1137,10 @@ module apr(
 			ar[0:17] <= 0;
 		if(arrt_clr)
 			ar[18:35] <= 0;
-		if(ar_cry_initiate)
-			ar <= ar + { ar_mb_cry[1:35], 1'b0 };
+		if(ar_cry_initiate) begin
+			cry1 <= (ar[1:35] + { ar_mb_cry[2:35], 1'b0 }) + 36'o0 >> 35;
+			{cry0, ar} <= ar + { ar_mb_cry[1:35], 1'b0 };
+		end
 		if(arlt_fm_mb_xor)
 			ar[0:17] <= ar[0:17] ^ mb[0:17];
 		if(arrt_fm_mb_xor)
@@ -1161,6 +1168,48 @@ module apr(
 			ar_cry0_flag <= 0;
 			ar_cry1_flag <= 0;
 		end
+
+		if(ar_jfcl_clr & ir[12] |
+		   cpa_cono_set & iob[29])
+			ar_pc_chg_flag <= 0;
+		if(ar_flag_set & mb[3] |
+		   et9 & pc_set_OR_pc_inc & ~ar_jrst_AND_ir11)
+			ar_pc_chg_flag <= 1;
+
+		if(ar_jfcl_clr & ir[9] |
+		   cpa_cono_set & iob[32])
+			ar_ov_flag <= 0;
+		if(ar_flag_set & mb[0] |
+		   set_flags_et10 & ar_ov_set |
+		   cfac_overflow |
+		   et10 & ir_fwt & ~ar_cry0 & ar_cry1 |
+		   sct1 & ~mb[18] & ir_ash_OR_ashc | ar0_xor_ar1)
+			ar_ov_flag <= 1;
+
+		if(ar_jfcl_clr & ir[10])
+			ar_cry0_flag <= 0;
+		if(ar_flag_set & mb[1] |
+		   set_flags_et10 & ar_cry0)
+			ar_cry0_flag <= 1;
+
+		if(ar_jfcl_clr & ir[11])
+			ar_cry1_flag <= 0;
+		if(ar_flag_set & mb[2] |
+		   set_flags_et10 & ar_cry1)
+			ar_cry1_flag <= 1;
+
+		if(mr_start) begin
+			cry0 <= 0;
+			cry1 <= 0;
+		end
+		if(cry0) begin
+			cry0 <= 0;
+			ar_cry0 <= 1;
+		end
+		if(cry1) begin
+			cry1 <= 0;
+			ar_cry1 <= 1;
+		end
 		if(et0) begin
 			ar_cry0 <= 0;
 			ar_cry1 <= 0;
@@ -1839,6 +1888,7 @@ module apr(
 	assign iobus_iob_fm_datai = 0;
 	assign iobus_iob_fm_status = 0;
 	assign iobus_iob_out = 0;
+	wire [0:35] iob = iobus_iob_in;
 
 	/*
 	 * PIH, PIR, PIO
diff --git a/verilog/test.v b/verilog/test.v
index dddfefb..ae8e87b 100644
--- a/verilog/test.v
+++ b/verilog/test.v
@@ -22,9 +22,13 @@ module test;
 	clock clock0(clk);
 	pdp6 pdp6(.clk(clk), .reset(reset));
 
-	initial
+	initial begin
 //		#110000 $finish;
 		#20000 $finish;
+	end
+	always @(pdp6.apr0.st7)
+		if(pdp6.apr0.st7)
+			$finish;
 
 	initial begin
 		#100 `TESTKEY = 1;
@@ -117,15 +121,15 @@ module test;
 		pdp6.datasw = 36'o111777222666;
 //		pdp6.mas = 18'o010100;
 //		pdp6.mas = 18'o000004;
-		pdp6.mas = 18'o000020;
+		pdp6.mas = 18'o000023;
 		//pdp6.mas = 18'o777777;
 
-		pdp6.fmem0.ff['o0] = 36'o000000010000;
-		pdp6.fmem0.ff['o1] = 36'o000000000222;
-		pdp6.fmem0.ff['o2] = 36'o700000000006;
-		pdp6.fmem0.ff['o3] = 36'o500000000004;
-		pdp6.fmem0.ff['o4] = 36'o000000010304;
-		pdp6.mem0.core['o4] = 36'o222333111666;
+		pdp6.fmem0.ff['o0] = 36'o000000_010000;
+		pdp6.fmem0.ff['o1] = 36'o000000_000222;
+		pdp6.fmem0.ff['o2] = 36'o700000_000006;
+		pdp6.fmem0.ff['o3] = 36'o500000_000004;
+		pdp6.fmem0.ff['o4] = 36'o000000_010304;
+		pdp6.fmem0.ff['o5] = 36'o377777_777777;
 		// MOVE 1,@104(4)	FAC_INH
 		pdp6.mem0.core['o20] = 36'o200_064_000104;
 		// MOVEM 1,@104(4)
@@ -133,6 +137,8 @@ module test;
 		// ROTC 2,3
 		pdp6.mem0.core['o22] = 36'o245_100_000003;
 
+		pdp6.mem0.core['o23] = 36'o200_005_000001;
+
 		pdp6.mem0.core['o10410] = 36'o000_000_000333;
 	end