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mirror of https://github.com/aap/pdp6.git synced 2026-04-26 12:17:11 +00:00

cleaned up the repo a bit

This commit is contained in:
aap
2019-03-08 20:56:20 +01:00
parent 93420ff2a9
commit ac77ceefea
10 changed files with 943 additions and 66 deletions

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@@ -21,13 +21,12 @@ The maintenance manual has flow charts, schematics and explanations:
The code is more or less a transcription of the schematics into C.
This means you will not understand it unless you're familiar with the maintenance manual.
Pulses are represented as functions, when a pulse triggers another pulse
it does so by the `nextpulse` function which adds a pulse to the list of next pulses.
In the main cpu loop the list of current pulses is iterated and each pulse is called,
then (after checking some external signals) the current and next pulse lists are swapped
and the process begins anew.
The timing was not accurately modeled and there is room for improvement.
Due to the inexact timing the hardware connections (through the memory and IO bus)
were not implemented too accurately. This may change in the future.
it does so by the `pulse` function which queues a pulse in a list
of pulses that are to happen, sorted chronologically.
Between pulses that happen at different times
various things are done like checking external pulses and advancing the
simulation state.
The timing is not yet 100% accurate but it's pretty close.
### Building
@@ -36,8 +35,8 @@ Otherwise you need SDL and pthread.
### Running
The cpu (apr), console tty and paper tape/punch are implemented.
There are no other external devices yet.
The cpu (apr), console tty, paper tape and punch,
the data control and DECtape are implemented.
The only things missing from the cpu is the repeat key mechanism.
## Verilog Simulation
@@ -59,17 +58,72 @@ The TTY is connected to UART over GPIO pins 4 (RX) and 5 (TX)
## File tree
* `emu` source for the emulator
* `verilog` source for the verilog simulation
* `art` everything graphical
* `code` some test code for the PDP-6
* `panel6` virtual panel for the FPGA
* `tools` tools like an assembler and linker
* `misc` some misc. and old stuff
* emu the C emulator
* emu/main_panel.c main file for emulator with panel simulation
* emu/main_serial.c main file for emulator with panel over serial line
* emu/emu.c top level emulator code
* emu/cmd.c command line interface
* emu/apr.c Arithmetic Processor 166 emulation
* emu/mem.c core and fast memory emulation
* emu/tty.c Teleprinter 626 emulator
* emu/pt.c Paper tape reader 760 and punch 761 emulation
* emu/dc.c Data Control 136 emulation
* emu/dt.c DECtape 551 and 555 emulation
* emu/netmem.c network protocol for shared memory
* emu/util.c various utility functions
* emu/util.h
* emu/test_*.c test code, not too important anymore
* emu/pdp6.h main header
* emu/args.h argument parsing
* emu/elements.inc panel definition
* emu/cmds.txt command line interface documentation
* emu/init.ini emulator init file
* emu/mem_* core memory backing store
* tools
* tools/dtr2dta.c convert between raw (dtr) and simh (dta) DECtape format
* tools/mkpty.c make a pty and connect to the controlling tty
* tools/mkpty33.c as above but try to pretend an ASR33
* tools/as6.c an assembler, roughly modeled on MACRO
* tools/ld6.c a loader or relocatable files
* tools/pdp6bin.h
* tools/pdp6common.c useful functions for PDP-6 code
* tools/pdp6common.h
* tools/rel.c I have no recollection of this code
* tools/reltest.c old test code to create a REL file
* tools/test.s old test code for the assembler/linker
* tools/test2.s
* tools/ptdump.c print a paper tape file in octal
* tools/dtdump.c print dtr DECtape
* verilog
* verilog/apr.v Arithmetic Processor 166 simulation
* verilog/core161c.v Core memory 161C simulation
* verilog/fast162.v Fast memory 162 simulation
* verilog/modules.v utility modules
* verilog/pdp6.v top level module
* verilog/quartus various files for my terasic board
* verilog/test_dec.v inst decoding test
* verilog/test.v misc tests
* verilog/test1.inc
* verilog/test2.inc
* verilog/test_fp.inc
* code random code for the PDP-6, mostly testing
* code/bootstrap.txt a list of boot loaders
* code/dtboot.s loads the first block from a DECtape
* code/main.s random entry
* code/tty.s tty character IO
* panel stand alone panel with lots of duplicate code
* art image files for the panel
* misc nothing important
## To do
- repeat and maint. switches
- test thoroughly!
- devices (test UT, implement 340)
- timing
- improve timing
- implement 340 display
- do more tests