From b82dc449b8f05b6bf59ac264efc7af878f2cf411 Mon Sep 17 00:00:00 2001 From: aap Date: Sat, 26 Oct 2019 16:49:04 +0200 Subject: [PATCH] fixed emu; new verilog code; fe6 for fpga --- emu/Makefile | 2 +- emu/apr.c | 17 +- emu/cmd.c | 9 +- emu/init.ini | 1 + emu/main_panel.c | 349 + emu/mem_0 | 4125 +++++++++- emu/netcons.c | 191 + emu/netmem.c | 7 +- emu/pdp6.h | 18 + emu/threading.c | 4 + fe6/Makefile | 13 + fe6/cmd.c | 377 + fe6/emu6.c | 497 ++ fe6/fake.c | 220 + fe6/fe6.c | 950 +++ fe6/fe6.h | 111 + fe6/hps_0.h | 160 + fe6/main_0.c | 103 + fe6/pdp6common.c | 909 ++ fe6/pdp6common.h | 35 + fe6/real6.c | 686 ++ fe6/test.h | 10 + fe6/util.c | 169 + fe6/util.h | 8 + verilog/Makefile | 8 - verilog/apr.v | 757 +- verilog/arbiter.v | 85 + verilog/clk.v | 31 + verilog/core161c.v | 304 +- verilog/core164.v | 362 + verilog/core32k.v | 362 + verilog/core64k.v | 367 + verilog/{modules.v => dly_50.v} | 388 +- verilog/fakeapr.v | 100 + verilog/fast162.v | 17 +- verilog/fast162_dp.v | 251 + verilog/fe_req.v | 13 + verilog/gendly6.py | 169 + verilog/inst.gtkw | 195 - verilog/iobus_0_connect.v | 22 + verilog/iobus_1_connect.v | 47 + verilog/iobus_2_connect.v | 72 + verilog/iobus_3_connect.v | 97 + verilog/membus_2_connect.v | 68 + verilog/membus_3_connect.v | 90 + verilog/membusif.v | 118 + verilog/memif.v | 80 + verilog/memory.v | 80 + verilog/memory_16.v | 42 + verilog/memory_16k.v | 42 + verilog/memory_32k.v | 42 + verilog/memory_64k.v | 42 + verilog/modules_50.v | 139 + verilog/onchip_ram.v | 30 + verilog/panel_6.v | 369 + verilog/pdp6.v | 248 - verilog/ptp.v | 185 + verilog/ptr.v | 195 + verilog/quartus/apr_test.v | 244 - verilog/quartus/fpdpga6.cdf | 13 - verilog/quartus/fpdpga6.qpf | 31 - verilog/quartus/fpdpga6.qsf | 208 - verilog/quartus/fpdpga6.sdc | 116 - verilog/quartus/fpdpga6.v | 535 -- verilog/quartus/i2c.v | 113 - verilog/quartus/i2c_core.v | 159 - verilog/quartus/test.stp | 1081 --- verilog/tb/Makefile | 29 + verilog/tb/tb_arbit.v | 120 + verilog/tb/tb_dly.v | 66 + verilog/tb/tb_mem.v | 54 + verilog/tb/tb_membusif | 5042 ++++++++++++ verilog/tb/tb_membusif.v | 232 + verilog/tb/tb_membusif_x | 12324 ++++++++++++++++++++++++++++ verilog/tb/tb_membusif_x.v | 327 + verilog/tb/tb_memif.v | 111 + verilog/tb/tb_panel.v | 284 + verilog/tb/tb_ptp.v | 177 + verilog/tb/tb_ptr.v | 154 + verilog/test.gtkw | 721 -- verilog/test.v | 171 - verilog/test1.inc | 50 - verilog/test2.inc | 21 - verilog/test_dec.v | 25 - verilog/test_fp.inc | 16 - verilog/testcore161.c | 334 + verilog/testfmem.v | 33 + verilog/testmem16k.v | 45 + verilog/{quartus/uart.v => tty.v} | 307 +- 89 files changed, 32584 insertions(+), 4947 deletions(-) create mode 100644 emu/netcons.c create mode 100644 fe6/Makefile create mode 100644 fe6/cmd.c create mode 100644 fe6/emu6.c create mode 100644 fe6/fake.c create mode 100644 fe6/fe6.c create mode 100644 fe6/fe6.h create mode 100755 fe6/hps_0.h create mode 100755 fe6/main_0.c create mode 100644 fe6/pdp6common.c create mode 100644 fe6/pdp6common.h create mode 100755 fe6/real6.c create mode 100644 fe6/test.h create mode 100644 fe6/util.c create mode 100644 fe6/util.h delete mode 100644 verilog/Makefile create mode 100644 verilog/arbiter.v create mode 100644 verilog/clk.v create mode 100644 verilog/core164.v create mode 100644 verilog/core32k.v create mode 100644 verilog/core64k.v rename verilog/{modules.v => dly_50.v} (52%) create mode 100644 verilog/fakeapr.v create mode 100644 verilog/fast162_dp.v create mode 100644 verilog/fe_req.v create mode 100755 verilog/gendly6.py delete mode 100644 verilog/inst.gtkw create mode 100644 verilog/iobus_0_connect.v create mode 100644 verilog/iobus_1_connect.v create mode 100644 verilog/iobus_2_connect.v create mode 100644 verilog/iobus_3_connect.v create mode 100644 verilog/membus_2_connect.v create mode 100644 verilog/membus_3_connect.v create mode 100644 verilog/membusif.v create mode 100644 verilog/memif.v create mode 100644 verilog/memory.v create mode 100755 verilog/memory_16.v create mode 100755 verilog/memory_16k.v create mode 100755 verilog/memory_32k.v create mode 100755 verilog/memory_64k.v create mode 100755 verilog/modules_50.v create mode 100755 verilog/onchip_ram.v create mode 100644 verilog/panel_6.v delete mode 100644 verilog/pdp6.v create mode 100644 verilog/ptp.v create mode 100644 verilog/ptr.v delete mode 100644 verilog/quartus/apr_test.v delete mode 100644 verilog/quartus/fpdpga6.cdf delete mode 100644 verilog/quartus/fpdpga6.qpf delete mode 100644 verilog/quartus/fpdpga6.qsf delete mode 100644 verilog/quartus/fpdpga6.sdc delete mode 100644 verilog/quartus/fpdpga6.v delete mode 100644 verilog/quartus/i2c.v delete mode 100644 verilog/quartus/i2c_core.v delete mode 100644 verilog/quartus/test.stp create mode 100644 verilog/tb/Makefile create mode 100644 verilog/tb/tb_arbit.v create mode 100644 verilog/tb/tb_dly.v create mode 100644 verilog/tb/tb_mem.v create mode 100755 verilog/tb/tb_membusif create mode 100644 verilog/tb/tb_membusif.v create mode 100755 verilog/tb/tb_membusif_x create mode 100644 verilog/tb/tb_membusif_x.v create mode 100644 verilog/tb/tb_memif.v create mode 100644 verilog/tb/tb_panel.v create mode 100644 verilog/tb/tb_ptp.v create mode 100644 verilog/tb/tb_ptr.v delete mode 100644 verilog/test.gtkw delete mode 100644 verilog/test.v delete mode 100644 verilog/test1.inc delete mode 100644 verilog/test2.inc delete mode 100644 verilog/test_dec.v delete mode 100644 verilog/test_fp.inc create mode 100644 verilog/testcore161.c create mode 100755 verilog/testfmem.v create mode 100755 verilog/testmem16k.v rename verilog/{quartus/uart.v => tty.v} (94%) diff --git a/emu/Makefile b/emu/Makefile index 602d555..8b013e6 100644 --- a/emu/Makefile +++ b/emu/Makefile @@ -1,4 +1,4 @@ -SRC=emu.c apr.c mem.c tty.c pt.c dc.c dt.c netmem.c cmd.c util.c threading.c rtc.c ../tools/pdp6common.c +SRC=emu.c apr.c mem.c tty.c pt.c dc.c dt.c netmem.c netcons.c cmd.c util.c threading.c rtc.c ../tools/pdp6common.c H=pdp6.h ../tools/pdp6common.h threading.h # clang #CFLAGS= -Wno-shift-op-parentheses -Wno-logical-op-parentheses \ diff --git a/emu/apr.c b/emu/apr.c index bf30e09..c0e191d 100644 --- a/emu/apr.c +++ b/emu/apr.c @@ -5,6 +5,11 @@ #define FIX_USER_IOT // Schematics have a bug in the divide subroutine #define FIX_DS +// flow diagrams have it, block diagrams don't. +// should guard against firing MC RS T0 twice +// on MEM CONT when RUN is 0. Although clearing +// the SBR FF probably prevents the same after MC RS T1 +#define FIX_MEMSTOP int loginst; @@ -3003,7 +3008,7 @@ defpulse(at5) defpulse(at4) { ARLT_CLEAR; // 6-8 - // TODO: what is MC DR SPLIT? what happens here anyway? + // no support for drums right now, so no MC DR SPLIT here if(apr->sw_addr_stop || apr->key_mem_stop) apr->mc_split_cyc_sync = 1; // 7-9 pulse(apr, apr->ir & 020 ? &at5 : &ft0, 0); // 5-3, 5-4 @@ -3152,7 +3157,9 @@ defpulse(mc_rs_t1) defpulse_(mc_rs_t0) { -// apr->mc_stop = 0; // ?? not found on 7-9 +#ifdef FIX_MEMSTOP + apr->mc_stop = 0; // ?? not found on 7-9 +#endif pulse(apr, &mc_rs_t1, 50); // 7-8 } @@ -3369,6 +3376,10 @@ defpulse(kt2) defpulse_(kt1) { + // has to happen before mc_stop_sync is cleared in MR CLR + // TODO: test this + if(KEY_MANUAL && apr->mc_stop && apr->mc_stop_sync && !apr->key_mem_cont) + pulse(apr, &mc_wr_rs, 0); // 7-8 if(apr->key_io_reset) pulse(apr, &mr_start, 0); // 5-2 if(KEY_MANUAL && !apr->key_mem_cont) @@ -3377,8 +3388,6 @@ defpulse_(kt1) set_key_rim_sbr(apr, 0); // 5-2 if(apr->key_mem_cont && apr->mc_stop) pulse(apr, &mc_rs_t0, 0); // 7-8 - if(KEY_MANUAL && apr->mc_stop && apr->mc_stop_sync && !apr->key_mem_cont) - pulse(apr, &mc_wr_rs, 0); // 7-8 if(apr->key_readin) set_key_rim_sbr(apr, 1); // 5-2 diff --git a/emu/cmd.c b/emu/cmd.c index 8ce3834..e67d523 100644 --- a/emu/cmd.c +++ b/emu/cmd.c @@ -237,6 +237,7 @@ DevDef definitions[] = { { DIS_IDENT, makedis }, #endif { NETMEM_IDENT, makenetmem }, + { NETCONS_IDENT, makenetcons }, { nil, nil } }; @@ -684,7 +685,7 @@ struct { "quit emulator" }, { "help", c_help, "print help" }, - { "", nil} + { nil, nil} }; static void @@ -692,7 +693,7 @@ c_help(int argc, char *argv[]) { int i; - for(i = 0; cmdtab[i].cmd[0]; i++) + for(i = 0; cmdtab[i].cmd; i++) printf(" %s:\t%s\n", cmdtab[i].cmd, cmdtab[i].desc); } @@ -709,7 +710,7 @@ commandline(char *line) if(numops && ops[0][0] != '#'){ nfound = 0; - for(i = 0; cmdtab[i].cmd[0]; i++){ + for(i = 0; cmdtab[i].cmd; i++){ cmd = cmdtab[i].cmd; l = strlen(ops[0]); if(strncmp(ops[0], cmd, l) == 0){ @@ -723,7 +724,7 @@ commandline(char *line) cmdtab[n].f(numops, ops); else{ printf("Ambiguous command: %s\n", ops[0]); - for(i = 0; cmdtab[i].cmd[0]; i++){ + for(i = 0; cmdtab[i].cmd; i++){ cmd = cmdtab[i].cmd; l = strlen(ops[0]); if(strncmp(ops[0], cmd, l) == 0) diff --git a/emu/init.ini b/emu/init.ini index d2af35c..dfbc7d4 100644 --- a/emu/init.ini +++ b/emu/init.ini @@ -17,6 +17,7 @@ mkdev mem0 moby mem_0 #mkdev netmem netmem its.pdp10.se 10006 #mkdev netmem netmem localhost 10006 #mkdev netmem netmem maya.papnet.eu 10006 +mkdev netcons netcons localhost 10007 connectdev dc dt0 connectdev dt0 dx1 1 diff --git a/emu/main_panel.c b/emu/main_panel.c index b843f19..83d99ef 100644 --- a/emu/main_panel.c +++ b/emu/main_panel.c @@ -156,6 +156,9 @@ getelements(Element *sw, int n) #define KEYPULSE(k) (apr->k && !oldapr.k) +Lock panellock; +Rendez panelsynch; + /* Set panel from internal APR state */ void updatepanel(Apr *apr) @@ -356,8 +359,353 @@ updateapr(Apr *apr, Ptr *ptr) setelements(apr->rlr, rlr_l, 8); setelements(apr->rla, rla_l, 8); setelements(apr->iobus.c12, iobus_l, 36); + + rwakeupall(&panelsynch); } +#include "mmregs.h" + +void +writeconsreg(Apr *apr, u32 addr, u32 data) +{ + switch(addr){ + case MM_APR_CTL1_UP: +//printf("write CTL1 UP %o\n", data); + if(data & 3){ + keys[0].active = 0; + keys[0].state = 0; + } + if(data & 014){ + keys[1].active = 0; + keys[1].state = 0; + } + if(data & 060){ + keys[2].active = 0; + keys[2].state = 0; + } + if(data & 0300){ + keys[3].active = 0; + keys[3].state = 0; + } + if(data & 0400) + misc_sw[1].state = 0; + break; + case MM_APR_CTL1_DN: +//printf("write CTL1 DN %o\n", data); + if(data & 1){ + keys[0].active = 1; + keys[0].state = 1; + } + if(data & 2){ + keys[0].active = 1; + keys[0].state = 2; + } + if(data & 4){ + keys[1].active = 1; + keys[1].state = 1; + } + if(data & 010){ + keys[1].active = 1; + keys[1].state = 2; + } + if(data & 020){ + keys[2].active = 1; + keys[2].state = 1; + } + if(data & 040){ + keys[2].active = 1; + keys[2].state = 2; + } + if(data & 0100){ + keys[3].active = 1; + keys[3].state = 1; + } + if(data & 0200){ + keys[3].active = 1; + keys[3].state = 2; + } + if(data & 0400) + misc_sw[1].state = 1; + break; + + case MM_APR_CTL2_UP: +//printf("write CTL2 UP %o\n", data); + if(data & 3){ + keys[4].active = 0; + keys[4].state = 0; + } + if(data & 014){ + keys[5].active = 0; + keys[5].state = 0; + } + if(data & 060){ + keys[6].active = 0; + keys[6].state = 0; + } + if(data & 0300){ + keys[7].active = 0; + keys[7].state = 0; + } + if(data & 0400) + misc_sw[0].state = 0; + if(data & 01000) + misc_sw[3].state = 0; + break; + case MM_APR_CTL2_DN: +//printf("write CTL2 DN %o\n", data); + if(data & 1){ + keys[4].active = 1; + keys[4].state = 1; + } + if(data & 2){ + keys[4].active = 1; + keys[4].state = 2; + } + if(data & 4){ + keys[5].active = 1; + keys[5].state = 1; + } + if(data & 010){ + keys[5].active = 1; + keys[5].state = 2; + } + if(data & 020){ + keys[6].active = 1; + keys[6].state = 1; + } + if(data & 040){ + keys[6].active = 1; + keys[6].state = 2; + } + if(data & 0100){ + keys[7].active = 1; + keys[7].state = 1; + } + if(data & 0200){ + keys[7].active = 1; + keys[7].state = 2; + } + if(data & 0400) + misc_sw[0].state = 1; + if(data & 01000) + misc_sw[3].state = 1; + break; + + case MM_APR_MAINT_DN: + // TODO: + break; + + case MM_APR_DSLT: + setelements(data, data_sw, 18); + break; + case MM_APR_DSRT: + setelements(data, data_sw+18, 18); + break; + case MM_APR_MAS: + setelements(data, ma_sw, 18); + break; + case MM_APR_REPEAT: + break; // TODO + } + + // wait for panel to pick up values + rsleep(&panelsynch); +} + +u32 +readconsreg(Apr *apr, u32 addr) +{ + u32 d; + switch(addr){ + case MM_APR_CTL1_DN: + d = apr->key_start; + d |= apr->key_readin<<1; + d |= apr->key_inst_cont<<2; + d |= apr->key_mem_cont<<3; + d |= apr->key_inst_stop<<4; + d |= apr->key_mem_stop<<5; + d |= apr->key_io_reset<<6; + d |= apr->key_exec<<7; + d |= apr->sw_addr_stop<<8; + d |= apr->run<<9; + d |= apr->mc_stop<<10; + d |= apr->sw_power<<11; + return d; + + case MM_APR_CTL2_DN: + d = apr->key_dep; + d |= apr->key_dep_nxt<<1; + d |= apr->key_ex<<2; + d |= apr->key_ex_nxt<<3; + d |= apr->key_rd_off<<4; + d |= apr->key_rd_on<<5; + d |= apr->key_pt_rd<<6; + d |= apr->key_pt_wr<<7; + d |= apr->sw_repeat<<8; + d |= apr->sw_mem_disable<<9; + return d; + + case MM_APR_MAINT_DN: + // TODO: + break; + + case MM_APR_DSLT: + return getelements(data_sw, 36)>>18; + case MM_APR_DSRT: + return getelements(data_sw, 36)&RT; + case MM_APR_MAS: + return getelements(ma_sw, 18); + case MM_APR_REPEAT: + return 0; // TODO + case MM_APR_IR: + return apr->ir; + case MM_APR_MILT: + return apr->mi>>18; + case MM_APR_MIRT: + return apr->mi&RT; + case MM_APR_PC: + return apr->pc; + case MM_APR_MA: + return apr->ma; + case MM_APR_PI: + return apr->pi_active | + apr->pio<<1 | + apr->pir<<8 | + apr->pih<<15; + + case MM_APR_MBLT: + return apr->c.mb>>18; + case MM_APR_MBRT: + return apr->c.mb&RT; + case MM_APR_ARLT: + return apr->c.ar>>18; + case MM_APR_ARRT: + return apr->c.ar&RT; + case MM_APR_MQLT: + return apr->c.mq>>18; + case MM_APR_MQRT: + return apr->c.mq&RT; + + case MM_APR_FF1: + d = 0; + d |= (u32)apr->key_ex_st << 31; + d |= (u32)apr->key_ex_sync << 30; + d |= (u32)apr->key_dep_st << 29; + d |= (u32)apr->key_dep_sync << 28; + d |= (u32)apr->key_rd_wr << 27; + d |= (u32)apr->mc_rd << 26; + d |= (u32)apr->mc_wr << 25; + d |= (u32)apr->mc_rq << 24; + d |= (u32)apr->if1a << 23; + d |= (u32)apr->af0 << 22; + d |= (u32)apr->af3 << 21; + d |= (u32)apr->af3a << 20; + d |= (u32)apr->et4_ar_pse << 19; + d |= (u32)apr->f1a << 18; + d |= (u32)apr->f4a << 17; + d |= (u32)apr->f6a << 16; + d |= (u32)apr->sf3 << 15; + d |= (u32)apr->sf5a << 14; + d |= (u32)apr->sf7 << 13; + d |= (u32)apr->ar_com_cont << 12; + d |= (u32)apr->blt_f0a << 11; + d |= (u32)apr->blt_f3a << 10; + d |= (u32)apr->blt_f5a << 9; + d |= (u32)apr->iot_f0a << 8; + d |= (u32)apr->fpf1 << 7; + d |= (u32)apr->fpf2 << 6; + d |= (u32)apr->faf1 << 5; + d |= (u32)apr->faf2 << 4; + d |= (u32)apr->faf3 << 3; + d |= (u32)apr->faf4 << 2; + d |= (u32)apr->fmf1 << 1; + d |= (u32)apr->fmf2 << 0; + return d; + case MM_APR_FF2: + d = 0; + d |= (u32)apr->fdf1 << 31; + d |= (u32)apr->fdf2 << 30; + d |= (u32)(apr->ir & H6 && apr->c.mq & F1 && !apr->nrf3) << 29; + d |= (u32)apr->nrf1 << 28; + d |= (u32)apr->nrf2 << 27; + d |= (u32)apr->nrf3 << 26; + d |= (u32)apr->fsf1 << 25; + d |= (u32)apr->chf7 << 24; + d |= (u32)apr->dsf1 << 23; + d |= (u32)apr->dsf2 << 22; + d |= (u32)apr->dsf3 << 21; + d |= (u32)apr->dsf4 << 20; + d |= (u32)apr->dsf5 << 19; + d |= (u32)apr->dsf6 << 18; + d |= (u32)apr->dsf7 << 17; + d |= (u32)apr->dsf8 << 16; + d |= (u32)apr->dsf9 << 15; + d |= (u32)apr->msf1 << 14; + d |= (u32)apr->mpf1 << 13; + d |= (u32)apr->mpf2 << 12; + d |= (u32)apr->mc_split_cyc_sync << 11; + d |= (u32)apr->mc_stop_sync << 10; + d |= (u32)apr->shf1 << 9; + d |= (u32)(apr->sc == 0777) << 8; + d |= (u32)apr->chf1 << 7; + d |= (u32)apr->chf2 << 6; + d |= (u32)apr->chf3 << 5; + d |= (u32)apr->chf4 << 4; + d |= (u32)apr->chf5 << 3; + d |= (u32)apr->chf6 << 2; + d |= (u32)apr->lcf1 << 1; + d |= (u32)apr->dcf1 << 0; + return d; + case MM_APR_FF3: + d = 0; + d |= (u32)apr->pi_ov << 31; + d |= (u32)apr->pi_cyc << 30; + d |= (u32)(!!apr->pi_req) << 29; + d |= (u32)apr->iot_go << 28; + d |= (u32)apr->a_long << 27; + d |= (u32)(apr->ma == apr->mas) << 26; + d |= (u32)apr->uuo_f1 << 25; + d |= (u32)apr->cpa_pdl_ov << 24; + d |= (u32)(apr->fe&0377) << 16; + d |= (u32)(apr->fe&0377) << 8; + d |= (u32)(!apr->ex_user) << 7; + d |= (u32)apr->cpa_illeg_op << 6; + d |= (u32)apr->ex_ill_op << 5; + d |= (u32)apr->ex_uuo_sync << 4; + d |= (u32)apr->ex_pi_sync << 3; + d |= (u32)apr->mq36 << 2; + d |= (u32)(!!(apr->sc&0400)) << 1; + d |= (u32)(!!(apr->fe&0400)) << 0; + return d; + case MM_APR_FF4: + d = 0; + d |= (u32)apr->key_rim_sbr << 31; + d |= (u32)apr->ar_cry0_xor_cry1 << 30; + d |= (u32)apr->ar_cry0 << 29; + d |= (u32)apr->ar_cry1 << 28; + d |= (u32)apr->ar_ov_flag << 27; + d |= (u32)apr->ar_cry0_flag << 26; + d |= (u32)apr->ar_cry1_flag << 25; + d |= (u32)apr->ar_pc_chg_flag << 24; + d |= (u32)apr->cpa_non_exist_mem << 23; + d |= (u32)apr->cpa_clock_enable << 22; + d |= (u32)apr->cpa_clock_flag << 21; + d |= (u32)apr->cpa_pc_chg_enable << 20; + d |= (u32)apr->cpa_arov_enable << 19; + d |= (u32)(!!(apr->cpa_pia&4)) << 18; + d |= (u32)(!!(apr->cpa_pia&2)) << 17; + d |= (u32)(!!(apr->cpa_pia&1)) << 16; + return d; + case MM_APR_MMU: + d = apr->pr; + d = (u32)apr->rlr << 8; + d = (u32)apr->rla << 16; + return d; + } + return 0; +} + + static void updatetty(Tty *tty) { @@ -873,6 +1221,7 @@ void main340(void); err("SDL_CreateWindowAndRenderer() failed: %s\n", SDL_GetError()); initpanel(); + panelsynch.l = &panellock; findlayout(&w, &h); diff --git a/emu/mem_0 b/emu/mem_0 index bf5df87..3c627b6 100644 --- a/emu/mem_0 +++ b/emu/mem_0 @@ -1,18 +1,19 @@ -255000000000 -205000255000 -700200635550 -700600011577 -721200223110 -720200004010 -720340001000 -254000000006 -720040000013 -345540000006 -602540777777 -700600014300 -254000000006 -000017: -254000777726 +000000000123 +000000777777 +000000777777 +1777777777677756000020 +710600000060 +710740000010 +1777777777727000000042 +710440000026 +710740000010 +254000000032 +1777777777727000000002 +1777777777727000000042 +710740000010 +254000000030 +254014000000 +710440000016 710600000060 710740000010 254000000021 @@ -29,8 +30,3844 @@ 324000000001 254200000000 000000037577 +000041: +264000033723 +544007033753 +610000027741 +264000001317 +264000001317 +264000033123 +000050: +264000033075 +000052: +264000032772 +000054: +264000032243 +000056: +713100034067 +254200000057 +1777777777777777701542 +220000030353 +600000050755 +144000075755 +304000077753 +600000067500 +220000011236 +400000044755 +104000006566 +000000044200 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-000000772752 +700000772752 000000773043 254000773430 205240604040 000000776627 776630: -000000000003 +777777777777 000000777777 776633: -740000000200 +740000000000 000000001177 000215000010 777777777777 -776673: +776663: +777777777777 +776665: +777666772664 +000000000120 +254000777076 +000000000010 +740000777632 +254000777076 777777777777 776675: 777666772664 -777777000010 +777777000130 254000777066 000000000010 -740000777604 +740000777632 254000777066 -000000000001 -400000000031 +000000000003 +400000000073 777777777777 -200500777260 +250500777265 776710: -740000777463 -776712: -000000000400 +740000777516 +034156261770 +776562000000 000000776060 000000776134 000000000010 @@ -2206,11 +6051,11 @@ 000000776134 000000000010 777777777777 -000000000001 -776724: -000000000002 -000600772516 -040000774011 +254000776732 +700640776626 +000000000006 +000600772572 +740000774011 336000776721 254000776733 350000776726 @@ -2305,7 +6150,7 @@ 712300000020 260040773176 476000776630 -254000777400 +254000777700 402000776630 333240773777 254000774000 @@ -2370,8 +6215,12 @@ 300600776626 360610776603 000040000040 +300600776577 +300600776622 +360610776577 +000040000040 777177: -400000000000 +516463000000 444464000000 400000000000 644543570000 diff --git a/emu/netcons.c b/emu/netcons.c new file mode 100644 index 0000000..9664d5a --- /dev/null +++ b/emu/netcons.c @@ -0,0 +1,191 @@ +#include "pdp6.h" +#include + +char *netcons_ident = NETCONS_IDENT; + +enum +{ + WRRQ = 1, + RDRQ = 2, + ACK = 3, + ERR = 4, +}; + +#include "mmregs.h" + +static word +memread(Apr *apr, u32 addr) +{ + word *p; + if(addr < 020) + p = getmemref(&apr->membus, addr, 1, nil); + else + p = getmemref(&apr->membus, addr&RT, 0, nil); + if(p == nil) return 0; + return *p; +} + +static void +memwrite(Apr *apr, u32 addr, word w) +{ + word *p; + if(addr < 020) + p = getmemref(&apr->membus, addr, 1, nil); + else + p = getmemref(&apr->membus, addr&RT, 0, nil); + if(p == nil) return; + *p = w; +} + +static u32 memif_addr; +static word memif_word; + +static void +writereg(Apr *apr, u32 addr, u32 data) +{ +// printf("writing %o to %o\n", data, addr); + if(addr < MM_APR_BASE){ + switch(addr){ + case MM_MEMIF_ADDR: + memif_addr = data; + break; + case MM_MEMIF_LOW: + memif_word = memif_word< | data&RT; + break; + case MM_MEMIF_HIGH: + memif_word = ((word)data<<18)< | memif_word&RT; + memwrite(apr, memif_addr, memif_word); + break; + } + }else if(addr <= MM_APR_PI) + writeconsreg(apr, addr, data); +} + +static u32 +readreg(Apr *apr, u32 addr) +{ +// printf("reading from %o\n", addr); + if(addr < MM_APR_BASE){ + switch(addr){ + case MM_MEMIF_LOW: + return memif_word&RT; + break; + case MM_MEMIF_HIGH: + memif_word = memread(apr, memif_addr); + return (memif_word>>18)&RT; + break; + } + }else if(addr <= MM_APR_PI) + return readconsreg(apr, addr); + return 0; +} + +static void +netconscycle(void *dev) +{ + Netcons *nc; + nc = (Netcons*)dev; + u16 len; + u32 a, d; + + if(nc->fd < 0) + return; + + + if(!hasinput(nc->fd)) + return; + + if(readn(nc->fd, nc->buf, 2)){ + fprintf(stderr, "netcons fd closed\n"); + nc->fd = -1; + return; + } + len = nc->buf[0]<<8 | nc->buf[1]; + if(len > 9){ + fprintf(stderr, "netcons botch(%d), closing\n", len); + close(nc->fd); + nc->fd = -1; + return; + } + memset(nc->buf, 0, sizeof(nc->buf)); + readn(nc->fd, nc->buf, len); + + + a = nc->buf[1] | nc->buf[2]<<8 | nc->buf[3]<<16 | nc->buf[4] << 24; + d = nc->buf[5] | nc->buf[6]<<8 | nc->buf[7]<<16 | nc->buf[8] << 24; + + switch(nc->buf[0]){ + case WRRQ: + writereg(nc->apr, a, d); + nc->buf[0] = 0; + nc->buf[1] = 1; + nc->buf[2] = ACK; + writen(nc->fd, nc->buf, nc->buf[1]+2); + break; + case RDRQ: + d = readreg(nc->apr, a); + // printf("got %lo\n", d); + nc->buf[0] = 0; + nc->buf[1] = 5; + nc->buf[2] = ACK; + nc->buf[3] = d; + nc->buf[4] = d>>8; + nc->buf[5] = d>>16; + nc->buf[6] = d>>24; + writen(nc->fd, nc->buf, nc->buf[1]+2); + break; + default: + fprintf(stderr, "unknown netcons message %d\n", nc->buf[0]); + break; + } + return; +err: + printf("error address %o\n", a); + nc->buf[0] = 1; + nc->buf[1] = 1; + nc->buf[2] = ERR; + writen(nc->fd, nc->buf, nc->buf[0]+2); + return; +} + +Device* +makenetcons(int argc, char *argv[]) +{ + const char *host; + int port; + Netcons *nc; + Device *apr; + Task t; + + nc = malloc(sizeof(Netcons)); + memset(nc, 0, sizeof(Netcons)); + nc->dev.type = netcons_ident; + nc->dev.name = ""; + + // TODO: don't hardcode; + apr = getdevice("apr"); + assert(apr); + assert(apr->type == apr_ident); + nc->apr = (Apr*)apr; + + if(argc > 0) + host = argv[0]; + else + host = "localhost"; + if(argc > 1) + port = atoi(argv[1]); + else + port = 10007; + + printf("connecting to %s %d\n", host, port); + + nc->fd = dial(host, port); + if(nc->fd < 0) + printf("couldn't connect\n"); + printf("netcons fd: %d\n", nc->fd); + + t = (Task){ nil, netconscycle, nc, 50, 0 }; + addtask(t); + + return &nc->dev; +} diff --git a/emu/netmem.c b/emu/netmem.c index 794582a..ab978cd 100644 --- a/emu/netmem.c +++ b/emu/netmem.c @@ -16,7 +16,7 @@ netmemcycle(void *dev) { Netmem *nm; nm = (Netmem*)dev; - u8 len; + u16 len; word a, d, *p; int busy; @@ -86,8 +86,9 @@ netmemcycle(void *dev) err: printf("error address %06lo\n", a); nm->buf[0] = 1; - nm->buf[1] = ERR; - writen(nm->fd, nm->buf, nm->buf[0]+1); + nm->buf[1] = 1; + nm->buf[2] = ERR; + writen(nm->fd, nm->buf, nm->buf[0]+2); return; wait: nm->waiting = 1; diff --git a/emu/pdp6.h b/emu/pdp6.h index a7711cc..4f941cc 100644 --- a/emu/pdp6.h +++ b/emu/pdp6.h @@ -674,3 +674,21 @@ struct Netmem #define NETMEM_IDENT "netmem" extern char *netmem_ident; Device *makenetmem(int argc, char *argv[]); + + +typedef struct Netcons Netcons; +struct Netcons +{ + Device dev; + int fd; + u8 buf[9]; + + // tmp? + Apr *apr; +}; +#define NETCONS_IDENT "netcons" +extern char *netcons_ident; +Device *makenetcons(int argc, char *argv[]); + +void writeconsreg(Apr *apr, u32 addr, u32 data); +u32 readconsreg(Apr *apr, u32 addr); diff --git a/emu/threading.c b/emu/threading.c index 3cb9f0f..d9b7be2 100644 --- a/emu/threading.c +++ b/emu/threading.c @@ -85,6 +85,8 @@ rsleep(Rendez *r) void rwakeup(Rendez *r) { + if(!r->init) + return; if(pthread_cond_signal(&r->cond) != 0) abort(); } @@ -92,6 +94,8 @@ rwakeup(Rendez *r) void rwakeupall(Rendez *r) { + if(!r->init) + return; if(pthread_cond_broadcast(&r->cond) != 0) abort(); } diff --git a/fe6/Makefile b/fe6/Makefile new file mode 100644 index 0000000..deb3a39 --- /dev/null +++ b/fe6/Makefile @@ -0,0 +1,13 @@ +XX=/u/aap/de0-nano-soc/gcc-linaro-6.5.0-2018.12-x86_64_arm-linux-gnueabihf/bin/arm-linux-gnueabihf- +CFLAGS=-DTEST + +all: fe6_emu fe6_fake fe6 + +fe6_emu: fe6.c emu6.c cmd.c util.c pdp6common.c + $(CC) $(CFLAGS) -o $@ $^ + +fe6_fake: fe6.c fake.c cmd.c util.c pdp6common.c + $(CC) $(CFLAGS) -o $@ $^ + +fe6: fe6.c real6.c cmd.c util.c pdp6common.c + $(XX)gcc $(CFLAGS) -o $@ $^ diff --git a/fe6/cmd.c b/fe6/cmd.c new file mode 100644 index 0000000..685af6f --- /dev/null +++ b/fe6/cmd.c @@ -0,0 +1,377 @@ +#include "fe6.h" +#include +#include + +#define MAXOPS 20 + +static char *lp; +static int numops; +static char *ops[MAXOPS]; + +static void +skipwhite(void) +{ + while(isspace(*lp)) + lp++; +} + +static int +isdelim(char c) +{ + return c == '\0' || strchr(" \t\n;'\"", c) != nil; +} + +/* tokenize lp into ops[numops] */ +static void +splitops(void) +{ + char delim; + char *p; + + numops = 0; + for(; *lp; lp++){ + skipwhite(); + if(*lp == ';' || *lp == '\0') + return; + if(numops == MAXOPS){ + fprintf(stderr, "Too many arguments, ignored <%s>\n", lp); + return; + } + if(*lp == '"' || *lp == '\''){ + delim = *lp++; + ops[numops++] = p = lp; + while(*lp && *lp != delim){ + if(*lp == '\\') + lp++; + *p++ = *lp++; + } + if(*lp == '\0') lp--; + *p = '\0'; + }else{ + ops[numops++] = p = lp; + while(!isdelim(*lp)){ + if(*lp == '\\') + lp++; + *p++ = *lp++; + } + if(*lp == '\0') lp--; + *p = '\0'; + } + } +} + +void +loadsblk(FILE *fp) +{ + word iowd, w, chk; + int d; + + /* Skip RIM loader */ + while(w = readwits(fp), w != ~0) + if(w == 0254000000001) + goto sblk; + goto format; +sblk: + /* Read a simple block */ + while(w = readwits(fp), w != ~0){ + /* We expect an AOBJN word here */ + if((w & F0) == 0) + goto end; + iowd = w; + chk = iowd; + d = right(iowd) != 0; /* 0 is symbol table */ + while(left(iowd) != 0){ + w = readwits(fp); + if(w == ~0) + goto format; + + chk = (chk<<1 | chk>>35) + w & FW; + + if(d) + deposit(right(iowd), w); + iowd += 01000001; + } + if(readwits(fp) != chk) + goto format; + } + goto format; +end: + /* use the first JRST, not the second */ + // w = readwits(fp); + if(left(w) != 0324000 && left(w) != 0254000) + goto format; +printf("PC: %o\r\n", right(w)); +fflush(stdout); + cpu_setpc(right(w)); + started = 1; + return; + +format: + printf("\r\nSBLK format botch\r\n"); + fflush(stdout); +} + +#define MAXBLK 01000 + +void +dumpsblk(FILE *fp, hword start, hword end) +{ + hword a; + word w, iowd, chk; + int last0; + + writewits(0254000000001, fp); + for(a = start; a <= end; /*a++*/){ + /* look for beginning of block */ + w = examine(a); + if(w == 0){ + a++; + continue; + } + + /* look for end of block */ + iowd = a; + last0 = 0; + for(; a <= end; a++){ + if(a - iowd >= MAXBLK) + break; + + w = examine(a); + if(w == 0){ + if(last0){ + a--; + break; + } + last0 = 1; + }else{ + last0 = 0; + } + } +//printf("%lo - %o\r\n", iowd, a); + + /* write block */ + iowd |= (01000000 - (a-iowd)) << 18; + writewits(iowd, fp); + chk = iowd; +//printf("%lo\r\n", iowd); + + while(left(iowd) != 0){ + w = examine(right(iowd)); + writewits(w, fp); + chk = (chk<<1 | chk>>35) + w & FW; +//printf(" %lo\r\n", w); + + iowd += 01000001; + } + writewits(chk, fp); + } + w = 0324000000000 | starta; + writewits(w, fp); + writewits(w, fp); + + writewits(~0, fp); // flush +//fflush(stdout); +} + +static void +printops(void) +{ + int i; + for(i = 0; i < numops; i++) + printf("<%s> ", ops[i]); + printf("\r\n"); + fflush(stdout); +} + +void +c_dump(int argc, char *argv[]) +{ + FILE *f; + if(argc < 2) + return; + f = fopen(ops[1], "wb"); + if(f == nil) + err("?F? "); + dumpsblk(f, 020, MAXMEM-1); + fclose(f); +} + +void +c_load(int argc, char *argv[]) +{ + FILE *f; + if(argc < 2) + return; + f = fopen(ops[1], "rb"); + if(f == nil) + err("?F? "); + loadsblk(f); + fclose(f); +} + +struct dev devtab[] = { + { "ptr", O_RDONLY, -1, nil }, + { "ptp", O_WRONLY | O_CREAT | O_TRUNC, -1, nil }, + nil, 0, 0 +}; + +struct dev* +finddev(char *str) +{ + struct dev *d; + for(d = devtab; d->devname; d++) + if(strcasecmp(d->devname, str) == 0) + return d; + return nil; +} + +void +c_mount(int argc, char *argv[]) +{ + char *devstr, *path; + struct dev *dev; + + if(argc == 1){ + /* with no arguments, print mounts */ + for(dev = devtab; dev->devname; dev++) + if(dev->fd >= 0) + printf("%s: %s\r\n", dev->devname, dev->path); + return; + } + + if(argc < 3) + err("?A? "); + devstr = argv[1]; + path = argv[2]; + + dev = finddev(devstr); + if(dev == nil) + err("?D? "); + if(dev->fd >= 0){ + close(dev->fd); + dev->fd = -1; + free(dev->path); + dev->path = nil; + } + dev->fd = open(path, dev->mode); + if(dev->fd < 0) + err("?F? "); + dev->path = strdup(path); +} + +void +c_unmount(int argc, char *argv[]) +{ + char *devstr; + struct dev *dev; + + if(argc < 2) + err("?A? "); + devstr = argv[1]; + + dev = finddev(devstr); + if(dev == nil) + err("?D? "); + if(dev->fd >= 0){ + close(dev->fd); + dev->fd = -1; + free(dev->path); + dev->path = nil; + } +} + +struct { + char *cmd; + void (*f)(int, char **); +} cmdtab[] = { + { "load", c_load }, + { "dump", c_dump }, + { "mount", c_mount }, + { "unmount", c_unmount }, + { nil, nil } +}; + +void +coloncmd(char *line) +{ + int i; + + lp = line; + splitops(); + if(numops < 1) + return; + + for(i = 0; cmdtab[i].cmd; i++) + if(strcasecmp(ops[0], cmdtab[i].cmd) == 0){ + cmdtab[i].f(numops, ops); + return; + } + err("?? "); +} + +void +docmd(char *cmd, char *line) +{ + char buf[256]; + sprintf(buf, "%s %s", cmd, line); + coloncmd(buf); +} + +char *helpstr = +"\n\ +? print help\n\ +◊? print colon command help\n\ +◊D clear input\n\ +◊G start at start address\n\ +◊G start at \n\ +◊◊G set start address to and start\n\ +◊R\n\ +◊R\n\ +◊◊R like their G counterparts but read-in instead of start\n\ +↑Z instruction stop\n\ +◊↑Z memory stop\n\ +◊P continue\n\ +↑N instruction step\n\ +◊↑N memory step\n\ +◊X execute instruction inst\n\ +◊I IO reset\n\ +◊Q last quantity\n\ ++ addition operator\n\ +- subtraction operator\n\ +* multiplication operator\n\ +| division operator\n\ +SPACE assembly field separator\n\ +, assembly field separator\n\ +(word) swap word and add to current full word\n\ +X(word) where X is an operator. parenthesize expression\n\ +/ open\n\ +\\ open, don't set .\n\ +[ open, constant typeout\n\ +] open, symbolic typeout\n\ +! open, no typeout\n\ +TAB deposit, open\n\ +^ deposit, open previous\n\ +↑J deposit, open next\n\ +↑M deposit, close\n\ +_ typeout symbolic\n\ += typeout constant\n\ +\" typeout ASCII\n\ +' typeout SIXBIT\n\ +& typeout SQUOZE\n\ +◊S ◊◊S symbolic mode\n\ +◊C ◊◊C constant mode\n\ +◊\" ◊◊\" ASCII mode\n\ +◊' ◊◊' SIXBIT mode\n\ +◊& ◊◊& SQUOZE mode\n\ +◊H ◊◊H half word mode\n\ +◊L load binary file\n\ +◊Y dump to binary file\n\ +"; + +char *colhelpstr = +"\n\ +:load load binary file\n\ +:dump dump to binary file\n\ +:mount mount file on device\n\ +:unmount unmount file on device\n\ +"; diff --git a/fe6/emu6.c b/fe6/emu6.c new file mode 100644 index 0000000..e2eb223 --- /dev/null +++ b/fe6/emu6.c @@ -0,0 +1,497 @@ +#include "fe6.h" +#include + +/* Memory mapped PDP-6 interface */ +enum +{ + MEMIF_BASE = 0, + APR_BASE = 010, + + + /* The more important keys, switches and lights */ + REG6_CTL1_DN = 0, + REG6_CTL1_UP = 1, + MM6_START = 1, + MM6_READIN = 2, + MM6_INSTCONT = 4, + MM6_MEMCONT = 010, + MM6_INSTSTOP = 020, + MM6_MEMSTOP = 040, + MM6_STOP = MM6_INSTSTOP|MM6_MEMSTOP, + MM6_RESET = 0100, + MM6_EXEC = 0200, + MM6_ADRSTOP = 0400, + /* lights - read only */ + MM6_RUN = 01000, + MM6_MCSTOP = 02000, + MM6_PWR = 04000, + + /* Less important keys and switches */ + REG6_CTL2_DN = 2, + REG6_CTL2_UP = 3, + MM6_THISDEP = 1, + MM6_NEXTDEP = 2, + MM6_THISEX = 4, + MM6_NEXTEX = 010, + MM6_READEROFF = 020, + MM6_READERON = 040, + MM6_FEEDPUNCH = 0100, + MM6_FEEDREAD = 0200, + MM6_REPEAT = 0400, + MM6_MEMDIS = 01000, + + /* Maintenance switches */ + REG6_MAINT_UP = 4, + REG6_MAINT_DN = 5, + + /* switches and knobs */ + REG6_DSLT = 6, + REG6_DSRT = 7, + REG6_MAS = 010, + REG6_REPEAT = 011, + + /* lights */ + REG6_IR = 012, + REG6_MILT = 013, + REG6_MIRT = 014, + REG6_PC = 015, + REG6_MA = 016, + REG6_PI = 017, + + /* TODO: more */ +}; + +static int fd6; + +enum +{ + WRRQ = 1, + RDRQ = 2, + ACK = 3, + ERR = 4, +}; + +void +writereg(u32 addr, u32 data) +{ + u8 msg[11]; + u16 len; + + msg[0] = 0; + msg[1] = 9; + msg[2] = WRRQ; + msg[3] = addr; + msg[4] = addr>>8; + msg[5] = addr>>16; + msg[6] = addr>>24; + msg[7] = data; + msg[8] = data>>8; + msg[9] = data>>16; + msg[10] = data>>24; + write(fd6, msg, msg[1]+2); + + // expecting ACK message + if(readn(fd6, msg, 2)){ + printf("CLOSE!\r\n"); + quit(); + } + len = msg[0]<<8 | msg[1]; + if(len != 1){ + printf("BOTCH! %X %X\r\n", msg[0], msg[1]); + quit(); + } + if(readn(fd6, msg, len)){ + printf("CLOSE!\r\n"); + quit(); + } + if(msg[0] != ACK){ + printf("BOTCH! type %d\r\n", msg[0]); + quit(); + } +} + +u32 +readreg(u32 addr) +{ + u8 msg[11]; + u16 len; + u32 data; + + msg[0] = 0; + msg[1] = 5; + msg[2] = RDRQ; + msg[3] = addr; + msg[4] = addr>>8; + msg[5] = addr>>16; + msg[6] = addr>>24; + write(fd6, msg, msg[1]+2); + + if(readn(fd6, msg, 2)){ + printf("CLOSE!\r\n"); + quit(); + } + len = msg[0]<<8 | msg[1]; + if(len != 5){ + printf("BOTCH! len %d\r\n", len); + quit(); + } + if(readn(fd6, msg, len)){ + printf("CLOSE!\r\n"); + quit(); + } + if(msg[0] != ACK){ + printf("BOTCH! %d\r\n", msg[0]); + quit(); + } + data = msg[1] | msg[2]<<8 | msg[3]<<16 | msg[4]<<24; + return data; +} + +void +deposit(hword a, word w) +{ + if(a <= 01000017){ + writereg(MEMIF_BASE, a); + writereg(MEMIF_BASE+1, w & 0777777); + writereg(MEMIF_BASE+2, (w>>18) & 0777777); + }else if(a >= APR_DS && a <= APR_END){ + switch(a){ + case APR_DS: + writereg(APR_BASE+REG6_DSLT, w>>18 & RT); + writereg(APR_BASE+REG6_DSRT, w & RT); + break; + case APR_MAS: + writereg(APR_BASE+REG6_MAS, w & RT); + break; + case APR_RPT: + writereg(APR_BASE+REG6_REPEAT, w); + break; + +#ifdef TEST + case APR_CTL1_DN: + writereg(APR_BASE+REG6_CTL1_DN, w); + break; + case APR_CTL1_UP: + writereg(APR_BASE+REG6_CTL1_UP, w); + break; + case APR_CTL2_DN: + writereg(APR_BASE+REG6_CTL2_DN, w); + break; + case APR_CTL2_UP: + writereg(APR_BASE+REG6_CTL2_UP, w); + break; +#endif + } + } +} + +word +examine(hword a) +{ + word w; + if(a <= 01000017){ + writereg(MEMIF_BASE, a); + w = readreg(MEMIF_BASE+2) & 0777777; + w <<= 18; + w |= readreg(MEMIF_BASE+1) & 0777777; + }else if(a >= APR_DS && a < APR_END){ + switch(a){ + case APR_DS: + w = readreg(APR_BASE+REG6_DSLT); + w <<= 18; + w |= readreg(APR_BASE+REG6_DSRT) & RT; + return w; + case APR_MAS: + w = readreg(APR_BASE+REG6_MAS); + break; + case APR_RPT: + w = readreg(APR_BASE+REG6_REPEAT); + break; + + case APR_IR: + return readreg(APR_BASE+REG6_IR); + case APR_MI: + w = readreg(APR_BASE+REG6_MILT); + w <<= 18; + w |= readreg(APR_BASE+REG6_MIRT) & RT; + return w; + case APR_PC: + return readreg(APR_BASE+REG6_PC); + case APR_MA: + return readreg(APR_BASE+REG6_MA); + case APR_PIO: + return readreg(APR_BASE+REG6_PI)>>1 & 0177; + case APR_PIR: + return readreg(APR_BASE+REG6_PI)>>8 & 0177; + case APR_PIH: + return readreg(APR_BASE+REG6_PI)>>15 & 0177; + case APR_PION: + return readreg(APR_BASE+REG6_PI) & 1; + + case APR_RUN: + return !!(readreg(APR_BASE+REG6_CTL1_DN) & MM6_RUN); + case APR_STOP: + return !!(readreg(APR_BASE+REG6_CTL1_DN) & MM6_MCSTOP); + +#ifdef TEST + case APR_CTL1_DN: + return readreg(APR_BASE+REG6_CTL1_DN); + case APR_CTL1_UP: + return readreg(APR_BASE+REG6_CTL1_UP); + case APR_CTL2_DN: + return readreg(APR_BASE+REG6_CTL2_DN); + case APR_CTL2_UP: + return readreg(APR_BASE+REG6_CTL2_UP); +#endif + + default: + w = 0; + } + }else + w = 0; + return w; +} + +static void set_ta(hword a) +{ + writereg(APR_BASE+REG6_MAS, a & RT); +} + +static void set_td(word d) +{ + writereg(APR_BASE+REG6_DSLT, d>>18 & RT); + writereg(APR_BASE+REG6_DSRT, d & RT); +} + +static void keydown(u32 k) +{ + writereg(APR_BASE+REG6_CTL1_DN, k); +} + +static void keyup(u32 k) +{ + writereg(APR_BASE+REG6_CTL1_UP, k); +} + +static void keytoggle(u32 k) { keydown(k); keyup(k); } + +int isrunning(void) +{ + return !!(readreg(APR_BASE+REG6_CTL1_DN) & MM6_RUN); +} +int isstopped(void) +{ + return !!(readreg(APR_BASE+REG6_CTL1_DN) & MM6_MCSTOP); +} + +static void waithalt(void) +{ + int i; + for(i = 0; i < 10; i++){ + if(!isrunning()) + return; + usleep(100); + } + keytoggle(MM6_INSTSTOP); + for(i = 0; i < 10; i++){ + if(!isrunning()) + return; + usleep(100); + } + typestr("not halted!!!\r\n"); +} + +static void waitmemstop(void) +{ + int i; + if(!isrunning()) + return; + for(i = 0; i < 10; i++){ + if(isstopped()) + return; + usleep(100); + } + keytoggle(MM6_MEMSTOP); + for(i = 0; i < 10; i++){ + if(isstopped()) + return; + usleep(100); + } + typestr("not stopped!!!\r\n"); +} + +static int run; +static int memstop; +#define X if(0) + +void +cpu_start(hword a) +{ +X typestr("\r\n"); + + cpu_stopinst(); + X run = 0; + keyup(MM6_STOP | MM6_ADRSTOP); + set_ta(a); + keytoggle(MM6_START); + X run = 1; + X memstop = 0; +} + +void +cpu_readin(hword a) +{ +X typestr("\r\n"); + + cpu_stopinst(); + X run = 0; + keyup(MM6_STOP | MM6_ADRSTOP); + set_ta(a); + keytoggle(MM6_READIN); + X run = 1; + X memstop = 0; +} + +void +cpu_setpc(hword a) +{ +X typestr("\r\n"); + + cpu_stopinst(); + X run = 0; + keydown(MM6_MEMSTOP); + keyup(MM6_ADRSTOP); + set_ta(a); + keytoggle(MM6_START); + X run = 1; + X memstop = 0; + waitmemstop(); + X memstop = 1; + keyup(MM6_MEMSTOP); + keytoggle(MM6_INSTSTOP); + X run = 0; +} + +void +cpu_stopinst(void) +{ +X typestr("\r\n"); + + if(!isrunning()) + return; + keytoggle(MM6_INSTSTOP); + waithalt(); + X run = 0; +} + +void +cpu_stopmem(void) +{ +X typestr("\r\n"); + + if(!isrunning() || isstopped()) + return; + keytoggle(MM6_MEMSTOP); + waitmemstop(); + X memstop = 1; +} + +static void +togglecont(void) +{ + if(isstopped()){ + keytoggle(MM6_MEMCONT); + X memstop = 0; + }else{ + keytoggle(MM6_INSTCONT); + X memstop = 0; + X run = 1; + } +} + +void +cpu_cont(void) +{ +X typestr("\r\n"); + + if(isrunning()) + return; + keyup(MM6_STOP); + togglecont(); +} + +void +cpu_nextinst(void) +{ +X typestr("\r\n"); + + if(isrunning() && !isstopped()) + err("?R? "); + keydown(MM6_INSTSTOP); + X run = 0; + togglecont(); + waithalt(); + X run = 0; + keyup(MM6_INSTSTOP); +} + +void +cpu_nextmem(void) +{ +X typestr("\r\n"); + + if(isrunning() && !isstopped()) + err("?R? "); + keydown(MM6_MEMSTOP); + togglecont(); + waitmemstop(); + X memstop = 1; + keyup(MM6_MEMSTOP); +} + +void +cpu_exec(word inst) +{ +X typestr("\r\n"); + + if(isrunning()) + err("?R? "); + set_td(inst); + keytoggle(MM6_EXEC); +} + +void +cpu_ioreset(void) +{ +X typestr("\r\n"); + + if(isrunning()) + err("?R? "); + keytoggle(MM6_RESET); +} + +void +cpu_printflags(void) +{ +} + +void fe_svc(void) {} + +void +init6(void) +{ + printf("waiting for connection\n"); + fd6 = serve1(10007); + printf("fd = %d\n", fd6); + if(fd6 < 0) + exit(0); + +// deposit(0, 0777000777000); +// deposit(1, 0000777000777); +// deposit(010, 01234); +} + +void +deinit6(void) +{ +} diff --git a/fe6/fake.c b/fe6/fake.c new file mode 100644 index 0000000..3118d20 --- /dev/null +++ b/fe6/fake.c @@ -0,0 +1,220 @@ +#include "fe6.h" +#include + +static word memory[01000000]; + +void +deposit(hword a, word w) +{ + if((a & LT) == 0) + memory[a&0777777] = w; +} + +word +examine(hword a) +{ + if((a & LT) == 0) + return memory[a&0777777]; + return 0; +} + +static int run; +static int memstop; + +static void set_ta(hword a) { printf(" TA<-%o\r\n", a); fflush(stdout); } +static void set_td(word d) { printf(" TD<-%llo\r\n", d); fflush(stdout); } +static void keydown(char *k) { printf(" %s down\r\n", k); fflush(stdout); } +static void keyup(char *k) { printf(" %s up\r\n", k); fflush(stdout); } +static void keytoggle(char *k) { keydown(k); keyup(k); } +static void waithalt(void) { printf(" WAIT HALT\r\n"); fflush(stdout); } +static void waitmemstop(void) { printf(" WAIT MEMSTOP\r\n"); fflush(stdout); } +int isrunning(void ) { return run; } +int isstopped(void ) { return memstop; } + +#define X if(1) + +void +cpu_start(hword a) +{ + typestr("\r\n"); + + cpu_stopinst(); + X run = 0; + keyup("STOP"); + keyup("ADR_STOP"); + set_ta(a); + keytoggle("START"); + X run = 1; + X memstop = 0; +} + +void +cpu_readin(hword a) +{ + typestr("\r\n"); + + cpu_stopinst(); + X run = 0; + keyup("STOP"); + keyup("ADR_STOP"); + set_ta(a); + keytoggle("READIN"); + X run = 1; + X memstop = 0; +} + +void +cpu_setpc(hword a) +{ + typestr("\r\n"); + + cpu_stopinst(); + X run = 0; + keydown("MEM_STOP"); + keyup("ADR_STOP"); + set_ta(a); + keytoggle("START"); + X run = 1; + X memstop = 0; + waitmemstop(); + X memstop = 1; + keyup("MEM_STOP"); + keytoggle("INST_STOP"); + X run = 0; +} + +void +cpu_stopinst(void) +{ + typestr("\r\n"); + + if(!isrunning()) + return; + keytoggle("INST_STOP"); + waithalt(); + X run = 0; +} + +void +cpu_stopmem(void) +{ + typestr("\r\n"); + + if(!isrunning() || isstopped()) + return; + keytoggle("MEM_STOP"); + waitmemstop(); + X memstop = 1; +} + +static void +togglecont(void) +{ + if(isstopped()){ + keytoggle("MEM_CONT"); + X memstop = 0; + }else{ + keytoggle("INST_CONT"); + X memstop = 0; + X run = 1; + } +} + +void +cpu_cont(void) +{ + typestr("\r\n"); + + if(isrunning()) + return; + keyup("STOP"); + togglecont(); +} + +void +cpu_nextinst(void) +{ + typestr("\r\n"); + + if(isrunning() && !isstopped()) + err("?R? "); + keydown("INST_STOP"); + X run = 0; + togglecont(); + waithalt(); + X run = 0; + keyup("INST_STOP"); +} + +void +cpu_nextmem(void) +{ + typestr("\r\n"); + + if(isrunning() && !isstopped()) + err("?R? "); + keydown("MEM_STOP"); + togglecont(); + waitmemstop(); + X memstop = 1; + keyup("MEM_STOP"); +} + +void +cpu_exec(word inst) +{ + typestr("\r\n"); + + if(isrunning()) + err("?R? "); + set_td(inst); + keytoggle("EXEC"); +} + +void +cpu_ioreset(void) +{ + typestr("\r\n"); + + if(isrunning()) + err("?R? "); + keytoggle("RESET"); +} + +void +cpu_printflags(void) +{ +} + +void fe_svc(void) {} + +void +init6(void) +{ +//return; + deposit(0, 0777000777000); + deposit(1, 0000777000777); + deposit(010, 01234); + +// deposit(020, 01324); + + + deposit(021, 02345); + deposit(022, 03456); + deposit(023, 01); + deposit(024, 0666666555555); + deposit(025, 0111111222222); + + deposit(030, 012341234); + + deposit(034, 01111111); + deposit(035, 02222222); + deposit(036, 03333333); + deposit(037, 04444444); + deposit(040, 05555555); +} + +void +deinit6(void) +{ +} diff --git a/fe6/fe6.c b/fe6/fe6.c new file mode 100644 index 0000000..157b45d --- /dev/null +++ b/fe6/fe6.c @@ -0,0 +1,950 @@ +#include +#include +#include +#include + +#include "fe6.h" + +struct termios tiosaved; +char erasec, killc, intrc; +jmp_buf errjmp; + +int +raw(int fd) +{ + struct termios tio; + if(tcgetattr(fd, &tio) < 0) return -1; + tiosaved = tio; + cfmakeraw(&tio); + if(tcsetattr(fd, TCSAFLUSH, &tio) < 0) return -1; + return 0; +} + +int +reset(int fd) +{ + if(tcsetattr(0, TCSAFLUSH, &tiosaved) < 0) return -1; + return 0; +} + +#define ALT 033 + +char +tyi(void) +{ + char c; + read(0, &c, 1); + return c; +} + +#define CTL(c) ((c) & 037) + +void +tyo_(char c) +{ + write(1, &c, 1); +} + +void +tyo(char c) +{ + static char *alt = "◊"; + static char *ctrl = "↑"; + + if(c < 040){ + switch(c){ + case ALT: + write(1, alt, strlen(alt)); + return; + case CTL('J'): + write(1, &c, 1); + c = CTL('M'); + case CTL('M'): + case CTL('H'): + case CTL('I'): + write(1, &c, 1); + break; + default: + write(1, ctrl, strlen(ctrl)); + c += 0100; + write(1, &c, 1); + } + }else + write(1, &c, 1); +} + +#define ADDRMASK 03777777 + +enum { + BUF_ERR = ~0, + BUF_EMPTY = ~0-1, + + /* typeout modes */ + MODE_NONE = 0, + MODE_NUM, + MODE_HALF, + MODE_SYM, + MODE_ASCII, + MODE_SIXBIT, + MODE_SQUOZE, + + /* flags */ + CF = 1, // one altmode + CCF = 2, // two altmodes + + /* fields */ + F_A = 1, + F_I = 2, + F_AC = 4, + F_FW = 8, + + /* line modes */ + LM_COLON = 1, + LM_LOAD, + LM_DUMP, + LM_MOUNT, + LM_UNMOUNT +}; + +#define BUFLEN 200 + +char buf[BUFLEN+1]; +char *bufstart; +int nbuf; + +int flags; +char ch; +int base = 8; +hword dot; +hword addr; +int opened; +word q; +word number; +int hasnum; +int permmode = MODE_SYM; +int curmode; +struct Assembler +{ + word fields[4]; + int f; + + word exp; + int op; + int gotexp; +}; +struct Assembler as; +struct Assembler astack[8]; +int asp; +hword starta; +int linemode; + +void +typenum(word n) +{ + word d; + d = n % base; + n /= base; + if(n) + typenum(n); + tyo(d + '0'); +} + +void +typestr(char *str) +{ + while(*str) + tyo(*str++); +} + +void +typestrnl(char *str) +{ + while(*str){ + if(*str == '\n') + tyo('\r'); + tyo(*str++); + } +} + +void +typestrnl_(char *str) +{ + while(*str){ + if(*str == '\n') + tyo_('\r'); + tyo_(*str++); + } +} + +void +err(char *str) +{ + typestr(str); + longjmp(errjmp, 0); +} + +void +num(void) +{ + number = number*base + ch-'0'; + hasnum = 1; +} + +void +ins(void) +{ + buf[nbuf++] = ch; + nbuf %= BUFLEN; + buf[nbuf] = '\0'; +} + +word +parsenum(void) +{ + word w; + char *c; + + w = 0; + for(c = bufstart; c < &buf[nbuf]; c++){ + if(*c >= '0' && *c <= '9') + w = w*base + *c-'0'; + else + return BUF_ERR; + w &= 0777777777777; + } + return w; +} + +typedef struct Symbol Symbol; +struct Symbol +{ + char *sym; + word value; +}; + +Symbol symtab[] = { + { "SM", 01000000 }, +// { "MM", 02000000 }, + { "DS", APR_DS }, + { "MAS", APR_MAS }, + { "RPT", APR_RPT }, + { "IR", APR_IR }, + { "MI", APR_MI }, + { "PC", APR_PC }, + { "MA", APR_MA }, + { "PIH", APR_PIH }, + { "PIR", APR_PIR }, + { "PIO", APR_PIO }, + { "RUN", APR_RUN }, + { "PION", APR_PION }, + { "STOP", APR_STOP }, + { "LED", 01001000 }, + { "SW", 01001001 }, + + /* some more instructions */ + { "HALT", 0254200000000 }, + + /* devices, decorated with % */ + { "%APR", 0 }, + { "%PI", 4 }, + { "%PTP", 0100 }, + { "%PTR", 0104 }, + { "%TTY", 0120 }, + { "%DIS", 0130 }, + { "%DC", 0200 }, + { "%UTC", 0204 }, + { "%UTS", 0210 }, +#ifdef TEST + { "CTL1U", APR_CTL1_UP }, + { "CTL1", APR_CTL1_DN }, + { "CTL2U", APR_CTL2_UP }, + { "CTL2", APR_CTL2_DN }, + { "MB", APR_MB }, + { "AR", APR_AR }, + { "MQ", APR_MQ }, + { "TTY.TTI", TTY_TTI }, + { "TTY.ST", TTY_ST }, + { "PTR.PTR", PTR_PTR }, + { "PTR.ST", PTR_ST }, + { "PTR.FE", PTR_FE }, + { "FE.REQ", FE_REQ }, +#endif + { nil, 0 }, +}; + +// for disasm +char *findacsym(word v) { return nil; } +char *findsymval(word v) { return nil; } + +word +parsesym(void) +{ + word i; + + if(strcmp(bufstart, ".") == 0) + return dot; + + for(i = 0; symtab[i].sym; i++) + if(strcasecmp(bufstart, symtab[i].sym) == 0) + return symtab[i].value; + + for(i = 0; i < 0700; i++) + if(mnemonics[i] && strcasecmp(mnemonics[i], bufstart) == 0) + return i << 27; + for(i = 0; i < 8; i++) + if(strcasecmp(iomnemonics[i], bufstart) == 0) + return (word)0700<<27 | i<<23; + return BUF_ERR; +} + +void +trimbuf(void) +{ + bufstart = buf; + while(isspace(*bufstart)) bufstart++; + while(&buf[nbuf] > bufstart && isspace(buf[nbuf-1])) nbuf--; + buf[nbuf] = '\0'; +} + +/* parse input buffer, error if can't parse + * return 0 if empty */ +int +parse(word *t) +{ + word w; + + // this should be unnecessary now + trimbuf(); + + w = parsenum(); + if(bufstart >= &buf[nbuf]) + return 0; + if((w = parsenum()) == BUF_ERR && (w = parsesym()) == BUF_ERR) + err("?U? "); + nbuf = 0; + *t = w; + return 1; +} + +void +resetexp(void) +{ + as.fields[0] = 0; + as.fields[1] = 0; + as.fields[2] = 0; + as.fields[3] = 0; + as.f = 0; + + as.exp = 0; + as.op = 0; + as.gotexp = 0; +} + +void +pushexp(void) +{ + astack[asp] = as; + asp++; + if(asp >= 8) + err(" XXX "); + resetexp(); +} + +void +popexp(void) +{ + if(asp < 0) + err(" XXX "); + asp--; + as = astack[asp]; +} + +/* combine word t into current expression */ +void +combine(word t) +{ + switch(as.op){ + case '+': + default: + as.exp += t; + break; + case '-': + as.exp -= t; + break; + case '*': + as.exp *= t; + break; + case '|': + as.exp /= t; + break; + } + as.gotexp = 1; + as.op = 0; +} + +/* assemble storage word and set *w + * if no word, don't change *w and return 0 */ +int +endword(word *w) +{ + word t; + + if(!parse(&t)){ + if(!as.gotexp) + return 0; + t = 0; + } + combine(t); + if(as.f & (F_FW|F_AC)){ + // add to address field + as.fields[3] += as.exp; + as.f |= F_A; + }else{ + as.fields[0] += as.exp; + as.f |= F_FW; + } + t = as.fields[0]; + if(as.f & F_AC){ + if((t & 0700000000000) == 0700000000000) + t += (as.fields[1]&0774)<<24; + else + t += (as.fields[1]&017)<<23; + } + if(as.f & F_I) + if((t & 020000000) == 0) + t += as.fields[2]&020000000; + if(as.f & F_A) + t = (t<) + ((t+as.fields[3])&RT); + t &= LT|RT; + *w = t; + resetexp(); + return 1; +} + +void +prword(int mode, word wd) +{ + int i; + char c; + char s[7]; + + switch(mode){ + case MODE_ASCII: + tyo(ALT); + tyo('0' + (wd&1)); + tyo('"'); + for(i = 0; i < 5; i++){ + c = (wd >> ((7*(4-i))+1)) & 0177; + if(c < 040 || c == 0177){ + tyo('^'); + tyo(c ^ 0100); + }else + tyo(c); + } + tyo(ALT); + break; + + case MODE_SIXBIT: + tyo(ALT); + tyo('1'); + tyo('\''); + for(i = 0; i < 6; i++){ + c = (wd >> (6*(5-i))) & 077; + tyo(c + 040); + } + tyo(ALT); + break; + + case MODE_SQUOZE: + tyo(ALT); + typenum(unrad50(wd, s)); + tyo('&'); + typestr(s); + tyo(ALT); + break; + + break; + + case MODE_SYM: + typestr(disasm(wd)); + break; + + case MODE_HALF: + tyo('('); + typenum(wd&0777777); + tyo(')'); + typenum((wd>>18)&0777777); + break; + + default: + typenum(wd); + } +} + +void +typeout(int mode) +{ + endword(&q); + prword(mode, q); + typestr(" "); +} + +void +propen(hword a) +{ + prword(curmode, a); + tyo('/'); +} + +void +aclose(int ins) +{ + // this is a bit ugly... + // we don't want ^M to set Q if no location is open + word t; + t = q; + if(endword(&q) && opened && ins) + deposit(addr, q); + addr = q & ADDRMASK; + if(!opened) + q = t; + opened = 0; +} + +void +aopen(int mode) +{ + opened = 1; + q = examine(addr); + typestr(" "); + if(mode != MODE_NONE) + typeout(mode); +} + +void +modechange(int mode) +{ + curmode = mode; + if(flags & CCF){ + permmode = mode; + typestr(" "); + } +} + +void +runline(void) +{ + /* TODO: this can be improved */ + switch(linemode){ + case LM_COLON: + coloncmd(buf); + break; + case LM_LOAD: + docmd("load", buf); + break; + case LM_DUMP: + docmd("dump", buf); + break; + case LM_MOUNT: + docmd("mount", buf); + break; + case LM_UNMOUNT: + docmd("unmount", buf); + break; + } +} + +void +quit(void) +{ + reset(0); + putchar('\n'); + + deinit6(); + exit(0); +} + +int started; + +int +main() +{ + char chu; + word t; + + init6(); + + raw(0); + erasec = tiosaved.c_cc[VERASE]; + killc = tiosaved.c_cc[VKILL]; + intrc = tiosaved.c_cc[VINTR]; + + setjmp(errjmp); + nbuf = 0; + opened = 0; + resetexp(); + flags = 0; + curmode = permmode; + number = 0; + hasnum = 0; + linemode = 0; + + for(;;){ + if(hasinput(0)){ + ch = tyi(); + }else{ + if(started && (!isrunning() || isstopped())){ + t = examine(APR_PC); + /* TODO: maybe do something different on stop? */ + typestrnl("\n"); + typenum(t); + if(!isrunning()) + typestr(">>"); + else + typestr("<<"); + t = examine(t); + prword(MODE_SYM, t); + typestr(" "); + + /* show AC or E */ + if((t&0700000000000) == 0700000000000){ + t = t&RT; + }else{ + t = t>>23 & 017; + } + dot = t; + prword(MODE_SYM, dot); + typestr("/ "); + t = examine(t); + prword(MODE_SYM, t); + typestr(" "); + + started = 0; + } + fe_svc(); + // usleep(1000); + continue; + } + + chu = toupper(ch); + if(ch == erasec || ch == CTL('H') || ch == CTL('?')){ + /* can't backspace in all cases */ + if((flags & CF) || nbuf <= 0) + err("\r\n"); + typestr("\b \b"); + nbuf--; + }else if(ch == killc) + err(""); + else if(ch == intrc) + break; + else if(linemode){ + if(ch == '\r' || ch == '\n'){ + typestrnl("\n"); + runline(); + err(""); + }else{ + tyo(ch); + ins(); + } + }else{ + tyo(ch); + + if((flags & CF) == 0 && + (ch >= 'A' && ch <= 'Z' || + ch >= 'a' && ch <= 'z')){ + ins(); + }else switch(chu){ + case ':': + linemode = LM_COLON; + nbuf = 0; + break; + case 'L': + tyo(' '); + linemode = LM_LOAD; + nbuf = 0; + break; + case 'Y': + tyo(' '); + linemode = LM_DUMP; + nbuf = 0; + break; + + case '?': + typestrnl_(flags & CF ? colhelpstr : helpstr); + break; + + case CTL('D'): + err("XXX? "); + break; + + case '.': case '%': case '$': + ins(); + break; + + case '0': case '1': case '2': case '3': + case '4': case '5': case '6': case '7': + case '8': case '9': + if(flags & CF){ + num(); + goto keepflags; + } + ins(); + break; + + case 'F': + cpu_printflags(); + break; + + case 'G': + if(!endword(&t)) + t = starta; + if(flags & CCF) + starta = t; + if(hasnum && number == 0) + cpu_setpc(t); + else + cpu_start(t); + started = 1; + break; + + case 'R': + if(!endword(&t)) + t = starta; + if(flags & CCF) + starta = t; + cpu_readin(t); + started = 1; + break; + + case CTL('Z'): + nbuf = 0; + if(flags & CF) + cpu_stopmem(); + else + cpu_stopinst(); + break; + + case 'P': + endword(&t); + cpu_cont(); + started = 1; + break; + + case CTL('N'): + endword(&t); + if(flags & CF) + cpu_nextmem(); + else + cpu_nextinst(); + started = 1; + break; + + case 'X': + if(!endword(&t)) + t = q; + cpu_exec(t); + typestrnl("\n"); + break; + + case 'I': + nbuf = 0; + cpu_ioreset(); + break; + + case 'Q': + combine(q); + break; + + case ALT: + if(flags & CF) + flags |= CCF; + flags |= CF; + goto keepflags; + + /* expressions */ + case '+': + case '-': + case '*': + case '|': + if(!parse(&t)){ + if(ch == '-') + as.op = '-'; + break; + } + combine(t); + as.op = ch; + break; + case '(': + if(parse(&t)) + combine(t); + pushexp(); + break; + case ')': + t = 0; + endword(&t); + popexp(); + if(as.op == 0){ + t = (t<)>>18 | (t&RT)<<18; + as.fields[0] += t; + as.gotexp = 1; + }else{ + combine(t); + } + as.op = 0; + break; + + /* word assembly */ + case ' ': + if(!parse(&t)) + break; + combine(t); + if(as.f & F_FW){ + // add to address field + // if we have a full word already + as.fields[3] += as.exp; + as.f |= F_A; + }else{ + as.fields[0] += as.exp; + as.f |= F_FW; + } + as.exp = 0; + break; + case ',': + if(!parse(&t)) + break; + combine(t); + if(as.f & F_AC){ + // add to address field + // if we have an AC already + as.fields[3] += as.exp; + as.f |= F_A; + }else{ + as.fields[1] += as.exp; + as.f |= F_AC; + } + as.exp = 0; + break; + case '@': + as.fields[2] += 020000000; + as.f |= F_I; + as.gotexp = 1; + break; + + /* opening */ + case '/': + aclose(0); + dot = addr; + aopen(curmode); + break; + case '\\': + aclose(0); + aopen(curmode); + break; + case '[': + if(flags & CF){ + tyo(' '); + linemode = LM_MOUNT; + nbuf = 0; + break; + } + aclose(0); + dot = addr; + aopen(MODE_NUM); + break; + case ']': + if(flags & CF){ + tyo(' '); + linemode = LM_UNMOUNT; + nbuf = 0; + break; + } + aclose(0); + dot = addr; + aopen(MODE_SYM); + break; + case '!': + aclose(0); + dot = addr; + aopen(MODE_NONE); + break; + + case CTL('I'): + typestrnl("\n"); + aclose(1); + dot = addr; + propen(addr); + aopen(curmode); + break; + case '^': + typestrnl("\n"); + aclose(1); + dot = (dot-1) & ADDRMASK; + addr = dot; + propen(addr); + aopen(curmode); + break; + case CTL('J'): + tyo('\r'); + aclose(1); + dot = (dot+1) & ADDRMASK; + addr = dot; + propen(addr); + aopen(curmode); + break; + + case CTL('M'): + tyo('\n'); + aclose(1); + curmode = permmode; + break; + + /* typeout */ + case '_': + typeout(MODE_SYM); + break; + case '=': + typeout(MODE_NUM); + break; + case '"': + if(flags & CF) + modechange(MODE_ASCII); + else + typeout(MODE_ASCII); + break; + case '\'': + if(flags & CF) + modechange(MODE_SIXBIT); + else + typeout(MODE_SIXBIT); + break; + case '&': + if(flags & CF) + modechange(MODE_SQUOZE); + else + typeout(MODE_SQUOZE); + break; + case 'S': + modechange(MODE_SYM); + break; + case 'C': + modechange(MODE_NUM); + break; + case 'H': + modechange(MODE_HALF); + break; + + default: + err(" ?? "); + break; + } + } + flags = 0; + number = 0; + hasnum = 0; +keepflags:; + } + + quit(); + + return 0; +} diff --git a/fe6/fe6.h b/fe6/fe6.h new file mode 100644 index 0000000..220d808 --- /dev/null +++ b/fe6/fe6.h @@ -0,0 +1,111 @@ +#include +#include +#include +#include +#include +#include "util.h" +#include "pdp6common.h" + +#define nil NULL + +typedef uint64_t u64, word; +typedef uint32_t u32, hword; +typedef uint16_t u16; +typedef uint8_t u8; + +#define LT 0777777000000 +#define RT 0777777 +#define FW (LT|RT) +#define F0 0400000000000 + +#define MAXMEM (16*1024) + +enum { + APR_DS = 01000020, + APR_MAS, + APR_RPT, + APR_IR, + APR_MI, + APR_PC, + APR_MA, + APR_PIH, + APR_PIR, + APR_PIO, + APR_RUN, + APR_PION, + APR_STOP, + +#ifdef TEST + APR_CTL1_DN, + APR_CTL1_UP, + APR_CTL2_DN, + APR_CTL2_UP, + APR_MB, + APR_AR, + APR_MQ, + + TTY_TTI, + TTY_ST, + PTR_PTR, + PTR_ST, + PTR_FE, + + FE_REQ, +#endif + + APR_END, +}; + +/* FE devices */ +enum +{ + DEV_PTR = 0, + DEV_PTP, +}; + +struct dev +{ + char *devname; + int mode; + int fd; + char *path; +}; +extern struct dev devtab[]; + + +extern hword starta; +extern int started; +extern char *helpstr, *colhelpstr; + +char *findacsym(word v); +char *findsymval(word v); + +void quit(void); +void err(char *str); +void typestr(char *str); +void typestrnl(char *str); + +void coloncmd(char *line); +void docmd(char *cmd, char *line); + +int isrunning(void); +int isstopped(void); + +void deposit(hword a, word w); +word examine(hword a); +void cpu_start(hword a); +void cpu_readin(hword a); +void cpu_setpc(hword pc); +void cpu_stopinst(void); +void cpu_stopmem(void); +void cpu_cont(void); +void cpu_nextinst(void); +void cpu_nextmem(void); +void cpu_exec(word inst); +void cpu_ioreset(void); +void cpu_printflags(void); + +void fe_svc(void); + +void init6(void); +void deinit6(void); diff --git a/fe6/hps_0.h b/fe6/hps_0.h new file mode 100755 index 0000000..4ad9d1c --- /dev/null +++ b/fe6/hps_0.h @@ -0,0 +1,160 @@ +#ifndef _ALTERA_HPS_0_H_ +#define _ALTERA_HPS_0_H_ + +/* + * This file was automatically generated by the swinfo2header utility. + * + * Created from SOPC Builder system 'soc_system' in + * file '/cygdrive/e/DE0_Nano_SoC/Dev/HPS_CONTROL_FPGA_LED/soc_system.sopcinfo'. + */ + +/* + * This file contains macros for module 'hps_0' and devices + * connected to the following masters: + * h2f_axi_master + * h2f_lw_axi_master + * + * Do not include this header file and another header file created for a + * different module or master group at the same time. + * Doing so may result in duplicate macro names. + * Instead, use the system header file which has macros with unique names. + */ + +/* + * Macros for device 'onchip_memory2_0', class 'altera_avalon_onchip_memory2' + * The macros are prefixed with 'ONCHIP_MEMORY2_0_'. + * The prefix is the slave descriptor. + */ +#define ONCHIP_MEMORY2_0_COMPONENT_TYPE altera_avalon_onchip_memory2 +#define ONCHIP_MEMORY2_0_COMPONENT_NAME onchip_memory2_0 +#define ONCHIP_MEMORY2_0_BASE 0x0 +#define ONCHIP_MEMORY2_0_SPAN 65536 +#define ONCHIP_MEMORY2_0_END 0xffff +#define ONCHIP_MEMORY2_0_ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0 +#define ONCHIP_MEMORY2_0_ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0 +#define ONCHIP_MEMORY2_0_CONTENTS_INFO "" +#define ONCHIP_MEMORY2_0_DUAL_PORT 0 +#define ONCHIP_MEMORY2_0_GUI_RAM_BLOCK_TYPE AUTO +#define ONCHIP_MEMORY2_0_INIT_CONTENTS_FILE soc_system_onchip_memory2_0 +#define ONCHIP_MEMORY2_0_INIT_MEM_CONTENT 1 +#define ONCHIP_MEMORY2_0_INSTANCE_ID NONE +#define ONCHIP_MEMORY2_0_NON_DEFAULT_INIT_FILE_ENABLED 0 +#define ONCHIP_MEMORY2_0_RAM_BLOCK_TYPE AUTO +#define ONCHIP_MEMORY2_0_READ_DURING_WRITE_MODE DONT_CARE +#define ONCHIP_MEMORY2_0_SINGLE_CLOCK_OP 0 +#define ONCHIP_MEMORY2_0_SIZE_MULTIPLE 1 +#define ONCHIP_MEMORY2_0_SIZE_VALUE 65536 +#define ONCHIP_MEMORY2_0_WRITABLE 1 +#define ONCHIP_MEMORY2_0_MEMORY_INFO_DAT_SYM_INSTALL_DIR SIM_DIR +#define ONCHIP_MEMORY2_0_MEMORY_INFO_GENERATE_DAT_SYM 1 +#define ONCHIP_MEMORY2_0_MEMORY_INFO_GENERATE_HEX 1 +#define ONCHIP_MEMORY2_0_MEMORY_INFO_HAS_BYTE_LANE 0 +#define ONCHIP_MEMORY2_0_MEMORY_INFO_HEX_INSTALL_DIR QPF_DIR +#define ONCHIP_MEMORY2_0_MEMORY_INFO_MEM_INIT_DATA_WIDTH 64 +#define ONCHIP_MEMORY2_0_MEMORY_INFO_MEM_INIT_FILENAME soc_system_onchip_memory2_0 + +/* + * Macros for device 'sysid_qsys', class 'altera_avalon_sysid_qsys' + * The macros are prefixed with 'SYSID_QSYS_'. + * The prefix is the slave descriptor. + */ +#define SYSID_QSYS_COMPONENT_TYPE altera_avalon_sysid_qsys +#define SYSID_QSYS_COMPONENT_NAME sysid_qsys +#define SYSID_QSYS_BASE 0x10000 +#define SYSID_QSYS_SPAN 8 +#define SYSID_QSYS_END 0x10007 +#define SYSID_QSYS_ID 2899645186 +#define SYSID_QSYS_TIMESTAMP 1420572267 + +/* + * Macros for device 'led_pio', class 'altera_avalon_pio' + * The macros are prefixed with 'LED_PIO_'. + * The prefix is the slave descriptor. + */ +#define LED_PIO_COMPONENT_TYPE altera_avalon_pio +#define LED_PIO_COMPONENT_NAME led_pio +#define LED_PIO_BASE 0x10040 +#define LED_PIO_SPAN 32 +#define LED_PIO_END 0x1005f +#define LED_PIO_BIT_CLEARING_EDGE_REGISTER 0 +#define LED_PIO_BIT_MODIFYING_OUTPUT_REGISTER 0 +#define LED_PIO_CAPTURE 0 +#define LED_PIO_DATA_WIDTH 4 +#define LED_PIO_DO_TEST_BENCH_WIRING 0 +#define LED_PIO_DRIVEN_SIM_VALUE 0 +#define LED_PIO_EDGE_TYPE NONE +#define LED_PIO_FREQ 50000000 +#define LED_PIO_HAS_IN 0 +#define LED_PIO_HAS_OUT 1 +#define LED_PIO_HAS_TRI 0 +#define LED_PIO_IRQ_TYPE NONE +#define LED_PIO_RESET_VALUE 0 + +/* + * Macros for device 'dipsw_pio', class 'altera_avalon_pio' + * The macros are prefixed with 'DIPSW_PIO_'. + * The prefix is the slave descriptor. + */ +#define DIPSW_PIO_COMPONENT_TYPE altera_avalon_pio +#define DIPSW_PIO_COMPONENT_NAME dipsw_pio +#define DIPSW_PIO_BASE 0x10080 +#define DIPSW_PIO_SPAN 32 +#define DIPSW_PIO_END 0x1009f +#define DIPSW_PIO_IRQ 0 +#define DIPSW_PIO_BIT_CLEARING_EDGE_REGISTER 1 +#define DIPSW_PIO_BIT_MODIFYING_OUTPUT_REGISTER 0 +#define DIPSW_PIO_CAPTURE 1 +#define DIPSW_PIO_DATA_WIDTH 4 +#define DIPSW_PIO_DO_TEST_BENCH_WIRING 0 +#define DIPSW_PIO_DRIVEN_SIM_VALUE 0 +#define DIPSW_PIO_EDGE_TYPE ANY +#define DIPSW_PIO_FREQ 50000000 +#define DIPSW_PIO_HAS_IN 1 +#define DIPSW_PIO_HAS_OUT 0 +#define DIPSW_PIO_HAS_TRI 0 +#define DIPSW_PIO_IRQ_TYPE EDGE +#define DIPSW_PIO_RESET_VALUE 0 + +/* + * Macros for device 'button_pio', class 'altera_avalon_pio' + * The macros are prefixed with 'BUTTON_PIO_'. + * The prefix is the slave descriptor. + */ +#define BUTTON_PIO_COMPONENT_TYPE altera_avalon_pio +#define BUTTON_PIO_COMPONENT_NAME button_pio +#define BUTTON_PIO_BASE 0x100c0 +#define BUTTON_PIO_SPAN 32 +#define BUTTON_PIO_END 0x100df +#define BUTTON_PIO_IRQ 1 +#define BUTTON_PIO_BIT_CLEARING_EDGE_REGISTER 1 +#define BUTTON_PIO_BIT_MODIFYING_OUTPUT_REGISTER 0 +#define BUTTON_PIO_CAPTURE 1 +#define BUTTON_PIO_DATA_WIDTH 4 +#define BUTTON_PIO_DO_TEST_BENCH_WIRING 0 +#define BUTTON_PIO_DRIVEN_SIM_VALUE 0 +#define BUTTON_PIO_EDGE_TYPE FALLING +#define BUTTON_PIO_FREQ 50000000 +#define BUTTON_PIO_HAS_IN 1 +#define BUTTON_PIO_HAS_OUT 0 +#define BUTTON_PIO_HAS_TRI 0 +#define BUTTON_PIO_IRQ_TYPE EDGE +#define BUTTON_PIO_RESET_VALUE 0 + +/* + * Macros for device 'jtag_uart', class 'altera_avalon_jtag_uart' + * The macros are prefixed with 'JTAG_UART_'. + * The prefix is the slave descriptor. + */ +#define JTAG_UART_COMPONENT_TYPE altera_avalon_jtag_uart +#define JTAG_UART_COMPONENT_NAME jtag_uart +#define JTAG_UART_BASE 0x20000 +#define JTAG_UART_SPAN 16 +#define JTAG_UART_END 0x2000f +#define JTAG_UART_IRQ 2 +#define JTAG_UART_READ_DEPTH 64 +#define JTAG_UART_READ_THRESHOLD 8 +#define JTAG_UART_WRITE_DEPTH 64 +#define JTAG_UART_WRITE_THRESHOLD 8 + + +#endif /* _ALTERA_HPS_0_H_ */ diff --git a/fe6/main_0.c b/fe6/main_0.c new file mode 100755 index 0000000..d6c4fa1 --- /dev/null +++ b/fe6/main_0.c @@ -0,0 +1,103 @@ +#include "test.h" +#include +#include +#include +#include "hps_0.h" +#include "led.h" + +#define H2F_BASE (0xC0000000) + +#define PERIPH_BASE (0xFC000000) +#define PERIPH_SPAN (0x04000000) +#define PERIPH_MASK (PERIPH_SPAN - 1) + +#define LWH2F_BASE (0xFF200000) + +u64 *h2f_base; +u32 *virtual_base; +u32 *getLWH2Faddr(u32 offset) +{ + return (u32*)((u32)virtual_base - PERIPH_BASE + (LWH2F_BASE+offset)); +} +u64 *getH2Faddr(u32 offset) +{ + return (u64*)((u32)h2f_base + offset); +} + +volatile u64 *h2f_axi_onchipmem; +volatile u32 *h2f_lw_led_addr; +volatile u32 *h2f_lw_sw_addr; + + +int +main(int argc, char **argv) +{ + int fd; + int i; + + if((fd = open("/dev/mem", (O_RDWR | O_SYNC))) == -1) { + fprintf(stderr, "ERROR: could not open /dev/mem...\n"); + return 1; + } + virtual_base = (u32*)mmap(nil, PERIPH_SPAN, (PROT_READ | PROT_WRITE), MAP_SHARED, fd, PERIPH_BASE); + if(virtual_base == MAP_FAILED) { + fprintf(stderr, "ERROR: mmap() failed...\n"); + close(fd); + return 1; + } + h2f_base = (u64*)mmap(nil, 0x100000, (PROT_READ | PROT_WRITE), MAP_SHARED, fd, H2F_BASE); + if(h2f_base == MAP_FAILED) { + fprintf(stderr, "ERROR: mmap() failed...\n"); + close(fd); + return 1; + } + + h2f_lw_led_addr = getLWH2Faddr(LED_PIO_BASE); + h2f_lw_sw_addr = getLWH2Faddr(DIPSW_PIO_BASE); + h2f_axi_onchipmem = getH2Faddr(0); + + volatile u32 *cntr_addr = getLWH2Faddr(0x10100); + + printf("%d\n", *cntr_addr); + int n = 0; +// for(i = 0; i < 50000000; i++) +// for(i = 0; i < 1000000; i++) +// n = *cntr_addr; +// printf("%d\n", n); +// return 0; + + h2f_axi_onchipmem[0] = 0xFFFF12345678; + h2f_axi_onchipmem[1] = 0xEEEE11111111; + h2f_axi_onchipmem[2] = 0xDDDD22222222; + h2f_axi_onchipmem[3] = 0xCCCC33333333; + h2f_axi_onchipmem[4] = 0xBBBB44444444; + + for(i = 0; i < 5; i++) + printf("%llX\n", h2f_axi_onchipmem[i]); + + while(1) { + printf("LED ON\n"); + for(i=0; i<=8; i++) { + LEDR_LightCount(i); + usleep(100*1000); + } + + printf("LED OFF\n"); + for(i=0; i<=8; i++) { + LEDR_OffCount(i); + usleep(100*1000); + } + + printf("sw: %X\n", *h2f_lw_sw_addr); + } + + if(munmap(virtual_base, PERIPH_SPAN) != 0) { + fprintf(stderr, "ERROR: munmap() failed...\n"); + close(fd); + return 1; + + } + close(fd); + + return 0; +} diff --git a/fe6/pdp6common.c b/fe6/pdp6common.c new file mode 100644 index 0000000..258dee7 --- /dev/null +++ b/fe6/pdp6common.c @@ -0,0 +1,909 @@ +#include +#include +#include +#include +#include +#include "pdp6common.h" + +word fw(hword l, hword r) { return ((word)right(l) << 18) | (word)right(r); } +word point(word pos, word sz, hword p) { return (pos<<30)|(sz<<24)|p; } +hword left(word w) { return (w >> 18) & 0777777; } +hword right(word w) { return w & 0777777; } +word negw(word w) { return (~w + 1) & 0777777777777; } +int isneg(word w) { return !!(w & 0400000000); } + +/* write word in rim format */ +void +writew(word w, FILE *fp) +{ + int j; + w &= 0777777777777; + for(j = 5; j >= 0; j--) + putc(0200 | (w>>j*6)&077, fp); +} + +word +readw(FILE *fp) +{ + int i, b; + word w; + w = 0; + for(i = 0; i < 6; i++){ + cont: + if(b = getc(fp), b == EOF) + return ~0; + if((b & 0200) == 0) + goto cont; + w = (w << 6) | (b & 077); + } + return w; +} + +/* write word in backup format. This is what pdp10-ka expects. */ +void +writewbak(word w, FILE *fp) +{ + putc((w >> 29) & 0177, fp); + putc((w >> 22) & 0177, fp); + putc((w >> 15) & 0177, fp); + putc((w >> 8) & 0177, fp); + putc((w>>1) & 0177 | (w & 1) << 7, fp); +} + +word +readwbak(FILE *fp) +{ + char buf[5]; + if(fread(buf, 1, 5, fp) != 5) + return ~0; + return (word)buf[0] << 29 | + (word)buf[1] << 22 | + (word)buf[2] << 15 | + (word)buf[3] << 8 | + ((word)buf[4]&0177) << 1 | + ((word)buf[4]&0200) >> 7; +} + + +static int prevbyte = -1; +static void +flush(FILE *fp) +{ + if(prevbyte == 015) + putc(0356, fp); + else if(prevbyte == 0177) + putc(0357, fp); + prevbyte = -1; +} + +static void +binword(word w, FILE *fp) +{ + flush(fp); + + putc(w>>32 & 017 | 0360, fp); + putc(w>>24 & 0377, fp); + putc(w>>16 & 0377, fp); + putc(w>>8 & 0377, fp); + putc(w & 0377, fp); +} + +static void +asciiword(word w, FILE *fp) +{ + int i; + char b, bytes[5]; + + bytes[0] = w>>29 & 0177; + bytes[1] = w>>22 & 0177; + bytes[2] = w>>15 & 0177; + bytes[3] = w>>8 & 0177; + bytes[4] = w>>1 & 0177; + + for(i = 0; i < 5; i++){ + b = bytes[i]; + +again: + if(prevbyte == 015){ + prevbyte = -1; + if(b == 012) + putc(012, fp); + else{ + putc(0356, fp); + goto again; + } + }else if(prevbyte == 0177){ + prevbyte = -1; + switch(b){ + case 7: putc(0177, fp); break; + case 012: putc(0215, fp); break; + case 015: putc(0212, fp); break; + case 0177: putc(0207, fp); break; + default: + if(b <= 0155) + putc(b + 0200, fp); + else{ + putc(0357, fp); + goto again; + } + } + }else if(b == 015 || b == 0177) + prevbyte = b; + else if(b == 012) + putc(015, fp); + else + putc(b, fp); + } +} + +/* write word in ITS evacuate format. */ +void +writewits(word w, FILE *fp) +{ + if(w == ~0){ + flush(fp); + return; + } + + if(w & 1) + binword(w, fp); + else + asciiword(w, fp); +} + +/* read word in ITS evacuate format. */ +static int leftover = -1; +word +readwits(FILE *fp) +{ +#define PUSH(x) w = (w<<7) | ((x) & 0177); bits += 7 + int o; + word w; + int bits; + + if(fp == NULL || feof(fp)){ + leftover = -1; + return ~0; + } + + w = 0; + bits = 0; + + if(leftover >= 0){ + w = leftover; + bits = 7; + leftover = -1; + } + + while(bits < 36){ + o = getc(fp); + if(o == EOF) + if(bits == 0) + return ~0; + + if(o == 012){ + PUSH(015); + PUSH(012); + }else if(o == 015){ + PUSH(012); + }else if(o <= 0176){ + PUSH(o); + }else if(o == 0177){ + PUSH(0177); + PUSH(7); + }else if(o == 0207){ + PUSH(0177); + PUSH(0177); + }else if(o == 0212){ + PUSH(0177); + PUSH(015); + }else if(o == 0215){ + PUSH(0177); + PUSH(012); + }else if(o <= 0355){ + PUSH(0177); + PUSH(o - 0200); + }else if(o == 0356){ + PUSH(015); + }else if(o == 0357){ + PUSH(0177); + }else{ + if(bits != 0){ + fprintf(stderr, "[error in 36-bit file format]\n"); + exit(1); + } + w = o & 017; + w = (w << 8) | getc(fp); + w = (w << 8) | getc(fp); + w = (w << 8) | getc(fp); + w = (w << 8) | getc(fp); + bits = 36; + } + + if(bits == 35){ + w <<= 1; + bits++; + }else if(bits == 42){ + leftover = w & 0177; + w >>= 7; + w <<= 1; + } + } + + if(w > 0777777777777){ + fprintf(stderr, "[error in 36-bit file format (word too large)]\n"); + exit(1); + } + + return w; +} + +/* decompose a double into sign, exponent and mantissa */ +void +decompdbl(double d, int *s, word *e, uint64_t *m) +{ + uint64_t x; + union { + uint64_t i; + double d; + } u; + + u.d = d; x = u.i; + *s = !!(x & 0x8000000000000000); + *e = (x >> 52) & 0x7FF; + *m = x & 0xFFFFFFFFFFFFF; + if(x != 0) + *m |= 0x10000000000000; +} + +/* convert double to PDP-6 float */ +word +dtopdp(double d) +{ + uint64_t x, e, m; + int sign; + word f; + union { + uint64_t i; + double d; + } u; + + sign = 0; + if(d < 0.0){ + sign = 1; + d *= -1.0; + } + u.d = d; x = u.i; + /* sign is guaranteed to be 0 now */ + e = (x >> 52) & 0x7FF; + m = x & 0xFFFFFFFFFFFFF; + e += 128-1023; + m >>= 25; + /* normalize */ + if(x != 0){ + m >>= 1; + m |= 0400000000; + e += 1; + }else + e = 0; + f = e << 27; + f |= m; + if(sign) + f = -f & 0777777777777; + return f; +} + +/* convert PDP-6 float to double */ +double +pdptod(word f) +{ + uint64_t x, s, e, m; + union { + uint64_t i; + double d; + } u; + + s = 0; + if(f & 0400000000000){ + f = -f & 0777777777777; + s = 1; + } + e = (f >> 27) & 0377; + m = f & 0777777777; + e += 1023-128; + /* normalize */ + if(m != 0){ + m &= ~0400000000; + m <<= 1; + e -= 1; + }else + e = 0; + m <<= 25; + x = m; + x |= (e & 0x7FF) << 52; + x |= s << 63; + u.i = x; + return u.d; +} + +/* map ascii to radix50/squoze, also map lower to upper case */ +char +ascii2rad(char c) +{ + static char tab[] = { + -1, -1, -1, -1, -1, -1, -1, -1, + -1, -1, -1, -1, -1, -1, -1, -1, + -1, -1, -1, -1, -1, -1, -1, -1, + -1, -1, -1, -1, -1, -1, -1, -1, + 0, -1, -1, -1, 046, 047, -1, -1, + -1, -1, -1, -1, -1, -1, 045, -1, + 001, 002, 003, 004, 005, 006, 007, 010, + 011, 012, -1, -1, -1, -1, -1, -1, + -1, 013, 014, 015, 016, 017, 020, 021, + 022, 023, 024, 025, 026, 027, 030, 031, + 032, 033, 034, 035, 036, 037, 040, 041, + 042, 043, 044, -1, -1, -1, -1, -1, + -1, 013, 014, 015, 016, 017, 020, 021, + 022, 023, 024, 025, 026, 027, 030, 031, + 032, 033, 034, 035, 036, 037, 040, 041, + 042, 043, 044, -1, -1, -1, -1, -1, + }; + return tab[c&0177]; +} + +static char rad50tab[] = { + ' ', '0', '1', '2', '3', '4', '5', '6', + '7', '8', '9', 'A', 'B', 'C', 'D', 'E', + 'F', 'G', 'H', 'I', 'J', 'K', 'L', 'M', + 'N', 'O', 'P', 'Q', 'R', 'S', 'T', 'U', + 'V', 'W', 'X', 'Y', 'Z', '.', '$', '%', + 0 +}; + +/* map radix50/squoze to ascii */ +char +rad2ascii(char c) +{ + return rad50tab[c%050]; +} + +int +israd50(char c) +{ + return strchr(rad50tab, toupper(c)) != NULL; +} + +/* convert ascii string + code to radix50 */ +word +rad50(int n, const char *s) +{ + word r; + char c; + int i; + + r = 0; + i = 0; + for(i = 0; i < 6 && *s; i++){ + c = ascii2rad(*s++); + if(c < 0) + break; + r = r*050 + c; + } + for(; i < 6; i++) + r = r*050; + r |= (word)(n&074) << 30; + return r; +} + +/* get null-terminated ascii string and code from radix50 */ +int +unrad50(word r, char *s) +{ + int i; + int n; + n = r>>30 & 074; + r &= ~0740000000000; + s += 6; + *s-- = '\0'; + for(i = 0; i < 6; i++){ + *s-- = rad2ascii(r%050); + r /= 050; + } + return n; +} + +/* map ascii to sixbit, also map lower to upper case */ +char +ascii2sixbit(char c) +{ + static char tab[] = { + -1, -1, -1, -1, -1, -1, -1, -1, + -1, -1, -1, -1, -1, -1, -1, -1, + -1, -1, -1, -1, -1, -1, -1, -1, + -1, -1, -1, -1, -1, -1, -1, -1, + + 000, 001, 002, 003, 004, 005, 006, 007, + 010, 011, 012, 013, 014, 015, 016, 017, + 020, 021, 022, 023, 024, 025, 026, 027, + 030, 031, 032, 033, 034, 035, 036, 037, + 040, 041, 042, 043, 044, 045, 046, 047, + 050, 051, 052, 053, 054, 055, 056, 057, + 060, 061, 062, 063, 064, 065, 066, 067, + 070, 071, 072, 073, 074, 075, 076, 077, + + 040, 041, 042, 043, 044, 045, 046, 047, + 050, 051, 052, 053, 054, 055, 056, 057, + 060, 061, 062, 063, 064, 065, 066, 067, + 070, 071, 072, 073, 074, 075, 076, 077, + }; + return tab[c&0177]; +} + +static char sixbittab[] = { + ' ', '!', '"', '#', '$', '%', '&', '\'', + '(', ')', '*', '+', ',', '-', '.', '/', + '0', '1', '2', '3', '4', '5', '6', '7', + '8', '9', ':', ';', '<', '=', '>', '?', + '@', 'A', 'B', 'C', 'D', 'E', 'F', 'G', + 'H', 'I', 'J', 'K', 'L', 'M', 'N', 'O', + 'P', 'Q', 'R', 'S', 'T', 'U', 'V', 'W', + 'X', 'Y', 'Z', '[', '\\', ']', '^', '_', + 0 + +}; + + +/* map sixbit to ascii */ +char +sixbit2ascii(char c) +{ + return sixbittab[c&077]; +} + +int +issixbit(char c) +{ + return strchr(sixbittab, toupper(c)) != NULL; +} + +/* convert ascii string to sixbit */ +word +sixbit(const char *s) +{ + word sx; + char c; + int i; + sx = 0; + i = 0; + for(i = 0; i < 6 && *s; i++){ + c = ascii2sixbit(*s++); + if(c < 0) + break; + sx = (sx<<6) + c; + } + sx <<= 6*(6-i); + return sx; +} + +/* get null-terminated ascii string from sixbit */ +void +unsixbit(word sx, char *s) +{ + int i; + s += 6; + *s-- = '\0'; + for(i = 0; i < 6; i++){ + *s-- = sixbit2ascii(sx&077); + sx >>= 6; + } +} + + +enum +{ + NOINST = 1, // not a valid instruction + NUMY = 2, // numeric Y + NOAC = 4, // don't print AC if zero + NOY = 8, // don't print Y if zero +}; + + +int instflags[0700] = { + NOINST, NOINST, NOINST, NOINST, + NOINST, NOINST, NOINST, NOINST, + NOINST, NOINST, NOINST, NOINST, + NOINST, NOINST, NOINST, NOINST, + NOINST, NOINST, NOINST, NOINST, + NOINST, NOINST, NOINST, NOINST, + NOINST, NOINST, NOINST, NOINST, + NOINST, NOINST, NOINST, NOINST, + NOINST, NOINST, NOINST, NOINST, + NOINST, NOINST, NOINST, NOINST, + NOINST, NOINST, NOINST, NOINST, + NOINST, NOINST, NOINST, NOINST, + NOINST, NOINST, NOINST, NOINST, + NOINST, NOINST, NOINST, NOINST, + NOINST, NOINST, NOINST, NOINST, + NOINST, NOINST, NOINST, NOINST, + + NOINST, NOINST, NOINST, NOINST, + NOINST, NOINST, NOINST, NOINST, + NOINST, NOINST, NOINST, NOINST, + NOINST, NOINST, NOINST, NOINST, + NOINST, NOINST, NOINST, NOINST, + NOINST, NOINST, NOINST, NOINST, + NOINST, NOINST, NUMY, NOAC, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + + 0, 0, 0, NOAC, + 0, 0, 0, NOAC, + 0, 0, 0, NOAC, + 0, 0, 0, NOAC, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + NUMY, NUMY, NUMY, NOINST, + NUMY, NUMY, NUMY, NOINST, + 0, 0, 0, 0, + NOAC, NOAC, NOAC, NOINST, + 0, 0, 0, NOY, + NOAC, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + + NOAC|NOY, 0, 0, 0, + NOAC|NOY, 0, 0, 0, + NOAC|NOY, 0, 0, 0, + NOAC|NOY, 0, 0, 0, + NOAC|NOY, 0, 0, 0, + NOAC|NOY, 0, 0, 0, + NOAC, NOAC, NOAC, NOAC, + NOAC, NOAC, NOAC, NOAC, + 0, 0, 0, 0, + 0, 0, 0, 0, + NOAC, NOAC, NOAC, NOAC, + NOAC, NOAC, NOAC, NOAC, + 0, 0, 0, 0, + 0, 0, 0, 0, + NOAC, NOAC, NOAC, NOAC, + NOAC, NOAC, NOAC, NOAC, + + NOY, NOY, NOAC, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, NOAC, 0, + 0, 0, 0, 0, + NOY, NOY, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + NOY, NOY, 0, 0, + 0, 0, 0, 0, + 0, 0, NOAC, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + NOY, NOY, NOAC, 0, + + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + + NOAC|NOY|NUMY, NOAC|NOY|NUMY, NUMY, NUMY, + NOAC|NOY|NUMY, NOAC|NOY|NUMY, NUMY, NUMY, + NOAC|NOY, NOAC|NOY, 0, 0, + NOAC|NOY, NOAC|NOY, 0, 0, + NUMY, NUMY, NUMY, NUMY, + NUMY, NUMY, NUMY, NUMY, + 0, 0, 0, 0, + 0, 0, 0, 0, + NUMY, NUMY, NUMY, NUMY, + NUMY, NUMY, NUMY, NUMY, + 0, 0, 0, 0, + 0, 0, 0, 0, + NUMY, NUMY, NUMY, NUMY, + NUMY, NUMY, NUMY, NUMY, + 0, 0, 0, 0, + 0, 0, 0, 0, +}; + +int ioinstflags[] = { + 0, 0, 0, 0, + NUMY, 0, NUMY, NUMY +}; + +char *devlist[] = { + // 000 + "APR", "PI", NULL, NULL, NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, + // 100 + "PTP", "PTR", "CP", "CR", "TTY", "LPT", "DIS", NULL, + NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, + // 200 + "DC", "UTC", "UTS", "MT", "MTS", "MTM", NULL, NULL, + NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, + // 300 + NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, + // 400 + NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, + // 500 + NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, + // 600 + NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, + // 700 + NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, +}; + + +char *mnemonics[0700] = { + "UUO00", "UUO01", "UUO02", "UUO03", + "UUO04", "UUO05", "UUO06", "UUO07", + "UUO10", "UUO11", "UUO12", "UUO13", + "UUO14", "UUO15", "UUO16", "UUO17", + "UUO20", "UUO21", "UUO22", "UUO23", + "UUO24", "UUO25", "UUO26", "UUO27", + "UUO30", "UUO31", "UUO32", "UUO33", + "UUO34", "UUO35", "UUO36", "UUO37", + "UUO40", "UUO41", "UUO42", "UUO43", + "UUO44", "UUO45", "UUO46", "UUO47", + "UUO50", "UUO51", "UUO52", "UUO53", + "UUO54", "UUO55", "UUO56", "UUO57", + "UUO60", "UUO61", "UUO62", "UUO63", + "UUO64", "UUO65", "UUO66", "UUO67", + "UUO70", "UUO71", "UUO72", "UUO73", + "UUO74", "UUO75", "UUO76", "UUO77", + + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", +// "", "", "FSC", "CAO", +// "LDCI", "LDC", "DPCI", "DPC", + "", "", "FSC", "IBP", + "ILDB", "LDB", "IDPB", "DPB", + "FAD", "FADL", "FADM", "FADB", + "FADR", "FADLR", "FADMR", "FADBR", + "FSB", "FSBL", "FSBM", "FSBB", + "FSBR", "FSBLR", "FSBMR", "FSBBR", + "FMP", "FMPL", "FMPM", "FMPB", + "FMPR", "FMPLR", "FMPMR", "FMPBR", + "FDV", "FDVL", "FDVM", "FDVB", + "FDVR", "FDVLR", "FDVMR", "FDVBR", + + "MOVE", "MOVEI", "MOVEM", "MOVES", + "MOVS", "MOVSI", "MOVSM", "MOVSS", + "MOVN", "MOVNI", "MOVNM", "MOVNS", + "MOVM", "MOVMI", "MOVMM", "MOVMS", + "IMUL", "IMULI", "IMULM", "IMULB", + "MUL", "MULI", "MULM", "MULB", + "IDIV", "IDIVI", "IDIVM", "IDIVB", + "DIV", "DIVI", "DIVM", "DIVB", + "ASH", "ROT", "LSH", "XX243", + "ASHC", "ROTC", "LSHC", "XX247", + "EXCH", "BLT", "AOBJP", "AOBJN", + "JRST", "JFCL", "XCT", "XX257", + "PUSHJ", "PUSH", "POP", "POPJ", + "JSR", "JSP", "JSA", "JRA", + "ADD", "ADDI", "ADDM", "ADDB", + "SUB", "SUBI", "SUBM", "SUBB", + + "CAI", "CAIL", "CAIE", "CAILE", + "CAIA", "CAIGE", "CAIN", "CAIG", + "CAM", "CAML", "CAME", "CAMLE", + "CAMA", "CAMGE", "CAMN", "CAMG", + "JUMP", "JUMPL", "JUMPE", "JUMPLE", + "JUMPA", "JUMPGE", "JUMPN", "JUMPG", + "SKIP", "SKIPL", "SKIPE", "SKIPLE", + "SKIPA", "SKIPGE", "SKIPN", "SKIPG", + "AOJ", "AOJL", "AOJE", "AOJLE", + "AOJA", "AOJGE", "AOJN", "AOJG", + "AOS", "AOSL", "AOSE", "AOSLE", + "AOSA", "AOSGE", "AOSN", "AOSG", + "SOJ", "SOJL", "SOJE", "SOJLE", + "SOJA", "SOJGE", "SOJN", "SOJG", + "SOS", "SOSL", "SOSE", "SOSLE", + "SOSA", "SOSGE", "SOSN", "SOSG", + + "SETZ", "SETZI", "SETZM", "SETZB", + "AND", "ANDI", "ANDM", "ANDB", + "ANDCA", "ANDCAI", "ANDCAM", "ANDCAB", + "SETM", "SETMI", "SETMM", "SETMB", + "ANDCM", "ANDCMI", "ANDCMM", "ANDCMB", + "SETA", "SETAI", "SETAM", "SETAB", + "XOR", "XORI", "XORM", "XORB", + "IOR", "IORI", "IORM", "IORB", + "ANDCB", "ANDCBI", "ANDCBM", "ANDCBB", + "EQV", "EQVI", "EQVM", "EQVB", + "SETCA", "SETCAI", "SETCAM", "SETCAB", + "ORCA", "ORCAI", "ORCAM", "ORCAB", + "SETCM", "SETCMI", "SETCMM", "SETCMB", + "ORCM", "ORCMI", "ORCMM", "ORCMB", + "ORCB", "ORCBI", "ORCBM", "ORCBB", + "SETO", "SETOI", "SETOM", "SETOB", + + "HLL", "HLLI", "HLLM", "HLLS", + "HRL", "HRLI", "HRLM", "HRLS", + "HLLZ", "HLLZI", "HLLZM", "HLLZS", + "HRLZ", "HRLZI", "HRLZM", "HRLZS", + "HLLO", "HLLOI", "HLLOM", "HLLOS", + "HRLO", "HRLOI", "HRLOM", "HRLOS", + "HLLE", "HLLEI", "HLLEM", "HLLES", + "HRLE", "HRLEI", "HRLEM", "HRLES", + "HRR", "HRRI", "HRRM", "HRRS", + "HLR", "HLRI", "HLRM", "HLRS", + "HRRZ", "HRRZI", "HRRZM", "HRRZS", + "HLRZ", "HLRZI", "HLRZM", "HLRZS", + "HRRO", "HRROI", "HRROM", "HRROS", + "HLRO", "HLROI", "HLROM", "HLROS", + "HRRE", "HRREI", "HRREM", "HRRES", + "HLRE", "HLREI", "HLREM", "HLRES", + + "TRN", "TLN", "TRNE", "TLNE", + "TRNA", "TLNA", "TRNN", "TLNN", + "TDN", "TSN", "TDNE", "TSNE", + "TDNA", "TSNA", "TDNN", "TSNN", + "TRZ", "TLZ", "TRZE", "TLZE", + "TRZA", "TLZA", "TRZN", "TLZN", + "TDZ", "TSZ", "TDZE", "TSZE", + "TDZA", "TSZA", "TDZN", "TSZN", + "TRC", "TLC", "TRCE", "TLCE", + "TRCA", "TLCA", "TRCN", "TLCN", + "TDC", "TSC", "TDCE", "TSCE", + "TDCA", "TSCA", "TDCN", "TSCN", + "TRO", "TLO", "TROE", "TLOE", + "TROA", "TLOA", "TRON", "TLON", + "TDO", "TSO", "TDOE", "TSOE", + "TDOA", "TSOA", "TDON", "TSON", +}; + +char *iomnemonics[] = { + "BLKI", + "DATAI", + "BLKO", + "DATAO", + "CONO", + "CONI", + "CONSZ", + "CONSO" +}; + +/* +char* +disasm(word w) +{ + static char s[100]; + char *p; + hword i, x, y; + hword ac, dev; + hword op; + hword f; + + y = w & 0777777; + if((w & 0777000000000) == 0){ + sprintf(s, "%llo", w); + return s; + } + x = (w >> 18) & 017; + i = (w >> 22) & 1; + ac = (w >> 23) & 017; + op = (w >> 27) & 0777; + dev = (w >> 24) & 0774; + f = ac & 07; + p = s; + if((op & 0700) == 0700){ + p += sprintf(p, "%s ", iomnemonics[f]); + p += sprintf(p, "%o,", dev); + }else{ + if(mnemonics[op][0] == '\0'){ + sprintf(s, "%llo", w); + return s; + } + p += sprintf(p, "%s ", mnemonics[op]); + p += sprintf(p, "%o,", ac); + } + if(i) + p += sprintf(p, "@"); + p += sprintf(p, "%o", y); + if(x) + p += sprintf(p, "(%o)", x); + return s; +} +*/ + +char *findacsym(word v); +char *findsymval(word v); + +char* +disasm(word w) +{ + static char s[100]; + char *p; + hword i, x, y; + hword ac, dev; + hword op; + hword f; + char *sym; + int flags; + + if((w & 0777000000000) == 0){ + sprintf(s, "%llo", w); + return s; + } + + y = w & 0777777; + x = (w >> 18) & 017; + i = (w >> 22) & 1; + ac = (w >> 23) & 017; + op = (w >> 27) & 0777; + dev = (w >> 24) & 0774; + f = ac & 07; + p = s; + if((op & 0700) == 0700){ + flags = ioinstflags[f]; + p += sprintf(p, "%s ", iomnemonics[f]); + if(devlist[dev>>2]) + p += sprintf(p, "%s,", devlist[dev>>2]); + else + p += sprintf(p, "%o,", dev); + }else{ + flags = instflags[op]; + p += sprintf(p, "%s ", mnemonics[op]); + if(ac || (flags & NOAC) == 0){ + sym = findacsym(ac); + if(sym) + p += sprintf(p, "%s,", sym); + else + p += sprintf(p, "%o,", ac); + } + } + if(flags & NOINST) + return ""; + if(i) + p += sprintf(p, "@"); + + if(y || (flags & NOY) == 0){ + sym = findsymval(y); + if(flags & NUMY && !i || sym == NULL) + p += sprintf(p, "%o", y); + else + p += sprintf(p, "%s", sym); + } + + if(x){ + sym = findacsym(x); + if(sym) + p += sprintf(p, "(%s)", sym); + else + p += sprintf(p, "(%o)", x); + } + return s; +} diff --git a/fe6/pdp6common.h b/fe6/pdp6common.h new file mode 100644 index 0000000..9641ca8 --- /dev/null +++ b/fe6/pdp6common.h @@ -0,0 +1,35 @@ +typedef uint64_t word; +typedef uint32_t hword; + +word fw(hword l, hword r); +word point(word pos, word sz, hword p); +hword left(word w); +hword right(word w); +word negw(word w); +int isneg(word w); + +void writew(word w, FILE *fp); +word readw(FILE *fp); +void writewbak(word w, FILE *fp); +word readwbak(FILE *fp); +void writewits(word w, FILE *fp); +word readwits(FILE *fp); + +void decompdbl(double d, int *s, word *e, uint64_t *m); +word dtopdp(double d); +double pdptod(word f); + +char ascii2rad(char c); +char rad2ascii(char c); +int israd50(char c); +word rad50(int n, const char *s); +int unrad50(word r, char *s); +char ascii2sixbit(char c); +char sixbit2ascii(char c); +int issixbit(char c); +word sixbit(const char *s); +void unsixbit(word sx, char *s); +char *disasm(word w); + +extern char *mnemonics[448]; +extern char *iomnemonics[8]; diff --git a/fe6/real6.c b/fe6/real6.c new file mode 100755 index 0000000..0a74bce --- /dev/null +++ b/fe6/real6.c @@ -0,0 +1,686 @@ +#include "fe6.h" +#include +#include +#include +//#include "hps_0.h" + +#define H2F_BASE (0xC0000000) + +#define PERIPH_BASE (0xFC000000) +#define PERIPH_SPAN (0x04000000) +#define PERIPH_MASK (PERIPH_SPAN - 1) + +#define LWH2F_BASE (0xFF200000) + +/* Memory mapped PDP-6 interface */ +enum +{ + /* The more important keys, switches and lights */ + REG6_CTL1_DN = 0, + REG6_CTL1_UP = 1, + MM6_START = 1, + MM6_READIN = 2, + MM6_INSTCONT = 4, + MM6_MEMCONT = 010, + MM6_INSTSTOP = 020, + MM6_MEMSTOP = 040, + MM6_STOP = MM6_INSTSTOP|MM6_MEMSTOP, + MM6_RESET = 0100, + MM6_EXEC = 0200, + MM6_ADRSTOP = 0400, + /* lights - read only */ + MM6_RUN = 01000, + MM6_MCSTOP = 02000, + MM6_PWR = 04000, + + /* Less important keys and switches */ + REG6_CTL2_DN = 2, + REG6_CTL2_UP = 3, + MM6_THISDEP = 1, + MM6_NEXTDEP = 2, + MM6_THISEX = 4, + MM6_NEXTEX = 010, + MM6_READEROFF = 020, + MM6_READERON = 040, + MM6_FEEDPUNCH = 0100, + MM6_FEEDREAD = 0200, + MM6_REPEAT = 0400, + MM6_MEMDIS = 01000, + + /* Maintenance switches */ + REG6_MAINT_DN = 4, + REG6_MAINT_UP = 5, + + /* switches and knobs */ + REG6_DSLT = 6, + REG6_DSRT = 7, + REG6_MAS = 010, + REG6_REPEAT = 011, + + /* lights */ + REG6_IR = 012, + REG6_MILT = 013, + REG6_MIRT = 014, + REG6_PC = 015, + REG6_MA = 016, + REG6_PI = 017, + + REG6_MBLT = 020, + REG6_MBRT = 021, + REG6_ARLT = 022, + REG6_ARRT = 023, + REG6_MQLT = 024, + REG6_MQRT = 025, + REG6_FF1 = 026, + REG6_FF2 = 027, + REG6_FF3 = 030, + REG6_FF4 = 031, + REG6_MMU = 032, + + REG6_TTY = 033, + REG6_PTP = 034, + REG6_PTR = 035, + REG6_PTR_LT = 036, + REG6_PTR_RT = 037, +}; + +enum { + FEREG_REQ = 0, + FEREG_PTR, + FEREG_PTP +}; + + +static u64 *h2f_base; +static u32 *virtual_base; +static u32 *getLWH2Faddr(u32 offset) +{ + return (u32*)((u32)virtual_base - PERIPH_BASE + (LWH2F_BASE+offset)); +} +static u64 *getH2Faddr(u32 offset) +{ + return (u64*)((u32)h2f_base + offset); +} + +static int memfd; +static volatile u32 *h2f_cmemif, *h2f_cmemif2; +static volatile u32 *h2f_fmemif, *h2f_fmemif2; +static volatile u32 *h2f_apr; +static volatile u32 *h2f_fe; +static volatile u32 *h2f_lw_led_addr; +static volatile u32 *h2f_lw_sw_addr; + +void +deposit(hword a, word w) +{ +/* + if(a < 01000000){ + h2f_cmemif[0] = a & RT; + h2f_cmemif[1] = w & RT; + h2f_cmemif[2] = (w >> 18) & RT; + }else if(a < 01000020){ + h2f_fmemif[0] = a & 017; + h2f_fmemif[1] = w & RT; + h2f_fmemif[2] = (w >> 18) & RT; + }else if(a < 01000040){ + h2f_fmemif2[0] = a & 017 | 01000000; + h2f_fmemif2[1] = w & RT; + h2f_fmemif2[2] = (w >> 18) & RT; + }else if(a >= 02000000 && a < 03000000){ + h2f_cmemif2[0] = a & RT; + h2f_cmemif2[1] = w & RT; + h2f_cmemif2[2] = (w >> 18) & RT; +*/ + + + if(a < 020){ + h2f_fmemif[0] = a & 017; + h2f_fmemif[1] = w & RT; + h2f_fmemif[2] = (w >> 18) & RT; + }else if(a < 01000020){ + h2f_cmemif[0] = a & RT; + h2f_cmemif[1] = w & RT; + h2f_cmemif[2] = (w >> 18) & RT; + }else if(a >= 02000000){ + h2f_cmemif2[0] = a & 01777777; + h2f_cmemif2[1] = w & RT; + h2f_cmemif2[2] = (w >> 18) & RT; + }else switch(a){ + case APR_DS: + h2f_apr[REG6_DSLT] = w>>18 & RT; + h2f_apr[REG6_DSRT] = w & RT; + break; + case APR_MAS: + h2f_apr[REG6_MAS] = w & RT; + break; + case APR_RPT: + h2f_apr[REG6_REPEAT] = w; + break; + +#ifdef TEST + case APR_CTL1_DN: + h2f_apr[REG6_CTL1_DN] = w; + break; + case APR_CTL1_UP: + h2f_apr[REG6_CTL1_UP] = w; + break; + case APR_CTL2_DN: + h2f_apr[REG6_CTL2_DN] = w; + break; + case APR_CTL2_UP: + h2f_apr[REG6_CTL2_UP] = w; + break; + + case PTR_FE: + h2f_fe[FEREG_PTR] = w; + break; +#endif + + case 01001000: + *h2f_lw_led_addr = w; + break; + } +} + +word +examine(hword a) +{ + u64 w; + w = 0; + +/* + if(a < 01000000){ + h2f_cmemif[0] = a & RT; + w = h2f_cmemif[2] & RT; + w <<= 18; + w |= h2f_cmemif[1] & RT; + }else if(a < 01000020){ + h2f_fmemif[0] = a & 017; + w = h2f_fmemif[2] & RT; + w <<= 18; + w |= h2f_fmemif[1] & RT; + }else if(a < 01000040){ + h2f_fmemif2[0] = a & 017 | 01000000; + w = h2f_fmemif2[2] & RT; + w <<= 18; + w |= h2f_fmemif2[1] & RT; + }else if(a >= 02000000 && a < 03000000){ + h2f_cmemif2[0] = a & RT; + w = h2f_cmemif2[2] & RT; + w <<= 18; + w |= h2f_cmemif2[1] & RT; +*/ + + + if(a < 020){ + h2f_fmemif[0] = a & 017; + w = h2f_fmemif[2] & RT; + w <<= 18; + w |= h2f_fmemif[1] & RT; + }else if(a < 01000020){ + h2f_cmemif[0] = a & RT; + w = h2f_cmemif[2] & RT; + w <<= 18; + w |= h2f_cmemif[1] & RT; + }else if(a >= 02000000){ + h2f_cmemif2[0] = a & 01777777; + w = h2f_cmemif2[2] & RT; + w <<= 18; + w |= h2f_cmemif2[1] & RT; + }else switch(a){ + case APR_DS: + w = h2f_apr[REG6_DSLT]; + w <<= 18; + w |= h2f_apr[REG6_DSRT] & RT; + return w; + case APR_MAS: + w = h2f_apr[REG6_MAS]; + break; + case APR_RPT: + w = h2f_apr[REG6_REPEAT]; + break; + + case APR_IR: + return h2f_apr[REG6_IR]; + case APR_MI: + w = h2f_apr[REG6_MILT]; + w <<= 18; + w |= h2f_apr[REG6_MIRT] & RT; + return w; + case APR_PC: + return h2f_apr[REG6_PC]; + case APR_MA: + return h2f_apr[REG6_MA]; + case APR_PIO: + return h2f_apr[REG6_PI]>>1 & 0177; + case APR_PIR: + return h2f_apr[REG6_PI]>>8 & 0177; + case APR_PIH: + return h2f_apr[REG6_PI]>>15 & 0177; + case APR_PION: + return h2f_apr[REG6_PI] & 1; + + case APR_RUN: + return !!(h2f_apr[REG6_CTL1_DN] & MM6_RUN); + case APR_STOP: + return !!(h2f_apr[REG6_CTL1_DN] & MM6_MCSTOP); + +#ifdef TEST + case APR_CTL1_DN: + return h2f_apr[REG6_CTL1_DN]; + case APR_CTL1_UP: + return h2f_apr[REG6_CTL1_UP]; + case APR_CTL2_DN: + return h2f_apr[REG6_CTL2_DN]; + case APR_CTL2_UP: + return h2f_apr[REG6_CTL2_UP]; + case APR_MB: + w = h2f_apr[REG6_MBLT]; + w <<= 18; + w |= h2f_apr[REG6_MBRT] & RT; + return w; + case APR_AR: + w = h2f_apr[REG6_ARLT]; + w <<= 18; + w |= h2f_apr[REG6_ARRT] & RT; + return w; + case APR_MQ: + w = h2f_apr[REG6_MQLT]; + w <<= 18; + w |= h2f_apr[REG6_MQRT] & RT; + return w; + + case TTY_TTI: + return (h2f_apr[REG6_TTY]>>9) & 0377; + case TTY_ST: + return h2f_apr[REG6_TTY] & 0177; + case PTR_PTR: + w = h2f_apr[REG6_PTR_LT]; + w <<= 18; + w |= h2f_apr[REG6_PTR_RT] & RT; + return w; + case PTR_ST: + return h2f_apr[REG6_PTR] & 0177; + + case FE_REQ: + return h2f_fe[FEREG_REQ]; +#endif + + case 01001000: + w = *h2f_lw_led_addr; + break; + case 01001001: + w = *h2f_lw_sw_addr; + break; + } + return w; +} + + + +static void set_ta(hword a) +{ + h2f_apr[REG6_MAS] = a & RT; +} + +static void set_td(word d) +{ + h2f_apr[REG6_DSLT] = d>>18 & RT; + h2f_apr[REG6_DSRT] = d & RT; +} + +static void keydown(u32 k) +{ + h2f_apr[REG6_CTL1_DN] = k; + if(k & MM6_INSTSTOP) + usleep(1000); // wait for AT1 INH to go down +} + +static void keyup(u32 k) +{ + h2f_apr[REG6_CTL1_UP] = k; +} + +static void keytoggle(u32 k) { + keydown(k); + usleep(1000); // TODO: maybe don't sleep? or different duration? + keyup(k); +} + +int isrunning(void) +{ + return !!(h2f_apr[REG6_CTL1_DN] & MM6_RUN); +} +int isstopped(void) +{ + return !!(h2f_apr[REG6_CTL1_DN] & MM6_MCSTOP); +} + +static void waithalt(void) +{ + int i; + for(i = 0; i < 10; i++){ + if(!isrunning()) + return; + usleep(100); + } + keytoggle(MM6_INSTSTOP); + for(i = 0; i < 10; i++){ + if(!isrunning()) + return; + usleep(100); + } + typestr("not halted!!!\r\n"); +} + +static void waitmemstop(void) +{ + int i; + if(!isrunning()) + return; + for(i = 0; i < 10; i++){ + if(isstopped()) + return; + usleep(100); + } + keytoggle(MM6_MEMSTOP); + for(i = 0; i < 10; i++){ + if(isstopped()) + return; + usleep(100); + } + typestr("not stopped!!!\r\n"); +} + +static int run; +static int memstop; +#define X if(0) + +void +cpu_start(hword a) +{ +X typestr("\r\n"); + + cpu_stopinst(); + X run = 0; + keyup(MM6_STOP | MM6_ADRSTOP); + set_ta(a); + keytoggle(MM6_START); + X run = 1; + X memstop = 0; +} + +void +cpu_readin(hword a) +{ +X typestr("\r\n"); + + cpu_stopinst(); + X run = 0; + keyup(MM6_STOP | MM6_ADRSTOP); + set_ta(a); + keytoggle(MM6_READIN); + X run = 1; + X memstop = 0; +} + +void +cpu_setpc(hword a) +{ +X typestr("\r\n"); + + cpu_stopinst(); + X run = 0; + keydown(MM6_MEMSTOP); + keyup(MM6_ADRSTOP); + set_ta(a); + keytoggle(MM6_START); + X run = 1; + X memstop = 0; + waitmemstop(); + X memstop = 1; + keyup(MM6_MEMSTOP); + keytoggle(MM6_INSTSTOP); + X run = 0; +} + +void +cpu_stopinst(void) +{ +X typestr("\r\n"); + + if(!isrunning()) + return; + keytoggle(MM6_INSTSTOP); + waithalt(); + X run = 0; +} + +void +cpu_stopmem(void) +{ +X typestr("\r\n"); + + if(!isrunning() || isstopped()) + return; + keytoggle(MM6_MEMSTOP); + waitmemstop(); + X memstop = 1; +} + +static void +togglecont(void) +{ + if(isstopped()){ + keytoggle(MM6_MEMCONT); + X memstop = 0; + }else{ + keytoggle(MM6_INSTCONT); + X memstop = 0; + X run = 1; + } +} + +void +cpu_cont(void) +{ +X typestr("\r\n"); + + if(isrunning()) + return; + keyup(MM6_STOP); + togglecont(); +} + +void +cpu_nextinst(void) +{ +X typestr("\r\n"); + + if(isrunning() && !isstopped()) + err("?R? "); + keydown(MM6_INSTSTOP); + X run = 0; + togglecont(); + waithalt(); + X run = 0; + keyup(MM6_INSTSTOP); +} + +void +cpu_nextmem(void) +{ +X typestr("\r\n"); + + if(isrunning() && !isstopped()) + err("?R? "); + keydown(MM6_MEMSTOP); + togglecont(); + waitmemstop(); + X memstop = 1; + keyup(MM6_MEMSTOP); +} + +void +cpu_exec(word inst) +{ +X typestr("\r\n"); + + if(isrunning()) + err("?R? "); + set_td(inst); + keytoggle(MM6_EXEC); +} + +void +cpu_ioreset(void) +{ +X typestr("\r\n"); + + if(isrunning()) + err("?R? "); + keytoggle(MM6_RESET); +} + +#include "flags.inc" + +void +prflags(const char *fmt, u8 flags) +{ + static const char *l = ".#"; + printf(fmt, + l[!!(flags&0200)], l[!!(flags&0100)], + l[!!(flags&040)], l[!!(flags&020)], + l[!!(flags&010)], l[!!(flags&04)], + l[!!(flags&02)], l[!!(flags&01)]); +} + +void +cpu_printflags(void) +{ + u32 ff1, ff2, ff3, ff4; + u32 ctl1, pi; + ff1 = h2f_apr[REG6_FF1]; + ff2 = h2f_apr[REG6_FF2]; + ff3 = h2f_apr[REG6_FF3]; + ff4 = h2f_apr[REG6_FF4]; + ctl1 = h2f_apr[REG6_CTL1_DN]; + pi = h2f_apr[REG6_PI]; + + printf("\r\n"); + prflags(ff0str, ff1>>24); + prflags(ff1str, ff1>>16); + prflags(ff2str, ff1>>8); + prflags(ff3str, ff1); + prflags(ff4str, ff2>>24); + prflags(ff5str, ff2>>16); + prflags(ff6str, ff2>>8); + prflags(ff7str, ff2); + prflags(ff8str, ff3>>24); + prflags(ff9str, ff3>>16); + prflags(ff10str, ff3>>8); + prflags(ff11str, ff3); + prflags(ff12str, ff4>>24); + prflags(ff13str, ff4>>16); + + printf("PIH/%03o PIR/%03o PIO/%03o PI ACTIVE/%o\r\n", + pi>>15 & 0177, pi>>8 & 0177, pi>>1 & 0177, !!(pi & 1)); + printf("RUN/%o MEM STOP/%o\r\n", + !!(ctl1 & MM6_RUN), !!(ctl1 & MM6_MCSTOP)); + + fflush(stdout); +} + +static void +svc_ptr(void) +{ + int fd; + u8 c; + + fd = devtab[DEV_PTR].fd; + if(fd < 0) + return; + if(read(fd, &c, 1) == 1){ +printf("%d%d%d%d%d%d%d%d -> PTR\r\n", + !!(c&0200), !!(c&0100), !!(c&040), !!(c&020), !!(c&010), + !!(c&04), !!(c&02), !!(c&01)); +fflush(stdout); + h2f_fe[FEREG_PTR] = c; + } +} + +static void +svc_ptp(void) +{ + int fd; + u8 c; + + c = h2f_fe[FEREG_PTP]; +printf("PTP <- %d%d%d%d%d%d%d%d\r\n", + !!(c&0200), !!(c&0100), !!(c&040), !!(c&020), !!(c&010), + !!(c&04), !!(c&02), !!(c&01)); +fflush(stdout); + + fd = devtab[DEV_PTP].fd; + if(fd < 0) + return; + write(fd, &c, 1); +} + +void +fe_svc(void) +{ + u32 req; + + req = h2f_fe[FEREG_REQ]; + + if(req & 1) svc_ptr(); + if(req & 2) svc_ptp(); +} + + +void +init6(void) +{ + if((memfd = open("/dev/mem", (O_RDWR | O_SYNC))) == -1) { + fprintf(stderr, "ERROR: could not open /dev/mem...\n"); + exit(1); + } + virtual_base = (u32*)mmap(nil, PERIPH_SPAN, + (PROT_READ | PROT_WRITE), MAP_SHARED, memfd, PERIPH_BASE); + if(virtual_base == MAP_FAILED) { + fprintf(stderr, "ERROR: mmap() failed...\n"); + close(memfd); + exit(1); + } + h2f_base = (u64*)mmap(nil, 0x100000, + (PROT_READ | PROT_WRITE), MAP_SHARED, memfd, H2F_BASE); + if(h2f_base == MAP_FAILED) { + fprintf(stderr, "ERROR: mmap() failed...\n"); + close(memfd); + exit(1); + } + + h2f_cmemif = getLWH2Faddr(0x10000); + h2f_cmemif2 = getLWH2Faddr(0x20000); + + h2f_fmemif = getLWH2Faddr(0x10010); + h2f_fmemif2 = getLWH2Faddr(0x20010); + + + h2f_apr = getLWH2Faddr(0x10100); + h2f_fe = getLWH2Faddr(0x20000); + h2f_lw_sw_addr = getLWH2Faddr(0x10020); + h2f_lw_led_addr = getLWH2Faddr(0x10040); +} + +void +deinit6(void) +{ + if(munmap(virtual_base, PERIPH_SPAN) != 0) { + fprintf(stderr, "ERROR: munmap() failed...\n"); + close(memfd); + exit(1); + } + close(memfd); +} diff --git a/fe6/test.h b/fe6/test.h new file mode 100644 index 0000000..c6f27d1 --- /dev/null +++ b/fe6/test.h @@ -0,0 +1,10 @@ +#include +#include + +#define nil NULL + +typedef uint64_t u64; +typedef uint32_t u32; +typedef uint8_t u8; + +volatile u32 *h2f_lw_led_addr; diff --git a/fe6/util.c b/fe6/util.c new file mode 100644 index 0000000..cdd48d5 --- /dev/null +++ b/fe6/util.c @@ -0,0 +1,169 @@ +#include +#include +#include + +#include +#include +#include + + +void +strtolower(char *s) +{ + for(; *s != '\0'; s++) + *s = tolower(*s); +} + +int +hasinput(int fd) +{ + fd_set fds; + struct timeval timeout; + + if(fd < 0) return 0; + + timeout.tv_sec = 0; + timeout.tv_usec = 0; + FD_ZERO(&fds); + FD_SET(fd, &fds); + return select(fd+1, &fds, NULL, NULL, &timeout) > 0; +} + +int +writen(int fd, void *data, int n) +{ + int m; + + while(n > 0){ + m = write(fd, data, n); + if(m == -1) + return -1; + data += m; + n -= m; + } + return 0; +} + +int +readn(int fd, void *data, int n) +{ + int m; + + while(n > 0){ + m = read(fd, data, n); + if(m <= 0) + return -1; + data += m; + n -= m; + } + return 0; +} + +int +dial(const char *host, int port) +{ + char portstr[32]; + int sockfd; + struct addrinfo *result, *rp, hints; + + memset(&hints, 0, sizeof(hints)); + hints.ai_family = AF_UNSPEC; + hints.ai_socktype = SOCK_STREAM; + + snprintf(portstr, 32, "%d", port); + if(getaddrinfo(host, portstr, &hints, &result)){ + perror("error: getaddrinfo"); + return -1; + } + + for(rp = result; rp; rp = rp->ai_next){ + sockfd = socket(rp->ai_family, rp->ai_socktype, rp->ai_protocol); + if(sockfd < 0) + continue; + if(connect(sockfd, rp->ai_addr, rp->ai_addrlen) >= 0) + goto win; + close(sockfd); + } + freeaddrinfo(result); + perror("error"); + return -1; + +win: + freeaddrinfo(result); + return sockfd; +} + +void +serve(int port, void (*handlecon)(int, void*), void *arg) +{ + int sockfd, confd; + socklen_t len; + struct sockaddr_in server, client; + int x; + + sockfd = socket(AF_INET, SOCK_STREAM, 0); + if(sockfd < 0){ + perror("error: socket"); + return; + } + + x = 1; + setsockopt (sockfd, SOL_SOCKET, SO_REUSEADDR, (void *)&x, sizeof x); + + memset(&server, 0, sizeof(server)); + server.sin_family = AF_INET; + server.sin_addr.s_addr = INADDR_ANY; + server.sin_port = htons(port); + if(bind(sockfd, (struct sockaddr*)&server, sizeof(server)) < 0){ + perror("error: bind"); + return; + } + listen(sockfd, 5); + len = sizeof(client); + while(confd = accept(sockfd, (struct sockaddr*)&client, &len), + confd >= 0) + handlecon(confd, arg); + perror("error: accept"); + return; +} + +int +serve1(int port) +{ + int sockfd, confd; + socklen_t len; + struct sockaddr_in server, client; + int x; + + sockfd = socket(AF_INET, SOCK_STREAM, 0); + if(sockfd < 0){ + perror("error: socket"); + return -1; + } + + x = 1; + setsockopt (sockfd, SOL_SOCKET, SO_REUSEADDR, (void *)&x, sizeof x); + + memset(&server, 0, sizeof(server)); + server.sin_family = AF_INET; + server.sin_addr.s_addr = INADDR_ANY; + server.sin_port = htons(port); + if(bind(sockfd, (struct sockaddr*)&server, sizeof(server)) < 0){ + perror("error: bind"); + return -1; + } + listen(sockfd, 5); + len = sizeof(client); + while(confd = accept(sockfd, (struct sockaddr*)&client, &len), + confd >= 0) + return confd; + perror("error: accept"); + return -1; +} + +void +nodelay(int fd) +{ + int flag = 1; + setsockopt(fd, IPPROTO_TCP, TCP_NODELAY, &flag, sizeof(flag)); +} diff --git a/fe6/util.h b/fe6/util.h new file mode 100644 index 0000000..34c617d --- /dev/null +++ b/fe6/util.h @@ -0,0 +1,8 @@ +void strtolower(char *s); +int hasinput(int fd); +int writen(int fd, void *data, int n); +int readn(int fd, void *data, int n); +int dial(const char *host, int port); +void serve(int port, void (*handlecon)(int, void*), void *arg); +int serve1(int port); +void nodelay(int fd); diff --git a/verilog/Makefile b/verilog/Makefile deleted file mode 100644 index 2ef2b54..0000000 --- a/verilog/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -test: test.v pdp6.v apr.v core161c.v fast162.v modules.v test1.inc test2.inc test_fp.inc - iverilog -o test test.v pdp6.v apr.v core161c.v fast162.v modules.v - -test_dec: test_dec.v pdp6.v apr.v core161c.v fast162.v modules.v - iverilog -o test_dec test_dec.v pdp6.v apr.v core161c.v fast162.v modules.v - -run: test - vvp test diff --git a/verilog/apr.v b/verilog/apr.v index 5e6393a..0ffeda6 100644 --- a/verilog/apr.v +++ b/verilog/apr.v @@ -1,3 +1,15 @@ +// two's complement of long dividend isn't taken correctly +`define FIX_DS +// USER IOT isn't implemented fully +`define FIX_USER_IOT +// A LONG flip-flop is missing +`define FIX_A_LONG +// guard against firing MC RS T0 twice on +// MEM CONT when RUN is 0. Although clearing +// the SBR FF probably prevents the same after MC RS T1 +`define FIX_MEMSTOP + + module apr( input wire clk, input wire reset, @@ -32,6 +44,7 @@ module apr( input wire sw_split_cyc, // lights + output wire power, output reg [0:17] ir, output reg [0:35] mi, output reg [0:35] ar, @@ -91,6 +104,14 @@ module apr( input wire [0:35] iobus_iob_in ); +`ifdef simulation + assign power = sw_power; +`else + assign power = ~key_pwr_clr_enbl & ~reset & sw_power; +`endif + wire rst = reset | ~sw_power; + + assign ff0 = { key_ex_st, key_ex_sync, key_dep_st, key_dep_sync, key_rdwr, mc_rd, mc_wr, mc_rq }; assign ff1 = { if1a, af0, af3, af3a, et4_ar_pse, f1a, f4a, f6a }; assign ff2 = { sf3, sf5a, sf7, ar_com_cont, blt_f0a, blt_f3a, blt_f5a, iot_f0a }; @@ -106,9 +127,6 @@ module apr( assign ff12 = { key_rim_sbr, ar_cry0_xor_cry1, ar_cry0, ar_cry1, ar_ov_flag, ar_cry0_flag, ar_cry1_flag, ar_pc_chg_flag }; assign ff13 = { cpa_non_exist_mem, cpa_clock_enable, cpa_clock_flag, cpa_pc_chg_enable, cpa_arov_enable, cpa_pia[33:35] }; - // TODO: - reg a_long = 1'b0; - /* * KEY */ @@ -162,40 +180,48 @@ module apr( wire key_wr = kt3 & key_dp_OR_dp_nxt; wire kt0a_D, kt1_D, kt2_D, kt3_D; - pg key_pg0(.clk(clk), .reset(reset), .in(key_inst_stop), .p(run_clr)); - pg key_pg1(.clk(clk), .reset(reset), .in(sw_power), .p(mr_pwr_clr)); - pg key_pg2(.clk(clk), .reset(reset), .in(key_manual), .p(kt0)); - pg key_pg3(.clk(clk), .reset(reset), +`ifdef simulation + pg key_pg0(.clk(clk), .reset(reset), .in(sw_power), .p(mr_pwr_clr)); +`else + wire sw_power_pulse; + wire key_pwr_clr_enbl; + pg key_pg7(clk, reset, sw_power, sw_power_pulse); + ldly5s key_dly4(.clk(clk), .reset(reset), .in(sw_power_pulse), .l(key_pwr_clr_enbl)); + clk25khz key_clk0(clk, key_pwr_clr_enbl, mr_pwr_clr); +`endif + pg key_pg1(.clk(clk), .reset(rst), .in(key_inst_stop), .p(run_clr)); + pg key_pg2(.clk(clk), .reset(rst), .in(key_manual), .p(kt0)); + pg key_pg3(.clk(clk), .reset(rst), .in(kt2 & key_execute_OR_dp_OR_dp_nxt | cpa & iobus_iob_fm_datai), .p(key_ar_fm_datasw1)); - pa key_pa0(.clk(clk), .reset(reset), .in(kt0), .p(kt0a)); - pa key_pa1(.clk(clk), .reset(reset), + pa key_pa0(.clk(clk), .reset(rst), .in(kt0), .p(kt0a)); + pa key_pa1(.clk(clk), .reset(rst), .in(kt0a_D & ~run | - kt0a & key_mem_cont | // TODO: check run? + kt0a & key_mem_cont | st7 & run & key_ex_OR_dep_st), .p(kt1)); - pa key_pa2(.clk(clk), .reset(reset), .in(kt1_D), .p(kt2)); - pa key_pa3(.clk(clk), .reset(reset), .in(kt2_D), .p(kt3)); - pa key_pa4(.clk(clk), .reset(reset), + pa key_pa2(.clk(clk), .reset(rst), .in(kt1_D), .p(kt2)); + pa key_pa3(.clk(clk), .reset(rst), .in(kt2_D), .p(kt3)); + pa key_pa4(.clk(clk), .reset(rst), .in(kt3 & key_execute | key_rdwr_ret | mc_stop_set & key_mem_cont | st7 & key_start_OR_cont_OR_read_in), .p(kt4)); - pa key_pa5(.clk(clk), .reset(reset), + pa key_pa5(.clk(clk), .reset(rst), .in(kt3 & key_start_OR_cont_OR_read_in | key_run_AND_ex_OR_dep), .p(key_go)); - pa key_pa6(.clk(clk), .reset(reset), + pa key_pa6(.clk(clk), .reset(rst), .in(key_rdwr & mc_rs_t1), .p(key_rdwr_ret)); - dly100ns key_dly0(.clk(clk), .reset(reset), .in(kt0a), .p(kt0a_D)); - dly200ns key_dly1(.clk(clk), .reset(reset), .in(kt1), .p(kt1_D)); - dly200ns key_dly2(.clk(clk), .reset(reset), .in(kt2), .p(kt2_D)); - dly100ns key_dly3(.clk(clk), .reset(reset), .in(kt3), .p(kt3_D)); + dly100ns key_dly0(.clk(clk), .reset(rst), .in(kt0a), .p(kt0a_D)); + dly200ns key_dly1(.clk(clk), .reset(rst), .in(kt1), .p(kt1_D)); + dly200ns key_dly2(.clk(clk), .reset(rst), .in(kt2), .p(kt2_D)); + dly100ns key_dly3(.clk(clk), .reset(rst), .in(kt3), .p(kt3_D)); `ifdef simulation /* add to this as needed */ @@ -256,33 +282,33 @@ module apr( wire it1; wire it1a; - pa i_pa0(.clk(clk), .reset(reset), + pa i_pa0(.clk(clk), .reset(rst), .in(key_go | (st7 & key_run_AND_NOT_ex_OR_dep)), .p(it0)); - pa i_pa1(.clk(clk), .reset(reset), + pa i_pa1(.clk(clk), .reset(rst), .in(pi_sync_D & pi_rq & ~pi_cyc), .p(iat0)); - pa i_pa2(.clk(clk), .reset(reset), + pa i_pa2(.clk(clk), .reset(rst), .in(iat0_D1 | pi_sync_D & if1a & ia_NOT_int), .p(it1)); - pa i_pa3(.clk(clk), .reset(reset), + pa i_pa3(.clk(clk), .reset(rst), .in(mc_rs_t1 & if1a | kt3_D & key_execute | xct_t0_D), .p(it1a)); wire it0_D, iat0_D0, iat0_D1; - ldly100us i_dly0(.clk(clk), .reset(reset), + ldly100us i_dly0(.clk(clk), .reset(rst), .in(run_clr), .l(at1_inh)); - dly50ns i_dly1(.clk(clk), .reset(reset), + dly50ns i_dly1(.clk(clk), .reset(rst), .in(it0), .p(it0_D)); - dly100ns i_dly2(.clk(clk), .reset(reset), + dly100ns i_dly2(.clk(clk), .reset(rst), .in(iat0), .p(iat0_D0)); - dly200ns i_dly23(.clk(clk), .reset(reset), + dly200ns i_dly23(.clk(clk), .reset(rst), .in(iat0), .p(iat0_D1)); @@ -307,33 +333,35 @@ module apr( wire at4; wire at5; - pa a_pa0(.clk(clk), .reset(reset), + reg a_long = 1'b0; + + pa a_pa0(.clk(clk), .reset(rst), .in(it1a | cht9 | mc_rs_t1 & af0), .p(at0)); - pa a_pa1(.clk(clk), .reset(reset), + pa a_pa1(.clk(clk), .reset(rst), .in(pi_sync_D & ~if1a & ia_NOT_int), .p(at1)); - pa a_pa2(.clk(clk), .reset(reset), + pa a_pa2(.clk(clk), .reset(rst), .in(at1 & ~ir14_17_eq_0), .p(at2)); - pa a_pa3(.clk(clk), .reset(reset), + pa a_pa3(.clk(clk), .reset(rst), .in(mc_rs_t1 & af3), .p(at3)); - pa a_pa4(.clk(clk), .reset(reset), + pa a_pa4(.clk(clk), .reset(rst), .in(ar_t3 & af3a), .p(at3a)); - pa a_pa5(.clk(clk), .reset(reset), + pa a_pa5(.clk(clk), .reset(rst), .in(at1 & ir14_17_eq_0 | at3a_D), .p(at4)); - pa a_pa6(.clk(clk), .reset(reset), + pa a_pa6(.clk(clk), .reset(rst), .in(at4 & ir[13]), .p(at5)); wire at3a_D, at5_D; - dly100ns a_dly0(.clk(clk), .reset(reset), + dly100ns a_dly0(.clk(clk), .reset(rst), .in(at3a), .p(at3a_D)); - dly50ns a_dly1(.clk(clk), .reset(reset), + dly50ns a_dly1(.clk(clk), .reset(rst), .in(at5), .p(at5_D)); @@ -350,6 +378,13 @@ module apr( af3a <= 0; if(at3) af3a <= 1; + +`ifdef FIX_A_LONG + if(mr_clr) + a_long <= 0; + if(at2 | at5) + a_long <= 1; +`endif end /* @@ -385,48 +420,48 @@ module apr( boole_as_10 | boole_as_11; wire f_c_e_OR_pse = f_c_e | f_c_e_pse; - pa f_pa0(.clk(clk), .reset(reset), + pa f_pa0(.clk(clk), .reset(rst), .in(at4 & ~ir[13] | iot_t0a_D), .p(ft0)); - pa f_pa1(.clk(clk), .reset(reset), + pa f_pa1(.clk(clk), .reset(rst), .in(ft0 & ~f_ac_inh), .p(ft1)); - pa f_pa2(.clk(clk), .reset(reset), + pa f_pa2(.clk(clk), .reset(rst), .in(f1a & mc_rs_t1 | blt_t6_D), .p(ft1a)); - pa f_pa4(.clk(clk), .reset(reset), + pa f_pa4(.clk(clk), .reset(rst), .in(ft1a_D & f_c_c_aclt_OR_rt), .p(ft3)); - pa f_pa5(.clk(clk), .reset(reset), + pa f_pa5(.clk(clk), .reset(rst), .in(ft3_D | ft1a_D & f_ac_2), .p(ft4)); - pa f_pa6(.clk(clk), .reset(reset), + pa f_pa6(.clk(clk), .reset(rst), .in(f4a & mc_rs_t1), .p(ft4a)); - pa f_pa7(.clk(clk), .reset(reset), + pa f_pa7(.clk(clk), .reset(rst), .in(ft0 & f_ac_inh | ft1a_D & ~f_ac_2_etc | ft4a_D), .p(ft5)); - pa f_pa8(.clk(clk), .reset(reset), + pa f_pa8(.clk(clk), .reset(rst), .in(ft5 & f_c_e), .p(ft6)); - pa f_pa9(.clk(clk), .reset(reset), + pa f_pa9(.clk(clk), .reset(rst), .in(ft5 & f_c_e_pse), .p(ft7)); - pa f_pa10(.clk(clk), .reset(reset), + pa f_pa10(.clk(clk), .reset(rst), .in(f6a & mc_rs_t1 | ft5 & ~f_c_e_OR_pse), .p(ft6a)); wire ft1a_D, ft3_D, ft4a_D; - dly100ns f_dly0(.clk(clk), .reset(reset), + dly100ns f_dly0(.clk(clk), .reset(rst), .in(ft1a), .p(ft1a_D)); - dly100ns f_dly1(.clk(clk), .reset(reset), + dly100ns f_dly1(.clk(clk), .reset(rst), .in(ft3), .p(ft3_D)); - dly100ns f_dly2(.clk(clk), .reset(reset), + dly100ns f_dly2(.clk(clk), .reset(rst), .in(ft4a), .p(ft4a_D)); @@ -466,38 +501,38 @@ module apr( wire e_long = iot_consz | ir_jp | ir_acbm | pc_set | mb_pc_sto | pc_inc_et9 | iot_conso | ir_accp_OR_memac; - pa e_pa0(.clk(clk), .reset(reset), + pa e_pa0(.clk(clk), .reset(rst), .in(ft6a), .p(et0a)); - pa e_pa1(.clk(clk), .reset(reset), + pa e_pa1(.clk(clk), .reset(rst), .in(ft6a), .p(et0)); - pa e_pa2(.clk(clk), .reset(reset), + pa e_pa2(.clk(clk), .reset(rst), .in(ft6a_D), .p(et1)); - pa e_pa3(.clk(clk), .reset(reset), + pa e_pa3(.clk(clk), .reset(rst), .in(et1_D), .p(et3)); - pa e_pa4(.clk(clk), .reset(reset), + pa e_pa4(.clk(clk), .reset(rst), .in(et3 & ~et4_inh | ar_t3 & et4_ar_pse), .p(et4)); - pa e_pa5(.clk(clk), .reset(reset), + pa e_pa5(.clk(clk), .reset(rst), .in(et4_D & ~et5_inh | iot_t3_D), .p(et5)); - pa e_pa6(.clk(clk), .reset(reset), + pa e_pa6(.clk(clk), .reset(rst), .in(et5_D & e_long), .p(et6)); - pa e_pa7(.clk(clk), .reset(reset), + pa e_pa7(.clk(clk), .reset(rst), .in(et6_D), .p(et7)); - pa e_pa8(.clk(clk), .reset(reset), + pa e_pa8(.clk(clk), .reset(rst), .in(et7_D), .p(et8)); - pa e_pa9(.clk(clk), .reset(reset), + pa e_pa9(.clk(clk), .reset(rst), .in(et8_D | dst21a & ir_div), .p(et9)); - pa e_pa10(.clk(clk), .reset(reset), + pa e_pa10(.clk(clk), .reset(rst), .in(et9_D | et5 & ~e_long | lct0a | dct3 | nrt6 | fst0a | sht1a | @@ -507,31 +542,31 @@ module apr( wire ft6a_D, et1_D, et4_D, et5_D; wire et6_D, et7_D, et8_D, et9_D; wire iot_t3_D; - dly100ns e_dly0(.clk(clk), .reset(reset), + dly100ns e_dly0(.clk(clk), .reset(rst), .in(ft6a), .p(ft6a_D)); - dly100ns e_dly1(.clk(clk), .reset(reset), + dly100ns e_dly1(.clk(clk), .reset(rst), .in(et1), .p(et1_D)); - dly200ns e_dly2(.clk(clk), .reset(reset), + dly200ns e_dly2(.clk(clk), .reset(rst), .in(iot_t3), .p(iot_t3_D)); - dly100ns e_dly3(.clk(clk), .reset(reset), + dly100ns e_dly3(.clk(clk), .reset(rst), .in(et4), .p(et4_D)); - dly100ns e_dly4(.clk(clk), .reset(reset), + dly100ns e_dly4(.clk(clk), .reset(rst), .in(et5), .p(et5_D)); - dly100ns e_dly5(.clk(clk), .reset(reset), + dly100ns e_dly5(.clk(clk), .reset(rst), .in(et6), .p(et6_D)); - dly100ns e_dly6(.clk(clk), .reset(reset), + dly100ns e_dly6(.clk(clk), .reset(rst), .in(et7), .p(et7_D)); - dly200ns e_dly7(.clk(clk), .reset(reset), + dly200ns e_dly7(.clk(clk), .reset(rst), .in(et8), .p(et8_D)); - dly200ns e_dly8(.clk(clk), .reset(reset), + dly200ns e_dly8(.clk(clk), .reset(rst), .in(et9), .p(et9_D)); @@ -569,32 +604,32 @@ module apr( wire s_ac_2 = sh_ac_2 | ir_fp_rem | ir_md_s_ac_2; wire s_ac_0 = ir[9:12] == 0; - pa s_pa0(.clk(clk), .reset(reset), + pa s_pa0(.clk(clk), .reset(rst), .in(et10 & s_c_e), .p(st1)); - pa s_pa1(.clk(clk), .reset(reset), + pa s_pa1(.clk(clk), .reset(rst), .in(et10 & f_c_e_pse), .p(st2)); - pa s_pa2(.clk(clk), .reset(reset), + pa s_pa2(.clk(clk), .reset(rst), .in(mc_rs_t1 & sf3 | et10 & ~f_c_e_pse & ~s_c_e), .p(st3)); - pa s_pa3(.clk(clk), .reset(reset), + pa s_pa3(.clk(clk), .reset(rst), .in(st3 & ~s_ac_inh), .p(st3a)); - pa s_pa4(.clk(clk), .reset(reset), + pa s_pa4(.clk(clk), .reset(rst), .in(st3a_D), .p(st5)); - pa s_pa5(.clk(clk), .reset(reset), + pa s_pa5(.clk(clk), .reset(rst), .in(mc_rs_t1 & sf5a), .p(st5a)); - pa s_pa6(.clk(clk), .reset(reset), + pa s_pa6(.clk(clk), .reset(rst), .in(st5a & s_ac_2), .p(st6)); - pa s_pa7(.clk(clk), .reset(reset), + pa s_pa7(.clk(clk), .reset(rst), .in(st6_D), .p(st6a)); - pa s_pa8(.clk(clk), .reset(reset), + pa s_pa8(.clk(clk), .reset(rst), .in(st3 & s_ac_inh | st5a & ~s_ac_2 | cht8b & ir_cao | @@ -605,13 +640,13 @@ module apr( .p(st7)); wire st3a_D, st6_D, mc_illeg_address_D; - dly100ns s_dly0(.clk(clk), .reset(reset), + dly100ns s_dly0(.clk(clk), .reset(rst), .in(st3a), .p(st3a_D)); - dly50ns s_dly1(.clk(clk), .reset(reset), + dly50ns s_dly1(.clk(clk), .reset(rst), .in(st6), .p(st6_D)); - dly100ns s_dly2(.clk(clk), .reset(reset), + dly100ns s_dly2(.clk(clk), .reset(rst), .in(mc_illeg_address), .p(mc_illeg_address_D)); @@ -804,12 +839,12 @@ module apr( /* XCT */ wire xct_t0; - pa xct_pa0(.clk(clk), .reset(reset), + pa xct_pa0(.clk(clk), .reset(rst), .in(et3 & ir_xct), .p(xct_t0)); wire xct_t0_D; - dly200ns xct_dly0(.clk(clk), .reset(reset), + dly200ns xct_dly0(.clk(clk), .reset(rst), .in(xct_t0), .p(xct_t0_D)); @@ -820,15 +855,15 @@ module apr( wire uuo_t1; wire uuo_t2; - pa uuo_pa0(.clk(clk), .reset(reset), + pa uuo_pa0(.clk(clk), .reset(rst), .in(uuo_f1 & mc_rs_t1), .p(uuo_t1)); - pa uuo_pa1(.clk(clk), .reset(reset), + pa uuo_pa1(.clk(clk), .reset(rst), .in(uuo_t1_D), .p(uuo_t2)); wire uuo_t1_D; - dly100ns uuo_dly0(.clk(clk), .reset(reset), + dly100ns uuo_dly0(.clk(clk), .reset(rst), .in(uuo_t1), .p(uuo_t1_D)); @@ -976,14 +1011,13 @@ module apr( wire mb_fm_pc1_et6 = jp_jsa; wire mc_mb_clr_D; - dly100ns mb_dly0(.clk(clk), .reset(reset), .in(mc_mb_clr), .p(mc_mb_clr_D)); - - wire membus_mb_pulse; - pg mb_pg0(.clk(clk), .reset(reset), .in(| membus_mb_in), .p(membus_mb_pulse)); + dly100ns mb_dly0(.clk(clk), .reset(rst), .in(mc_mb_clr), .p(mc_mb_clr_D)); always @(posedge clk) begin: mbctl integer i; + if(mc_mb_membus_enable) + mb <= mb | membus_mb_in; if(mblt_clr) mb[0:17] <= 0; if(mbrt_clr) @@ -1027,9 +1061,10 @@ module apr( if(ar_pc_chg_flag) mb[3] <= 1; if(chf7) mb[4] <= 1; if(ex_user) mb[5] <= 1; +`ifdef FIX_USER_IOT + if(cpa_iot_user) mb[6] <= 1; +`endif end - if(membus_mb_pulse & mc_mb_membus_enable) - mb <= mb | membus_mb_in; end /* @@ -1158,56 +1193,56 @@ module apr( wire set_flags_et10 = et10 & (memac | ir_as); - pa ar_pa0(.clk(clk), .reset(reset), + pa ar_pa0(.clk(clk), .reset(rst), .in(et3 & ar_dec), .p(ar_incdec_t0)); - pa ar_pa1(.clk(clk), .reset(reset), + pa ar_pa1(.clk(clk), .reset(rst), .in(et3 & fwt_negate | et3 & ir_fsb | cfac_ar_negate), .p(ar_negate_t0)); - pa ar_pa2(.clk(clk), .reset(reset), + pa ar_pa2(.clk(clk), .reset(rst), .in(ar_incdec_t0_D | ar_negate_t0_D | et3 & ar_inc | blt_t5 | nrt5 | cht4), .p(ar_incdec_t1)); pa ar_pa3(); // AR17 CRY IN - pa ar_pa4(.clk(clk), .reset(reset), + pa ar_pa4(.clk(clk), .reset(rst), .in(et3 & ar_sub | cfac_ar_sub | blt_t3), .p(ar_as_t0)); - pa ar_pa5(.clk(clk), .reset(reset), + pa ar_pa5(.clk(clk), .reset(rst), .in(ar_as_t0_D | et3 & ar_add | at3 | cfac_ar_add), .p(ar_as_t1)); - pa ar_pa6(.clk(clk), .reset(reset), + pa ar_pa6(.clk(clk), .reset(rst), .in(ar_as_t1_D), .p(ar_as_t2)); - pa ar_pa7(.clk(clk), .reset(reset), + pa ar_pa7(.clk(clk), .reset(rst), .in(ar_as_t2 | ar_incdec_t1 | ar17_cry_in), .p(ar_cry_comp)); - pa ar_pa8(.clk(clk), .reset(reset), + pa ar_pa8(.clk(clk), .reset(rst), .in(ar_cry_comp & ~ar_com_cont | ar_cry_comp_D & ar_com_cont), .p(ar_t3)); wire ar_incdec_t0_D, ar_negate_t0_D; wire ar_as_t0_D, ar_as_t1_D, ar_cry_comp_D; - dly100ns ar_dly0(.clk(clk), .reset(reset), + dly100ns ar_dly0(.clk(clk), .reset(rst), .in(ar_incdec_t0), .p(ar_incdec_t0_D)); - dly100ns ar_dly1(.clk(clk), .reset(reset), + dly100ns ar_dly1(.clk(clk), .reset(rst), .in(ar_negate_t0), .p(ar_negate_t0_D)); - dly100ns ar_dly2(.clk(clk), .reset(reset), + dly100ns ar_dly2(.clk(clk), .reset(rst), .in(ar_as_t0), .p(ar_as_t0_D)); - dly100ns ar_dly3(.clk(clk), .reset(reset), + dly100ns ar_dly3(.clk(clk), .reset(rst), .in(ar_as_t1), .p(ar_as_t1_D)); - dly100ns ar_dly4(.clk(clk), .reset(reset), + dly100ns ar_dly4(.clk(clk), .reset(rst), .in(ar_cry_comp), .p(ar_cry_comp_D)); @@ -1438,33 +1473,33 @@ module apr( wire sat21; wire sat3; - pa sa_pa0(.clk(clk), .reset(reset), + pa sa_pa0(.clk(clk), .reset(rst), .in(cht3 | fst0 | fat1 | fpt1 | fpt1aa), .p(sat0)); - pa sa_pa1(.clk(clk), .reset(reset), + pa sa_pa1(.clk(clk), .reset(rst), .in(sat0_D), .p(sat1)); - pa sa_pa2(.clk(clk), .reset(reset), + pa sa_pa2(.clk(clk), .reset(rst), .in(sat1_D), .p(sat2)); - pa sa_pa3(.clk(clk), .reset(reset), + pa sa_pa3(.clk(clk), .reset(rst), .in(sat2_D), .p(sat21)); - pa sa_pa4(.clk(clk), .reset(reset), + pa sa_pa4(.clk(clk), .reset(rst), .in(sat21_D), .p(sat3)); wire sat0_D, sat1_D, sat2_D, sat21_D; - dly150ns sa_dly0(.clk(clk), .reset(reset), + dly150ns sa_dly0(.clk(clk), .reset(rst), .in(sat0), .p(sat0_D)); - dly200ns sa_dly1(.clk(clk), .reset(reset), + dly200ns sa_dly1(.clk(clk), .reset(rst), .in(sat1), .p(sat1_D)); - dly50ns sa_dly2(.clk(clk), .reset(reset), + dly50ns sa_dly2(.clk(clk), .reset(rst), .in(sat2), .p(sat2_D)); - dly100ns sa_dly3(.clk(clk), .reset(reset), + dly100ns sa_dly3(.clk(clk), .reset(rst), .in(sat21), .p(sat21_D)); @@ -1472,23 +1507,23 @@ module apr( wire sct1; wire sct2; - pa sc_pa0(.clk(clk), .reset(reset), + pa sc_pa0(.clk(clk), .reset(rst), .in(lct0 | dct0 | sht1 | fat5 | cht8b & ~ir_cao), .p(sct0)); - pa sc_pa1(.clk(clk), .reset(reset), + pa sc_pa1(.clk(clk), .reset(rst), .in((sct0_D | sct1_D) & ~sc_eq_777), .p(sct1)); - pa sc_pa2(.clk(clk), .reset(reset), + pa sc_pa2(.clk(clk), .reset(rst), .in((sct0_D | sct1_D) & sc_eq_777), .p(sct2)); wire sct0_D, sct1_D; - dly200ns sc_dly0(.clk(clk), .reset(reset), + dly200ns sc_dly0(.clk(clk), .reset(rst), .in(sct0), .p(sct0_D)); // should be 75ns - dly70ns sc_dly1(.clk(clk), .reset(reset), + dly70ns sc_dly1(.clk(clk), .reset(rst), .in(sct1), .p(sct1_D)); @@ -1581,56 +1616,56 @@ module apr( wire blt_t5a; wire blt_t6; - pa blt_pa0(.clk(clk), .reset(reset), + pa blt_pa0(.clk(clk), .reset(rst), .in(et3 & ir_blt), .p(blt_t0)); - pa blt_pa1(.clk(clk), .reset(reset), + pa blt_pa1(.clk(clk), .reset(rst), .in(mc_rs_t1 & blt_f0a), .p(blt_t0a)); - pa blt_pa2(.clk(clk), .reset(reset), + pa blt_pa2(.clk(clk), .reset(rst), .in(blt_t0a_D), .p(blt_t1)); - pa blt_pa3(.clk(clk), .reset(reset), + pa blt_pa3(.clk(clk), .reset(rst), .in(blt_t1_D), .p(blt_t2)); - pa blt_pa4(.clk(clk), .reset(reset), + pa blt_pa4(.clk(clk), .reset(rst), .in(blt_t2_D), .p(blt_t3)); - pa blt_pa5(.clk(clk), .reset(reset), + pa blt_pa5(.clk(clk), .reset(rst), .in(ar_t3 & blt_f3a), .p(blt_t3a)); - pa blt_pa6(.clk(clk), .reset(reset), + pa blt_pa6(.clk(clk), .reset(rst), .in(blt_t3a_D), .p(blt_t4)); - pa blt_pa7(.clk(clk), .reset(reset), + pa blt_pa7(.clk(clk), .reset(rst), .in(blt_t4_D), .p(blt_t5)); - pa blt_pa8(.clk(clk), .reset(reset), + pa blt_pa8(.clk(clk), .reset(rst), .in(ar_t3 & blt_f5a), .p(blt_t5a)); - pa blt_pa9(.clk(clk), .reset(reset), + pa blt_pa9(.clk(clk), .reset(rst), .in(blt_t5a & ~blt_done), .p(blt_t6)); wire blt_t0a_D, blt_t1_D; wire blt_t2_D, blt_t3a_D; wire blt_t4_D, blt_t6_D; - dly100ns blt_dly0(.clk(clk), .reset(reset), + dly100ns blt_dly0(.clk(clk), .reset(rst), .in(blt_t0a), .p(blt_t0a_D)); - dly100ns blt_dly1(.clk(clk), .reset(reset), + dly100ns blt_dly1(.clk(clk), .reset(rst), .in(blt_t1), .p(blt_t1_D)); - dly100ns blt_dly2(.clk(clk), .reset(reset), + dly100ns blt_dly2(.clk(clk), .reset(rst), .in(blt_t2), .p(blt_t2_D)); - dly100ns blt_dly3(.clk(clk), .reset(reset), + dly100ns blt_dly3(.clk(clk), .reset(rst), .in(blt_t3a), .p(blt_t3a_D)); - dly100ns blt_dly4(.clk(clk), .reset(reset), + dly100ns blt_dly4(.clk(clk), .reset(rst), .in(blt_t4), .p(blt_t4_D)); - dly100ns blt_dly5(.clk(clk), .reset(reset), + dly100ns blt_dly5(.clk(clk), .reset(rst), .in(blt_t6), .p(blt_t6_D)); @@ -1660,13 +1695,13 @@ module apr( wire fst0a; wire fst1; - pa fs_pa0(.clk(clk), .reset(reset), + pa fs_pa0(.clk(clk), .reset(rst), .in(et3 & fsc), .p(fst0)); - pa fs_pa1(.clk(clk), .reset(reset), + pa fs_pa1(.clk(clk), .reset(rst), .in(et3 & fsc & ar[0]), .p(fst1)); - pa fs_pa2(.clk(clk), .reset(reset), + pa fs_pa2(.clk(clk), .reset(rst), .in(sat3 & fsf1), .p(fst0a)); @@ -1706,61 +1741,61 @@ module apr( wire cht8b; wire cht9; - pa ch_pa0(.clk(clk), .reset(reset), + pa ch_pa0(.clk(clk), .reset(rst), .in(et0 & ch_inc_op), .p(cht1)); - pa ch_pa1(.clk(clk), .reset(reset), + pa ch_pa1(.clk(clk), .reset(rst), .in(cht1_D), .p(cht2)); - pa ch_pa2(.clk(clk), .reset(reset), + pa ch_pa2(.clk(clk), .reset(rst), .in(cht2 | cht4a), .p(cht3)); - pa ch_pa3(.clk(clk), .reset(reset), + pa ch_pa3(.clk(clk), .reset(rst), .in(sat3 & chf2), .p(cht3a)); - pa ch_pa4(.clk(clk), .reset(reset), + pa ch_pa4(.clk(clk), .reset(rst), .in(cht3a & ~sc[0]), .p(cht4)); - pa ch_pa5(.clk(clk), .reset(reset), + pa ch_pa5(.clk(clk), .reset(rst), .in(ar_t3 & chf3), .p(cht4a)); - pa ch_pa6(.clk(clk), .reset(reset), + pa ch_pa6(.clk(clk), .reset(rst), .in(cht3a & sc[0]), .p(cht5)); - pa ch_pa7(.clk(clk), .reset(reset), + pa ch_pa7(.clk(clk), .reset(rst), .in(et0 & ch_NOT_inc_op | cht5_D), .p(cht6)); - pa ch_pa8(.clk(clk), .reset(reset), + pa ch_pa8(.clk(clk), .reset(rst), .in(cht6_D), .p(cht7)); - pa ch_pa9(.clk(clk), .reset(reset), + pa ch_pa9(.clk(clk), .reset(rst), .in(cht7_D & ch_inc_op), .p(cht8)); - pa ch_pa10(.clk(clk), .reset(reset), + pa ch_pa10(.clk(clk), .reset(rst), .in(cht7_D & ch_NOT_inc_op | mc_rs_t1 & chf6), .p(cht8b)); - pa ch_pa11(.clk(clk), .reset(reset), + pa ch_pa11(.clk(clk), .reset(rst), .in(sct2 & chf4), .p(cht8a)); - pa ch_pa12(.clk(clk), .reset(reset), + pa ch_pa12(.clk(clk), .reset(rst), .in(cht8a), .p(cht9)); wire cht1_D, cht5_D, cht6_D, cht7_D, cht8a_D; - dly100ns ch_dly0(.clk(clk), .reset(reset), + dly100ns ch_dly0(.clk(clk), .reset(rst), .in(cht1), .p(cht1_D)); - dly100ns ch_dly1(.clk(clk), .reset(reset), + dly100ns ch_dly1(.clk(clk), .reset(rst), .in(cht5), .p(cht5_D)); - dly150ns ch_dly2(.clk(clk), .reset(reset), + dly150ns ch_dly2(.clk(clk), .reset(rst), .in(cht6), .p(cht6_D)); - dly100ns ch_dly3(.clk(clk), .reset(reset), + dly100ns ch_dly3(.clk(clk), .reset(rst), .in(cht7), .p(cht7_D)); - dly100ns ch_dly4(.clk(clk), .reset(reset), + dly100ns ch_dly4(.clk(clk), .reset(rst), .in(cht8a), .p(cht8a_D)); @@ -1812,10 +1847,10 @@ module apr( wire lct0; wire lct0a; - pa lc_pa0(.clk(clk), .reset(reset), + pa lc_pa0(.clk(clk), .reset(rst), .in(et0 & ch_load), .p(lct0)); - pa lc_pa1(.clk(clk), .reset(reset), + pa lc_pa1(.clk(clk), .reset(rst), .in(sct2 & lcf1), .p(lct0a)); @@ -1839,30 +1874,30 @@ module apr( wire dct2; wire dct3; - pa dc_pa0(.clk(clk), .reset(reset), + pa dc_pa0(.clk(clk), .reset(rst), .in(et0 & ch_dep), .p(dct0)); - pa dc_pa1(.clk(clk), .reset(reset), + pa dc_pa1(.clk(clk), .reset(rst), .in(sct2 & dcf1), .p(dct0a)); - pa dc_pa2(.clk(clk), .reset(reset), + pa dc_pa2(.clk(clk), .reset(rst), .in(dct0a_D), .p(dct1)); - pa dc_pa3(.clk(clk), .reset(reset), + pa dc_pa3(.clk(clk), .reset(rst), .in(dct1_D), .p(dct2)); - pa dc_pa4(.clk(clk), .reset(reset), + pa dc_pa4(.clk(clk), .reset(rst), .in(dct2_D), .p(dct3)); wire dct0a_D, dct1_D, dct2_D; - dly150ns dc_dly0(.clk(clk), .reset(reset), + dly150ns dc_dly0(.clk(clk), .reset(rst), .in(dct0a), .p(dct0a_D)); - dly100ns dc_dly1(.clk(clk), .reset(reset), + dly100ns dc_dly1(.clk(clk), .reset(rst), .in(dct1), .p(dct1_D)); - dly100ns dc_dly2(.clk(clk), .reset(reset), + dly100ns dc_dly2(.clk(clk), .reset(rst), .in(dct2), .p(dct2_D)); @@ -1886,18 +1921,18 @@ module apr( wire sht1; wire sht1a; - pa sh_p0(.clk(clk), .reset(reset), + pa sh_p0(.clk(clk), .reset(rst), .in(et1 & shift_op & mb[18]), .p(sht0)); - pa sh_p1(.clk(clk), .reset(reset), + pa sh_p1(.clk(clk), .reset(rst), .in(et3_D & shift_op), .p(sht1)); - pa sh_p2(.clk(clk), .reset(reset), + pa sh_p2(.clk(clk), .reset(rst), .in(sct2 & shf1), .p(sht1a)); wire et3_D; - dly100ns sh_dly(.clk(clk), .reset(reset), + dly100ns sh_dly(.clk(clk), .reset(rst), .in(et3), .p(et3_D)); @@ -1920,27 +1955,27 @@ module apr( wire mpt1; wire mpt2; - pa mp_pa0(.clk(clk), .reset(reset), + pa mp_pa0(.clk(clk), .reset(rst), .in(et0 & ir_mul), .p(mpt0)); - pa mp_pa1(.clk(clk), .reset(reset), + pa mp_pa1(.clk(clk), .reset(rst), .in(mst6 & mpf1), .p(mpt0a)); - pa mp_pa2(.clk(clk), .reset(reset), + pa mp_pa2(.clk(clk), .reset(rst), .in(mpt0a_D & ~ir[6]), .p(mpt1)); - pa mp_pa3(.clk(clk), .reset(reset), + pa mp_pa3(.clk(clk), .reset(rst), .in(mpt1_D), .p(mpt2)); wire mpt0a_D, mpt1_D, mpt2_D; - dly200ns mp_dly0(.clk(clk), .reset(reset), + dly200ns mp_dly0(.clk(clk), .reset(rst), .in(mpt0a), .p(mpt0a_D)); - dly100ns mp_dly1(.clk(clk), .reset(reset), + dly100ns mp_dly1(.clk(clk), .reset(rst), .in(mpt1), .p(mpt1_D)); - dly100ns mp_dly2(.clk(clk), .reset(reset), + dly100ns mp_dly2(.clk(clk), .reset(rst), .in(mpt2), .p(mpt2_D)); @@ -1980,80 +2015,80 @@ module apr( wire fat9; wire fat10; - pa fa_pa0(.clk(clk), .reset(reset), + pa fa_pa0(.clk(clk), .reset(rst), .in(et0 & ir_fad | et4 & ir_fsb), .p(fat0)); - pa fa_pa1(.clk(clk), .reset(reset), + pa fa_pa1(.clk(clk), .reset(rst), .in(fat0_D), .p(fat1)); - pa fa_pa2(.clk(clk), .reset(reset), + pa fa_pa2(.clk(clk), .reset(rst), .in(sat3 & faf2), .p(fat1a)); - pa fa_pa3(.clk(clk), .reset(reset), + pa fa_pa3(.clk(clk), .reset(rst), .in(fat1_D), .p(fat1b)); - pa fa_pa4(.clk(clk), .reset(reset), + pa fa_pa4(.clk(clk), .reset(rst), .in(fat1a & ~sc[0]), .p(fat2)); - pa fa_pa5(.clk(clk), .reset(reset), + pa fa_pa5(.clk(clk), .reset(rst), .in(fat2_D), .p(fat3)); - pa fa_pa6(.clk(clk), .reset(reset), + pa fa_pa6(.clk(clk), .reset(rst), .in(fat1a & sc[0]), .p(fat4)); - pa fa_pa7(.clk(clk), .reset(reset), + pa fa_pa7(.clk(clk), .reset(rst), .in((fat3_D | fat4_D) & sc0_2_eq_7), .p(fat5)); - pa fa_pa8(.clk(clk), .reset(reset), + pa fa_pa8(.clk(clk), .reset(rst), .in(sct2 & faf3), .p(fat5a)); - pa fa_pa9(.clk(clk), .reset(reset), + pa fa_pa9(.clk(clk), .reset(rst), .in((fat3_D | fat4_D) & ~sc0_2_eq_7), .p(fat6)); - pa fa_pa10(.clk(clk), .reset(reset), + pa fa_pa10(.clk(clk), .reset(rst), .in(fat5a_D), .p(fat7)); - pa fa_pa11(.clk(clk), .reset(reset), + pa fa_pa11(.clk(clk), .reset(rst), .in(fat7_D), .p(fat8)); - pa fa_pa12(.clk(clk), .reset(reset), + pa fa_pa12(.clk(clk), .reset(rst), .in(fat8_D), .p(fat8a)); - pa fa_pa13(.clk(clk), .reset(reset), + pa fa_pa13(.clk(clk), .reset(rst), .in(fat8a_D), .p(fat9)); - pa fa_pa14(.clk(clk), .reset(reset), + pa fa_pa14(.clk(clk), .reset(rst), .in(ar_t3 & faf4), .p(fat10)); wire fat0_D, fat1_D, fat2_D, fat3_D, fat4_D; wire fat5a_D, fat7_D, fat8_D, fat8a_D; - dly100ns fa_dly0(.clk(clk), .reset(reset), + dly100ns fa_dly0(.clk(clk), .reset(rst), .in(fat0), .p(fat0_D)); - dly50ns fa_dly1(.clk(clk), .reset(reset), + dly50ns fa_dly1(.clk(clk), .reset(rst), .in(fat1), .p(fat1_D)); - dly150ns fa_dly2(.clk(clk), .reset(reset), + dly150ns fa_dly2(.clk(clk), .reset(rst), .in(fat2), .p(fat2_D)); - dly150ns fa_dly3(.clk(clk), .reset(reset), + dly150ns fa_dly3(.clk(clk), .reset(rst), .in(fat3), .p(fat3_D)); - dly100ns fa_dly4(.clk(clk), .reset(reset), + dly100ns fa_dly4(.clk(clk), .reset(rst), .in(fat4), .p(fat4_D)); - dly100ns fa_dly5(.clk(clk), .reset(reset), + dly100ns fa_dly5(.clk(clk), .reset(rst), .in(fat5a), .p(fat5a_D)); - dly100ns fa_dly6(.clk(clk), .reset(reset), + dly100ns fa_dly6(.clk(clk), .reset(rst), .in(fat7), .p(fat7_D)); - dly50ns fa_dly7(.clk(clk), .reset(reset), + dly50ns fa_dly7(.clk(clk), .reset(rst), .in(fat8), .p(fat8_D)); - dly100ns fa_dly8(.clk(clk), .reset(reset), + dly100ns fa_dly8(.clk(clk), .reset(rst), .in(fat8a), .p(fat8a_D)); @@ -2089,18 +2124,18 @@ module apr( wire fmt0a; wire fmt0b; - pa fm_pa0(.clk(clk), .reset(reset), + pa fm_pa0(.clk(clk), .reset(rst), .in(et0 & ir_fmp), .p(fmt0)); - pa fm_pa1(.clk(clk), .reset(reset), + pa fm_pa1(.clk(clk), .reset(rst), .in(fpt4 & fmf1), .p(fmt0a)); - pa fm_pa2(.clk(clk), .reset(reset), + pa fm_pa2(.clk(clk), .reset(rst), .in(mst6 & fmf2), .p(fmt0b)); wire fmt0b_D; - dly100ns fm_dly0(.clk(clk), .reset(reset), + dly100ns fm_dly0(.clk(clk), .reset(rst), .in(fmt0b), .p(fmt0b_D)); @@ -2127,21 +2162,21 @@ module apr( wire fdt0b; wire fdt1; - pa fd_pa0(.clk(clk), .reset(reset), + pa fd_pa0(.clk(clk), .reset(rst), .in(et0 & ir_fdv), .p(fdt0)); - pa fd_pa1(.clk(clk), .reset(reset), + pa fd_pa1(.clk(clk), .reset(rst), .in(fpt4 & fdf1), .p(fdt0a)); - pa fd_pa2(.clk(clk), .reset(reset), + pa fd_pa2(.clk(clk), .reset(rst), .in(dst21a & fdf2), .p(fdt0b)); - pa fd_pa3(.clk(clk), .reset(reset), + pa fd_pa3(.clk(clk), .reset(rst), .in(fdt0b_D), .p(fdt1)); wire fdt0b_D; - dly100ns fd_dly0(.clk(clk), .reset(reset), + dly100ns fd_dly0(.clk(clk), .reset(rst), .in(fdt0b), .p(fdt0b_D)); @@ -2176,45 +2211,45 @@ module apr( wire fpt3; wire fpt4; - pa fp_pa0(.clk(clk), .reset(reset), + pa fp_pa0(.clk(clk), .reset(rst), .in(fmt0 | fdt0), .p(fpt0)); - pa fp_pa1(.clk(clk), .reset(reset), + pa fp_pa1(.clk(clk), .reset(rst), .in(fpt0), .p(fpt01)); - pa fp_pa2(.clk(clk), .reset(reset), + pa fp_pa2(.clk(clk), .reset(rst), .in(fpt01_D), .p(fpt1)); - pa fp_pa3(.clk(clk), .reset(reset), + pa fp_pa3(.clk(clk), .reset(rst), .in(sat3 & fpf1), .p(fpt1a)); - pa fp_pa4(.clk(clk), .reset(reset), + pa fp_pa4(.clk(clk), .reset(rst), .in(fpt1a_D), .p(fpt1aa)); - pa fp_pa5(.clk(clk), .reset(reset), + pa fp_pa5(.clk(clk), .reset(rst), .in(sat3 & fpf2), .p(fpt1b)); - pa fp_pa6(.clk(clk), .reset(reset), + pa fp_pa6(.clk(clk), .reset(rst), .in(fpt1a & fp_ar0_xor_mb0_xor_fmf1), .p(fpt2)); - pa fp_pa7(.clk(clk), .reset(reset), + pa fp_pa7(.clk(clk), .reset(rst), .in(fpt1b_D), .p(fpt3)); - pa fp_pa8(.clk(clk), .reset(reset), + pa fp_pa8(.clk(clk), .reset(rst), .in(fpt3_D), .p(fpt4)); wire fpt01_D, fpt1a_D, fpt1b_D, fpt3_D; - dly100ns fp_dly0(.clk(clk), .reset(reset), + dly100ns fp_dly0(.clk(clk), .reset(rst), .in(fpt01), .p(fpt01_D)); - dly100ns fp_dly1(.clk(clk), .reset(reset), + dly100ns fp_dly1(.clk(clk), .reset(rst), .in(fpt1a), .p(fpt1a_D)); - dly100ns fp_dly2(.clk(clk), .reset(reset), + dly100ns fp_dly2(.clk(clk), .reset(rst), .in(fpt1b), .p(fpt1b_D)); - dly100ns fp_dly3(.clk(clk), .reset(reset), + dly100ns fp_dly3(.clk(clk), .reset(rst), .in(fpt3), .p(fpt3_D)); @@ -2244,40 +2279,40 @@ module apr( wire mst5; wire mst6; - pa ms_pa0(.clk(clk), .reset(reset), + pa ms_pa0(.clk(clk), .reset(rst), .in(mpt0 | fmt0a), .p(mst1)); - pa ms_pa1(.clk(clk), .reset(reset), + pa ms_pa1(.clk(clk), .reset(rst), .in(((mst1_D1 | mst2_D) & mq35_eq_mq36 | mst3a) & ~sc_eq_777), .p(mst2)); - pa ms_pa2(.clk(clk), .reset(reset), + pa ms_pa2(.clk(clk), .reset(rst), .in((mst1_D1 | mst2_D) & ~mq[35] & mq36), .p(mst3)); - pa ms_pa3(.clk(clk), .reset(reset), + pa ms_pa3(.clk(clk), .reset(rst), .in((mst1_D1 | mst2_D) & mq[35] & ~mq36), .p(mst4)); - pa ms_pa4(.clk(clk), .reset(reset), + pa ms_pa4(.clk(clk), .reset(rst), .in(ar_t3 & msf1), .p(mst3a)); - pa ms_pa5(.clk(clk), .reset(reset), + pa ms_pa5(.clk(clk), .reset(rst), .in((mst2_D & mq35_eq_mq36 | mst3a) & sc_eq_777), .p(mst5)); - pa ms_pa6(.clk(clk), .reset(reset), + pa ms_pa6(.clk(clk), .reset(rst), .in(mst5_D), .p(mst6)); wire mst1_D0, mst1_D1; wire mst2_D, mst5_D; - dly50ns ms_dly0(.clk(clk), .reset(reset), + dly50ns ms_dly0(.clk(clk), .reset(rst), .in(mst1), .p(mst1_D0)); - dly200ns ms_dly1(.clk(clk), .reset(reset), + dly200ns ms_dly1(.clk(clk), .reset(rst), .in(mst1), .p(mst1_D1)); - dly150ns ms_dly2(.clk(clk), .reset(reset), + dly150ns ms_dly2(.clk(clk), .reset(rst), .in(mst2), .p(mst2_D)); - dly100ns ms_dly3(.clk(clk), .reset(reset), + dly100ns ms_dly3(.clk(clk), .reset(rst), .in(mst5), .p(mst5_D)); @@ -2341,116 +2376,124 @@ module apr( wire ds_div_t0; - pa ds_pa0(.clk(clk), .reset(reset), + pa ds_pa0(.clk(clk), .reset(rst), .in(mr_clr), .p(ds_clr)); - pa ds_pa1(.clk(clk), .reset(reset), + pa ds_pa1(.clk(clk), .reset(rst), .in(et0 & ir_div), .p(ds_div_t0)); - pa ds_pa2(.clk(clk), .reset(reset), + pa ds_pa2(.clk(clk), .reset(rst), .in((et0 & ds_divi | fdt0a) & ar[0]), .p(dst0)); - pa ds_pa3(.clk(clk), .reset(reset), + pa ds_pa3(.clk(clk), .reset(rst), .in(ar_t3 & dsf1), .p(dst0a)); - pa ds_pa4(.clk(clk), .reset(reset), + pa ds_pa4(.clk(clk), .reset(rst), .in((et0 & ~ar[0] | dst0a) & ds_divi), .p(dst1)); - pa ds_pa5(.clk(clk), .reset(reset), + pa ds_pa5(.clk(clk), .reset(rst), .in(dst1_D), .p(dst2)); - pa ds_pa6(.clk(clk), .reset(reset), + pa ds_pa6(.clk(clk), .reset(rst), .in(et0 & ar[0] & ds_div), .p(dst3)); - pa ds_pa7(.clk(clk), .reset(reset), + pa ds_pa7(.clk(clk), .reset(rst), .in(dst3_D), .p(dst4)); - pa ds_pa8(.clk(clk), .reset(reset), + pa ds_pa8(.clk(clk), .reset(rst), .in(dst4_D), .p(dst5)); - pa ds_pa9(.clk(clk), .reset(reset), + pa ds_pa9(.clk(clk), .reset(rst), .in(ar_t3 & dsf2), .p(dst5a)); - pa ds_pa10(.clk(clk), .reset(reset), + pa ds_pa10(.clk(clk), .reset(rst), +`ifdef FIX_DS .in(dst5a_D & ~ar_eq_0), +`else + .in(dst5a_D & ~ar_cry1), +`endif .p(dst6)); - pa ds_pa11(.clk(clk), .reset(reset), + pa ds_pa11(.clk(clk), .reset(rst), .in(dst6_D), .p(dst7)); - pa ds_pa12(.clk(clk), .reset(reset), + pa ds_pa12(.clk(clk), .reset(rst), +`ifdef FIX_DS .in(dst5a_D & ar_eq_0), +`else + .in(dst5a_D & ar_cry1), +`endif .p(dst8)); - pa ds_pa13(.clk(clk), .reset(reset), + pa ds_pa13(.clk(clk), .reset(rst), .in(dst8_D), .p(dst9)); - pa ds_pa14(.clk(clk), .reset(reset), + pa ds_pa14(.clk(clk), .reset(rst), .in(ar_t3 & dsf3 | fdt0a & ~ar[0] | dst0a & ~ds_divi | et0 & ds_div & ~ar[0] | dst2 | dst7), .p(dst10)); - pa ds_pa15(.clk(clk), .reset(reset), + pa ds_pa15(.clk(clk), .reset(rst), .in(dst10_D & ir_fdv), .p(dst10a)); - pa ds_pa16(.clk(clk), .reset(reset), + pa ds_pa16(.clk(clk), .reset(rst), .in(dst10_D & ir_div), .p(dst10b)); - pa ds_pa17(.clk(clk), .reset(reset), + pa ds_pa17(.clk(clk), .reset(rst), .in((dst10a_D | dst10b_D) & mb[0]), .p(dst11)); - pa ds_pa18(.clk(clk), .reset(reset), + pa ds_pa18(.clk(clk), .reset(rst), .in((dst10a_D | dst10b_D) & ~mb[0]), .p(dst12)); - pa ds_pa19(.clk(clk), .reset(reset), + pa ds_pa19(.clk(clk), .reset(rst), .in(ar_t3 & dsf4), .p(dst11a)); - pa ds_pa20(.clk(clk), .reset(reset), + pa ds_pa20(.clk(clk), .reset(rst), .in(dst11a & ~ar[0]), .p(dst13)); - pa ds_pa21(.clk(clk), .reset(reset), + pa ds_pa21(.clk(clk), .reset(rst), .in(ar_t3 & dsf5 | dst11a & ar[0]), .p(dst14a)); - pa ds_pa22(.clk(clk), .reset(reset), + pa ds_pa22(.clk(clk), .reset(rst), .in(dst14a), .p(dst14b)); - pa ds_pa23(.clk(clk), .reset(reset), + pa ds_pa23(.clk(clk), .reset(rst), .in(dst14b_D & ~sc_eq_777 & mq35_xor_mb0), .p(dst14)); - pa ds_pa24(.clk(clk), .reset(reset), + pa ds_pa24(.clk(clk), .reset(rst), .in(dst14b_D & ~sc_eq_777 & ~mq35_xor_mb0), .p(dst15)); - pa ds_pa25(.clk(clk), .reset(reset), + pa ds_pa25(.clk(clk), .reset(rst), .in(dst14b_D & sc_eq_777), .p(dst16)); - pa ds_pa26(.clk(clk), .reset(reset), + pa ds_pa26(.clk(clk), .reset(rst), .in(dst16_D & ar[0] & ~mb[0]), .p(dst17)); - pa ds_pa27(.clk(clk), .reset(reset), + pa ds_pa27(.clk(clk), .reset(rst), .in(dst16_D & ar[0] & mb[0]), .p(dst18)); - pa ds_pa28(.clk(clk), .reset(reset), + pa ds_pa28(.clk(clk), .reset(rst), .in(dst16_D & ~ar[0] | ar_t3 & dsf6), .p(dst17a)); - pa ds_pa29(.clk(clk), .reset(reset), + pa ds_pa29(.clk(clk), .reset(rst), .in(dst17a & dsf7), .p(dst19)); - pa ds_pa30(.clk(clk), .reset(reset), + pa ds_pa30(.clk(clk), .reset(rst), .in(dst17a & ~dsf7 | ar_t3 & dsf8), .p(dst19a)); - pa ds_pa31(.clk(clk), .reset(reset), + pa ds_pa31(.clk(clk), .reset(rst), .in(dst19_D), .p(dst19b)); - pa ds_pa32(.clk(clk), .reset(reset), + pa ds_pa32(.clk(clk), .reset(rst), .in(dst19a_D), .p(dst20)); - pa ds_pa33(.clk(clk), .reset(reset), + pa ds_pa33(.clk(clk), .reset(rst), .in(dst20_D & dsf7_xor_mq0), .p(dst21)); - pa ds_pa34(.clk(clk), .reset(reset), + pa ds_pa34(.clk(clk), .reset(rst), .in(dst20_D & ~dsf7_xor_mq0 | ar_t3 & dsf9), .p(dst21a)); @@ -2459,46 +2502,46 @@ module apr( wire dst1_D, dst3_D, dst4_D, dst5a_D, dst6_D, dst8_D; wire dst10_D, dst10a_D, dst10b_D, dst14b_D, dst16_D; wire dst19_D, dst19a_D, dst20_D; - dly150ns ds_dly0(.clk(clk), .reset(reset), + dly150ns ds_dly0(.clk(clk), .reset(rst), .in(dst1), .p(dst1_D)); - dly100ns ds_dly1(.clk(clk), .reset(reset), + dly100ns ds_dly1(.clk(clk), .reset(rst), .in(dst3), .p(dst3_D)); - dly100ns ds_dly2(.clk(clk), .reset(reset), + dly100ns ds_dly2(.clk(clk), .reset(rst), .in(dst4), .p(dst4_D)); - dly100ns ds_dly3(.clk(clk), .reset(reset), + dly100ns ds_dly3(.clk(clk), .reset(rst), .in(dst5a), .p(dst5a_D)); - dly100ns ds_dly4(.clk(clk), .reset(reset), + dly100ns ds_dly4(.clk(clk), .reset(rst), .in(dst6), .p(dst6_D)); - dly100ns ds_dly5(.clk(clk), .reset(reset), + dly100ns ds_dly5(.clk(clk), .reset(rst), .in(dst8), .p(dst8_D)); - dly100ns ds_dly6(.clk(clk), .reset(reset), + dly100ns ds_dly6(.clk(clk), .reset(rst), .in(dst10), .p(dst10_D)); - dly200ns ds_dly7(.clk(clk), .reset(reset), + dly200ns ds_dly7(.clk(clk), .reset(rst), .in(dst10a), .p(dst10a_D)); - dly200ns ds_dly8(.clk(clk), .reset(reset), + dly200ns ds_dly8(.clk(clk), .reset(rst), .in(dst10b), .p(dst10b_D)); - dly100ns ds_dly9(.clk(clk), .reset(reset), + dly100ns ds_dly9(.clk(clk), .reset(rst), .in(dst14b), .p(dst14b_D)); - dly100ns ds_dly10(.clk(clk), .reset(reset), + dly100ns ds_dly10(.clk(clk), .reset(rst), .in(dst16), .p(dst16_D)); - dly50ns ds_dly11(.clk(clk), .reset(reset), + dly50ns ds_dly11(.clk(clk), .reset(rst), .in(dst19), .p(dst19_D)); - dly100ns ds_dly12(.clk(clk), .reset(reset), + dly100ns ds_dly12(.clk(clk), .reset(rst), .in(dst19a), .p(dst19a_D)); - dly100ns ds_dly13(.clk(clk), .reset(reset), + dly100ns ds_dly13(.clk(clk), .reset(rst), .in(dst20), .p(dst20_D)); @@ -2571,37 +2614,37 @@ module apr( wire nrt5a; wire nrt6; - pa nr_pa0(.clk(clk), .reset(reset), + pa nr_pa0(.clk(clk), .reset(rst), .in(fdt1 | fat10 | nrt5a), .p(nrt05)); - pa nr_pa1(.clk(clk), .reset(reset), + pa nr_pa1(.clk(clk), .reset(rst), .in(nrt05_D), .p(nrt0)); - pa nr_pa2(.clk(clk), .reset(reset), + pa nr_pa2(.clk(clk), .reset(rst), .in(nrt0), .p(nrt01)); - pa nr_pa3(.clk(clk), .reset(reset), + pa nr_pa3(.clk(clk), .reset(rst), .in((fmt0b_D | nrt01_D) & ~nr_ar_eq_0_AND_mq1_0), .p(nrt1)); - pa nr_pa4(.clk(clk), .reset(reset), + pa nr_pa4(.clk(clk), .reset(rst), .in((nrt1_D | nrt2_D) & nr_ar9_eq_ar0 & ~ar_eq_fp_half), .p(nrt2)); - pa nr_pa5(.clk(clk), .reset(reset), + pa nr_pa5(.clk(clk), .reset(rst), .in((nrt1_D | nrt2_D) & (~nr_ar9_eq_ar0 | ar_eq_fp_half)), .p(nrt3)); - pa nr_pa6(.clk(clk), .reset(reset), + pa nr_pa6(.clk(clk), .reset(rst), .in(nrt3), .p(nrt31)); - pa nr_pa7(.clk(clk), .reset(reset), + pa nr_pa7(.clk(clk), .reset(rst), .in(nrt31_D & ~nr_round), .p(nrt4)); - pa nr_pa8(.clk(clk), .reset(reset), + pa nr_pa8(.clk(clk), .reset(rst), .in(nrt31_D & nr_round), .p(nrt5)); - pa nr_pa9(.clk(clk), .reset(reset), + pa nr_pa9(.clk(clk), .reset(rst), .in(ar_t3 & nrf1), .p(nrt5a)); - pa nr_pa10(.clk(clk), .reset(reset), + pa nr_pa10(.clk(clk), .reset(rst), .in((fmt0b_D | nrt01_D) & nr_ar_eq_0_AND_mq1_0 | nrt4 | mpt0a & ir[6] | @@ -2609,19 +2652,19 @@ module apr( .p(nrt6)); wire nrt05_D, nrt01_D, nrt1_D, nrt2_D, nrt31_D; - dly100ns nr_dly0(.clk(clk), .reset(reset), + dly100ns nr_dly0(.clk(clk), .reset(rst), .in(nrt05), .p(nrt05_D)); - dly200ns nr_dly1(.clk(clk), .reset(reset), + dly200ns nr_dly1(.clk(clk), .reset(rst), .in(nrt01), .p(nrt01_D)); - dly100ns nr_dly2(.clk(clk), .reset(reset), + dly100ns nr_dly2(.clk(clk), .reset(rst), .in(nrt1), .p(nrt1_D)); - dly150ns nr_dly3(.clk(clk), .reset(reset), + dly150ns nr_dly3(.clk(clk), .reset(rst), .in(nrt2), .p(nrt2_D)); - dly100ns nr_dly4(.clk(clk), .reset(reset), + dly100ns nr_dly4(.clk(clk), .reset(rst), .in(nrt31), .p(nrt31_D)); @@ -2746,17 +2789,17 @@ module apr( wire mi_clr; wire mi_fm_mb1; - pa mi_pa0(.clk(clk), .reset(reset), + pa mi_pa0(.clk(clk), .reset(rst), .in(mc_rs_t1 & key_ex_OR_dep_nxt | mc_wr_rs & ma_eq_mas | mai_rd_rs & ma_eq_mas), .p(mi_clr)); - pa mi_pa1(.clk(clk), .reset(reset), + pa mi_pa1(.clk(clk), .reset(rst), .in(mi_clr_D), .p(mi_fm_mb1)); wire mi_clr_D; - dly100ns mi_dly0(.clk(clk), .reset(reset), + dly100ns mi_dly0(.clk(clk), .reset(rst), .in(mi_clr), .p(mi_clr_D)); @@ -2780,8 +2823,8 @@ module apr( // reg mc_stop; reg mc_stop_sync; reg mc_split_cyc_sync; - // TODO: what is MC DR SPLIT? - wire mc_sw_stop = key_mem_stop | sw_addr_stop; + wire mc_dr_split = 0; // we don't support drums right now + wire mc_sw_stop = key_mem_stop | sw_addr_stop | mc_dr_split; wire mc_rd_rq_pulse; wire mc_wr_rq_pulse; wire mc_rdwr_rq_pulse; @@ -2807,88 +2850,88 @@ module apr( wire mc_membus_fm_mb1; wire mc_mb_membus_enable = mc_rd; - pg mc_pg0(.clk(clk), .reset(reset), + pg mc_pg0(.clk(clk), .reset(rst), .in(membus_addr_ack), .p(mai_addr_ack)); - pg mc_pg1(.clk(clk), .reset(reset), + pg mc_pg1(.clk(clk), .reset(rst), .in(membus_rd_rs), .p(mai_rd_rs)); - pa mc_pa0(.clk(clk), .reset(reset), + pa mc_pa0(.clk(clk), .reset(rst), .in(it1 | at2 | at5 | ft1 | ft4 | ft6 | key_rd | uuo_t2 | mc_split_rd_rq), .p(mc_rd_rq_pulse)); - pa mc_pa1(.clk(clk), .reset(reset), + pa mc_pa1(.clk(clk), .reset(rst), .in(st1 | st5 | st6 | key_wr | mblt_fm_ir1_uuo_t0 | mc_split_wr_rq | blt_t0), .p(mc_wr_rq_pulse)); - pa mc_pa2(.clk(clk), .reset(reset), + pa mc_pa2(.clk(clk), .reset(rst), .in(ft7 & ~mc_split_cyc_sync), .p(mc_rdwr_rq_pulse)); - pa mc_pa3(.clk(clk), .reset(reset), + pa mc_pa3(.clk(clk), .reset(rst), .in(mc_rdwr_rq_pulse | mc_rd_rq_pulse | mc_wr_rq_pulse), .p(mc_rq_pulse)); - pa mc_pa4(.clk(clk), .reset(reset), + pa mc_pa4(.clk(clk), .reset(rst), .in(st2 | iot_t0 | cht8), .p(mc_rdwr_rs_pulse)); - pa mc_pa5(.clk(clk), .reset(reset), + pa mc_pa5(.clk(clk), .reset(rst), .in(ft7 & mc_split_cyc_sync), .p(mc_split_rd_rq)); - pa mc_pa6(.clk(clk), .reset(reset), + pa mc_pa6(.clk(clk), .reset(rst), .in(mc_rdwr_rs_pulse & mc_split_cyc_sync), .p(mc_split_wr_rq)); - pa mc_pa7(.clk(clk), .reset(reset), + pa mc_pa7(.clk(clk), .reset(rst), .in(mc_rd_rq_pulse | mc_rdwr_rq_pulse), .p(mc_mb_clr)); - pa mc_pa8(.clk(clk), .reset(reset), + pa mc_pa8(.clk(clk), .reset(rst), .in(mc_rq_pulse_D3 & mc_rq & ~mc_stop), .p(mc_non_exist_mem)); - pa mc_pa9(.clk(clk), .reset(reset), + pa mc_pa9(.clk(clk), .reset(rst), .in(mc_non_exist_mem & ~sw_mem_disable), .p(mc_non_exist_mem_rst)); - pa mc_pa10(.clk(clk), .reset(reset), + pa mc_pa10(.clk(clk), .reset(rst), .in(mc_non_exist_mem_rst & mc_rd), .p(mc_non_exist_rd)); - pa mc_pa11(.clk(clk), .reset(reset), + pa mc_pa11(.clk(clk), .reset(rst), .in(mc_rq_pulse_D0 & ex_inh_rel | mc_rq_pulse_D1 & pr_rel_AND_ma_ok), .p(mc_rq_set)); - pa mc_pa12(.clk(clk), .reset(reset), + pa mc_pa12(.clk(clk), .reset(rst), .in(mc_rq_pulse_D1 & pr_rel_AND_NOT_ma_ok), .p(mc_illeg_address)); - pa mc_pa13(.clk(clk), .reset(reset), + pa mc_pa13(.clk(clk), .reset(rst), .in(mai_addr_ack | mc_non_exist_mem_rst), .p(mc_addr_ack)); - pa mc_pa14(.clk(clk), .reset(reset), + pa mc_pa14(.clk(clk), .reset(rst), .in(mc_addr_ack & ~mc_rd & mc_wr | mc_rdwr_rs_pulse_D & ~mc_split_cyc_sync | kt1 & key_manual & mc_stop & mc_stop_sync & ~key_mem_cont), .p(mc_wr_rs)); - pa mc_pa15(.clk(clk), .reset(reset), + pa mc_pa15(.clk(clk), .reset(rst), .in(kt1 & key_mem_cont & mc_stop | ~mc_stop & (mc_wr_rs | mai_rd_rs | mc_non_exist_rd)), .p(mc_rs_t0)); - pa mc_pa16(.clk(clk), .reset(reset), .in(mc_rs_t0_D), .p(mc_rs_t1)); + pa mc_pa16(.clk(clk), .reset(rst), .in(mc_rs_t0_D), .p(mc_rs_t1)); - bd mc_bd0(.clk(clk), .reset(reset), .in(mc_wr_rs), .p(membus_wr_rs)); - bd2 mb_bd1(.clk(clk), .reset(reset), .in(mc_wr_rs), .p(mc_membus_fm_mb1)); + bd mc_bd0(.clk(clk), .reset(rst), .in(mc_wr_rs), .p(membus_wr_rs)); + bd2 mb_bd1(.clk(clk), .reset(rst), .in(mc_wr_rs), .p(mc_membus_fm_mb1)); wire mc_rdwr_rs_pulse_D, mc_rs_t0_D; wire mc_rq_pulse_D0, mc_rq_pulse_D1, mc_rq_pulse_D2, mc_rq_pulse_D3; - dly100ns mc_dly0(.clk(clk), .reset(reset), + dly100ns mc_dly0(.clk(clk), .reset(rst), .in(mc_rdwr_rs_pulse), .p(mc_rdwr_rs_pulse_D)); - dly50ns mc_dly1(.clk(clk), .reset(reset), + dly50ns mc_dly1(.clk(clk), .reset(rst), .in(mc_rq_pulse), .p(mc_rq_pulse_D0)); - dly150ns mc_dly2(.clk(clk), .reset(reset), + dly150ns mc_dly2(.clk(clk), .reset(rst), .in(mc_rq_pulse), .p(mc_rq_pulse_D1)); - dly200ns mc_dly3(.clk(clk), .reset(reset), + dly200ns mc_dly3(.clk(clk), .reset(rst), .in(mc_rq_pulse), .p(mc_rq_pulse_D2)); - dly100us mc_dly4(.clk(clk), .reset(reset), .in(mc_rq_pulse), + dly100us mc_dly4(.clk(clk), .reset(rst), .in(mc_rq_pulse), .p(mc_rq_pulse_D3)); - dly50ns mc_dly5(.clk(clk), .reset(reset), .in(mc_rs_t0), + dly50ns mc_dly5(.clk(clk), .reset(rst), .in(mc_rs_t0), .p(mc_rs_t0_D)); assign membus_rq_cyc = mc_rq & (mc_rd | mc_wr); @@ -2920,7 +2963,11 @@ module apr( mc_rq <= 0; if(mc_rq_set) mc_rq <= 1; - if(mc_rq_pulse) + if(mc_rq_pulse +`ifdef FIX_MEMSTOP + | mc_rs_t0 +`endif + ) mc_stop <= 0; if(mc_stop_set) mc_stop <= 1; @@ -2962,30 +3009,30 @@ module apr( wire iot_t4; wire iot_go_P; - pg iot_pg0(.clk(clk), .reset(reset), + pg iot_pg0(.clk(clk), .reset(rst), .in(iot_go & ~iot_reset), .p(iot_go_P)); assign iobus_iob_poweron = sw_power; - pa iot_pa0(.clk(clk), .reset(reset), + pa iot_pa0(.clk(clk), .reset(rst), .in(mr_start | cpa_cono_set & iob[19]), .p(iobus_iob_reset)); - pa iot_pa1(.clk(clk), .reset(reset), + pa iot_pa1(.clk(clk), .reset(rst), .in(iot_t2 & iot_cono), .p(iobus_cono_clear)); - pa iot_pa2(.clk(clk), .reset(reset), + pa iot_pa2(.clk(clk), .reset(rst), .in(iot_t3 & iot_cono), .p(iobus_cono_set)); - pa iot_pa3(.clk(clk), .reset(reset), + pa iot_pa3(.clk(clk), .reset(rst), .in(iot_t2 & iot_datao), .p(iobus_datao_clear)); - pa iot_pa4(.clk(clk), .reset(reset), + pa iot_pa4(.clk(clk), .reset(rst), .in(iot_t3 & iot_datao), .p(iobus_datao_set)); - pa iot_pa5(.clk(clk), .reset(reset), + pa iot_pa5(.clk(clk), .reset(rst), .in(et4 & iot_blk), .p(iot_t0)); - pa iot_pa6(.clk(clk), .reset(reset), + pa iot_pa6(.clk(clk), .reset(rst), .in(mc_rs_t1 & iot_f0a), .p(iot_t0a)); assign iobus_iob_fm_datai = iot_datai & iot_drive; @@ -2993,22 +3040,22 @@ module apr( wire iob_fm_ar1 = iot_outgoing & iot_drive; wire iot_t0a_D; - dly200ns iot_dly0(.clk(clk), .reset(reset), + dly200ns iot_dly0(.clk(clk), .reset(rst), .in(iot_t0a), .p(iot_t0a_D)); - ldly1us iot_dly1(.clk(clk), .reset(reset), + ldly1us iot_dly1(.clk(clk), .reset(rst), .in(iot_go_P), .p(iot_t2), .l(iot_init_setup)); - ldly1_5us iot_dly2(.clk(clk), .reset(reset), + ldly1_5us iot_dly2(.clk(clk), .reset(rst), .in(iot_t2), .p(iot_t3a), .l(iot_final_setup)); - ldly2us iot_dly3(.clk(clk), .reset(reset), + ldly2us iot_dly3(.clk(clk), .reset(rst), .in(iot_t3a), .p(iot_t4), .l(iot_reset)); - ldly1us iot_dly4(.clk(clk), .reset(reset), + ldly1us iot_dly4(.clk(clk), .reset(rst), .in(iot_t2), .p(iot_t3), .l(iot_restart)); @@ -3123,19 +3170,19 @@ module apr( wire [0:35] pi_iob = { 28'b0, pi_active, pio }; - pa pi_pa0(.clk(clk), .reset(reset), + pa pi_pa0(.clk(clk), .reset(rst), .in(it0 | at0), .p(pi_sync)); - pa pi_pa1(.clk(clk), .reset(reset), + pa pi_pa1(.clk(clk), .reset(rst), .in(pi_sync & ~pi_cyc | blt_t4), .p(pir_stb)); - pa pi_pa2(.clk(clk), .reset(reset), + pa pi_pa2(.clk(clk), .reset(rst), .in(mr_start | pi_select & iobus_cono_clear & iob[23]), .p(pi_reset)); wire pi_sync_D; - dly200ns pi_dly0(.clk(clk), .reset(reset), + dly200ns pi_dly0(.clk(clk), .reset(rst), .in(pi_sync), .p(pi_sync_D)); @@ -3207,10 +3254,22 @@ module apr( cpa_pia <= 0; end +`ifdef FIX_USER_IOT + // 20 and 21 seem to be flipped + // IO reset seems to reset it too + if(cpa_cono_set & iob[20] | iobus_iob_reset) + cpa_iot_user <= 0; + if(cpa_cono_set & iob[21]) + cpa_iot_user <= 1; + + if(ar_flag_set & ~ex_user) + cpa_iot_user <= mb[6]; +`else if(cpa_cono_set & iob[21]) cpa_iot_user <= 0; if(cpa_cono_set & iob[20]) cpa_iot_user <= 1; +`endif if(cpa_cono_set & iob[22]) cpa_illeg_op <= 0; diff --git a/verilog/arbiter.v b/verilog/arbiter.v new file mode 100644 index 0000000..5aedb7f --- /dev/null +++ b/verilog/arbiter.v @@ -0,0 +1,85 @@ +module arbiter( + input wire clk, + input wire reset, + + // Slave 0 + input wire [17:0] s0_address, + input wire s0_write, + input wire s0_read, + input wire [35:0] s0_writedata, + output reg [35:0] s0_readdata, + output reg s0_waitrequest, + + // Slave 1 + input wire [17:0] s1_address, + input wire s1_write, + input wire s1_read, + input wire [35:0] s1_writedata, + output reg [35:0] s1_readdata, + output reg s1_waitrequest, + + // Master + output reg [17:0] m_address, + output reg m_write, + output reg m_read, + output reg [35:0] m_writedata, + input wire [35:0] m_readdata, + input wire m_waitrequest +); + + wire cyc0 = s0_read | s0_write; + wire cyc1 = s1_read | s1_write; + reg sel0, sel1; + wire connected = sel0 | sel1; + + always @(posedge clk or negedge reset) begin + if(~reset) begin + sel0 <= 0; + sel1 <= 0; + end else begin + if(sel0 & ~cyc0 | sel1 & ~cyc1) begin + // disconnect if cycle is done + sel0 <= 0; + sel1 <= 0; + end else if(~connected) begin + // connect to master 0 or 1 + if(cyc0) + sel0 <= 1; + else if(cyc1) + sel1 <= 1; + end + end + end + + // Do the connection + always @(*) begin + if(sel0) begin + m_address <= s0_address; + m_write <= s0_write; + m_read <= s0_read; + m_writedata <= s0_writedata; + s0_readdata <= m_readdata; + s0_waitrequest <= m_waitrequest; + s1_readdata <= 0; + s1_waitrequest <= 1; + end else if(sel1) begin + m_address <= s1_address; + m_write <= s1_write; + m_read <= s1_read; + m_writedata <= s1_writedata; + s1_readdata <= m_readdata; + s1_waitrequest <= m_waitrequest; + s0_readdata <= 0; + s0_waitrequest <= 1; + end else begin + m_address <= 0; + m_write <= 0; + m_read <= 0; + m_writedata <= 0; + s0_readdata <= 0; + s0_waitrequest <= 1; + s1_readdata <= 0; + s1_waitrequest <= 1; + end + end +endmodule diff --git a/verilog/clk.v b/verilog/clk.v new file mode 100644 index 0000000..20d0548 --- /dev/null +++ b/verilog/clk.v @@ -0,0 +1,31 @@ +module clock(clk, reset); + output reg clk; + output reg reset; + + initial begin + clk = 0; + reset = 0; + #50 reset = 1; + end + + always +// #5 clk = ~clk; + #10 clk = ~clk; +endmodule + +module edgedet(clk, reset, signal, p); + input wire clk; + input wire reset; + input wire signal; + output wire p; + + reg last; + always @(posedge clk or negedge reset) begin + if(~reset) + last <= 0; + else + last <= signal; + end + + assign p = signal & ~last; +endmodule diff --git a/verilog/core161c.v b/verilog/core161c.v index 414adf0..7a6b9db 100644 --- a/verilog/core161c.v +++ b/verilog/core161c.v @@ -1,4 +1,4 @@ -module core161c( +module core161c_x( input wire clk, input wire reset, input wire power, @@ -51,18 +51,15 @@ module core161c( input wire [0:35] membus_mb_in_p3, output wire membus_addr_ack_p3, output wire membus_rd_rs_p3, - output wire [0:35] membus_mb_out_p3 + output wire [0:35] membus_mb_out_p3, -`ifdef synthesis - , - output reg [17:0] sram_a, - inout reg [15:0] sram_d, - output reg sram_ce, - output reg sram_oe, - output reg sram_we, - output reg sram_lb, - output reg sram_ub -`endif + // 36 bit Avalon Master + output wire [17:0] m_address, + output reg m_write, + output reg m_read, + output wire [35:0] m_writedata, + input wire [35:0] m_readdata, + input wire m_waitrequest ); /* Jumpers */ @@ -88,10 +85,6 @@ module core161c( reg cmc_pse_sync; reg cmc_stop; -`ifdef simulation - reg [0:35] core[0:'o40000]; -`endif - wire cyc_rq_p0 = memsel_p0 == membus_sel_p0 & ~membus_fmc_select_p0 & membus_rq_cyc_p0; wire cyc_rq_p1 = memsel_p1 == membus_sel_p1 & @@ -175,7 +168,6 @@ module core161c( pg cmc_pg2(.clk(clk), .reset(reset), .in(cmpc_p0_rq | cmpc_p1_rq | cmpc_p2_rq | cmpc_p3_rq), .p(cmc_t0)); - pg cmc_pg3(.clk(clk), .reset(reset), .in(| mb_in), .p(mb_pulse_in)); pg cmc_pg4(.clk(clk), .reset(reset), .in(wr_rs), .p(cmpc_rs_strb)); pg cmc_pg5(.clk(clk), .reset(reset), .in(cmc_proc_rs), .p(cmc_proc_rs_P)); pg cmc_pg6(.clk(clk), .reset(reset), .in(cmc_pse_sync & cmc_proc_rs), .p(cmc_wr_rs)); @@ -184,14 +176,19 @@ module core161c( pa cmc_pa0(.clk(clk), .reset(reset), .in(cmc_pwr_clr | cmc_t9a_D), .p(cmc_t12)); pa cmc_pa1(.clk(clk), .reset(reset), .in(cmc_pwr_clr_D), .p(cmc_pwr_start)); pa cmc_pa2(.clk(clk), .reset(reset), - .in(cmc_t9a & ~cmc_stop | cmc_pwr_start | cmc_key_restart), + .in(cmc_t9a & ~cmc_stop | + cmc_pwr_start | + cmc_key_restart), .p(cmc_t10)); pa cmc_pa3(.clk(clk), .reset(reset), .in(cmc_t10_D), .p(cmc_t11)); pa cmc_pa4(.clk(clk), .reset(reset), - .in(cmc_t10 | ~cma_wr_rq & cmc_strb_sa_D1 | cmc_proc_rs_P), + .in(cmc_t10 | + cmc_strb_sa_D1 & ~cma_wr_rq | + cmc_proc_rs_P), .p(cmc_state_clr)); pa cmc_pa5(.clk(clk), .reset(reset), - .in(cmc_t0 | cmc_strb_sa_D2 & cma_wr_rq), + .in(cmc_t0 | + cmc_strb_sa_D2 & cma_wr_rq), .p(cmc_cmb_clr)); pa cmc_pa6(.clk(clk), .reset(reset), .in(cmc_t0_D), .p(cmc_t1)); pa cmc_pa7(.clk(clk), .reset(reset), .in(cmc_t1_D), .p(cmc_t2)); @@ -209,9 +206,9 @@ module core161c( .p(cmc_strb_sa)); // not on schematics - bd cmc_bd0(.clk(clk), .reset(reset), .in(cmc_t1), .p(cmc_addr_ack)); - bd cmc_bd1(.clk(clk), .reset(reset), .in(cmc_strb_sa_D0), .p(cmc_rd_rs)); - bd2 cmc_bd2(.clk(clk), .reset(reset), .in(cmc_strb_sa), .p(mb_pulse_out)); + bd cmc_bd0(.clk(clk), .reset(reset), .in(cmc_t1), .p(cmc_addr_ack)); + bd cmc_bd1(.clk(clk), .reset(reset), .in(cmc_strb_sa_D0), .p(cmc_rd_rs)); + bd cmc_bd2(.clk(clk), .reset(reset), .in(cmc_strb_sa), .p(mb_pulse_out)); wire cmc_pwr_clr_D; wire cmc_t0_D, cmc_t1_D, cmc_t2_D0, cmc_t2_D1, cmc_t4_D; @@ -236,197 +233,106 @@ module core161c( dly250ns cmc_dly14(.clk(clk), .reset(reset), .in(cmc_strb_sa), .p(cmc_strb_sa_D2)); -`ifdef synthesis - reg [2:0] memstate; reg [0:35] sa; // "sense amplifiers" - initial begin - sram_a <= 0; - sram_d <= 16'bz; - sram_ce <= 1; - sram_oe <= 1; - sram_we <= 1; - sram_lb <= 1; - sram_ub <= 1; - memstate <= 0; - end -`endif -`ifdef simulation - wire [0:35] sa = core[cma]; // "sense amplifiers" - always @(posedge reset) begin - cmc_await_rq <= 0; - cmc_last_proc <= 0; - cmc_proc_rs <= 0; - end -`endif + wire [13:0] core_addr = cma[22:35]; - always @(posedge clk) begin - if(cmc_state_clr) begin - cmc_p0_act <= 0; - cmc_p1_act <= 0; - cmc_p2_act <= 0; - cmc_p3_act <= 0; - end - if(cmc_cmb_clr) - cmb <= 0; - if(cmc_strb_sa) - cmb <= cmb | sa; - if(mb_pulse_in) - cmb <= cmb | mb_in; - if(cmpc_rs_strb) - cmc_proc_rs <= 1; - if(cmc_t0) begin + assign m_address = { 4'b0, core_addr }; + assign m_writedata = cmb; + + always @(posedge clk or posedge reset) begin + if(reset) begin cmc_await_rq <= 0; + cmc_last_proc <= 0; cmc_proc_rs <= 0; - cmc_pse_sync <= 0; - cmc_stop <= 0; - cma <= 0; - cma_rd_rq <= 0; - cma_wr_rq <= 0; - // this happens between t0 and t1 */ - if(cmpc_p0_rq) - cmc_p0_act <= 1; - else if(cmpc_p1_rq) - cmc_p1_act <= 1; - else if(cmpc_p2_rq) begin - if(~cmpc_p3_rq | cmc_last_proc) - cmc_p2_act <= 1; - end else if(cmpc_p3_rq) begin - if(~cmpc_p2_rq | ~cmc_last_proc) - cmc_p3_act <= 1; + m_read <= 0; + m_write <= 0; + sa <= 0; + end else begin + if(m_write & ~m_waitrequest) begin + m_write <= 0; + end + if(m_read & ~m_waitrequest) begin + m_read <= 0; + sa <= m_readdata; end - end - if(cmc_t1) begin // this seems to be missing from the schematics - cma <= cma | ma[22:35]; - if(rd_rq) - cma_rd_rq <= 1; - if(wr_rq) - cma_wr_rq <= 1; - end - if(cmc_t2) begin - cmc_rd <= 1; - if(cmc_p2_act) - cmc_last_proc <= 0; - if(cmc_p3_act) - cmc_last_proc <= 1; -`ifdef synthesis - memstate <= 1; // start SRAM read -`endif - end -`ifdef simulation - if(cmc_t4) - /* As a hack zero core here */ - core[cma[22:35]] <= 0; -`endif - if(cmc_t5) begin - cmc_rd <= 0; - cmc_pse_sync <= 1; - end - if(cmc_t7) begin - cmc_inhibit <= 1; - if(sw_single_step) - cmc_stop <= 1; - end - if(cmc_t8) begin - cmc_wr <= 1; -`ifdef synthesis - memstate <= 1; // start SRAM write -`endif - end -`ifdef simulation - if(cmc_t9 & cmc_wr) - /* again a hack. core is written some time after t8. - * (cmc_wr is always set here) */ - core[cma[22:35]] <= core[cma[22:35]] | cmb; -`endif - if(cmc_t11) - cmc_await_rq <= 1; - if(cmc_t12) begin - cmc_rd <= 0; - cmc_inhibit <= 0; - cmc_wr <= 0; - end -`ifdef synthesis - if(cmc_rd) - case(memstate) - 1: begin - sram_a <= (cma << 1) + cma; - sram_ce <= 0; - sram_oe <= 0; - sram_lb <= 0; - sram_ub <= 0; - memstate <= 2; + if(cmc_state_clr) begin + cmc_p0_act <= 0; + cmc_p1_act <= 0; + cmc_p2_act <= 0; + cmc_p3_act <= 0; end - 2: memstate <= 3; - 3: begin - sram_a <= sram_a + 18'b1; - sa[0:11] <= sram_d[15:4]; - memstate <= 4; + cmb <= cmb | mb_in; + if(cmc_cmb_clr) + cmb <= 0; + if(cmc_strb_sa) + cmb <= cmb | sa; + if(cmpc_rs_strb) + cmc_proc_rs <= 1; + + if(cmc_t0) begin + cmc_await_rq <= 0; + cmc_proc_rs <= 0; + cmc_pse_sync <= 0; + cmc_stop <= 0; + cma <= 0; + cma_rd_rq <= 0; + cma_wr_rq <= 0; + + // this happens between t0 and t1 */ + if(cmpc_p0_rq) + cmc_p0_act <= 1; + else if(cmpc_p1_rq) + cmc_p1_act <= 1; + else if(cmpc_p2_rq) begin + if(~cmpc_p3_rq | cmc_last_proc) + cmc_p2_act <= 1; + end else if(cmpc_p3_rq) begin + if(~cmpc_p2_rq | ~cmc_last_proc) + cmc_p3_act <= 1; + end end - 4: memstate <= 5; - 5: begin - sram_a <= sram_a + 18'b1; - sa[12:23] <= sram_d[15:4]; - memstate <= 6; + if(cmc_t1) begin // this seems to be missing from the schematics + cma <= cma | ma[22:35]; + if(rd_rq) + cma_rd_rq <= 1; + if(wr_rq) + cma_wr_rq <= 1; end - 6: memstate <= 7; - 7: begin - sram_a <= 0; - sa[24:35] <= sram_d[15:4]; - sram_ce <= 1; - sram_oe <= 1; - sram_lb <= 1; - sram_ub <= 1; - memstate <= 0; + if(cmc_t2) begin + cmc_rd <= 1; + if(cmc_p2_act) + cmc_last_proc <= 0; + if(cmc_p3_act) + cmc_last_proc <= 1; + + /* start read */ + m_read <= 1; end - endcase - if(cmc_wr) // write - case(memstate) - 1: begin - sram_a <= (cma << 1) + cma; - sram_d <= { cmb[0:11], 4'b0 }; - sram_ce <= 0; - sram_we <= 1; - sram_lb <= 0; - sram_ub <= 0; - memstate <= 2; + // hack: zero memory at cmc_t4 + if(cmc_t5) begin + cmc_rd <= 0; + cmc_pse_sync <= 1; end - 2: begin - sram_we <= 0; - memstate <= 3; + if(cmc_t7) begin + cmc_inhibit <= 1; + if(sw_single_step) + cmc_stop <= 1; end - 3: begin - sram_a <= sram_a + 18'b1; - sram_d <= { cmb[12:23], 4'b0 }; - sram_we <= 1; - memstate <= 4; + if(cmc_t8) begin + cmc_wr <= 1; + /* again a hack. core is written some time after t8. */ + m_write <= 1; end - 4: begin - sram_we <= 0; - memstate <= 5; + if(cmc_t11) + cmc_await_rq <= 1; + if(cmc_t12) begin + cmc_rd <= 0; + cmc_inhibit <= 0; + cmc_wr <= 0; end - 5: begin - sram_a <= sram_a + 18'b1; - sram_d <= { cmb[24:35], 4'b0 }; - sram_we <= 1; - memstate <= 6; - end - 6: begin - sram_we <= 0; - memstate <= 7; - end - 7: begin - sram_a <= 0; - sram_d <= 16'bz; - sram_ce <= 1; - sram_we <= 1; - sram_lb <= 1; - sram_ub <= 1; - memstate <= 0; - end - endcase -`endif + end end endmodule diff --git a/verilog/core164.v b/verilog/core164.v new file mode 100644 index 0000000..f5e7626 --- /dev/null +++ b/verilog/core164.v @@ -0,0 +1,362 @@ +module core164( + input wire clk, + input wire reset, + input wire power, + input wire sw_single_step, + input wire sw_restart, + + input wire membus_wr_rs_p0, + input wire membus_rq_cyc_p0, + input wire membus_rd_rq_p0, + input wire membus_wr_rq_p0, + input wire [21:35] membus_ma_p0, + input wire [18:21] membus_sel_p0, + input wire membus_fmc_select_p0, + input wire [0:35] membus_mb_in_p0, + output wire membus_addr_ack_p0, + output wire membus_rd_rs_p0, + output wire [0:35] membus_mb_out_p0, + + input wire membus_wr_rs_p1, + input wire membus_rq_cyc_p1, + input wire membus_rd_rq_p1, + input wire membus_wr_rq_p1, + input wire [21:35] membus_ma_p1, + input wire [18:21] membus_sel_p1, + input wire membus_fmc_select_p1, + input wire [0:35] membus_mb_in_p1, + output wire membus_addr_ack_p1, + output wire membus_rd_rs_p1, + output wire [0:35] membus_mb_out_p1, + + input wire membus_wr_rs_p2, + input wire membus_rq_cyc_p2, + input wire membus_rd_rq_p2, + input wire membus_wr_rq_p2, + input wire [21:35] membus_ma_p2, + input wire [18:21] membus_sel_p2, + input wire membus_fmc_select_p2, + input wire [0:35] membus_mb_in_p2, + output wire membus_addr_ack_p2, + output wire membus_rd_rs_p2, + output wire [0:35] membus_mb_out_p2, + + input wire membus_wr_rs_p3, + input wire membus_rq_cyc_p3, + input wire membus_rd_rq_p3, + input wire membus_wr_rq_p3, + input wire [21:35] membus_ma_p3, + input wire [18:21] membus_sel_p3, + input wire membus_fmc_select_p3, + input wire [0:35] membus_mb_in_p3, + output wire membus_addr_ack_p3, + output wire membus_rd_rs_p3, + output wire [0:35] membus_mb_out_p3, + + // 36 bit Avalon Master + output wire [17:0] m_address, + output reg m_write, + output reg m_read, + output wire [35:0] m_writedata, + input wire [35:0] m_readdata, + input wire m_waitrequest +); + /* Jumpers */ + parameter memsel_p0 = 4'b0; + parameter memsel_p1 = 4'b0; + parameter memsel_p2 = 4'b0; + parameter memsel_p3 = 4'b0; + + // TODO: SP + wire cmc_sp = 0; + + reg [22:35] cma; + reg cma_rd_rq, cma_wr_rq; + reg [0:35] cmb; + + // TODO: interleave + + wire cmpc_p0_rq = (membus_sel_p0 == memsel_p0) & + ~membus_fmc_select_p0 & + membus_rq_cyc_p0 & + cmc_await_rq; + wire cmpc_p1_rq = (membus_sel_p1 == memsel_p1) & + ~membus_fmc_select_p1 & + membus_rq_cyc_p1 & + cmc_await_rq; + wire cmpc_p2_rq = (membus_sel_p2 == memsel_p2) & + ~membus_fmc_select_p2 & + membus_rq_cyc_p2 & + cmc_await_rq; + wire cmpc_p3_rq = (membus_sel_p3 == memsel_p3) & + ~membus_fmc_select_p3 & + membus_rq_cyc_p3 & + cmc_await_rq; + + wire [22:35] ma_in = + {14{cmc_p0_sel}}&membus_ma_p0 | + {14{cmc_p1_sel}}&membus_ma_p1 | + {14{cmc_p2_sel}}&membus_ma_p2 | + {14{cmc_p3_sel}}&membus_ma_p3; + wire rd_rq_in = + cmc_p0_sel&membus_rd_rq_p0 | + cmc_p1_sel&membus_rd_rq_p1 | + cmc_p2_sel&membus_rd_rq_p2 | + cmc_p3_sel&membus_rd_rq_p3; + wire wr_rq_in = + cmc_p0_sel&membus_wr_rq_p0 | + cmc_p1_sel&membus_wr_rq_p1 | + cmc_p2_sel&membus_wr_rq_p2 | + cmc_p3_sel&membus_wr_rq_p3; + wire [0:35] mb_in = + {36{cmc_p0_sel}}&membus_mb_in_p0 | + {36{cmc_p1_sel}}&membus_mb_in_p1 | + {36{cmc_p2_sel}}&membus_mb_in_p2 | + {36{cmc_p3_sel}}&membus_mb_in_p3; + pa cmpc_pa0(clk, reset, cmc_t1b&cmc_p0_sel, membus_addr_ack_p0); + pa cmpc_pa1(clk, reset, cmc_t1b&cmc_p1_sel, membus_addr_ack_p1); + pa cmpc_pa2(clk, reset, cmc_t1b&cmc_p2_sel, membus_addr_ack_p2); + pa cmpc_pa3(clk, reset, cmc_t1b&cmc_p3_sel, membus_addr_ack_p3); + assign membus_rd_rs_p0 = cmc_rd_rs&cmc_p0_sel; + assign membus_rd_rs_p1 = cmc_rd_rs&cmc_p1_sel; + assign membus_rd_rs_p2 = cmc_rd_rs&cmc_p2_sel; + assign membus_rd_rs_p3 = cmc_rd_rs&cmc_p3_sel; + assign membus_mb_out_p0 = sa & {36{strobe_sense & cmc_p0_sel}}; + assign membus_mb_out_p1 = sa & {36{strobe_sense & cmc_p1_sel}}; + assign membus_mb_out_p2 = sa & {36{strobe_sense & cmc_p2_sel}}; + assign membus_mb_out_p3 = sa & {36{strobe_sense & cmc_p3_sel}}; + wire cmpc_rs_set = membus_wr_rs_p0 & cmc_p0_sel | + membus_wr_rs_p1 & cmc_p1_sel | + membus_wr_rs_p2 & cmc_p2_sel | + membus_wr_rs_p3 & cmc_p3_sel; + + + // TODO: this is all wrong + wire pwr_t1, pwr_t2, pwr_t3; + wire cmc_await_rq_reset, cmc_pwr_clr, cmc_pwr_start; + pg pg0(clk, reset, power, pwr_t1); + // 200ms + ldly1us dly0(clk, reset, pwr_t1, pwr_t2, cmc_await_rq_reset); + // 100μs + ldly1us dly1(clk, reset, pwr_t2, pwr_t3, cmc_pwr_clr); + pa pa0(clk, reset, pwr_t3, cmc_pwr_start); + + + // core control, we don't really have a use for it + reg cmc_read, cmc_write, cmc_inh; + + reg cmc_rq_sync, cmc_cyc_done; + reg cmc_await_rq, cmc_pse_sync, cmc_proc_rs, cmc_stop; + + reg cmc_p0_act, cmc_p1_act, cmc_p2_act, cmc_p3_act; + reg cmc_last_proc; + + // TODO: SP + wire cmc_p0_sel = cmc_p0_act; + wire cmc_p1_sel = cmc_p1_act; + wire cmc_p2_sel = cmc_p2_act; + wire cmc_p3_sel = cmc_p3_act; + + wire cmc_t0, cmc_t1b, cmc_t1a, cmc_t2, cmc_t3; + wire cmc_t4, cmc_t5, cmc_t6, cmc_t6p; + wire cmc_t0_D, cmc_t1b_D, cmc_t1a_D1, cmc_t2_D1, cmc_t2_D2; + wire cmc_t3_D1, cmc_t3_D2; + + wire cmc_restart; + wire cmc_start; + wire cmc_state_clr; + wire cmc_pn_act = cmc_p0_act | cmc_p1_act | cmc_p2_act | cmc_p3_act; + wire cmc_aw_rq_set = cmc_t0_D & ~cmc_pn_act; + wire cmc_rq_sync_set = cmc_t0_D & ~cmc_sp & cmc_pn_act; + wire cmc_jam_cma = cmc_t1b; + wire cmc_cmb_clr; + wire cmc_read_off; + wire cmc_pse_sync_set; + wire strobe_sense; + wire cmc_rd_rs; + wire cmpc_rs_set_D; + wire cmc_proc_rs_pulse; + + pa pa1(clk, reset, + (cmpc_p0_rq | cmpc_p1_rq | cmpc_p2_rq | cmpc_p3_rq), + cmc_t0); + pa pa2(clk, reset, cmc_restart | cmc_pwr_start, cmc_start); + pa pa3(clk, reset, cmc_start | cmc_t3_D1, cmc_t5); + pa pa4(clk, reset, cmc_start | cmc_t3_D2, cmc_t6p); + pa pa5(clk, reset, + cmc_start | cmc_t3 & ~cma_wr_rq | cmc_proc_rs_pulse, + cmc_state_clr); + pa pa6(clk, reset, cmc_rq_sync&cmc_cyc_done, cmc_t1b); + pa pa7(clk, reset, cmc_t1b, cmc_t1b_D); + pa pa8(clk, reset, cmc_t1b_D, cmc_t1a); + pa pa9(clk, reset, + cmc_t1b | cmc_t2_D2&cma_rd_rq&cma_wr_rq, + cmc_cmb_clr); + pa pa10(clk, reset, cmc_t1a_D1, cmc_t2); + pa pa11(clk, reset, cmc_t2_D1&cma_rd_rq, strobe_sense); + pa pa12(clk, reset, strobe_sense, cmc_rd_rs); + + pa pa13(clk, reset, cmc_pse_sync&(cmc_proc_rs | ~cma_wr_rq), cmc_t3); + pa pa14(clk, reset, cmc_proc_rs, cmc_proc_rs_pulse); + // probably wrong + pa pa15(clk, reset, sw_restart, cmc_restart); + + + dly250ns dly2(clk, reset, cmc_t6p, cmc_t6); + dly100ns dly3(clk, reset, cmc_t0, cmc_t0_D); + dly250ns dly4(clk, reset, cmc_t1a, cmc_t1a_D1); + dly450ns dly5(clk, reset, cmc_t1a, cmc_read_off); + dly550ns dly6(clk, reset, cmc_t1a, cmc_pse_sync_set); + // Variable 35-100ns + dly70ns dly7(clk, reset, cmc_t2, cmc_t2_D1); + dly300ns dly8(clk, reset, cmc_t2, cmc_t2_D2); + dly50ns dly9(clk, reset, cmc_t3, cmc_t4); + dly550ns dly10(clk, reset, cmc_t3, cmc_t3_D1); + dly750ns dly11(clk, reset, cmc_t3, cmc_t3_D2); + dly50ns dly12(clk, reset, cmpc_rs_set, cmpc_rs_set_D); + + + reg [0:35] sa; // "sense amplifiers" + wire [13:0] core_addr = cma[22:35]; + + assign m_address = { 4'b0, core_addr }; + assign m_writedata = cmb; + + + always @(posedge clk or posedge reset) begin + if(reset) begin + m_read <= 0; + m_write <= 0; + sa <= 0; + + // value doesn't matter + cmc_last_proc <= 0; + // these should probably be reset but aren't + cmc_proc_rs <= 0; + cmc_pse_sync <= 0; + end else begin + if(m_write & ~m_waitrequest) begin + m_write <= 0; + end + if(m_read & ~m_waitrequest) begin + m_read <= 0; + sa <= m_readdata; + end + + + if(cmc_state_clr) begin + cmc_p0_act <= 0; + cmc_p1_act <= 0; + cmc_p2_act <= 0; + cmc_p3_act <= 0; + end + if(cmpc_p0_rq | cmpc_p1_rq | cmpc_p2_rq | cmpc_p3_rq) begin + if(cmpc_p0_rq) begin + cmc_p0_act <= 1; + cmc_p1_act <= 0; + cmc_p2_act <= 0; + cmc_p3_act <= 0; + end else if(cmpc_p1_rq) begin + cmc_p0_act <= 0; + cmc_p1_act <= 1; + cmc_p2_act <= 0; + cmc_p3_act <= 0; + end else if(cmpc_p2_rq & cmpc_p3_rq) begin + cmc_p0_act <= 0; + cmc_p1_act <= 0; + cmc_p2_act <= cmc_last_proc; + cmc_p3_act <= ~cmc_last_proc; + cmc_last_proc <= ~cmc_last_proc; + end else if(cmpc_p2_rq) begin + cmc_p0_act <= 0; + cmc_p1_act <= 0; + cmc_p2_act <= 1; + cmc_p3_act <= 0; + end else if(cmpc_p3_rq) begin + cmc_p0_act <= 0; + cmc_p1_act <= 0; + cmc_p2_act <= 0; + cmc_p3_act <= 1; + end + end + if(cmc_t2) begin + if(cmc_p2_act) + cmc_last_proc <= 0; + if(cmc_p3_act) + cmc_last_proc <= 1; + end + + if(cmc_t0 | cmc_await_rq_reset) + cmc_await_rq <= 0; + if(cmc_t5 | cmc_aw_rq_set) + cmc_await_rq <= 1; + + if(cmc_start | cmc_pwr_clr) + cmc_rq_sync <= 0; + if(cmc_rq_sync_set | cmc_t0 & cmc_sp) + cmc_rq_sync <= 1; + + if(cmc_pwr_clr) + cmc_cyc_done <= 0; + if(cmc_t6 & ~cmc_stop) + cmc_cyc_done <= 1; + + if(cmc_t1b) begin + cmc_pse_sync <= 0; + cmc_proc_rs <= 0; + cmc_stop <= 0; + end + + // actually through another PA + if(cmc_pse_sync_set) + cmc_pse_sync <= 1; + + if(cmpc_rs_set_D) + cmc_proc_rs <= 1; + + if(cmc_start) + cmc_stop <= 0; + if(cmc_t2 & sw_single_step) + cmc_stop <= 1; + + if(cmc_t2) begin + cmc_rq_sync <= 0; + cmc_cyc_done <= 0; + end + + + if(cmc_jam_cma) begin + cma <= ma_in; + cma_rd_rq <= rd_rq_in; + cma_wr_rq <= wr_rq_in; + end + + cmb <= cmb | mb_in; + if(cmc_cmb_clr) + cmb <= 0; + if(strobe_sense) + cmb <= cmb | sa; + + /* Core */ + if(cmc_pwr_clr | cmc_t5) begin + cmc_read <= 0; + cmc_write <= 0; + cmc_inh <= 0; + end + if(cmc_t1a) begin + cmc_read <= 1; + m_read <= 1; + cmc_write <= 0; + end + if(cmc_read_off) + cmc_read <= 0; + if(cmc_t3) + cmc_inh <= 1; + if(cmc_t4) begin + cmc_write <= 1; + m_write <= 1; + cmc_read <= 0; + end + end + end +endmodule diff --git a/verilog/core32k.v b/verilog/core32k.v new file mode 100644 index 0000000..1196b1b --- /dev/null +++ b/verilog/core32k.v @@ -0,0 +1,362 @@ +module core32k( + input wire clk, + input wire reset, + input wire power, + input wire sw_single_step, + input wire sw_restart, + + input wire membus_wr_rs_p0, + input wire membus_rq_cyc_p0, + input wire membus_rd_rq_p0, + input wire membus_wr_rq_p0, + input wire [21:35] membus_ma_p0, + input wire [18:21] membus_sel_p0, + input wire membus_fmc_select_p0, + input wire [0:35] membus_mb_in_p0, + output wire membus_addr_ack_p0, + output wire membus_rd_rs_p0, + output wire [0:35] membus_mb_out_p0, + + input wire membus_wr_rs_p1, + input wire membus_rq_cyc_p1, + input wire membus_rd_rq_p1, + input wire membus_wr_rq_p1, + input wire [21:35] membus_ma_p1, + input wire [18:21] membus_sel_p1, + input wire membus_fmc_select_p1, + input wire [0:35] membus_mb_in_p1, + output wire membus_addr_ack_p1, + output wire membus_rd_rs_p1, + output wire [0:35] membus_mb_out_p1, + + input wire membus_wr_rs_p2, + input wire membus_rq_cyc_p2, + input wire membus_rd_rq_p2, + input wire membus_wr_rq_p2, + input wire [21:35] membus_ma_p2, + input wire [18:21] membus_sel_p2, + input wire membus_fmc_select_p2, + input wire [0:35] membus_mb_in_p2, + output wire membus_addr_ack_p2, + output wire membus_rd_rs_p2, + output wire [0:35] membus_mb_out_p2, + + input wire membus_wr_rs_p3, + input wire membus_rq_cyc_p3, + input wire membus_rd_rq_p3, + input wire membus_wr_rq_p3, + input wire [21:35] membus_ma_p3, + input wire [18:21] membus_sel_p3, + input wire membus_fmc_select_p3, + input wire [0:35] membus_mb_in_p3, + output wire membus_addr_ack_p3, + output wire membus_rd_rs_p3, + output wire [0:35] membus_mb_out_p3, + + // 36 bit Avalon Master + output wire [17:0] m_address, + output reg m_write, + output reg m_read, + output wire [35:0] m_writedata, + input wire [35:0] m_readdata, + input wire m_waitrequest +); + /* Jumpers */ + parameter [3:0] memsel_p0 = 4'b0; + parameter [3:0] memsel_p1 = 4'b0; + parameter [3:0] memsel_p2 = 4'b0; + parameter [3:0] memsel_p3 = 4'b0; + + // TODO: SP + wire cmc_sp = 0; + + reg [21:35] cma; + reg cma_rd_rq, cma_wr_rq; + reg [0:35] cmb; + + // TODO: interleave + + wire cmpc_p0_rq = (membus_sel_p0[18:20] == memsel_p0[3:1]) & + ~membus_fmc_select_p0 & + membus_rq_cyc_p0 & + cmc_await_rq; + wire cmpc_p1_rq = (membus_sel_p1[18:20] == memsel_p1[3:1]) & + ~membus_fmc_select_p1 & + membus_rq_cyc_p1 & + cmc_await_rq; + wire cmpc_p2_rq = (membus_sel_p2[18:20] == memsel_p2[3:1]) & + ~membus_fmc_select_p2 & + membus_rq_cyc_p2 & + cmc_await_rq; + wire cmpc_p3_rq = (membus_sel_p3[18:20] == memsel_p3[3:1]) & + ~membus_fmc_select_p3 & + membus_rq_cyc_p3 & + cmc_await_rq; + + wire [21:35] ma_in = + {15{cmc_p0_sel}}&membus_ma_p0 | + {15{cmc_p1_sel}}&membus_ma_p1 | + {15{cmc_p2_sel}}&membus_ma_p2 | + {15{cmc_p3_sel}}&membus_ma_p3; + wire rd_rq_in = + cmc_p0_sel&membus_rd_rq_p0 | + cmc_p1_sel&membus_rd_rq_p1 | + cmc_p2_sel&membus_rd_rq_p2 | + cmc_p3_sel&membus_rd_rq_p3; + wire wr_rq_in = + cmc_p0_sel&membus_wr_rq_p0 | + cmc_p1_sel&membus_wr_rq_p1 | + cmc_p2_sel&membus_wr_rq_p2 | + cmc_p3_sel&membus_wr_rq_p3; + wire [0:35] mb_in = + {36{cmc_p0_sel}}&membus_mb_in_p0 | + {36{cmc_p1_sel}}&membus_mb_in_p1 | + {36{cmc_p2_sel}}&membus_mb_in_p2 | + {36{cmc_p3_sel}}&membus_mb_in_p3; + pa cmpc_pa0(clk, reset, cmc_t1b&cmc_p0_sel, membus_addr_ack_p0); + pa cmpc_pa1(clk, reset, cmc_t1b&cmc_p1_sel, membus_addr_ack_p1); + pa cmpc_pa2(clk, reset, cmc_t1b&cmc_p2_sel, membus_addr_ack_p2); + pa cmpc_pa3(clk, reset, cmc_t1b&cmc_p3_sel, membus_addr_ack_p3); + assign membus_rd_rs_p0 = cmc_rd_rs&cmc_p0_sel; + assign membus_rd_rs_p1 = cmc_rd_rs&cmc_p1_sel; + assign membus_rd_rs_p2 = cmc_rd_rs&cmc_p2_sel; + assign membus_rd_rs_p3 = cmc_rd_rs&cmc_p3_sel; + assign membus_mb_out_p0 = sa & {36{strobe_sense & cmc_p0_sel}}; + assign membus_mb_out_p1 = sa & {36{strobe_sense & cmc_p1_sel}}; + assign membus_mb_out_p2 = sa & {36{strobe_sense & cmc_p2_sel}}; + assign membus_mb_out_p3 = sa & {36{strobe_sense & cmc_p3_sel}}; + wire cmpc_rs_set = membus_wr_rs_p0 & cmc_p0_sel | + membus_wr_rs_p1 & cmc_p1_sel | + membus_wr_rs_p2 & cmc_p2_sel | + membus_wr_rs_p3 & cmc_p3_sel; + + + // TODO: this is all wrong + wire pwr_t1, pwr_t2, pwr_t3; + wire cmc_await_rq_reset, cmc_pwr_clr, cmc_pwr_start; + pg pg0(clk, reset, power, pwr_t1); + // 200ms + ldly1us dly0(clk, reset, pwr_t1, pwr_t2, cmc_await_rq_reset); + // 100μs + ldly1us dly1(clk, reset, pwr_t2, pwr_t3, cmc_pwr_clr); + pa pa0(clk, reset, pwr_t3, cmc_pwr_start); + + + // core control, we don't really have a use for it + reg cmc_read, cmc_write, cmc_inh; + + reg cmc_rq_sync, cmc_cyc_done; + reg cmc_await_rq, cmc_pse_sync, cmc_proc_rs, cmc_stop; + + reg cmc_p0_act, cmc_p1_act, cmc_p2_act, cmc_p3_act; + reg cmc_last_proc; + + // TODO: SP + wire cmc_p0_sel = cmc_p0_act; + wire cmc_p1_sel = cmc_p1_act; + wire cmc_p2_sel = cmc_p2_act; + wire cmc_p3_sel = cmc_p3_act; + + wire cmc_t0, cmc_t1b, cmc_t1a, cmc_t2, cmc_t3; + wire cmc_t4, cmc_t5, cmc_t6, cmc_t6p; + wire cmc_t0_D, cmc_t1b_D, cmc_t1a_D1, cmc_t2_D1, cmc_t2_D2; + wire cmc_t3_D1, cmc_t3_D2; + + wire cmc_restart; + wire cmc_start; + wire cmc_state_clr; + wire cmc_pn_act = cmc_p0_act | cmc_p1_act | cmc_p2_act | cmc_p3_act; + wire cmc_aw_rq_set = cmc_t0_D & ~cmc_pn_act; + wire cmc_rq_sync_set = cmc_t0_D & ~cmc_sp & cmc_pn_act; + wire cmc_jam_cma = cmc_t1b; + wire cmc_cmb_clr; + wire cmc_read_off; + wire cmc_pse_sync_set; + wire strobe_sense; + wire cmc_rd_rs; + wire cmpc_rs_set_D; + wire cmc_proc_rs_pulse; + + pa pa1(clk, reset, + (cmpc_p0_rq | cmpc_p1_rq | cmpc_p2_rq | cmpc_p3_rq), + cmc_t0); + pa pa2(clk, reset, cmc_restart | cmc_pwr_start, cmc_start); + pa pa3(clk, reset, cmc_start | cmc_t3_D1, cmc_t5); + pa pa4(clk, reset, cmc_start | cmc_t3_D2, cmc_t6p); + pa pa5(clk, reset, + cmc_start | cmc_t3 & ~cma_wr_rq | cmc_proc_rs_pulse, + cmc_state_clr); + pa pa6(clk, reset, cmc_rq_sync&cmc_cyc_done, cmc_t1b); + pa pa7(clk, reset, cmc_t1b, cmc_t1b_D); + pa pa8(clk, reset, cmc_t1b_D, cmc_t1a); + pa pa9(clk, reset, + cmc_t1b | cmc_t2_D2&cma_rd_rq&cma_wr_rq, + cmc_cmb_clr); + pa pa10(clk, reset, cmc_t1a_D1, cmc_t2); + pa pa11(clk, reset, cmc_t2_D1&cma_rd_rq, strobe_sense); + pa pa12(clk, reset, strobe_sense, cmc_rd_rs); + + pa pa13(clk, reset, cmc_pse_sync&(cmc_proc_rs | ~cma_wr_rq), cmc_t3); + pa pa14(clk, reset, cmc_proc_rs, cmc_proc_rs_pulse); + // probably wrong + pa pa15(clk, reset, sw_restart, cmc_restart); + + + dly250ns dly2(clk, reset, cmc_t6p, cmc_t6); + dly100ns dly3(clk, reset, cmc_t0, cmc_t0_D); + dly250ns dly4(clk, reset, cmc_t1a, cmc_t1a_D1); + dly450ns dly5(clk, reset, cmc_t1a, cmc_read_off); + dly550ns dly6(clk, reset, cmc_t1a, cmc_pse_sync_set); + // Variable 35-100ns + dly70ns dly7(clk, reset, cmc_t2, cmc_t2_D1); + dly300ns dly8(clk, reset, cmc_t2, cmc_t2_D2); + dly50ns dly9(clk, reset, cmc_t3, cmc_t4); + dly550ns dly10(clk, reset, cmc_t3, cmc_t3_D1); + dly750ns dly11(clk, reset, cmc_t3, cmc_t3_D2); + dly50ns dly12(clk, reset, cmpc_rs_set, cmpc_rs_set_D); + + + reg [0:35] sa; // "sense amplifiers" + wire [14:0] core_addr = cma[21:35]; + + assign m_address = { 3'b0, core_addr }; + assign m_writedata = cmb; + + + always @(posedge clk or posedge reset) begin + if(reset) begin + m_read <= 0; + m_write <= 0; + sa <= 0; + + // value doesn't matter + cmc_last_proc <= 0; + // these should probably be reset but aren't + cmc_proc_rs <= 0; + cmc_pse_sync <= 0; + end else begin + if(m_write & ~m_waitrequest) begin + m_write <= 0; + end + if(m_read & ~m_waitrequest) begin + m_read <= 0; + sa <= m_readdata; + end + + + if(cmc_state_clr) begin + cmc_p0_act <= 0; + cmc_p1_act <= 0; + cmc_p2_act <= 0; + cmc_p3_act <= 0; + end + if(cmpc_p0_rq | cmpc_p1_rq | cmpc_p2_rq | cmpc_p3_rq) begin + if(cmpc_p0_rq) begin + cmc_p0_act <= 1; + cmc_p1_act <= 0; + cmc_p2_act <= 0; + cmc_p3_act <= 0; + end else if(cmpc_p1_rq) begin + cmc_p0_act <= 0; + cmc_p1_act <= 1; + cmc_p2_act <= 0; + cmc_p3_act <= 0; + end else if(cmpc_p2_rq & cmpc_p3_rq) begin + cmc_p0_act <= 0; + cmc_p1_act <= 0; + cmc_p2_act <= cmc_last_proc; + cmc_p3_act <= ~cmc_last_proc; + cmc_last_proc <= ~cmc_last_proc; + end else if(cmpc_p2_rq) begin + cmc_p0_act <= 0; + cmc_p1_act <= 0; + cmc_p2_act <= 1; + cmc_p3_act <= 0; + end else if(cmpc_p3_rq) begin + cmc_p0_act <= 0; + cmc_p1_act <= 0; + cmc_p2_act <= 0; + cmc_p3_act <= 1; + end + end + if(cmc_t2) begin + if(cmc_p2_act) + cmc_last_proc <= 0; + if(cmc_p3_act) + cmc_last_proc <= 1; + end + + if(cmc_t0 | cmc_await_rq_reset) + cmc_await_rq <= 0; + if(cmc_t5 | cmc_aw_rq_set) + cmc_await_rq <= 1; + + if(cmc_start | cmc_pwr_clr) + cmc_rq_sync <= 0; + if(cmc_rq_sync_set | cmc_t0 & cmc_sp) + cmc_rq_sync <= 1; + + if(cmc_pwr_clr) + cmc_cyc_done <= 0; + if(cmc_t6 & ~cmc_stop) + cmc_cyc_done <= 1; + + if(cmc_t1b) begin + cmc_pse_sync <= 0; + cmc_proc_rs <= 0; + cmc_stop <= 0; + end + + // actually through another PA + if(cmc_pse_sync_set) + cmc_pse_sync <= 1; + + if(cmpc_rs_set_D) + cmc_proc_rs <= 1; + + if(cmc_start) + cmc_stop <= 0; + if(cmc_t2 & sw_single_step) + cmc_stop <= 1; + + if(cmc_t2) begin + cmc_rq_sync <= 0; + cmc_cyc_done <= 0; + end + + + if(cmc_jam_cma) begin + cma <= ma_in; + cma_rd_rq <= rd_rq_in; + cma_wr_rq <= wr_rq_in; + end + + cmb <= cmb | mb_in; + if(cmc_cmb_clr) + cmb <= 0; + if(strobe_sense) + cmb <= cmb | sa; + + /* Core */ + if(cmc_pwr_clr | cmc_t5) begin + cmc_read <= 0; + cmc_write <= 0; + cmc_inh <= 0; + end + if(cmc_t1a) begin + cmc_read <= 1; + m_read <= 1; + cmc_write <= 0; + end + if(cmc_read_off) + cmc_read <= 0; + if(cmc_t3) + cmc_inh <= 1; + if(cmc_t4) begin + cmc_write <= 1; + m_write <= 1; + cmc_read <= 0; + end + end + end +endmodule diff --git a/verilog/core64k.v b/verilog/core64k.v new file mode 100644 index 0000000..527e0b0 --- /dev/null +++ b/verilog/core64k.v @@ -0,0 +1,367 @@ +module core64k( + input wire clk, + input wire reset, + input wire power, + input wire sw_single_step, + input wire sw_restart, + + input wire membus_wr_rs_p0, + input wire membus_rq_cyc_p0, + input wire membus_rd_rq_p0, + input wire membus_wr_rq_p0, + input wire [21:35] membus_ma_p0, + input wire [18:21] membus_sel_p0, + input wire membus_fmc_select_p0, + input wire [0:35] membus_mb_in_p0, + output wire membus_addr_ack_p0, + output wire membus_rd_rs_p0, + output wire [0:35] membus_mb_out_p0, + + input wire membus_wr_rs_p1, + input wire membus_rq_cyc_p1, + input wire membus_rd_rq_p1, + input wire membus_wr_rq_p1, + input wire [21:35] membus_ma_p1, + input wire [18:21] membus_sel_p1, + input wire membus_fmc_select_p1, + input wire [0:35] membus_mb_in_p1, + output wire membus_addr_ack_p1, + output wire membus_rd_rs_p1, + output wire [0:35] membus_mb_out_p1, + + input wire membus_wr_rs_p2, + input wire membus_rq_cyc_p2, + input wire membus_rd_rq_p2, + input wire membus_wr_rq_p2, + input wire [21:35] membus_ma_p2, + input wire [18:21] membus_sel_p2, + input wire membus_fmc_select_p2, + input wire [0:35] membus_mb_in_p2, + output wire membus_addr_ack_p2, + output wire membus_rd_rs_p2, + output wire [0:35] membus_mb_out_p2, + + input wire membus_wr_rs_p3, + input wire membus_rq_cyc_p3, + input wire membus_rd_rq_p3, + input wire membus_wr_rq_p3, + input wire [21:35] membus_ma_p3, + input wire [18:21] membus_sel_p3, + input wire membus_fmc_select_p3, + input wire [0:35] membus_mb_in_p3, + output wire membus_addr_ack_p3, + output wire membus_rd_rs_p3, + output wire [0:35] membus_mb_out_p3, + + // 36 bit Avalon Master + output wire [17:0] m_address, + output reg m_write, + output reg m_read, + output wire [35:0] m_writedata, + input wire [35:0] m_readdata, + input wire m_waitrequest +); + /* Jumpers */ + parameter [3:0] memsel_p0 = 4'b0; + parameter [3:0] memsel_p1 = 4'b0; + parameter [3:0] memsel_p2 = 4'b0; + parameter [3:0] memsel_p3 = 4'b0; + + // TODO: SP + wire cmc_sp = 0; + + reg [20:35] cma; + reg cma_rd_rq, cma_wr_rq; + reg [0:35] cmb; + + // TODO: interleave + + wire cmpc_p0_rq = (membus_sel_p0[18:19] == memsel_p0[3:2]) & + ~membus_fmc_select_p0 & + membus_rq_cyc_p0 & + cmc_await_rq; + wire cmpc_p1_rq = (membus_sel_p1[18:19] == memsel_p1[3:2]) & + ~membus_fmc_select_p1 & + membus_rq_cyc_p1 & + cmc_await_rq; + wire cmpc_p2_rq = (membus_sel_p2[18:19] == memsel_p2[3:2]) & + ~membus_fmc_select_p2 & + membus_rq_cyc_p2 & + cmc_await_rq; + wire cmpc_p3_rq = (membus_sel_p3[18:19] == memsel_p3[3:2]) & + ~membus_fmc_select_p3 & + membus_rq_cyc_p3 & + cmc_await_rq; + + wire ma_p0 = { membus_sel_p0[18:21], membus_ma_p0[22:35] }; + wire ma_p1 = { membus_sel_p1[18:21], membus_ma_p1[22:35] }; + wire ma_p2 = { membus_sel_p2[18:21], membus_ma_p2[22:35] }; + wire ma_p3 = { membus_sel_p3[18:21], membus_ma_p3[22:35] }; + + wire [20:35] ma_in = + {16{cmc_p0_sel}}&ma_p0 | + {16{cmc_p1_sel}}&ma_p1 | + {16{cmc_p2_sel}}&ma_p2 | + {16{cmc_p3_sel}}&ma_p3; + wire rd_rq_in = + cmc_p0_sel&membus_rd_rq_p0 | + cmc_p1_sel&membus_rd_rq_p1 | + cmc_p2_sel&membus_rd_rq_p2 | + cmc_p3_sel&membus_rd_rq_p3; + wire wr_rq_in = + cmc_p0_sel&membus_wr_rq_p0 | + cmc_p1_sel&membus_wr_rq_p1 | + cmc_p2_sel&membus_wr_rq_p2 | + cmc_p3_sel&membus_wr_rq_p3; + wire [0:35] mb_in = + {36{cmc_p0_sel}}&membus_mb_in_p0 | + {36{cmc_p1_sel}}&membus_mb_in_p1 | + {36{cmc_p2_sel}}&membus_mb_in_p2 | + {36{cmc_p3_sel}}&membus_mb_in_p3; + pa cmpc_pa0(clk, reset, cmc_t1b&cmc_p0_sel, membus_addr_ack_p0); + pa cmpc_pa1(clk, reset, cmc_t1b&cmc_p1_sel, membus_addr_ack_p1); + pa cmpc_pa2(clk, reset, cmc_t1b&cmc_p2_sel, membus_addr_ack_p2); + pa cmpc_pa3(clk, reset, cmc_t1b&cmc_p3_sel, membus_addr_ack_p3); + assign membus_rd_rs_p0 = cmc_rd_rs&cmc_p0_sel; + assign membus_rd_rs_p1 = cmc_rd_rs&cmc_p1_sel; + assign membus_rd_rs_p2 = cmc_rd_rs&cmc_p2_sel; + assign membus_rd_rs_p3 = cmc_rd_rs&cmc_p3_sel; + assign membus_mb_out_p0 = sa & {36{strobe_sense & cmc_p0_sel}}; + assign membus_mb_out_p1 = sa & {36{strobe_sense & cmc_p1_sel}}; + assign membus_mb_out_p2 = sa & {36{strobe_sense & cmc_p2_sel}}; + assign membus_mb_out_p3 = sa & {36{strobe_sense & cmc_p3_sel}}; + wire cmpc_rs_set = membus_wr_rs_p0 & cmc_p0_sel | + membus_wr_rs_p1 & cmc_p1_sel | + membus_wr_rs_p2 & cmc_p2_sel | + membus_wr_rs_p3 & cmc_p3_sel; + + + // TODO: this is all wrong + wire pwr_t1, pwr_t2, pwr_t3; + wire cmc_await_rq_reset, cmc_pwr_clr, cmc_pwr_start; + pg pg0(clk, reset, power, pwr_t1); + // 200ms + ldly1us dly0(clk, reset, pwr_t1, pwr_t2, cmc_await_rq_reset); + // 100μs + ldly1us dly1(clk, reset, pwr_t2, pwr_t3, cmc_pwr_clr); + pa pa0(clk, reset, pwr_t3, cmc_pwr_start); + + + // core control, we don't really have a use for it + reg cmc_read, cmc_write, cmc_inh; + + reg cmc_rq_sync, cmc_cyc_done; + reg cmc_await_rq, cmc_pse_sync, cmc_proc_rs, cmc_stop; + + reg cmc_p0_act, cmc_p1_act, cmc_p2_act, cmc_p3_act; + reg cmc_last_proc; + + // TODO: SP + wire cmc_p0_sel = cmc_p0_act; + wire cmc_p1_sel = cmc_p1_act; + wire cmc_p2_sel = cmc_p2_act; + wire cmc_p3_sel = cmc_p3_act; + + wire cmc_t0, cmc_t1b, cmc_t1a, cmc_t2, cmc_t3; + wire cmc_t4, cmc_t5, cmc_t6, cmc_t6p; + wire cmc_t0_D, cmc_t1b_D, cmc_t1a_D1, cmc_t2_D1, cmc_t2_D2; + wire cmc_t3_D1, cmc_t3_D2; + + wire cmc_restart; + wire cmc_start; + wire cmc_state_clr; + wire cmc_pn_act = cmc_p0_act | cmc_p1_act | cmc_p2_act | cmc_p3_act; + wire cmc_aw_rq_set = cmc_t0_D & ~cmc_pn_act; + wire cmc_rq_sync_set = cmc_t0_D & ~cmc_sp & cmc_pn_act; + wire cmc_jam_cma = cmc_t1b; + wire cmc_cmb_clr; + wire cmc_read_off; + wire cmc_pse_sync_set; + wire strobe_sense; + wire cmc_rd_rs; + wire cmpc_rs_set_D; + wire cmc_proc_rs_pulse; + + pa pa1(clk, reset, + (cmpc_p0_rq | cmpc_p1_rq | cmpc_p2_rq | cmpc_p3_rq), + cmc_t0); + pa pa2(clk, reset, cmc_restart | cmc_pwr_start, cmc_start); + pa pa3(clk, reset, cmc_start | cmc_t3_D1, cmc_t5); + pa pa4(clk, reset, cmc_start | cmc_t3_D2, cmc_t6p); + pa pa5(clk, reset, + cmc_start | cmc_t3 & ~cma_wr_rq | cmc_proc_rs_pulse, + cmc_state_clr); + pa pa6(clk, reset, cmc_rq_sync&cmc_cyc_done, cmc_t1b); + pa pa7(clk, reset, cmc_t1b, cmc_t1b_D); + pa pa8(clk, reset, cmc_t1b_D, cmc_t1a); + pa pa9(clk, reset, + cmc_t1b | cmc_t2_D2&cma_rd_rq&cma_wr_rq, + cmc_cmb_clr); + pa pa10(clk, reset, cmc_t1a_D1, cmc_t2); + pa pa11(clk, reset, cmc_t2_D1&cma_rd_rq, strobe_sense); + pa pa12(clk, reset, strobe_sense, cmc_rd_rs); + + pa pa13(clk, reset, cmc_pse_sync&(cmc_proc_rs | ~cma_wr_rq), cmc_t3); + pa pa14(clk, reset, cmc_proc_rs, cmc_proc_rs_pulse); + // probably wrong + pa pa15(clk, reset, sw_restart, cmc_restart); + + + dly250ns dly2(clk, reset, cmc_t6p, cmc_t6); + dly100ns dly3(clk, reset, cmc_t0, cmc_t0_D); + dly250ns dly4(clk, reset, cmc_t1a, cmc_t1a_D1); + dly450ns dly5(clk, reset, cmc_t1a, cmc_read_off); + dly550ns dly6(clk, reset, cmc_t1a, cmc_pse_sync_set); + // Variable 35-100ns + dly70ns dly7(clk, reset, cmc_t2, cmc_t2_D1); + dly300ns dly8(clk, reset, cmc_t2, cmc_t2_D2); + dly50ns dly9(clk, reset, cmc_t3, cmc_t4); + dly550ns dly10(clk, reset, cmc_t3, cmc_t3_D1); + dly750ns dly11(clk, reset, cmc_t3, cmc_t3_D2); + dly50ns dly12(clk, reset, cmpc_rs_set, cmpc_rs_set_D); + + + reg [0:35] sa; // "sense amplifiers" + wire [15:0] core_addr = cma[20:35]; + + assign m_address = { 2'b0, core_addr }; + assign m_writedata = cmb; + + + always @(posedge clk or posedge reset) begin + if(reset) begin + m_read <= 0; + m_write <= 0; + sa <= 0; + + // value doesn't matter + cmc_last_proc <= 0; + // these should probably be reset but aren't + cmc_proc_rs <= 0; + cmc_pse_sync <= 0; + end else begin + if(m_write & ~m_waitrequest) begin + m_write <= 0; + end + if(m_read & ~m_waitrequest) begin + m_read <= 0; + sa <= m_readdata; + end + + + if(cmc_state_clr) begin + cmc_p0_act <= 0; + cmc_p1_act <= 0; + cmc_p2_act <= 0; + cmc_p3_act <= 0; + end + if(cmpc_p0_rq | cmpc_p1_rq | cmpc_p2_rq | cmpc_p3_rq) begin + if(cmpc_p0_rq) begin + cmc_p0_act <= 1; + cmc_p1_act <= 0; + cmc_p2_act <= 0; + cmc_p3_act <= 0; + end else if(cmpc_p1_rq) begin + cmc_p0_act <= 0; + cmc_p1_act <= 1; + cmc_p2_act <= 0; + cmc_p3_act <= 0; + end else if(cmpc_p2_rq & cmpc_p3_rq) begin + cmc_p0_act <= 0; + cmc_p1_act <= 0; + cmc_p2_act <= cmc_last_proc; + cmc_p3_act <= ~cmc_last_proc; + cmc_last_proc <= ~cmc_last_proc; + end else if(cmpc_p2_rq) begin + cmc_p0_act <= 0; + cmc_p1_act <= 0; + cmc_p2_act <= 1; + cmc_p3_act <= 0; + end else if(cmpc_p3_rq) begin + cmc_p0_act <= 0; + cmc_p1_act <= 0; + cmc_p2_act <= 0; + cmc_p3_act <= 1; + end + end + if(cmc_t2) begin + if(cmc_p2_act) + cmc_last_proc <= 0; + if(cmc_p3_act) + cmc_last_proc <= 1; + end + + if(cmc_t0 | cmc_await_rq_reset) + cmc_await_rq <= 0; + if(cmc_t5 | cmc_aw_rq_set) + cmc_await_rq <= 1; + + if(cmc_start | cmc_pwr_clr) + cmc_rq_sync <= 0; + if(cmc_rq_sync_set | cmc_t0 & cmc_sp) + cmc_rq_sync <= 1; + + if(cmc_pwr_clr) + cmc_cyc_done <= 0; + if(cmc_t6 & ~cmc_stop) + cmc_cyc_done <= 1; + + if(cmc_t1b) begin + cmc_pse_sync <= 0; + cmc_proc_rs <= 0; + cmc_stop <= 0; + end + + // actually through another PA + if(cmc_pse_sync_set) + cmc_pse_sync <= 1; + + if(cmpc_rs_set_D) + cmc_proc_rs <= 1; + + if(cmc_start) + cmc_stop <= 0; + if(cmc_t2 & sw_single_step) + cmc_stop <= 1; + + if(cmc_t2) begin + cmc_rq_sync <= 0; + cmc_cyc_done <= 0; + end + + + if(cmc_jam_cma) begin + cma <= ma_in; + cma_rd_rq <= rd_rq_in; + cma_wr_rq <= wr_rq_in; + end + + cmb <= cmb | mb_in; + if(cmc_cmb_clr) + cmb <= 0; + if(strobe_sense) + cmb <= cmb | sa; + + /* Core */ + if(cmc_pwr_clr | cmc_t5) begin + cmc_read <= 0; + cmc_write <= 0; + cmc_inh <= 0; + end + if(cmc_t1a) begin + cmc_read <= 1; + m_read <= 1; + cmc_write <= 0; + end + if(cmc_read_off) + cmc_read <= 0; + if(cmc_t3) + cmc_inh <= 1; + if(cmc_t4) begin + cmc_write <= 1; + m_write <= 1; + cmc_read <= 0; + end + end + end +endmodule diff --git a/verilog/modules.v b/verilog/dly_50.v similarity index 52% rename from verilog/modules.v rename to verilog/dly_50.v index 1fbcf2f..c9ff6f4 100644 --- a/verilog/modules.v +++ b/verilog/dly_50.v @@ -1,76 +1,50 @@ -// input 100mhz, output ~60hz -module clk60hz( - input wire clk, - output wire outclk -); - reg [21:0] cnt = 0; - assign outclk = cnt == 1666666; - always @(posedge clk) - if(outclk) - cnt <= 0; - else - cnt <= cnt + 22'b1; -endmodule - -module pg( - input clk, - input reset, - input in, - output p -); - reg [1:0] x; - always @(posedge clk or posedge reset) - if(reset) - x <= 0; - else - x <= { x[0], in }; - assign p = x[0] & !x[1]; -endmodule - -module pa(input clk, input reset, input in, output reg p); - always @(posedge clk or posedge reset) - if(reset) - p <= 0; - else - p <= in; -endmodule - -/* "bus driver", 40ns delayed pulse */ -module bd(input clk, input reset, input in, output p); - reg [2:0] r; - always @(posedge clk or posedge reset) begin - if(reset) - r <= 0; - else begin - if(r) - r <= r + 3'b1; - if(in) - r <= 1; - end - end - assign p = r == 4; -endmodule - -/* Same as above but with longer pulse. Used to pulse mb - * because one more clock cycle is needed to get the data - * after the pulse has been synchronized. */ -module bd2(input clk, input reset, input in, output p); - reg [2:0] r; - always @(posedge clk or posedge reset) begin - if(reset) - r <= 0; - else begin - if(r) - r <= r + 3'b1; - if(in) - r <= 1; - end - end - assign p = r == 4 || r == 5 || r == 6 || r == 7; -endmodule - module dly50ns(input clk, input reset, input in, output p); - reg [2:0] r; + reg [2-1:0] r; + always @(posedge clk or posedge reset) begin + if(reset) + r <= 0; + else begin + if(r) + r <= r + 2'b1; + if(in) + r <= 1; + end + end + assign p = r == 2; +endmodule + +module dly70ns(input clk, input reset, input in, output p); + reg [2-1:0] r; + always @(posedge clk or posedge reset) begin + if(reset) + r <= 0; + else begin + if(r) + r <= r + 2'b1; + if(in) + r <= 1; + end + end + assign p = r == 3; +endmodule + +module dly100ns(input clk, input reset, input in, output p); + reg [3-1:0] r; + always @(posedge clk or posedge reset) begin + if(reset) + r <= 0; + else begin + if(r) + r <= r + 3'b1; + if(in) + r <= 1; + end + end + assign p = r == 5; +endmodule + +module dly150ns(input clk, input reset, input in, output p); + reg [3-1:0] r; always @(posedge clk or posedge reset) begin if(reset) r <= 0; @@ -84,8 +58,8 @@ module dly50ns(input clk, input reset, input in, output p); assign p = r == 7; endmodule -module dly70ns(input clk, input reset, input in, output p); - reg [3:0] r; +module dly200ns(input clk, input reset, input in, output p); + reg [4-1:0] r; always @(posedge clk or posedge reset) begin if(reset) r <= 0; @@ -96,11 +70,11 @@ module dly70ns(input clk, input reset, input in, output p); r <= 1; end end - assign p = r == 9; + assign p = r == 10; endmodule -module dly100ns(input clk, input reset, input in, output p); - reg [3:0] r; +module dly250ns(input clk, input reset, input in, output p); + reg [4-1:0] r; always @(posedge clk or posedge reset) begin if(reset) r <= 0; @@ -114,8 +88,23 @@ module dly100ns(input clk, input reset, input in, output p); assign p = r == 12; endmodule -module dly150ns(input clk, input reset, input in, output p); - reg [4:0] r; +module dly300ns(input clk, input reset, input in, output p); + reg [4-1:0] r; + always @(posedge clk or posedge reset) begin + if(reset) + r <= 0; + else begin + if(r) + r <= r + 4'b1; + if(in) + r <= 1; + end + end + assign p = r == 15; +endmodule + +module dly400ns(input clk, input reset, input in, output p); + reg [5-1:0] r; always @(posedge clk or posedge reset) begin if(reset) r <= 0; @@ -126,11 +115,11 @@ module dly150ns(input clk, input reset, input in, output p); r <= 1; end end - assign p = r == 17; + assign p = r == 20; endmodule -module dly200ns(input clk, input reset, input in, output p); - reg [4:0] r; +module dly450ns(input clk, input reset, input in, output p); + reg [5-1:0] r; always @(posedge clk or posedge reset) begin if(reset) r <= 0; @@ -144,8 +133,8 @@ module dly200ns(input clk, input reset, input in, output p); assign p = r == 22; endmodule -module dly250ns(input clk, input reset, input in, output p); - reg [4:0] r; +module dly550ns(input clk, input reset, input in, output p); + reg [5-1:0] r; always @(posedge clk or posedge reset) begin if(reset) r <= 0; @@ -159,8 +148,8 @@ module dly250ns(input clk, input reset, input in, output p); assign p = r == 27; endmodule -module dly400ns(input clk, input reset, input in, output p); - reg [5:0] r; +module dly750ns(input clk, input reset, input in, output p); + reg [6-1:0] r; always @(posedge clk or posedge reset) begin if(reset) r <= 0; @@ -171,133 +160,262 @@ module dly400ns(input clk, input reset, input in, output p); r <= 1; end end - assign p = r == 42; + assign p = r == 37; endmodule module dly800ns(input clk, input reset, input in, output p); - reg [6:0] r; + reg [6-1:0] r; always @(posedge clk or posedge reset) begin if(reset) r <= 0; else begin if(r) - r <= r + 7'b1; + r <= r + 6'b1; if(in) r <= 1; end end - assign p = r == 82; + assign p = r == 40; endmodule + module dly1us(input clk, input reset, input in, output p); - reg [6:0] r; + reg [6-1:0] r; always @(posedge clk or posedge reset) begin if(reset) r <= 0; else begin if(r) - r <= r + 7'b1; + r <= r + 6'b1; if(in) r <= 1; end end - assign p = r == 102; + assign p = r == 50; endmodule + module ldly1us(input clk, input reset, input in, output p, output reg l); - reg [6:0] r; + reg [6-1:0] r; always @(posedge clk or posedge reset) begin if(reset) begin - l <= 0; r <= 0; + l <= 0; + end else begin + if(r) + r <= r + 6'b1; + if(in) begin + r <= 1; + l <= 1; + end + if(p) begin + r <= 0; + l <= 0; + end + end + end + assign p = r == 50; +endmodule + + +module ldly1_5us(input clk, input reset, input in, output p, output reg l); + reg [7-1:0] r; + always @(posedge clk or posedge reset) begin + if(reset) begin + r <= 0; + l <= 0; end else begin if(r) r <= r + 7'b1; if(in) begin - l <= 1; r <= 1; + l <= 1; end - if(r == 101) begin + if(p) begin + r <= 0; l <= 0; - //r <= 0; end end end - assign p = r == 102; + assign p = r == 75; endmodule -module ldly1_5us(input clk, input reset, input in, output p, output reg l); - reg [7:0] r; - always @(posedge clk or posedge reset) begin - if(reset) begin - l <= 0; - r <= 0; - end else begin - if(r) - r <= r + 8'b1; - if(in) begin - l <= 1; - r <= 1; - end - if(r == 151) begin - l <= 0; - //r <= 0; - end - end - end - assign p = r == 152; -endmodule module ldly2us(input clk, input reset, input in, output p, output reg l); - reg [7:0] r; + reg [7-1:0] r; always @(posedge clk or posedge reset) begin if(reset) begin - l <= 0; r <= 0; + l <= 0; end else begin if(r) - r <= r + 8'b1; + r <= r + 7'b1; if(in) begin - l <= 1; r <= 1; + l <= 1; end - if(r == 201) begin + if(p) begin + r <= 0; l <= 0; - //r <= 0; end end end - assign p = r == 202; + assign p = r == 100; endmodule + module dly100us(input clk, input reset, input in, output p); - reg [15:0] r; + reg [13-1:0] r; always @(posedge clk or posedge reset) begin if(reset) r <= 0; else begin if(r) - r <= r + 16'b1; + r <= r + 13'b1; if(in) r <= 1; end end - assign p = r == 10002; + assign p = r == 5000; endmodule -module ldly100us(input clk, input reset, input in, output p, output l); - reg [15:0] r; + +module ldly100us(input clk, input reset, input in, output p, output reg l); + reg [13-1:0] r; + always @(posedge clk or posedge reset) begin + if(reset) begin + r <= 0; + l <= 0; + end else begin + if(r) + r <= r + 13'b1; + if(in) begin + r <= 1; + l <= 1; + end + if(p) begin + r <= 0; + l <= 0; + end + end + end + assign p = r == 5000; +endmodule + + +module dly2_1ms(input clk, input reset, input in, output p); + reg [17-1:0] r; always @(posedge clk or posedge reset) begin if(reset) r <= 0; else begin if(r) - r <= r + 16'b1; + r <= r + 17'b1; if(in) r <= 1; end end - assign p = r == 10002; - assign l = r != 0 && r < 10002; + assign p = r == 105000; +endmodule + + +module dly2_5ms(input clk, input reset, input in, output p); + reg [17-1:0] r; + always @(posedge clk or posedge reset) begin + if(reset) + r <= 0; + else begin + if(r) + r <= r + 17'b1; + if(in) + r <= 1; + end + end + assign p = r == 125000; +endmodule + + +module dly5ms(input clk, input reset, input in, output p); + reg [18-1:0] r; + always @(posedge clk or posedge reset) begin + if(reset) + r <= 0; + else begin + if(r) + r <= r + 18'b1; + if(in) + r <= 1; + end + end + assign p = r == 250000; +endmodule + + +module ldly5ms(input clk, input reset, input in, output p, output reg l); + reg [18-1:0] r; + always @(posedge clk or posedge reset) begin + if(reset) begin + r <= 0; + l <= 0; + end else begin + if(r) + r <= r + 18'b1; + if(in) begin + r <= 1; + l <= 1; + end + if(p) begin + r <= 0; + l <= 0; + end + end + end + assign p = r == 250000; +endmodule + + +module ldly1s(input clk, input reset, input in, output p, output reg l); + reg [26-1:0] r; + always @(posedge clk or posedge reset) begin + if(reset) begin + r <= 0; + l <= 0; + end else begin + if(r) + r <= r + 26'b1; + if(in) begin + r <= 1; + l <= 1; + end + if(p) begin + r <= 0; + l <= 0; + end + end + end + assign p = r == 50000000; +endmodule + + +module ldly5s(input clk, input reset, input in, output p, output reg l); + reg [28-1:0] r; + always @(posedge clk or posedge reset) begin + if(reset) begin + r <= 0; + l <= 0; + end else begin + if(r) + r <= r + 28'b1; + if(in) begin + r <= 1; + l <= 1; + end + if(p) begin + r <= 0; + l <= 0; + end + end + end + assign p = r == 250000000; endmodule diff --git a/verilog/fakeapr.v b/verilog/fakeapr.v new file mode 100644 index 0000000..21cb86d --- /dev/null +++ b/verilog/fakeapr.v @@ -0,0 +1,100 @@ +module fakeapr( + input wire clk, + input wire reset, + + // keys + input wire key_start, + input wire key_read_in, + input wire key_mem_cont, + input wire key_inst_cont, + input wire key_mem_stop, + input wire key_inst_stop, + input wire key_exec, + input wire key_io_reset, + input wire key_dep, + input wire key_dep_nxt, + input wire key_ex, + input wire key_ex_nxt, + + // switches + input wire sw_addr_stop, + input wire sw_mem_disable, + input wire sw_repeat, + input wire sw_power, + input wire [0:35] datasw, + input wire [18:35] mas, + + // maintenance switches + input wire sw_rim_maint, + input wire sw_repeat_bypass, + input wire sw_art3_maint, + input wire sw_sct_maint, + input wire sw_split_cyc, + + // lights + output wire power, + output wire [0:17] ir, + output wire [0:35] mi, + output wire [0:35] ar, + output wire [0:35] mb, + output wire [0:35] mq, + output wire [18:35] pc, + output wire [18:35] ma, + output wire run, + output wire mc_stop, + output wire pi_active, + output wire [1:7] pih, + output wire [1:7] pir, + output wire [1:7] pio, + output wire [18:25] pr, + output wire [18:25] rlr, + output wire [18:25] rla, + output wire [0:7] ff0, + output wire [0:7] ff1, + output wire [0:7] ff2, + output wire [0:7] ff3, + output wire [0:7] ff4, + output wire [0:7] ff5, + output wire [0:7] ff6, + output wire [0:7] ff7, + output wire [0:7] ff8, + output wire [0:7] ff9, + output wire [0:7] ff10, + output wire [0:7] ff11, + output wire [0:7] ff12, + output wire [0:7] ff13 +); + + assign power = sw_power; + assign ir = 18'o111111; + assign mi = 36'o222222333333; + assign ar = 36'o444444555555; + assign mb = 36'o666666777777; + assign mq = 36'o101010202020; + assign pc = 18'o303030; + assign ma = 18'o404040; + assign run = datasw[35]; + assign mc_stop = datasw[34]; + assign pi_active = 0; + assign pih = 7'o123; + assign pir = 7'o134; + assign pio = 7'o145; + assign pr = 8'o352; + assign rlr = 8'o333; + assign rla = 8'o222; + assign ff0 = 8'o201; + assign ff1 = 8'o202; + assign ff2 = 8'o203; + assign ff3 = 8'o204; + assign ff4 = 8'o205; + assign ff5 = 8'o206; + assign ff6 = 8'o207; + assign ff7 = 8'o210; + assign ff8 = 8'o211; + assign ff9 = 8'o212; + assign ff10 = 8'o213; + assign ff11 = 8'o214; + assign ff12 = 8'o215; + assign ff13 = 8'o216; + +endmodule diff --git a/verilog/fast162.v b/verilog/fast162.v index a74aa22..9b15a35 100644 --- a/verilog/fast162.v +++ b/verilog/fast162.v @@ -71,7 +71,7 @@ module fast162( reg fmc_stop; reg fmc_wr; wire [0:35] fm_out = (fma != 0 | fmc_rd0) ? ff[fma] : 0; - reg [0:35] ff[0:16]; + reg [0:35] ff[0:15]; wire wr_rs = fmc_p0_sel ? membus_wr_rs_p0 : fmc_p1_sel ? membus_wr_rs_p1 : @@ -149,11 +149,11 @@ module fast162( .p(fmc_restart)); pg fmc_pg2(.clk(clk), .reset(reset), .in(fmc_act), .p(fmct0)); pg fmc_pg3(.clk(clk), .reset(reset), .in(fma_rd_rq), .p(fma_rd_rq_P)); - pg cmc_pg4(.clk(clk), .reset(reset), .in(| mb_in), .p(mb_pulse_in)); pg cmc_pg5(.clk(clk), .reset(reset), .in(wr_rs), .p(fmc_wr_rs)); pa fmc_pa0(.clk(clk), .reset(reset), - .in(fmc_start | fmct4 & ~fmc_stop), + .in(fmc_start | + fmct4 & ~fmc_stop), .p(fmct5)); pa fmc_pa1(.clk(clk), .reset(reset), .in(fmct0 & fma_rd_rq), @@ -172,7 +172,8 @@ module fast162( fmct1_D & fma_wr_rq), .p(fmct3)); pa fmc_pa6(.clk(clk), .reset(reset), - .in(fmct1_D & ~fma_wr_rq | fmc_wr_rs), + .in(fmct1_D & ~fma_wr_rq | + fmc_wr_rs), .p(fmct4)); dly200ns fmc_dly0(.clk(clk), .reset(reset), @@ -188,9 +189,9 @@ module fast162( .in(fmct3), .p(fmct3_D)); - bd fmc_bd0(.clk(clk), .reset(reset), .in(fmct0), .p(fmc_addr_ack)); - bd fmc_bd1(.clk(clk), .reset(reset), .in(fmct1), .p(fmc_rd_rs)); - bd2 fmc_bd2(.clk(clk), .reset(reset), .in(fmct1), .p(fmc_rd_strb)); + bd fmc_bd0(.clk(clk), .reset(reset), .in(fmct0), .p(fmc_addr_ack)); + bd fmc_bd1(.clk(clk), .reset(reset), .in(fmct1), .p(fmc_rd_rs)); + bd fmc_bd2(.clk(clk), .reset(reset), .in(fmct1), .p(fmc_rd_strb)); `ifdef simulation always @(posedge reset) begin @@ -215,7 +216,7 @@ module fast162( fmc_wr <= 1; if(fm_clr) ff[fma] <= 0; - if(mb_pulse_in & fmc_wr) + if(fmc_wr) ff[fma] <= ff[fma] | mb_in; if(fmct0) begin fmc_rs <= 0; diff --git a/verilog/fast162_dp.v b/verilog/fast162_dp.v new file mode 100644 index 0000000..a98ad55 --- /dev/null +++ b/verilog/fast162_dp.v @@ -0,0 +1,251 @@ +module fast162_dp( + input wire clk, + input wire reset, + input wire power, + input wire sw_single_step, + input wire sw_restart, + + // 4 Membus slaves + input wire membus_wr_rs_p0, + input wire membus_rq_cyc_p0, + input wire membus_rd_rq_p0, + input wire membus_wr_rq_p0, + input wire [21:35] membus_ma_p0, + input wire [18:21] membus_sel_p0, + input wire membus_fmc_select_p0, + input wire [0:35] membus_mb_in_p0, + output wire membus_addr_ack_p0, + output wire membus_rd_rs_p0, + output wire [0:35] membus_mb_out_p0, + + input wire membus_wr_rs_p1, + input wire membus_rq_cyc_p1, + input wire membus_rd_rq_p1, + input wire membus_wr_rq_p1, + input wire [21:35] membus_ma_p1, + input wire [18:21] membus_sel_p1, + input wire membus_fmc_select_p1, + input wire [0:35] membus_mb_in_p1, + output wire membus_addr_ack_p1, + output wire membus_rd_rs_p1, + output wire [0:35] membus_mb_out_p1, + + input wire membus_wr_rs_p2, + input wire membus_rq_cyc_p2, + input wire membus_rd_rq_p2, + input wire membus_wr_rq_p2, + input wire [21:35] membus_ma_p2, + input wire [18:21] membus_sel_p2, + input wire membus_fmc_select_p2, + input wire [0:35] membus_mb_in_p2, + output wire membus_addr_ack_p2, + output wire membus_rd_rs_p2, + output wire [0:35] membus_mb_out_p2, + + input wire membus_wr_rs_p3, + input wire membus_rq_cyc_p3, + input wire membus_rd_rq_p3, + input wire membus_wr_rq_p3, + input wire [21:35] membus_ma_p3, + input wire [18:21] membus_sel_p3, + input wire membus_fmc_select_p3, + input wire [0:35] membus_mb_in_p3, + output wire membus_addr_ack_p3, + output wire membus_rd_rs_p3, + output wire [0:35] membus_mb_out_p3, + + // 36 bit Avalon Slave + input wire [17:0] s_address, + input wire s_write, + input wire s_read, + input wire [35:0] s_writedata, + output wire [35:0] s_readdata, + output wire s_waitrequest +); + + /* Jumpers */ + parameter memsel_p0 = 4'b0; + parameter memsel_p1 = 4'b0; + parameter memsel_p2 = 4'b0; + parameter memsel_p3 = 4'b0; + parameter fmc_p0_sel = 1'b1; + parameter fmc_p1_sel = 1'b0; + parameter fmc_p2_sel = 1'b0; + parameter fmc_p3_sel = 1'b0; + + + reg fmc_act; + reg fmc_rd0; + reg fmc_rs; // not used, what is this? + reg fmc_stop; + reg fmc_wr; + wire [0:35] fm_out = (fma != 0 | fmc_rd0) ? ff[fma] : 0; + reg [0:35] ff[0:15]; + + wire wr_rs = fmc_p0_sel ? membus_wr_rs_p0 : + fmc_p1_sel ? membus_wr_rs_p1 : + fmc_p2_sel ? membus_wr_rs_p2 : + fmc_p3_sel ? membus_wr_rs_p3 : 1'b0; + wire fma_rd_rq = fmc_p0_sel ? membus_rd_rq_p0 : + fmc_p1_sel ? membus_rd_rq_p1 : + fmc_p2_sel ? membus_rd_rq_p2 : + fmc_p3_sel ? membus_rd_rq_p3 : 1'b0; + wire fma_wr_rq = fmc_p0_sel ? membus_wr_rq_p0 : + fmc_p1_sel ? membus_wr_rq_p1 : + fmc_p2_sel ? membus_wr_rq_p2 : + fmc_p3_sel ? membus_wr_rq_p3 : 1'b0; + wire [21:35] fma = fmc_p0_sel ? membus_ma_p0[32:35] : + fmc_p1_sel ? membus_ma_p1[32:35] : + fmc_p2_sel ? membus_ma_p2[32:35] : + fmc_p3_sel ? membus_ma_p3[32:35] : 1'b0; + wire [0:35] mb_in = fmc_p0_wr_sel ? membus_mb_in_p0 : + fmc_p1_wr_sel ? membus_mb_in_p1 : + fmc_p2_wr_sel ? membus_mb_in_p2 : + fmc_p3_wr_sel ? membus_mb_in_p3 : 1'b0; + assign membus_addr_ack_p0 = fmc_addr_ack & fmc_p0_sel; + assign membus_rd_rs_p0 = fmc_rd_rs & fmc_p0_sel; + assign membus_mb_out_p0 = fmc_p0_sel ? mb_out : 1'b0; + assign membus_addr_ack_p1 = fmc_addr_ack & fmc_p1_sel; + assign membus_rd_rs_p1 = fmc_rd_rs & fmc_p1_sel; + assign membus_mb_out_p1 = fmc_p1_sel ? mb_out : 1'b0; + assign membus_addr_ack_p2 = fmc_addr_ack & fmc_p2_sel; + assign membus_rd_rs_p2 = fmc_rd_rs & fmc_p2_sel; + assign membus_mb_out_p2 = fmc_p2_sel ? mb_out : 1'b0; + assign membus_addr_ack_p3 = fmc_addr_ack & fmc_p3_sel; + assign membus_rd_rs_p3 = fmc_rd_rs & fmc_p3_sel; + assign membus_mb_out_p3 = fmc_p3_sel ? mb_out : 1'b0; + + wire fmc_addr_ack; + wire fmc_rd_rs; + wire [0:35] mb_out = fmc_rd_strb ? fm_out : 36'b0; + + wire fmc_p0_sel1 = fmc_p0_sel & ~fmc_stop; + wire fmc_p1_sel1 = fmc_p1_sel & ~fmc_stop; + wire fmc_p2_sel1 = fmc_p2_sel & ~fmc_stop; + wire fmc_p3_sel1 = fmc_p3_sel & ~fmc_stop; + wire fmc_p0_wr_sel = fmc_p0_sel & fmc_act & ~fma_rd_rq; + wire fmc_p1_wr_sel = fmc_p1_sel & fmc_act & ~fma_rd_rq; + wire fmc_p2_wr_sel = fmc_p2_sel & fmc_act & ~fma_rd_rq; + wire fmc_p3_wr_sel = fmc_p3_sel & fmc_act & ~fma_rd_rq; + wire fmpc_p0_rq = fmc_p0_sel1 & memsel_p0 == membus_sel_p0 & + membus_fmc_select_p0 & membus_rq_cyc_p0; + wire fmpc_p1_rq = fmc_p1_sel1 & memsel_p1 == membus_sel_p1 & + membus_fmc_select_p1 & membus_rq_cyc_p1; + wire fmpc_p2_rq = fmc_p2_sel1 & memsel_p2 == membus_sel_p2 & + membus_fmc_select_p2 & membus_rq_cyc_p2; + wire fmpc_p3_rq = fmc_p3_sel1 & memsel_p3 == membus_sel_p3 & + membus_fmc_select_p3 & membus_rq_cyc_p3; + + wire fmc_pwr_on; + wire fmc_restart; + wire fmc_start; + wire fmc_rd_strb; + wire fmct0; + wire fmct1; + wire fmct3; + wire fmct4; + wire fmct5; + + wire fm_clr; + wire fmc_wr_set; + wire fmc_wr_rs; + wire fma_rd_rq_P, fma_rd_rq_D, fmc_rd0_set; + wire fmct1_D, fmct3_D; + wire mb_pulse_in; + + pg fmc_pg0(.clk(clk), .reset(reset), .in(power), .p(fmc_pwr_on)); + pg fmc_pg1(.clk(clk), .reset(reset), .in(sw_restart & fmc_stop), + .p(fmc_restart)); + pg fmc_pg2(.clk(clk), .reset(reset), .in(fmc_act), .p(fmct0)); + pg fmc_pg3(.clk(clk), .reset(reset), .in(fma_rd_rq), .p(fma_rd_rq_P)); + pg cmc_pg5(.clk(clk), .reset(reset), .in(wr_rs), .p(fmc_wr_rs)); + + pa fmc_pa0(.clk(clk), .reset(reset), + .in(fmc_start | + fmct4 & ~fmc_stop), + .p(fmct5)); + pa fmc_pa1(.clk(clk), .reset(reset), + .in(fmct0 & fma_rd_rq), + .p(fmct1)); + pa fmc_pa2(.clk(clk), .reset(reset), + .in(fma_rd_rq_D), + .p(fmc_rd0_set)); + pa fmc_pa3(.clk(clk), .reset(reset), + .in(fmct3), + .p(fm_clr)); + pa fmc_pa4(.clk(clk), .reset(reset), + .in(fmct3_D), + .p(fmc_wr_set)); + pg fmc_pg5(.clk(clk), .reset(reset), + .in(fmct0 & ~fma_rd_rq & fma_wr_rq | + fmct1_D & fma_wr_rq), + .p(fmct3)); + pa fmc_pa6(.clk(clk), .reset(reset), + .in(fmct1_D & ~fma_wr_rq | + fmc_wr_rs), + .p(fmct4)); + + dly200ns fmc_dly0(.clk(clk), .reset(reset), + .in(fmc_restart | fmc_pwr_on), + .p(fmc_start)); + dly50ns fmc_dly1(.clk(clk), .reset(reset), + .in(fma_rd_rq_P), + .p(fma_rd_rq_D)); + dly100ns fmc_dly3(.clk(clk), .reset(reset), + .in(fmct1), + .p(fmct1_D)); + dly50ns fmc_dly4(.clk(clk), .reset(reset), + .in(fmct3), + .p(fmct3_D)); + + bd fmc_bd0(.clk(clk), .reset(reset), .in(fmct0), .p(fmc_addr_ack)); + bd fmc_bd1(.clk(clk), .reset(reset), .in(fmct1), .p(fmc_rd_rs)); + bd fmc_bd2(.clk(clk), .reset(reset), .in(fmct1), .p(fmc_rd_strb)); + +`ifdef simulation + always @(posedge reset) begin + fmc_act <= 0; + end +`endif + + always @(posedge clk) begin + if(fmc_restart | fmc_pwr_on) begin + fmc_act <= 0; + fmc_stop <= 1; + end + if(fmpc_p0_rq | fmpc_p1_rq | fmpc_p2_rq | fmpc_p3_rq) + fmc_act <= 1; + if(fmc_wr_rs) + fmc_rs <= 1; + if(~fma_rd_rq) + fmc_rd0 <= 0; + if(fmc_rd0_set) + fmc_rd0 <= 1; + if(fmc_wr_set) + fmc_wr <= 1; + if(fm_clr) + ff[fma] <= 0; + if(fmc_wr) + ff[fma] <= ff[fma] | mb_in; + if(fmct0) begin + fmc_rs <= 0; + fmc_stop <= sw_single_step; + end + if(fmct4) begin + fmc_act <= 0; + fmc_rd0 <= 0; + end + if(fmct5) begin + fmc_stop <= 0; + fmc_wr <= 0; + end + + if(s_write) + ff[s_address[3:0]] <= s_writedata; + end + + + assign s_readdata = ff[s_address[3:0]]; + assign s_waitrequest = 0; + +endmodule diff --git a/verilog/fe_req.v b/verilog/fe_req.v new file mode 100644 index 0000000..2617d16 --- /dev/null +++ b/verilog/fe_req.v @@ -0,0 +1,13 @@ +module fe_req( + // unused + input wire clk, + input wire reset, + + // requests + input wire [31:0] req, + + // Avalon slave + output wire [31:0] readdata +); + assign readdata = req; +endmodule diff --git a/verilog/gendly6.py b/verilog/gendly6.py new file mode 100755 index 0000000..3879255 --- /dev/null +++ b/verilog/gendly6.py @@ -0,0 +1,169 @@ +#!/usr/bin/python +from math import * + +# delays are rounded down +clock=20 # cycle time of clock in ns + +nsdly="""module dly{ns}ns(input clk, input reset, input in, output p); + reg [{width}-1:0] r; + always @(posedge clk or posedge reset) begin + if(reset) + r <= 0; + else begin + if(r) + r <= r + {width}'b1; + if(in) + r <= 1; + end + end + assign p = r == {n}; +endmodule +""" + +def gendlyns(ns): + n = ns//clock + nb = ceil(log(n+1,2)) + print(nsdly.format(ns=ns, width=nb, n=n)) + +gendlyns(50) +gendlyns(70) +gendlyns(100) +gendlyns(150) +gendlyns(200) +gendlyns(250) +gendlyns(300) +gendlyns(400) +gendlyns(450) +gendlyns(550) +gendlyns(750) +gendlyns(800) + + +usdly=""" +module dly{us}us(input clk, input reset, input in, output p); + reg [{width}-1:0] r; + always @(posedge clk or posedge reset) begin + if(reset) + r <= 0; + else begin + if(r) + r <= r + {width}'b1; + if(in) + r <= 1; + end + end + assign p = r == {n}; +endmodule +""" + +usldly=""" +module ldly{us}us(input clk, input reset, input in, output p, output reg l); + reg [{width}-1:0] r; + always @(posedge clk or posedge reset) begin + if(reset) begin + r <= 0; + l <= 0; + end else begin + if(r) + r <= r + {width}'b1; + if(in) begin + r <= 1; + l <= 1; + end + if(p) begin + r <= 0; + l <= 0; + end + end + end + assign p = r == {n}; +endmodule +""" + +def genldlyus(us): + s = str(us).replace('.', '_') + n = int(us*1000//clock) + nb = ceil(log(n+1,2)) + print(usldly.format(us=s, width=nb, n=n)) + +def gendlyus(us): + s = str(us).replace('.', '_') + n = int(us*1000//clock) + nb = ceil(log(n+1,2)) + print(usdly.format(us=s, width=nb, n=n)) + +gendlyus(1) +genldlyus(1) +genldlyus(1.5) +genldlyus(2) +gendlyus(100) +genldlyus(100) + + +dly=""" +module dly{type}(input clk, input reset, input in, output p); + reg [{width}-1:0] r; + always @(posedge clk or posedge reset) begin + if(reset) + r <= 0; + else begin + if(r) + r <= r + {width}'b1; + if(in) + r <= 1; + end + end + assign p = r == {n}; +endmodule +""" + +ldly=""" +module ldly{type}(input clk, input reset, input in, output p, output reg l); + reg [{width}-1:0] r; + always @(posedge clk or posedge reset) begin + if(reset) begin + r <= 0; + l <= 0; + end else begin + if(r) + r <= r + {width}'b1; + if(in) begin + r <= 1; + l <= 1; + end + if(p) begin + r <= 0; + l <= 0; + end + end + end + assign p = r == {n}; +endmodule +""" + +def gendlyms(ms): + t = str(ms).replace('.', '_') + n = int(ms*1000*1000//clock) + nb = ceil(log(n+1,2)) + print(dly.format(type='%sms' % t, width=nb, n=n)) + +def genldlyms(ms): + t = str(ms).replace('.', '_') + n = int(ms*1000*1000//clock) + nb = ceil(log(n+1,2)) + print(ldly.format(type='%sms' % t, width=nb, n=n)) + +def genldlys(s): + t = str(s).replace('.', '_') + n = int(s*1000*1000*1000//clock) + nb = ceil(log(n+1,2)) + print(ldly.format(type='%ss' % t, width=nb, n=n)) + + +gendlyms(2.1) +gendlyms(2.5) +gendlyms(5) +genldlyms(5) + +genldlys(1) +genldlys(5) diff --git a/verilog/inst.gtkw b/verilog/inst.gtkw deleted file mode 100644 index 0ad415d..0000000 --- a/verilog/inst.gtkw +++ /dev/null @@ -1,195 +0,0 @@ -[*] -[*] GTKWave Analyzer v3.3.76 (w)1999-2016 BSI -[*] Mon Nov 14 22:43:38 2016 -[*] -[dumpfile] "/home/aap/src/pdp6/verilog/inst.vcd" -[dumpfile_mtime] "Mon Nov 14 22:43:33 2016" -[dumpfile_size] 102150 -[savefile] "/home/aap/src/pdp6/verilog/inst.gtkw" -[timestart] 4438 -[size] 1424 1076 -[pos] -1 -1 -*-4.849143 4467 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -[treeopen] test. -[treeopen] test.pdp6. -[sst_width] 240 -[signals_width] 223 -[sst_expanded] 1 -[sst_vpaned_height] 318 -@30 -test.pdp6.apr0.ir[0:17] -@28 -test.pdp6.apr0.ir_uuo_a -@c00200 --IR_FPCH -@28 -test.pdp6.apr0.ir_fpch -test.pdp6.apr0.ir_130 -test.pdp6.apr0.ir_131 -test.pdp6.apr0.ir_fsc -test.pdp6.apr0.ir_cao -test.pdp6.apr0.ir_ldci -test.pdp6.apr0.ir_ldc -test.pdp6.apr0.ir_dpci -test.pdp6.apr0.ir_dpc -test.pdp6.apr0.ir_fp -test.pdp6.apr0.ir_fp_dir -test.pdp6.apr0.ir_fp_rem -test.pdp6.apr0.ir_fp_mem -test.pdp6.apr0.ir_fp_both -test.pdp6.apr0.ir_fad -test.pdp6.apr0.ir_fsb -test.pdp6.apr0.ir_fmp -test.pdp6.apr0.ir_fdv -test.pdp6.apr0.nr_round -@1401200 --IR_FPCH -@c00200 ->4063 --IR 2XX -@28 ->0 -test.pdp6.apr0.ir_2xx -test.pdp6.apr0.ir_fwt -test.pdp6.apr0.ir_fwt_mov_s -test.pdp6.apr0.ir_fwt_movn_m -test.pdp6.apr0.fwt_swap -test.pdp6.apr0.fwt_negate -test.pdp6.apr0.fwt_00 -test.pdp6.apr0.fwt_01 -test.pdp6.apr0.fwt_10 -test.pdp6.apr0.fwt_11 -test.pdp6.apr0.ir_md -test.pdp6.apr0.ir_mul -test.pdp6.apr0.ir_div -test.pdp6.apr0.ir_md_s_c_e -test.pdp6.apr0.ir_md_f_c_e -test.pdp6.apr0.ir_md_s_ac_2 -test.pdp6.apr0.ir_md_f_ac_2 -test.pdp6.apr0.ir_sh -test.pdp6.apr0.ir_ash -test.pdp6.apr0.ir_rot -test.pdp6.apr0.ir_lsh -test.pdp6.apr0.ir_243 -test.pdp6.apr0.ir_ashc -test.pdp6.apr0.ir_rotc -test.pdp6.apr0.ir_lshc -test.pdp6.apr0.ir_247 -test.pdp6.apr0.ir_25x -test.pdp6.apr0.ir_exch -test.pdp6.apr0.ir_blt -test.pdp6.apr0.ir_aobjp -test.pdp6.apr0.ir_aobjn -test.pdp6.apr0.ir_jrst_a -test.pdp6.apr0.ir_jrst -test.pdp6.apr0.ir_jfcl -test.pdp6.apr0.ir_xct -test.pdp6.apr0.ir_257 -test.pdp6.apr0.ir_jp -test.pdp6.apr0.jp_pushj -test.pdp6.apr0.jp_push -test.pdp6.apr0.jp_pop -test.pdp6.apr0.jp_popj -test.pdp6.apr0.jp_jsr -test.pdp6.apr0.jp_jsp -test.pdp6.apr0.jp_jsa -test.pdp6.apr0.jp_jra -test.pdp6.apr0.jp_jmp -test.pdp6.apr0.jp_flag_stor -test.pdp6.apr0.jp_AND_ir6_0 -test.pdp6.apr0.jp_AND_NOT_jsr -test.pdp6.apr0.ir_as -test.pdp6.apr0.as_plus -test.pdp6.apr0.as_minus -@1401200 ->4063 --IR 2XX -@c00200 ->0 --ACCP V MEMAC -@28 -test.pdp6.apr0.ir_accp_OR_memac -test.pdp6.apr0.accp -test.pdp6.apr0.accp_etc_cond -test.pdp6.apr0.accp_etal_test -test.pdp6.apr0.accp_dir -test.pdp6.apr0.memac -test.pdp6.apr0.memac_tst -test.pdp6.apr0.memac_inc -test.pdp6.apr0.memac_dec -test.pdp6.apr0.memac_mem -test.pdp6.apr0.memac_ac -@1401200 --ACCP V MEMAC -@c00200 --BOOLE -@28 -test.pdp6.apr0.ir_boole -test.pdp6.apr0.boole_0 -test.pdp6.apr0.boole_1 -test.pdp6.apr0.boole_2 -test.pdp6.apr0.boole_3 -test.pdp6.apr0.boole_4 -test.pdp6.apr0.boole_5 -test.pdp6.apr0.boole_6 -test.pdp6.apr0.boole_7 -test.pdp6.apr0.boole_10 -test.pdp6.apr0.boole_11 -test.pdp6.apr0.boole_12 -test.pdp6.apr0.boole_13 -test.pdp6.apr0.boole_14 -test.pdp6.apr0.boole_15 -test.pdp6.apr0.boole_16 -test.pdp6.apr0.boole_17 -test.pdp6.apr0.boole_as_00 -test.pdp6.apr0.boole_as_01 -test.pdp6.apr0.boole_as_10 -test.pdp6.apr0.boole_as_11 -@1401200 --BOOLE -@c00200 --HWT -@28 -test.pdp6.apr0.ir_hwt -test.pdp6.apr0.hwt_lt_set -test.pdp6.apr0.hwt_rt_set -test.pdp6.apr0.hwt_lt -test.pdp6.apr0.hwt_rt -test.pdp6.apr0.hwt_swap -test.pdp6.apr0.hwt_ar_clr -test.pdp6.apr0.hwt_00 -test.pdp6.apr0.hwt_01 -test.pdp6.apr0.hwt_10 -test.pdp6.apr0.hwt_11 -@1401200 --HWT -@c00200 --ACBM -@28 -test.pdp6.apr0.ir_acbm -test.pdp6.apr0.acbm_dir -test.pdp6.apr0.acbm_dn -test.pdp6.apr0.acbm_cl -test.pdp6.apr0.acbm_com -test.pdp6.apr0.acbm_set -@1401200 --ACBM -@28 -test.pdp6.apr0.ir_iot_a -test.pdp6.apr0.ir_iot -test.pdp6.apr0.iot_blk -test.pdp6.apr0.iot_datai_o -test.pdp6.apr0.iot_status -@29 -test.pdp6.apr0.iot_outgoing -@28 -test.pdp6.apr0.iot_blki -test.pdp6.apr0.iot_datai -test.pdp6.apr0.iot_blko -test.pdp6.apr0.iot_datao -test.pdp6.apr0.iot_cono -test.pdp6.apr0.iot_coni -test.pdp6.apr0.iot_consz -test.pdp6.apr0.iot_conso -[pattern_trace] 1 -[pattern_trace] 0 diff --git a/verilog/iobus_0_connect.v b/verilog/iobus_0_connect.v new file mode 100644 index 0000000..d1ee0aa --- /dev/null +++ b/verilog/iobus_0_connect.v @@ -0,0 +1,22 @@ +module iobus_0_connect( + // unused + input wire clk, + input wire reset, + + // Master + input wire m_iob_poweron, + input wire m_iob_reset, + input wire m_datao_clear, + input wire m_datao_set, + input wire m_cono_clear, + input wire m_cono_set, + input wire m_iob_fm_datai, + input wire m_iob_fm_status, + input wire [3:9] m_ios, + input wire [0:35] m_iob_out, + output wire [1:7] m_pi_req, + output wire [0:35] m_iob_in +); + assign m_pi_req = 0; + assign m_iob_in = m_iob_out; +endmodule diff --git a/verilog/iobus_1_connect.v b/verilog/iobus_1_connect.v new file mode 100644 index 0000000..92b9701 --- /dev/null +++ b/verilog/iobus_1_connect.v @@ -0,0 +1,47 @@ +module iobus_1_connect( + // unused + input wire clk, + input wire reset, + + // Master + input wire m_iob_poweron, + input wire m_iob_reset, + input wire m_datao_clear, + input wire m_datao_set, + input wire m_cono_clear, + input wire m_cono_set, + input wire m_iob_fm_datai, + input wire m_iob_fm_status, + input wire [3:9] m_ios, + input wire [0:35] m_iob_write, + output wire [1:7] m_pi_req, + output wire [0:35] m_iob_read, + + // Slave 0 + output wire s0_iob_poweron, + output wire s0_iob_reset, + output wire s0_datao_clear, + output wire s0_datao_set, + output wire s0_cono_clear, + output wire s0_cono_set, + output wire s0_iob_fm_datai, + output wire s0_iob_fm_status, + output wire [3:9] s0_ios, + output wire [0:35] s0_iob_write, + input wire [1:7] s0_pi_req, + input wire [0:35] s0_iob_read +); + assign m_pi_req = s0_pi_req; + assign m_iob_read = m_iob_write | s0_iob_read; + + assign s0_iob_poweron = m_iob_poweron; + assign s0_iob_reset = m_iob_reset; + assign s0_datao_clear = m_datao_clear; + assign s0_datao_set = m_datao_set; + assign s0_cono_clear = m_cono_clear; + assign s0_cono_set = m_cono_set; + assign s0_iob_fm_datai = m_iob_fm_datai; + assign s0_iob_fm_status = m_iob_fm_status; + assign s0_ios = m_ios; + assign s0_iob_write = m_iob_write; +endmodule diff --git a/verilog/iobus_2_connect.v b/verilog/iobus_2_connect.v new file mode 100644 index 0000000..07cc375 --- /dev/null +++ b/verilog/iobus_2_connect.v @@ -0,0 +1,72 @@ +module iobus_2_connect( + // unused + input wire clk, + input wire reset, + + // Master + input wire m_iob_poweron, + input wire m_iob_reset, + input wire m_datao_clear, + input wire m_datao_set, + input wire m_cono_clear, + input wire m_cono_set, + input wire m_iob_fm_datai, + input wire m_iob_fm_status, + input wire [3:9] m_ios, + input wire [0:35] m_iob_write, + output wire [1:7] m_pi_req, + output wire [0:35] m_iob_read, + + // Slave 0 + output wire s0_iob_poweron, + output wire s0_iob_reset, + output wire s0_datao_clear, + output wire s0_datao_set, + output wire s0_cono_clear, + output wire s0_cono_set, + output wire s0_iob_fm_datai, + output wire s0_iob_fm_status, + output wire [3:9] s0_ios, + output wire [0:35] s0_iob_write, + input wire [1:7] s0_pi_req, + input wire [0:35] s0_iob_read, + + // Slave + output wire s1_iob_poweron, + output wire s1_iob_reset, + output wire s1_datao_clear, + output wire s1_datao_set, + output wire s1_cono_clear, + output wire s1_cono_set, + output wire s1_iob_fm_datai, + output wire s1_iob_fm_status, + output wire [3:9] s1_ios, + output wire [0:35] s1_iob_write, + input wire [1:7] s1_pi_req, + input wire [0:35] s1_iob_read +); + assign m_pi_req = s0_pi_req | s1_pi_req; + assign m_iob_read = m_iob_write | s0_iob_read | s1_iob_read; + + assign s0_iob_poweron = m_iob_poweron; + assign s0_iob_reset = m_iob_reset; + assign s0_datao_clear = m_datao_clear; + assign s0_datao_set = m_datao_set; + assign s0_cono_clear = m_cono_clear; + assign s0_cono_set = m_cono_set; + assign s0_iob_fm_datai = m_iob_fm_datai; + assign s0_iob_fm_status = m_iob_fm_status; + assign s0_ios = m_ios; + assign s0_iob_write = m_iob_write; + + assign s1_iob_poweron = m_iob_poweron; + assign s1_iob_reset = m_iob_reset; + assign s1_datao_clear = m_datao_clear; + assign s1_datao_set = m_datao_set; + assign s1_cono_clear = m_cono_clear; + assign s1_cono_set = m_cono_set; + assign s1_iob_fm_datai = m_iob_fm_datai; + assign s1_iob_fm_status = m_iob_fm_status; + assign s1_ios = m_ios; + assign s1_iob_write = m_iob_write; +endmodule diff --git a/verilog/iobus_3_connect.v b/verilog/iobus_3_connect.v new file mode 100644 index 0000000..f38013f --- /dev/null +++ b/verilog/iobus_3_connect.v @@ -0,0 +1,97 @@ +module iobus_3_connect( + // unused + input wire clk, + input wire reset, + + // Master + input wire m_iob_poweron, + input wire m_iob_reset, + input wire m_datao_clear, + input wire m_datao_set, + input wire m_cono_clear, + input wire m_cono_set, + input wire m_iob_fm_datai, + input wire m_iob_fm_status, + input wire [3:9] m_ios, + input wire [0:35] m_iob_write, + output wire [1:7] m_pi_req, + output wire [0:35] m_iob_read, + + // Slave 0 + output wire s0_iob_poweron, + output wire s0_iob_reset, + output wire s0_datao_clear, + output wire s0_datao_set, + output wire s0_cono_clear, + output wire s0_cono_set, + output wire s0_iob_fm_datai, + output wire s0_iob_fm_status, + output wire [3:9] s0_ios, + output wire [0:35] s0_iob_write, + input wire [1:7] s0_pi_req, + input wire [0:35] s0_iob_read, + + // Slave 1 + output wire s1_iob_poweron, + output wire s1_iob_reset, + output wire s1_datao_clear, + output wire s1_datao_set, + output wire s1_cono_clear, + output wire s1_cono_set, + output wire s1_iob_fm_datai, + output wire s1_iob_fm_status, + output wire [3:9] s1_ios, + output wire [0:35] s1_iob_write, + input wire [1:7] s1_pi_req, + input wire [0:35] s1_iob_read, + + // Slave 2 + output wire s2_iob_poweron, + output wire s2_iob_reset, + output wire s2_datao_clear, + output wire s2_datao_set, + output wire s2_cono_clear, + output wire s2_cono_set, + output wire s2_iob_fm_datai, + output wire s2_iob_fm_status, + output wire [3:9] s2_ios, + output wire [0:35] s2_iob_write, + input wire [1:7] s2_pi_req, + input wire [0:35] s2_iob_read +); + assign m_pi_req = s0_pi_req | s1_pi_req | s2_pi_req; + assign m_iob_read = m_iob_write | s0_iob_read | s1_iob_read | s2_iob_read; + + assign s0_iob_poweron = m_iob_poweron; + assign s0_iob_reset = m_iob_reset; + assign s0_datao_clear = m_datao_clear; + assign s0_datao_set = m_datao_set; + assign s0_cono_clear = m_cono_clear; + assign s0_cono_set = m_cono_set; + assign s0_iob_fm_datai = m_iob_fm_datai; + assign s0_iob_fm_status = m_iob_fm_status; + assign s0_ios = m_ios; + assign s0_iob_write = m_iob_write; + + assign s1_iob_poweron = m_iob_poweron; + assign s1_iob_reset = m_iob_reset; + assign s1_datao_clear = m_datao_clear; + assign s1_datao_set = m_datao_set; + assign s1_cono_clear = m_cono_clear; + assign s1_cono_set = m_cono_set; + assign s1_iob_fm_datai = m_iob_fm_datai; + assign s1_iob_fm_status = m_iob_fm_status; + assign s1_ios = m_ios; + assign s1_iob_write = m_iob_write; + + assign s2_iob_poweron = m_iob_poweron; + assign s2_iob_reset = m_iob_reset; + assign s2_datao_clear = m_datao_clear; + assign s2_datao_set = m_datao_set; + assign s2_cono_clear = m_cono_clear; + assign s2_cono_set = m_cono_set; + assign s2_iob_fm_datai = m_iob_fm_datai; + assign s2_iob_fm_status = m_iob_fm_status; + assign s2_ios = m_ios; + assign s2_iob_write = m_iob_write; +endmodule diff --git a/verilog/membus_2_connect.v b/verilog/membus_2_connect.v new file mode 100644 index 0000000..dd21460 --- /dev/null +++ b/verilog/membus_2_connect.v @@ -0,0 +1,68 @@ +module membus_2_connect( + // unused + input wire clk, + input wire reset, + + // Master + input wire m_wr_rs, + input wire m_rq_cyc, + input wire m_rd_rq, + input wire m_wr_rq, + input wire [21:35] m_ma, + input wire [18:21] m_sel, + input wire m_fmc_select, + input wire [0:35] m_mb_write, + output wire m_addr_ack, + output wire m_rd_rs, + output wire [0:35] m_mb_read, + + // Slave 0 + output wire s0_wr_rs, + output wire s0_rq_cyc, + output wire s0_rd_rq, + output wire s0_wr_rq, + output wire [21:35] s0_ma, + output wire [18:21] s0_sel, + output wire s0_fmc_select, + output wire [0:35] s0_mb_write, + input wire s0_addr_ack, + input wire s0_rd_rs, + input wire [0:35] s0_mb_read, + + // Slave 1 + output wire s1_wr_rs, + output wire s1_rq_cyc, + output wire s1_rd_rq, + output wire s1_wr_rq, + output wire [21:35] s1_ma, + output wire [18:21] s1_sel, + output wire s1_fmc_select, + output wire [0:35] s1_mb_write, + input wire s1_addr_ack, + input wire s1_rd_rs, + input wire [0:35] s1_mb_read +); + wire [0:35] mb_out = m_mb_write | s0_mb_read | s1_mb_read; + + assign m_addr_ack = s0_addr_ack | s1_addr_ack; + assign m_rd_rs = s0_rd_rs | s1_rd_rs; + assign m_mb_read = mb_out; + + assign s0_wr_rs = m_wr_rs; + assign s0_rq_cyc = m_rq_cyc; + assign s0_rd_rq = m_rd_rq; + assign s0_wr_rq = m_wr_rq; + assign s0_ma = m_ma; + assign s0_sel = m_sel; + assign s0_fmc_select = m_fmc_select; + assign s0_mb_write = mb_out; + + assign s1_wr_rs = m_wr_rs; + assign s1_rq_cyc = m_rq_cyc; + assign s1_rd_rq = m_rd_rq; + assign s1_wr_rq = m_wr_rq; + assign s1_ma = m_ma; + assign s1_sel = m_sel; + assign s1_fmc_select = m_fmc_select; + assign s1_mb_write = mb_out; +endmodule diff --git a/verilog/membus_3_connect.v b/verilog/membus_3_connect.v new file mode 100644 index 0000000..113fcdf --- /dev/null +++ b/verilog/membus_3_connect.v @@ -0,0 +1,90 @@ +module membus_3_connect( + // unused + input wire clk, + input wire reset, + + // Master + input wire m_wr_rs, + input wire m_rq_cyc, + input wire m_rd_rq, + input wire m_wr_rq, + input wire [21:35] m_ma, + input wire [18:21] m_sel, + input wire m_fmc_select, + input wire [0:35] m_mb_write, + output wire m_addr_ack, + output wire m_rd_rs, + output wire [0:35] m_mb_read, + + // Slave 0 + output wire s0_wr_rs, + output wire s0_rq_cyc, + output wire s0_rd_rq, + output wire s0_wr_rq, + output wire [21:35] s0_ma, + output wire [18:21] s0_sel, + output wire s0_fmc_select, + output wire [0:35] s0_mb_write, + input wire s0_addr_ack, + input wire s0_rd_rs, + input wire [0:35] s0_mb_read, + + // Slave 1 + output wire s1_wr_rs, + output wire s1_rq_cyc, + output wire s1_rd_rq, + output wire s1_wr_rq, + output wire [21:35] s1_ma, + output wire [18:21] s1_sel, + output wire s1_fmc_select, + output wire [0:35] s1_mb_write, + input wire s1_addr_ack, + input wire s1_rd_rs, + input wire [0:35] s1_mb_read, + + // Slave 2 + output wire s2_wr_rs, + output wire s2_rq_cyc, + output wire s2_rd_rq, + output wire s2_wr_rq, + output wire [21:35] s2_ma, + output wire [18:21] s2_sel, + output wire s2_fmc_select, + output wire [0:35] s2_mb_write, + input wire s2_addr_ack, + input wire s2_rd_rs, + input wire [0:35] s2_mb_read +); + wire [0:35] mb_out = m_mb_write | s0_mb_read | s1_mb_read | s2_mb_read; + + assign m_addr_ack = s0_addr_ack | s1_addr_ack | s2_addr_ack; + assign m_rd_rs = s0_rd_rs | s1_rd_rs | s2_rd_rs; + assign m_mb_read = mb_out; + + assign s0_wr_rs = m_wr_rs; + assign s0_rq_cyc = m_rq_cyc; + assign s0_rd_rq = m_rd_rq; + assign s0_wr_rq = m_wr_rq; + assign s0_ma = m_ma; + assign s0_sel = m_sel; + assign s0_fmc_select = m_fmc_select; + assign s0_mb_write = mb_out; + + assign s1_wr_rs = m_wr_rs; + assign s1_rq_cyc = m_rq_cyc; + assign s1_rd_rq = m_rd_rq; + assign s1_wr_rq = m_wr_rq; + assign s1_ma = m_ma; + assign s1_sel = m_sel; + assign s1_fmc_select = m_fmc_select; + assign s1_mb_write = mb_out; + + assign s2_wr_rs = m_wr_rs; + assign s2_rq_cyc = m_rq_cyc; + assign s2_rd_rq = m_rd_rq; + assign s2_wr_rq = m_wr_rq; + assign s2_ma = m_ma; + assign s2_sel = m_sel; + assign s2_fmc_select = m_fmc_select; + assign s2_mb_write = mb_out; +endmodule diff --git a/verilog/membusif.v b/verilog/membusif.v new file mode 100644 index 0000000..4ad1891 --- /dev/null +++ b/verilog/membusif.v @@ -0,0 +1,118 @@ +module membusif( + input wire clk, + input wire reset, + + // Avalon Slave + input wire [1:0] s_address, + input wire s_write, + input wire s_read, + input wire [31:0] s_writedata, + output reg [31:0] s_readdata, + output wire s_waitrequest, + + // Membus Master + output reg m_rq_cyc, + output reg m_rd_rq, + output reg m_wr_rq, + output wire [21:35] m_ma, + output wire [18:21] m_sel, + output reg m_fmc_select, + output wire [0:35] m_mb_write, + output wire m_wr_rs, + input wire [0:35] m_mb_read, + input wire m_addr_ack, + input wire m_rd_rs +); + reg [0:17] addr; + reg [0:35] word; + + assign m_ma = addr[3:17]; + assign m_sel = addr[0:3]; + + wire write_edge, read_edge; + edgedet e0(clk, reset, s_write, write_edge); + edgedet e1(clk, reset, s_read, read_edge); + + reg waiting; + wire req = (write_edge|read_edge) & s_address == 2'h2; + assign s_waitrequest = req | waiting | (|waitcyc); + + wire mb_write_pulse; + wire wr_rs = m_addr_ack & m_wr_rq; + bd mc_bd0(clk, ~reset, wr_rs, m_wr_rs); + bd2 mb_bd1(clk, ~reset, wr_rs, mb_write_pulse); + assign m_mb_write = mb_write_pulse ? word : 0; + + reg [7:0] waitcyc; + + always @(posedge clk or negedge reset) begin + if(~reset) begin + m_rq_cyc <= 0; + m_rd_rq <= 0; + m_wr_rq <= 0; + waiting <= 0; + + addr <= 0; + m_fmc_select <= 0; + word <= 0; + + waitcyc <= 0; + end else begin + if(write_edge) begin + case(s_address) + 2'h0: begin + addr <= s_writedata[17:0]; + m_fmc_select <= s_writedata[18]; + end + 2'h1: word[18:35] <= s_writedata[17:0]; + 2'h2: word[0:17] <= s_writedata[17:0]; + endcase + end + + if(req) begin + waiting <= 1; + m_rq_cyc <= 1; + if(s_write) + m_wr_rq <= 1; + else if(s_read) begin + m_rd_rq <= 1; + word <= 0; + end + end + // have to wait between cycles + // because fastmem can get stuck + if(waitcyc) begin + if(waitcyc == 'o14) + waitcyc <= 0; + else + waitcyc <= waitcyc + 1; + end + + if(waiting & m_rd_rq) + word <= m_mb_read; + + if(m_addr_ack) begin + m_rq_cyc <= 0; + waitcyc <= 1; + end + + if(m_rd_rs) begin + m_rd_rq <= 0; + waiting <= 0; + end + + if(m_wr_rs) begin + m_wr_rq <= 0; + waiting <= 0; + end + end + end + + always @(*) begin + case(s_address) + 2'h1: s_readdata <= { 14'b0, word[18:35] }; + 2'h2: s_readdata <= { 14'b0, word[0:17] }; + default: s_readdata <= 32'b0; + endcase + end +endmodule diff --git a/verilog/memif.v b/verilog/memif.v new file mode 100644 index 0000000..3edfeac --- /dev/null +++ b/verilog/memif.v @@ -0,0 +1,80 @@ +module memif( + input wire clk, + input wire reset, + + // Avalon Slave + input wire [1:0] s_address, + input wire s_write, + input wire s_read, + input wire [31:0] s_writedata, + output reg [31:0] s_readdata, + output wire s_waitrequest, + + // 36 bit Avalon Master + output wire [17:0] m_address, + output reg m_write, + output reg m_read, + output wire [35:0] m_writedata, + input wire [35:0] m_readdata, + input wire m_waitrequest +); + + reg [17:0] addr; + reg [35:0] word; + + assign m_address = addr; + assign m_writedata = word; + + wire write_edge, read_edge; + edgedet e0(clk, reset, s_write, write_edge); + edgedet e1(clk, reset, s_read, read_edge); + + reg waiting; + wire req = (write_edge|read_edge) & s_address == 2'h2; + assign s_waitrequest = req | waiting; + + always @(posedge clk or negedge reset) begin + if(~reset) begin + m_write <= 0; + m_read <= 0; + waiting <= 0; + + addr <= 0; + word <= 0; + end else begin + if(write_edge) begin + case(s_address) + 2'h0: addr <= s_writedata[17:0]; + 2'h1: word[17:0] <= s_writedata[17:0]; + 2'h2: word[35:18] <= s_writedata[17:0]; + endcase + end + + if(req) begin + waiting <= 1; + if(s_write) + m_write <= 1; + else if(s_read) + m_read <= 1; + end + + if(m_write & ~m_waitrequest) begin + m_write <= 0; + waiting <= 0; + end + if(m_read & ~m_waitrequest) begin + m_read <= 0; + waiting <= 0; + word <= m_readdata; + end + end + end + + always @(*) begin + case(s_address) + 2'h1: s_readdata <= { 14'b0, word[17:0] }; + 2'h2: s_readdata <= { 14'b0, word[35:18] }; + default: s_readdata <= 32'b0; + endcase + end +endmodule diff --git a/verilog/memory.v b/verilog/memory.v new file mode 100644 index 0000000..d4e8fad --- /dev/null +++ b/verilog/memory.v @@ -0,0 +1,80 @@ +module memory( + // input + i_clk, i_reset_n, + i_address, i_write, i_read, i_writedata, + // output + o_readdata, o_waitrequest +); + input wire i_clk; + input wire i_reset_n; + input wire [17:0] i_address; + input wire i_write; + input wire i_read; + input wire [35:0] i_writedata; + output wire [35:0] o_readdata; + output wire o_waitrequest; + + reg [35:0] mem[0:'o40000-1]; + wire addrok = i_address[17:14] == 0; + wire [13:0] addr = i_address[13:0]; + wire [35:0] memword = addrok ? mem[addr] : 0; + + always @(posedge i_clk or negedge i_reset_n) begin + if(~i_reset_n) begin + end else begin + if(i_write & addrok) begin + mem[addr] <= i_writedata; + end + end + end + + assign o_readdata = i_read ? memword : 0; + assign o_waitrequest = 0; +endmodule + + +module dlymemory( + // input + i_clk, i_reset_n, + i_address, i_write, i_read, i_writedata, + // output + o_readdata, o_waitrequest +); + input wire i_clk; + input wire i_reset_n; + input wire [17:0] i_address; + input wire i_write; + input wire i_read; + input wire [35:0] i_writedata; + output wire [35:0] o_readdata; + output wire o_waitrequest; + + reg [35:0] mem[0:'o40000-1]; + wire addrok = i_address[17:14] == 0; + wire [13:0] addr = i_address[13:0]; + wire [35:0] memword = addrok ? mem[addr] : 0; + + wire write_edge, read_edge; + reg [3:0] dly; + wire ready = dly == 0; + + edgedet e0(i_clk, i_reset_n, i_write, write_edge); + edgedet e1(i_clk, i_reset_n, i_read, read_edge); + + always @(posedge i_clk or negedge i_reset_n) begin + if(~i_reset_n) begin + dly <= 4; + end else begin + if(i_write & ready & addrok) begin + mem[addr] <= i_writedata; + end + if(~(i_write | i_read)) + dly <= 4; + else if(dly) + dly <= dly - 1; + end + end + + assign o_readdata = i_read ? memword : 0; + assign o_waitrequest = ~ready; +endmodule diff --git a/verilog/memory_16.v b/verilog/memory_16.v new file mode 100755 index 0000000..010c0a3 --- /dev/null +++ b/verilog/memory_16.v @@ -0,0 +1,42 @@ +module memory_16( + input wire i_clk, + input wire i_reset_n, + input wire [17:0] i_address, + input wire i_write, + input wire i_read, + input wire [35:0] i_writedata, + output wire [35:0] o_readdata, + output reg o_waitrequest +); + + wire addrok = i_address[17:4] == 0; + wire [3:0] addr = i_address[3:0]; + reg we; + + onchip_ram #( + .ADDR_WIDTH(4) + ) ram ( + .clk(i_clk), + .data(i_writedata), + .addr(addr), + .we(we), + .q(o_readdata)); + + /* have to wait one clock for ram address */ + always @(posedge i_clk) begin + if(~i_reset_n) begin + we <= 0; + o_waitrequest <= 0; + end else begin + if(i_read | i_write) + o_waitrequest <= 0; + else + o_waitrequest <= 1; + + if(we) + we <= 0; + else + we <= i_write & addrok; + end + end +endmodule diff --git a/verilog/memory_16k.v b/verilog/memory_16k.v new file mode 100755 index 0000000..59182ec --- /dev/null +++ b/verilog/memory_16k.v @@ -0,0 +1,42 @@ +module memory_16k( + input wire i_clk, + input wire i_reset_n, + input wire [17:0] i_address, + input wire i_write, + input wire i_read, + input wire [35:0] i_writedata, + output wire [35:0] o_readdata, + output reg o_waitrequest +); + + wire addrok = i_address[17:14] == 0; + wire [13:0] addr = i_address[13:0]; + reg we; + + onchip_ram #( + .ADDR_WIDTH(14) + ) ram ( + .clk(i_clk), + .data(i_writedata), + .addr(addr), + .we(we), + .q(o_readdata)); + + /* have to wait one clock for ram address */ + always @(posedge i_clk) begin + if(~i_reset_n) begin + we <= 0; + o_waitrequest <= 0; + end else begin + if(i_read | i_write) + o_waitrequest <= 0; + else + o_waitrequest <= 1; + + if(we) + we <= 0; + else + we <= i_write & addrok; + end + end +endmodule diff --git a/verilog/memory_32k.v b/verilog/memory_32k.v new file mode 100755 index 0000000..3a7adb6 --- /dev/null +++ b/verilog/memory_32k.v @@ -0,0 +1,42 @@ +module memory_32k( + input wire i_clk, + input wire i_reset_n, + input wire [17:0] i_address, + input wire i_write, + input wire i_read, + input wire [35:0] i_writedata, + output wire [35:0] o_readdata, + output reg o_waitrequest +); + + wire addrok = i_address[17:15] == 0; + wire [14:0] addr = i_address[14:0]; + reg we; + + onchip_ram #( + .ADDR_WIDTH(15) + ) ram ( + .clk(i_clk), + .data(i_writedata), + .addr(addr), + .we(we), + .q(o_readdata)); + + /* have to wait one clock for ram address */ + always @(posedge i_clk) begin + if(~i_reset_n) begin + we <= 0; + o_waitrequest <= 0; + end else begin + if(i_read | i_write) + o_waitrequest <= 0; + else + o_waitrequest <= 1; + + if(we) + we <= 0; + else + we <= i_write & addrok; + end + end +endmodule diff --git a/verilog/memory_64k.v b/verilog/memory_64k.v new file mode 100755 index 0000000..ece40a8 --- /dev/null +++ b/verilog/memory_64k.v @@ -0,0 +1,42 @@ +module memory_64k( + input wire i_clk, + input wire i_reset_n, + input wire [17:0] i_address, + input wire i_write, + input wire i_read, + input wire [35:0] i_writedata, + output wire [35:0] o_readdata, + output reg o_waitrequest +); + + wire addrok = i_address[17:16] == 0; + wire [15:0] addr = i_address[15:0]; + reg we; + + onchip_ram #( + .ADDR_WIDTH(16) + ) ram ( + .clk(i_clk), + .data(i_writedata), + .addr(addr), + .we(we), + .q(o_readdata)); + + /* have to wait one clock for ram address */ + always @(posedge i_clk) begin + if(~i_reset_n) begin + we <= 0; + o_waitrequest <= 0; + end else begin + if(i_read | i_write) + o_waitrequest <= 0; + else + o_waitrequest <= 1; + + if(we) + we <= 0; + else + we <= i_write & addrok; + end + end +endmodule diff --git a/verilog/modules_50.v b/verilog/modules_50.v new file mode 100755 index 0000000..decdae7 --- /dev/null +++ b/verilog/modules_50.v @@ -0,0 +1,139 @@ +// input 50mhz, output ~60hz +module clk60hz( + input wire clk, + output wire outclk +); + reg [19:0] cnt = 0; + assign outclk = cnt == 833333; + always @(posedge clk) + if(outclk) + cnt <= 0; + else + cnt <= cnt + 20'b1; +endmodule + +// input 50mhz, output 63.3hz +module clk63_3hz( + input wire clk, + output wire outclk +); + reg [19:0] cnt = 0; + assign outclk = cnt == 789900; + always @(posedge clk) + if(outclk) + cnt <= 0; + else + cnt <= cnt + 20'b1; +endmodule + +// input 50mhz, output 25khz +module clk25khz( + input wire clk, + input wire en, + output wire outclk +); + reg [10:0] cnt = 0; + assign outclk = en & (cnt == 2000); + always @(posedge clk) + if(outclk) + cnt <= 0; + else + cnt <= cnt + 11'b1; +endmodule + +// input 50mhz, output 50khz +module clk50khz( + input wire clk, + output wire outclk +); + reg [9:0] cnt = 0; + assign outclk = cnt == 1000; + always @(posedge clk) + if(outclk) + cnt <= 0; + else + cnt <= cnt + 10'b1; +endmodule + + +module pg( + input clk, + input reset, + input in, + output p +); + reg [1:0] x; + always @(posedge clk or posedge reset) + if(reset) + x <= 0; + else + x <= { x[0], in }; + assign p = x[0] & !x[1]; +endmodule + +/* +// This breaks things because it doesn't detect power on +module pg(input wire clk, input wire reset, input wire in, output wire p); + reg [1:0] x; + reg [1:0] init = 0; + always @(posedge clk or posedge reset) + if(reset) + init <= 0; + else begin + x <= { x[0], in }; + init <= { init[0], 1'b1 }; + end + assign p = (&init) & x[0] & !x[1]; +endmodule +*/ + +module pa(input wire clk, input wire reset, input wire in, output wire p); + reg [1:0] x; + reg [1:0] init = 0; + always @(posedge clk or posedge reset) + if(reset) + init <= 0; + else begin + x <= { x[0], in }; + init <= { init[0], 1'b1 }; + end + assign p = (&init) & x[0] & !x[1]; +endmodule + + +// TODO: check the purpose of these + +/* "bus driver", 40ns delayed pulse */ +module bd(input clk, input reset, input in, output p); + reg [2:0] r; + always @(posedge clk or posedge reset) begin + if(reset) + r <= 0; + else begin + if(r) + r <= r + 3'b1; + if(in) + r <= 1; + end + end + assign p = r == 4; +endmodule + +/* Same as above but with longer pulse. Used to pulse mb + * because one more clock cycle is needed to get the data + * after the pulse has been synchronized. */ +// TODO? get rid of this and just latch +module bd2(input clk, input reset, input in, output p); + reg [2:0] r; + always @(posedge clk or posedge reset) begin + if(reset) + r <= 0; + else begin + if(r) + r <= r + 3'b1; + if(in) + r <= 1; + end + end + assign p = r == 4 || r == 5 || r == 6 || r == 7; +endmodule diff --git a/verilog/onchip_ram.v b/verilog/onchip_ram.v new file mode 100755 index 0000000..4b42f1a --- /dev/null +++ b/verilog/onchip_ram.v @@ -0,0 +1,30 @@ +module onchip_ram +#(parameter DATA_WIDTH=36, parameter ADDR_WIDTH=14) +( + input [(DATA_WIDTH-1):0] data, + input [(ADDR_WIDTH-1):0] addr, + input we, clk, + output [(DATA_WIDTH-1):0] q +); + + // Declare the RAM variable + reg [DATA_WIDTH-1:0] ram[2**ADDR_WIDTH-1:0]; + + // Variable to hold the registered read address + reg [ADDR_WIDTH-1:0] addr_reg; + + always @ (posedge clk) + begin + // Write + if (we) + ram[addr] <= data; + + addr_reg <= addr; + end + + // Continuous assignment implies read returns NEW data. + // This is the natural behavior of the TriMatrix memory + // blocks in Single Port mode. + assign q = ram[addr_reg]; + +endmodule diff --git a/verilog/panel_6.v b/verilog/panel_6.v new file mode 100644 index 0000000..0067da7 --- /dev/null +++ b/verilog/panel_6.v @@ -0,0 +1,369 @@ +/* + +0 CTL1_DN +1 CTL1_UP +2 CTL2_DN +3 CTL2_UP +4 MAINT_DN +5 MAINT_UP + +6 DS LT +7 DS RT +10 MAS +11 REPEAT +12 IR +13 MI LT +14 MI RT +15 PC +16 MA +17 PI + +20 MB LT +21 MB RT +22 AR LT +23 AR RT +24 MQ LT +25 MQ RT +26 FF1 +27 FF2 +30 FF3 +31 FF4 + +32 MMU +33 TTY +34 PTP +35 PTR +36 PTR B LT +37 PTR B RT + + +40 IO STATUS + +*/ + +module panel_6( + input wire clk, + input wire reset, + + // Avalon Slave + input wire [4:0] s_address, + input wire s_write, + input wire s_read, + input wire [31:0] s_writedata, + output reg [31:0] s_readdata, + output wire s_waitrequest, + + /* + * APR + */ + + // keys + output reg key_start, + output reg key_read_in, + output reg key_mem_cont, + output reg key_inst_cont, + output reg key_mem_stop, + output reg key_inst_stop, + output reg key_exec, + output reg key_io_reset, + output reg key_dep, + output reg key_dep_nxt, + output reg key_ex, + output reg key_ex_nxt, + + // switches + output reg sw_addr_stop, + output reg sw_mem_disable, + output reg sw_repeat, + output reg sw_power, + output reg [0:35] datasw, + output reg [18:35] mas, + + // maintenance switches + output reg sw_rim_maint, + output reg sw_repeat_bypass, + output reg sw_art3_maint, + output reg sw_sct_maint, + output reg sw_split_cyc, + + // lights + input wire power, + input wire [0:17] ir, + input wire [0:35] mi, + input wire [0:35] ar, + input wire [0:35] mb, + input wire [0:35] mq, + input wire [18:35] pc, + input wire [18:35] ma, + input wire run, + input wire mc_stop, + input wire pi_active, + input wire [1:7] pih, + input wire [1:7] pir, + input wire [1:7] pio, + input wire [18:25] pr, + input wire [18:25] rlr, + input wire [18:25] rla, + input wire [0:7] ff0, + input wire [0:7] ff1, + input wire [0:7] ff2, + input wire [0:7] ff3, + input wire [0:7] ff4, + input wire [0:7] ff5, + input wire [0:7] ff6, + input wire [0:7] ff7, + input wire [0:7] ff8, + input wire [0:7] ff9, + input wire [0:7] ff10, + input wire [0:7] ff11, + input wire [0:7] ff12, + input wire [0:7] ff13, + + /* + * TTY + */ + input wire [7:0] tty_tti, + input wire [6:0] tty_status, + + /* + * PTR + */ + output reg ptr_key_start, + output reg ptr_key_stop, + output reg ptr_key_tape_feed, + input wire [35:0] ptr, + input wire [6:0] ptr_status, // also includes motor on + + /* + * PTP + */ + output reg ptp_key_tape_feed, + input wire [7:0] ptp, + input wire [6:0] ptp_status, // also includes motor on + + /* + * External panel + */ + input wire [3:0] switches, + input wire [7:0] ext, + output reg [7:0] leds +); + + wire ext_sw_power = switches[0]; + + wire [7:0] apr_status = { 5'b0, mc_stop, run, power }; + always @(*) begin + case(switches[3:1]) + 3'b000: leds <= apr_status; + 3'b001: leds <= tty_tti; + 3'b010: leds <= tty_status; + 3'b011: leds <= ptr; + 3'b100: leds <= ptr_status; + 3'b101: leds <= ptp; + 3'b110: leds <= ptp_status; + 3'b111: leds <= ext; + default: leds <= 0; + endcase + end + + + always @(*) begin + case(s_address) + 5'o00: s_readdata <= + { 20'b0, + power, mc_stop, run, sw_addr_stop, + key_exec, key_io_reset, key_mem_stop, key_inst_stop, + key_mem_cont, key_inst_cont, key_read_in, key_start + }; + 5'o01: s_readdata <= 0; + + 5'o02: s_readdata <= + { 22'b0, + sw_mem_disable, sw_repeat, + ptr_key_tape_feed, ptp_key_tape_feed, + ptr_key_start, ptr_key_stop, + key_ex_nxt, key_ex, key_dep_nxt, key_dep + }; + 5'o03: s_readdata <= 0; + + 5'o04: s_readdata <= + { 26'b0, + sw_split_cyc, sw_sct_maint, + sw_art3_maint, sw_repeat_bypass, sw_rim_maint, + 1'b0 // spare? + }; + 5'o05: s_readdata <= 0; + + 5'o06: s_readdata <= { 14'b0, datasw[0:17] }; + 5'o07: s_readdata <= { 14'b0, datasw[18:35] }; + 5'o10: s_readdata <= { 14'b0, mas }; + 5'o11: s_readdata <= 0; // TODO: repeat + 5'o12: s_readdata <= { 14'b0, ir }; + 5'o13: s_readdata <= { 14'b0, mi[0:17] }; + 5'o14: s_readdata <= { 14'b0, mi[18:35] }; + 5'o15: s_readdata <= { 14'b0, pc }; + 5'o16: s_readdata <= { 14'b0, ma }; + 5'o17: s_readdata <= { 10'b0, pih, pir, pio, pi_active }; + 5'o20: s_readdata <= { 14'b0, mb[0:17] }; + 5'o21: s_readdata <= { 14'b0, mb[18:35] }; + 5'o22: s_readdata <= { 14'b0, ar[0:17] }; + 5'o23: s_readdata <= { 14'b0, ar[18:35] }; + 5'o24: s_readdata <= { 14'b0, mq[0:17] }; + 5'o25: s_readdata <= { 14'b0, mq[18:35] }; + 5'o26: s_readdata <= { ff0, ff1, ff2, ff3 }; + 5'o27: s_readdata <= { ff4, ff5, ff6, ff7 }; + 5'o30: s_readdata <= { ff8, ff9, ff10, ff11 }; + 5'o31: s_readdata <= { ff12, ff13, 16'b0 }; + 5'o32: s_readdata <= { 8'b0, rla, rlr, pr }; + 5'o33: s_readdata <= { tty_tti, 2'b0, tty_status }; + 5'o34: s_readdata <= { ptp, 2'b0, ptp_status }; + 5'o35: s_readdata <= ptr_status; + 5'o36: s_readdata <= ptr[35:18]; + 5'o37: s_readdata <= ptr[17:0]; + default: s_readdata <= 0; + endcase + end + + assign s_waitrequest = 0; + + always @(posedge clk or negedge reset) begin + if(~reset) begin + // keys + key_start <= 0; + key_read_in <= 0; + key_mem_cont <= 0; + key_inst_cont <= 0; + key_mem_stop <= 0; + key_inst_stop <= 0; + key_exec <= 0; + key_io_reset <= 0; + key_dep <= 0; + key_dep_nxt <= 0; + key_ex <= 0; + key_ex_nxt <= 0; + + ptr_key_start <= 0; + ptr_key_stop <= 0; + ptr_key_tape_feed <= 0; + ptp_key_tape_feed <= 0; + + + // switches + sw_addr_stop <= 0; + sw_mem_disable <= 0; + sw_repeat <= 0; +/**/ sw_power <= 0; + datasw <= 0; + mas <= 0; + + // maintenance switches + sw_rim_maint <= 0; + sw_repeat_bypass <= 0; + sw_art3_maint <= 0; + sw_sct_maint <= 0; + sw_split_cyc <= 0; + end else begin + sw_power <= ext_sw_power; + + if(s_write) case(s_address) + 5'o00: begin + if(s_writedata[0]) + { key_read_in, key_start } <= 2'b01; + if(s_writedata[1]) + { key_read_in, key_start } <= 2'b10; + if(s_writedata[2]) + { key_mem_cont, key_inst_cont } <= 2'b01; + if(s_writedata[3]) + { key_mem_cont, key_inst_cont } <= 2'b10; + if(s_writedata[4]) + { key_mem_stop, key_inst_stop } <= 2'b01; + if(s_writedata[5]) + { key_mem_stop, key_inst_stop } <= 2'b10; + if(s_writedata[6]) + { key_exec, key_io_reset } <= 2'b01; + if(s_writedata[7]) + { key_exec, key_io_reset } <= 2'b10; + if(s_writedata[8]) + sw_addr_stop <= 1; + end + 5'o01: begin + if(s_writedata[0] | s_writedata[1]) + { key_read_in, key_start } <= 2'b00; + if(s_writedata[2] | s_writedata[3]) + { key_mem_cont, key_inst_cont } <= 2'b00; + if(s_writedata[4] | s_writedata[5]) + { key_mem_stop, key_inst_stop } <= 2'b00; + if(s_writedata[6] |s_writedata[7]) + { key_exec, key_io_reset } <= 2'b00; + if(s_writedata[8]) + sw_addr_stop <= 0; + end + 5'o02: begin + if(s_writedata[0]) + { key_dep_nxt, key_dep } <= 2'b01; + if(s_writedata[1]) + { key_dep_nxt, key_dep } <= 2'b10; + if(s_writedata[2]) + { key_ex_nxt, key_ex } <= 2'b01; + if(s_writedata[3]) + { key_ex_nxt, key_ex } <= 2'b10; + if(s_writedata[4]) + { ptr_key_start, ptr_key_stop } <= 2'b01; + if(s_writedata[5]) + { ptr_key_start, ptr_key_stop } <= 2'b10; + if(s_writedata[6]) + { ptp_key_tape_feed, ptr_key_tape_feed } <= 2'b10; + if(s_writedata[7]) + { ptp_key_tape_feed, ptr_key_tape_feed } <= 2'b01; + if(s_writedata[8]) + sw_repeat <= 1; + if(s_writedata[9]) + sw_mem_disable <= 1; + end + 5'o03: begin + if(s_writedata[0] | s_writedata[1]) + { key_dep_nxt, key_dep } <= 2'b00; + if(s_writedata[2] | s_writedata[3]) + { key_ex_nxt, key_ex } <= 2'b00; + if(s_writedata[4] | s_writedata[5]) + { ptr_key_start, ptr_key_stop } <= 2'b00; + if(s_writedata[6] | s_writedata[7]) + { ptp_key_tape_feed, ptr_key_tape_feed } <= 2'b00; + if(s_writedata[8]) + sw_repeat <= 0; + if(s_writedata[9]) + sw_mem_disable <= 0; + end + 5'o04: begin + if(s_writedata[1]) + sw_rim_maint <= 1; + if(s_writedata[2]) + sw_repeat_bypass <= 1; + if(s_writedata[3]) + sw_art3_maint <= 1; + if(s_writedata[4]) + sw_sct_maint <= 1; + if(s_writedata[5]) + sw_split_cyc <= 1; + end + 5'o05: begin + if(s_writedata[1]) + sw_rim_maint <= 0; + if(s_writedata[2]) + sw_repeat_bypass <= 0; + if(s_writedata[3]) + sw_art3_maint <= 0; + if(s_writedata[4]) + sw_sct_maint <= 0; + if(s_writedata[5]) + sw_split_cyc <= 0; + end + 5'o06: datasw[0:17] <= s_writedata; + 5'o07: datasw[18:35] <= s_writedata; + 5'o10: mas <= s_writedata; + // TODO: 11 REPEAT + endcase + end + end + +endmodule diff --git a/verilog/pdp6.v b/verilog/pdp6.v deleted file mode 100644 index 1ebecf0..0000000 --- a/verilog/pdp6.v +++ /dev/null @@ -1,248 +0,0 @@ -`default_nettype none - -module pdp6( - input wire clk, - input wire reset -); - // keys - reg key_start; - reg key_read_in; - reg key_mem_cont; - reg key_inst_cont; - reg key_mem_stop; - reg key_inst_stop; - reg key_exec; - reg key_io_reset; - reg key_dep; - reg key_dep_nxt; - reg key_ex; - reg key_ex_nxt; - - // switches - reg sw_addr_stop; - reg sw_mem_disable; - reg sw_repeat; - reg sw_power; - reg [0:35] datasw; - reg [18:35] mas; - - // maintenance switches - reg sw_rim_maint; - reg sw_repeat_bypass; - reg sw_art3_maint; - reg sw_sct_maint; - reg sw_split_cyc; - - // lights - wire [0:17] ir; - wire [0:35] mi; - wire [0:35] ar; - wire [0:35] mb; - wire [0:35] mq; - wire [18:35] pc; - wire [18:35] ma; - wire run; - wire mc_stop; - wire pi_active; - wire [1:7] pih; - wire [1:7] pir; - wire [1:7] pio; - wire [18:25] pr; - wire [18:25] rlr; - wire [18:25] rla; - - - /* Mem bus */ - wire membus_wr_rs_p0; - wire membus_rq_cyc_p0; - wire membus_rd_rq_p0; - wire membus_wr_rq_p0; - wire [21:35] membus_ma_p0; - wire [18:21] membus_sel_p0; - wire membus_fmc_select_p0; - wire membus_addr_ack_p0; - wire membus_rd_rs_p0; - wire [0:35] membus_mb_in_p0; - - /* Out of apr0 */ - wire [0:35] membus_mb_out_p0_p; - - /* Out of fmem0 */ - wire [0:35] membus_mb_out_p0_0; - wire membus_addr_ack_p0_0; - wire membus_rd_rs_p0_0; - - /* Out of mem0 */ - wire [0:35] membus_mb_out_p0_1; - wire membus_addr_ack_p0_1; - wire membus_rd_rs_p0_1; - - /* IO bus */ - wire iobus_iob_poweron; - wire iobus_iob_reset; - wire iobus_datao_clear; - wire iobus_datao_set; - wire iobus_cono_clear; - wire iobus_cono_set; - wire iobus_iob_fm_datai; - wire iobus_iob_fm_status; - wire [3:9] iobus_ios; - wire [0:35] iobus_iob_out; - wire [1:7] iobus_pi_req; - wire [0:35] iobus_iob_in = iobus_iob_out; - - - assign membus_mb_in_p0 = membus_mb_out_p0_p | membus_mb_out_p0_0 | membus_mb_out_p0_1; - assign membus_addr_ack_p0 = membus_addr_ack_p0_0 | membus_addr_ack_p0_1; - assign membus_rd_rs_p0 = membus_rd_rs_p0_0 | membus_rd_rs_p0_1; - - - apr apr0( - .clk(clk), - .reset(reset), - - .key_start(key_start), - .key_read_in(key_read_in), - .key_mem_cont(key_mem_cont), - .key_inst_cont(key_inst_cont), - .key_mem_stop(key_mem_stop), - .key_inst_stop(key_inst_stop), - .key_exec(key_exec), - .key_io_reset(key_io_reset), - .key_dep(key_dep), - .key_dep_nxt(key_dep_nxt), - .key_ex(key_ex), - .key_ex_nxt(key_ex_nxt), - - .sw_addr_stop(sw_addr_stop), - .sw_mem_disable(sw_mem_disable), - .sw_repeat(sw_repeat), - .sw_power(sw_power), - .datasw(datasw), - .mas(mas), - - .sw_rim_maint(sw_rim_maint), - .sw_repeat_bypass(sw_repeat_bypass), - .sw_art3_maint(sw_art3_maint), - .sw_sct_maint(sw_sct_maint), - .sw_split_cyc(sw_split_cyc), - - .ir(ir), - .mi(mi), - .ar(ar), - .mb(mb), - .mq(mq), - .pc(pc), - .ma(ma), - .run(run), - .mc_stop(mc_stop), - .pi_active(pi_active), - .pih(pih), - .pir(pir), - .pio(pio), - .pr(pr), - .rlr(rlr), - .rla(rla), - - .membus_wr_rs(membus_wr_rs_p0), - .membus_rq_cyc(membus_rq_cyc_p0), - .membus_rd_rq(membus_rd_rq_p0), - .membus_wr_rq(membus_wr_rq_p0), - .membus_ma(membus_ma_p0), - .membus_sel(membus_sel_p0), - .membus_fmc_select(membus_fmc_select_p0), - .membus_mb_out(membus_mb_out_p0_p), - .membus_addr_ack(membus_addr_ack_p0), - .membus_rd_rs(membus_rd_rs_p0), - .membus_mb_in(membus_mb_in_p0), - - .iobus_iob_poweron(iobus_iob_poweron), - .iobus_iob_reset(iobus_iob_reset), - .iobus_datao_clear(iobus_datao_clear), - .iobus_datao_set(iobus_datao_set), - .iobus_cono_clear(iobus_cono_clear), - .iobus_cono_set(iobus_cono_set), - .iobus_iob_fm_datai(iobus_iob_fm_datai), - .iobus_iob_fm_status(iobus_iob_fm_status), - .iobus_ios(iobus_ios), - .iobus_iob_out(iobus_iob_out), - .iobus_pi_req(iobus_pi_req), - .iobus_iob_in(iobus_iob_in) - ); - - reg mem0_sw_single_step; - reg mem0_sw_restart; - - fast162 - #(.memsel_p0(4'b0), .memsel_p1(4'b0), - .memsel_p2(4'b0), .memsel_p3(4'b0), - .fmc_p0_sel(1'b1), .fmc_p1_sel(1'b0), - .fmc_p2_sel(1'b0), .fmc_p3_sel(1'b0)) - fmem0( - .clk(clk), - .reset(reset), - .power(sw_power), - .sw_single_step(mem0_sw_single_step), - .sw_restart(mem0_sw_restart), - - .membus_wr_rs_p0(membus_wr_rs_p0), - .membus_rq_cyc_p0(membus_rq_cyc_p0), - .membus_rd_rq_p0(membus_rd_rq_p0), - .membus_wr_rq_p0(membus_wr_rq_p0), - .membus_ma_p0(membus_ma_p0), - .membus_sel_p0(membus_sel_p0), - .membus_fmc_select_p0(membus_fmc_select_p0), - .membus_mb_in_p0(membus_mb_in_p0), - .membus_addr_ack_p0(membus_addr_ack_p0_0), - .membus_rd_rs_p0(membus_rd_rs_p0_0), - .membus_mb_out_p0(membus_mb_out_p0_0), - - .membus_rq_cyc_p1(1'b0), - .membus_sel_p1(4'b0), - .membus_fmc_select_p1(1'b0), - - .membus_rq_cyc_p2(1'b0), - .membus_sel_p2(4'b0), - .membus_fmc_select_p2(1'b0), - - .membus_rq_cyc_p3(1'b0), - .membus_sel_p3(4'b0), - .membus_fmc_select_p3(1'b0) - ); - - core161c - #(.memsel_p0(4'b0), .memsel_p1(4'b0), - .memsel_p2(4'b0), .memsel_p3(4'b0)) - mem0( - .clk(clk), - .reset(reset), - .power(sw_power), - .sw_single_step(mem0_sw_single_step), - .sw_restart(mem0_sw_restart), - - .membus_wr_rs_p0(membus_wr_rs_p0), - .membus_rq_cyc_p0(membus_rq_cyc_p0), - .membus_rd_rq_p0(membus_rd_rq_p0), - .membus_wr_rq_p0(membus_wr_rq_p0), - .membus_ma_p0(membus_ma_p0), - .membus_sel_p0(membus_sel_p0), - .membus_fmc_select_p0(membus_fmc_select_p0), - .membus_mb_in_p0(membus_mb_in_p0), - .membus_addr_ack_p0(membus_addr_ack_p0_1), - .membus_rd_rs_p0(membus_rd_rs_p0_1), - .membus_mb_out_p0(membus_mb_out_p0_1), - - .membus_rq_cyc_p1(1'b0), - .membus_sel_p1(4'b0), - .membus_fmc_select_p1(1'b0), - - .membus_rq_cyc_p2(1'b0), - .membus_sel_p2(4'b0), - .membus_fmc_select_p2(1'b0), - - .membus_rq_cyc_p3(1'b0), - .membus_sel_p3(4'b0), - .membus_fmc_select_p3(1'b0) - ); - -endmodule diff --git a/verilog/ptp.v b/verilog/ptp.v new file mode 100644 index 0000000..fdc8f06 --- /dev/null +++ b/verilog/ptp.v @@ -0,0 +1,185 @@ +module ptp( + input wire clk, + input wire reset, + + /* IO bus */ + input wire iobus_iob_poweron, + input wire iobus_iob_reset, + input wire iobus_datao_clear, + input wire iobus_datao_set, + input wire iobus_cono_clear, + input wire iobus_cono_set, + input wire iobus_iob_fm_datai, + input wire iobus_iob_fm_status, + input wire [3:9] iobus_ios, + input wire [0:35] iobus_iob_in, + output wire [1:7] iobus_pi_req, + output wire [0:35] iobus_iob_out, + + /* Console panel */ + input wire key_tape_feed, + output wire [7:0] ptp_ind, + output wire [6:0] status_ind, // also includes motor on + + /* Avalon slave */ + input wire s_read, + output wire [31:0] s_readdata, + + output wire fe_data_rq +); + assign ptp_ind = ptp; + assign status_ind = { ptp_speed, ptp_b, ptp_busy, ptp_flag, ptp_pia }; + + + wire ptp_sel = iobus_ios == 7'b001_000_0; + + wire ptp_data_clr; + wire ptp_data_set; + wire ptp_ic_clr; + wire ptp_ic_set; + wire iob_reset; + wire ptp_datai = ptp_sel & iobus_iob_fm_datai; + wire ptp_status = ptp_sel & iobus_iob_fm_status; + wire ptp_start_clr, ptp_stop_clr; + wire ptp_busy_set; + pa ptp_pa0(clk, reset, ptp_sel & iobus_datao_clear, ptp_data_clr); + pa ptp_pa1(clk, reset, ptp_sel & iobus_datao_set, ptp_data_set); + pa ptp_pa2(clk, reset, ptp_sel & iobus_cono_clear | iob_reset, ptp_ic_clr); + pa ptp_pa3(clk, reset, ptp_sel & iobus_cono_set, ptp_ic_set); + pa ptp_pa4(clk, reset, iobus_iob_reset, iob_reset); + + reg [8:1] ptp; + + assign iobus_iob_out = + ptp_status ? { 30'b0, ptp_b, ptp_busy, ptp_flag, ptp_pia } : + 36'b0; + + wire [1:7] ptp_req = { ptp_flag, 7'b0 } >> ptp_pia; + assign iobus_pi_req = ptp_req; + + reg [33:35] ptp_pia; + reg ptp_busy; + reg ptp_flag; + reg ptp_b; + +`ifdef simulation + initial begin + ptp_busy <= 0; + ptp_flag <= 0; + ptp_b <= 0; + end +`endif + + always @(posedge clk) begin + if(ptp_ic_clr) begin + ptp_pia <= 0; + ptp_busy <= 0; + ptp_flag <= 0; + ptp_b <= 0; + end + if(ptp_ic_set) begin + ptp_pia <= iobus_iob_in[33:35]; + if(iobus_iob_in[32]) + ptp_flag <= 1; + if(iobus_iob_in[31]) + ptp_busy <= 1; + if(iobus_iob_in[30]) + ptp_b <= 1; + end + + if(ptp_data_clr) begin + ptp_busy <= 1; + ptp_flag <= 0; + end + if(ptp_done) begin + ptp_busy <= 0; + ptp_flag <= 1; + end + + if(ptp_b) + ptp[8:7] <= 2'b10; + if(ptp_data_clr) + ptp <= 0; + if(ptp_data_set) + ptp <= ptp | iobus_iob_in[28:35]; + end + + + wire ptp_go = ptp_busy | key_tape_feed; + + wire start_dly; + wire motor_on, on_pulse; + wire scr_driver = motor_on; // TODO: PWR CLR + + wire ptp_done; + wire ptp_speed = ~start_dly & motor_on_dly[1]; + wire ptp_ready = ptp_speed & ptp_busy; +`ifdef simulation + ldly2us ptp_dly0(.clk(clk), .reset(reset), .in(ptp_go), .l(motor_on)); + ldly1us ptp_dly1(.clk(clk), .reset(reset), .in(on_pulse), .l(start_dly)); +`else + ldly5s ptp_dly0(.clk(clk), .reset(reset), .in(ptp_go), .l(motor_on)); + ldly1s ptp_dly1(.clk(clk), .reset(reset), .in(on_pulse), .l(start_dly)); +`endif + + pa ptp_pa5(clk, reset, motor_on, on_pulse); + + /* Have to delay the signal a bit so we don't get a glitch in ptp_speed */ + reg [1:0] motor_on_dly; + always @(posedge clk) + if(reset) + motor_on_dly <= 0; + else + motor_on_dly <= { motor_on_dly[0], motor_on }; + + + // front end interface + assign fe_data_rq = fe_req; + assign s_readdata = (ptp_busy & ptp_write_sync) ? ptp : 0; + reg fe_req; + reg fe_rs; + wire ptp_clk; + // write gates buffer to solenoid drivers, done_pulse when done + wire ptp_write; + wire ptp_done_pulse; + // want to synchronize with the FE, so we'll actually use these two + reg ptp_write_sync; + reg ptp_done_sync; + +`ifdef simulation + clk50khz ptp_clk0(clk, ptp_clk); + ldly2us ptp_dly2(clk, reset, ptp_clk & ptp_ready, ptp_done_pulse, ptp_write); +`else + clk63_3hz ptp_clk0(clk, ptp_clk); + ldly5ms ptp_dly2(clk, reset, ptp_clk & ptp_ready, ptp_done_pulse, ptp_write); +`endif + pa ptp_pa6(clk, reset, fe_rs & ptp_done_sync, ptp_done); + + always @(posedge clk) begin + if(reset) begin + ptp_write_sync <= 0; + ptp_done_sync <= 0; + fe_req <= 0; + fe_rs <= 0; + end else begin + if(ptp_clk & (ptp_ready | key_tape_feed & ptp_speed)) begin + fe_req <= 1; + fe_rs <= 0; + end + if(s_read) begin + fe_req <= 0; + fe_rs <= 1; + end + + if(ptp_done_pulse) + ptp_done_sync <= 1; + if(ptp_done) begin + ptp_write_sync <= 0; + ptp_done_sync <= 0; + end + if(ptp_write) + ptp_write_sync <= 1; + end + end + +endmodule diff --git a/verilog/ptr.v b/verilog/ptr.v new file mode 100644 index 0000000..aec6a3e --- /dev/null +++ b/verilog/ptr.v @@ -0,0 +1,195 @@ +module ptr( + input wire clk, + input wire reset, + + /* IO bus */ + input wire iobus_iob_poweron, + input wire iobus_iob_reset, + input wire iobus_datao_clear, + input wire iobus_datao_set, + input wire iobus_cono_clear, + input wire iobus_cono_set, + input wire iobus_iob_fm_datai, + input wire iobus_iob_fm_status, + input wire [3:9] iobus_ios, + input wire [0:35] iobus_iob_in, + output wire [1:7] iobus_pi_req, + output wire [0:35] iobus_iob_out, + + /* Console panel */ + input wire key_start, + input wire key_stop, + input wire key_tape_feed, + output wire [35:0] ptr_ind, + output wire [6:0] status_ind, // also includes motor on + + /* Avalon slave */ + input wire s_write, + input wire [31:0] s_writedata, + + output wire fe_data_rq +); + assign ptr_ind = ptr; + assign status_ind = { motor_on, ptr_b, ptr_busy, ptr_flag, ptr_pia }; + + + wire ptr_sel = iobus_ios == 7'b001_000_1; + + wire [8:1] stb_hole = ptr_b ? { 2'b0, hole[6:1] } : hole[8:1]; + + wire ptr_data_clr; + wire ptr_data_set; + wire ptr_ic_clr; + wire ptr_ic_set; + wire iob_reset; + wire ptr_datai = ptr_sel & iobus_iob_fm_datai; + wire ptr_status = ptr_sel & iobus_iob_fm_status; + wire ptr_start_clr, ptr_stop_clr; + wire ptr_busy_set; + pa ptr_pa0(clk, reset, ptr_sel & iobus_datao_clear, ptr_data_clr); + pa ptr_pa1(clk, reset, ptr_sel & iobus_datao_set, ptr_data_set); + pa ptr_pa2(clk, reset, ptr_sel & iobus_cono_clear | iob_reset, ptr_ic_clr); + pa ptr_pa3(clk, reset, ptr_sel & iobus_cono_set, ptr_ic_set); + pa ptr_pa4(clk, reset, iobus_iob_reset, iob_reset); + pg ptr_pg0(clk, reset, motor_on, ptr_start_clr); + pg ptr_pg1(clk, reset, ~motor_on, ptr_stop_clr); + pa ptr_pa5(clk, reset, ~ptr_datai, ptr_busy_set); // CDG actually + + wire ptr_clr; + pa ptr_pa6(clk, reset, ptr_busy, ptr_clr); + + reg [36:31] ptr_sr; // actually 36,30,24,18,12,6 + reg [35:0] ptr; + reg motor_on = 0; + wire ptr_lead; + wire ptr_mid; // mid hole, this is where the strobe happens. + // normally 400μs after leading edge of feed hole + wire ptr_strobe = ptr_mid & (~ptr_b | hole[8]); + wire ptr_trail; + + assign iobus_iob_out = + ptr_datai ? ptr : + ptr_status ? { 27'b0, motor_on, 2'b0, ptr_b, ptr_busy, ptr_flag, ptr_pia } : + 36'b0; + + wire [1:7] ptr_req = { ptr_flag, 7'b0 } >> ptr_pia; + assign iobus_pi_req = ptr_req; + + reg [33:35] ptr_pia; + reg ptr_busy; + reg ptr_flag; + reg ptr_b; + +`ifdef simulation + initial begin + ptr_busy <= 0; + ptr_flag <= 0; + ptr_b <= 0; + end +`endif + + always @(posedge clk) begin + if(ptr_ic_clr) begin + ptr_pia <= 0; + ptr_busy <= 0; + ptr_flag <= 0; + ptr_b <= 0; + end + if(ptr_ic_set) begin + ptr_pia <= iobus_iob_in[33:35]; + if(iobus_iob_in[32]) + ptr_flag <= 1; + if(iobus_iob_in[31]) + ptr_busy <= 1; + if(iobus_iob_in[30]) + ptr_b <= 1; + end + + if(ptr_busy_set) + ptr_busy <= 1; + if(ptr_start_clr) + ptr_busy <= 0; + + if(ptr_start_clr | ptr_stop_clr) + ptr_flag <= 1; + if(ptr_datai) + ptr_flag <= 0; + + if(ptr_trail & ptr_busy & (~ptr_b | ptr_sr[36])) begin + ptr_busy <= 0; + ptr_flag <= 1; + end + + if(ptr_clr) begin + ptr <= 0; + ptr_sr <= 0; + end + + if(ptr_strobe) begin + ptr_sr <= { ptr_sr[35:31], 1'b1 }; + ptr <= { ptr[29:0], 6'b0 } | stb_hole; + end + + if(key_start) + motor_on <= 1; + if(key_stop | reset) + motor_on <= 0; + end + + + // front end interface + assign fe_data_rq = fe_req; + wire moving = motor_on & (key_tape_feed | ptr_busy); + reg fe_req; // requesting data from FE + reg fe_rs; // FE responded with data + reg [8:1] hole; // FE data + reg mid_sync; // set when mid hole + reg trail_sync; // set when trailing edge of feed hole would happen + + wire start_signal = ~moving | ptr_trail; + wire start_pulse; + dly50ns fe_dly3(clk, reset, start_signal, start_pulse); + + wire fe_mid_pulse, fe_trail_pulse; +`ifdef simulation + dly200ns fe_dly0(clk, reset, start_signal, ptr_lead); + dly800ns fe_dly1(clk, reset, start_signal, fe_mid_pulse); + dly1us fe_dly2(clk, reset, start_signal, fe_trail_pulse); +`else + dly1us fe_dly0(clk, reset, start_signal, ptr_lead); + dly2_1ms fe_dly1(clk, reset, start_signal, fe_mid_pulse); + dly2_5ms fe_dly2(clk, reset, start_signal, fe_trail_pulse); +`endif + + pa fe_pa0(clk, reset, fe_rs & mid_sync & ptr_busy, ptr_mid); + pa fe_pa1(clk, reset, fe_rs & trail_sync, ptr_trail); + + always @(posedge clk) begin + if(~moving | start_pulse) begin + fe_req <= 0; + fe_rs <= 0; + hole <= 0; + mid_sync <= 0; + trail_sync <= 0; + end + + + // start FE request + if(ptr_lead) + fe_req <= 1; + // got response from FE + if(s_write & fe_req) begin + hole <= s_writedata[7:0]; + fe_req <= 0; + fe_rs <= 1; + end + if(fe_mid_pulse) + mid_sync <= 1; + if(fe_trail_pulse) + trail_sync <= 1; + // all done + if(ptr_trail) + fe_rs <= 0; + end + +endmodule diff --git a/verilog/quartus/apr_test.v b/verilog/quartus/apr_test.v deleted file mode 100644 index c6c8d3b..0000000 --- a/verilog/quartus/apr_test.v +++ /dev/null @@ -1,244 +0,0 @@ -// UNUSED - -module apr( - input wire clk, - input wire reset, - input wire key_start, - input wire key_read_in, - input wire key_inst_cont, - input wire key_mem_cont, - input wire key_inst_stop, - input wire key_mem_stop, - input wire key_io_reset, - input wire key_exec, - input wire key_dep, - input wire key_dep_nxt, - input wire key_ex, - input wire key_ex_nxt, - - input wire sw_repeat, - input wire sw_addr_stop, - input wire sw_power, - input wire sw_mem_disable, - input wire [0:35] datasw, - input wire [18:35] mas, - - input wire sw_rim_maint, - input wire sw_repeat_bypass, - input wire sw_art3_maint, - input wire sw_sct_maint, - input wire sw_split_cyc, - - output reg [0:17] ir, - output reg [0:35] mi, - output reg [0:35] ar, - output reg [0:35] mb, - output reg [0:35] mq, - output reg [18:35] pc, - output reg [18:35] ma, - output reg run, - output reg mc_stop, - output reg pi_active, - output reg [1:7] pih, - output reg [1:7] pir, - output reg [1:7] pio, - output reg [18:25] pr, - output reg [18:25] rlr, - output reg [18:25] rla, - output wire [0:7] ff0, - output wire [0:7] ff1, - output wire [0:7] ff2, - output wire [0:7] ff3, - output wire [0:7] ff4, - output wire [0:7] ff5, - output wire [0:7] ff6, - output wire [0:7] ff7, - output wire [0:7] ff8, - output wire [0:7] ff9, - output wire [0:7] ff10, - output wire [0:7] ff11, - output wire [0:7] ff12, - output wire [0:7] ff13, - - // membus - output wire membus_wr_rs, - output wire membus_rq_cyc, - output wire membus_rd_rq, - output wire membus_wr_rq, - output wire [21:35] membus_ma, - output wire [18:21] membus_sel, - output wire membus_fmc_select, - output wire [0:35] membus_mb_out, - input wire membus_addr_ack, - input wire membus_rd_rs, - input wire [0:35] membus_mb_in, - - // IO bus - output wire iobus_iob_poweron, - output wire iobus_iob_reset, - output wire iobus_datao_clear, - output wire iobus_datao_set, - output wire iobus_cono_clear, - output wire iobus_cono_set, - output wire iobus_iob_fm_datai, - output wire iobus_iob_fm_status, - output wire [3:9] iobus_ios, - output wire [0:35] iobus_iob_out, - input wire [1:7] iobus_pi_req, - input wire [0:35] iobus_iob_in -); - - wire key_any = key_start | key_read_in | key_inst_cont | key_mem_cont | key_inst_stop | key_mem_stop | key_ex | key_ex_nxt | key_dep | key_dep_nxt; - wire key_pulse; - pg pg0(.clk(clk), .reset(reset), - .in(key_any), - .p(key_pulse)); - - assign ff1 = 2; - assign ff2 = 3; - assign ff3 = 4; - assign ff4 = 5; - assign ff5 = 6; - assign ff6 = 7; - assign ff7 = 8; - assign ff8 = 9; - assign ff9 = 10; - assign ff10 = 11; - assign ff11 = 12; - assign ff12 = 13; - assign ff13 = 14; - - //initial begin - // mb <= 36'o111111111111; - // ar <= 36'o222222222222; - // mq <= 36'o333333333333; - // mi <= 36'o444444444444; - // ir <= 18'o555555; - // ma <= 18'o666666; - // pc <= 18'o777777; - //end - - - wire kt0, kt1, kt2; - wire key_rd, key_wr; - pa key_pa0(.clk(clk), .reset(reset), - .in(key_pulse), - .p(kt0)); - pa key_pa1(.clk(clk), .reset(reset), - .in(mc_rs_t1 & key_rdwr), - .p(kt2)); - - dly200ns dly0(.clk(clk), .reset(reset), - .in(kt0), - .p(kt1)); - dly200ns dly1(.clk(clk), .reset(reset), - .in(kt1 & (key_ex | key_ex_nxt)), - .p(key_rd)); - dly200ns dly2(.clk(clk), .reset(reset), - .in(kt1 & (key_dep | key_dep_nxt)), - .p(key_wr)); - - always @(posedge clk) begin - if(kt0 & (key_ex | key_dep)) - ma <= 0; - if(kt0 & (key_ex_nxt | key_dep_nxt)) - ma <= ma + 18'b1; - if(kt0 & (key_dep | key_dep_nxt)) - ar <= 0; - - if(kt1 & (key_ex | key_dep)) - ma <= ma | mas; - if(kt1 & (key_dep | key_dep_nxt)) - ar <= ar | datasw; - - if(key_rd | key_wr) - key_rdwr <= 1; - if(kt2) - key_rdwr <= 0; - end - - - assign membus_rq_cyc = mc_rq & (mc_rd | mc_wr); - assign membus_rd_rq = mc_rd; - assign membus_wr_rq = mc_wr; - assign membus_ma = ma[21:35]; - assign membus_sel = 0; - assign membus_fmc_select = sw_rim_maint; - - assign membus_mb_out = mc_membus_fm_mb1 ? mb : 0; - - wire mai_addr_ack, mai_rd_rs; - wire mb_pulse; - pg mc_pg0(.clk(clk), .reset(reset), - .in(membus_addr_ack), .p(mai_addr_ack)); - pg mc_pg1(.clk(clk), .reset(reset), - .in(membus_rd_rs), .p(mai_rd_rs)); - pg mc_pg2(.clk(clk), .reset(reset), - .in(| membus_mb_in), - .p(mb_pulse)); - - wire mc_wr_rs, mc_membus_fm_mb1; - bd mc_bd0(.clk(clk), .reset(reset), .in(mc_wr_rs), .p(membus_wr_rs)); - bd2 mb_bd1(.clk(clk), .reset(reset), .in(mc_wr_rs), .p(mc_membus_fm_mb1)); - - - reg key_rdwr = 0; - reg mc_rd = 0, mc_wr = 0, mc_rq = 0; - - wire mc_addr_ack; - wire mc_rd_rq_pulse, mc_wr_rq_pulse, mc_rq_pulse; - wire mc_rs_t0, mc_rs_t1; - pa mc_pa1(.clk(clk), .reset(reset), - .in(key_rd), - .p(mc_rd_rq_pulse)); - pa mc_pa2(.clk(clk), .reset(reset), - .in(key_wr), - .p(mc_wr_rq_pulse)); - pa mc_pa3(.clk(clk), .reset(reset), - .in(mc_rd_rq_pulse | mc_wr_rq_pulse), - .p(mc_rq_pulse)); - pa mc_pa4(.clk(clk), .reset(reset), - .in(mai_rd_rs | mc_wr_rs), - .p(mc_rs_t0)); - pa mc_pa5(.clk(clk), .reset(reset), - .in(mc_rs_t0), - .p(mc_rs_t1)); - pa mc_pa6(.clk(clk), .reset(reset), - .in(mai_addr_ack), - .p(mc_addr_ack)); - pa mc_pa7(.clk(clk), .reset(reset), - .in(mc_addr_ack & ~mc_rd & mc_wr), - .p(mc_wr_rs)); - - - reg f0 = 0; - reg f1 = 0; - always @(posedge clk) begin - if(mc_rd_rq_pulse) begin - mc_rd <= 1; - mc_wr <= 0; - mb <= 0; - end - if(mc_wr_rq_pulse) begin - mc_rd <= 0; - mc_wr <= 1; - end - if(mc_rq_pulse) - mc_rq <= 1; - - if(mc_addr_ack) - mc_rq <= 0; - if(mai_rd_rs) - f1 <= 1; - if(mb_pulse & mc_rd) - mb <= mb | membus_mb_in; - if(mc_rs_t1) - mc_rd <= 0; - - if(key_wr) - mb <= ar; - end - - assign ff0 = { 2'b0, f0, f1, key_rdwr, mc_rd, mc_wr, mc_rq }; - -endmodule diff --git a/verilog/quartus/fpdpga6.cdf b/verilog/quartus/fpdpga6.cdf deleted file mode 100644 index c5caeb7..0000000 --- a/verilog/quartus/fpdpga6.cdf +++ /dev/null @@ -1,13 +0,0 @@ -/* Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition */ -JedecChain; - FileRevision(JESD32A); - DefaultMfr(6E); - - P ActionCode(Cfg) - Device PartName(5CGXFC5C6F27) Path("C:/Users/aap/src/pdp6/verilog/quartus/output_files/") File("fpdpga6.sof") MfrSpec(OpMask(1)); - -ChainEnd; - -AlteraBegin; - ChainType(JTAG); -AlteraEnd; diff --git a/verilog/quartus/fpdpga6.qpf b/verilog/quartus/fpdpga6.qpf deleted file mode 100644 index 8c7bfd3..0000000 --- a/verilog/quartus/fpdpga6.qpf +++ /dev/null @@ -1,31 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 2016 Intel Corporation. All rights reserved. -# Your use of Intel Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Intel Program License -# Subscription Agreement, the Intel Quartus Prime License Agreement, -# the Intel MegaCore Function License Agreement, or other -# applicable license agreement, including, without limitation, -# that your use is for the sole purpose of programming logic -# devices manufactured by Intel and sold by Intel or its -# authorized distributors. Please refer to the applicable -# agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus Prime -# Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition -# Date created = 10:24:53 December 02, 2016 -# -# -------------------------------------------------------------------------- # - -QUARTUS_VERSION = "16.1" -DATE = "10:24:53 December 02, 2016" - -# Revisions - -PROJECT_REVISION = "fpdpga6" diff --git a/verilog/quartus/fpdpga6.qsf b/verilog/quartus/fpdpga6.qsf deleted file mode 100644 index 8e4559c..0000000 --- a/verilog/quartus/fpdpga6.qsf +++ /dev/null @@ -1,208 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 2016 Intel Corporation. All rights reserved. -# Your use of Intel Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Intel Program License -# Subscription Agreement, the Intel Quartus Prime License Agreement, -# the Intel MegaCore Function License Agreement, or other -# applicable license agreement, including, without limitation, -# that your use is for the sole purpose of programming logic -# devices manufactured by Intel and sold by Intel or its -# authorized distributors. Please refer to the applicable -# agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus Prime -# Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition -# Date created = 10:24:53 December 02, 2016 -# -# -------------------------------------------------------------------------- # -# -# Notes: -# -# 1) The default values for assignments are stored in the file: -# fpdpga6_assignment_defaults.qdf -# If this file doesn't exist, see file: -# assignment_defaults.qdf -# -# 2) Altera recommends that you do not modify this file. This -# file is updated automatically by the Quartus Prime software -# and any changes you make may be lost or overwritten. -# -# -------------------------------------------------------------------------- # - - -set_global_assignment -name FAMILY "Cyclone V" -set_global_assignment -name DEVICE 5CGXFC5C6F27C7 -set_global_assignment -name TOP_LEVEL_ENTITY fpdpga6 -set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.0 -set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:24:53 DECEMBER 02, 2016" -set_global_assignment -name LAST_QUARTUS_VERSION "16.1.0 Lite Edition" -set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files -set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 -set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 -set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256 -set_global_assignment -name VERILOG_FILE fpdpga6.v -set_global_assignment -name VERILOG_FILE i2c.v -set_global_assignment -name VERILOG_FILE i2c_core.v -set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top -set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top -set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top -set_location_assignment PIN_P11 -to key[0] -set_location_assignment PIN_P12 -to key[1] -set_location_assignment PIN_Y15 -to key[2] -set_location_assignment PIN_Y16 -to key[3] -set_location_assignment PIN_AB24 -to key[4] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to key[4] -set_instance_assignment -name IO_STANDARD "1.2 V" -to key[3] -set_instance_assignment -name IO_STANDARD "1.2 V" -to key[2] -set_instance_assignment -name IO_STANDARD "1.2 V" -to key[1] -set_instance_assignment -name IO_STANDARD "1.2 V" -to key[0] -set_location_assignment PIN_R20 -to clk -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to clk -set_location_assignment PIN_B25 -to sram_a[0] -set_location_assignment PIN_B26 -to sram_a[1] -set_location_assignment PIN_H19 -to sram_a[2] -set_location_assignment PIN_H20 -to sram_a[3] -set_location_assignment PIN_D25 -to sram_a[4] -set_location_assignment PIN_C25 -to sram_a[5] -set_location_assignment PIN_J20 -to sram_a[6] -set_location_assignment PIN_J21 -to sram_a[7] -set_location_assignment PIN_D22 -to sram_a[8] -set_location_assignment PIN_E23 -to sram_a[9] -set_location_assignment PIN_G20 -to sram_a[10] -set_location_assignment PIN_F21 -to sram_a[11] -set_location_assignment PIN_E21 -to sram_a[12] -set_location_assignment PIN_F22 -to sram_a[13] -set_location_assignment PIN_J25 -to sram_a[14] -set_location_assignment PIN_J26 -to sram_a[15] -set_location_assignment PIN_N24 -to sram_a[16] -set_location_assignment PIN_M24 -to sram_a[17] -set_location_assignment PIN_E24 -to sram_d[0] -set_location_assignment PIN_E25 -to sram_d[1] -set_location_assignment PIN_K24 -to sram_d[2] -set_location_assignment PIN_K23 -to sram_d[3] -set_location_assignment PIN_F24 -to sram_d[4] -set_location_assignment PIN_G24 -to sram_d[5] -set_location_assignment PIN_L23 -to sram_d[6] -set_location_assignment PIN_L24 -to sram_d[7] -set_location_assignment PIN_H23 -to sram_d[8] -set_location_assignment PIN_H24 -to sram_d[9] -set_location_assignment PIN_H22 -to sram_d[10] -set_location_assignment PIN_J23 -to sram_d[11] -set_location_assignment PIN_F23 -to sram_d[12] -set_location_assignment PIN_G22 -to sram_d[13] -set_location_assignment PIN_L22 -to sram_d[14] -set_location_assignment PIN_K21 -to sram_d[15] -set_location_assignment PIN_N23 -to sram_ce -set_location_assignment PIN_H25 -to sram_lb -set_location_assignment PIN_G25 -to sram_we -set_location_assignment PIN_M25 -to sram_ub -set_location_assignment PIN_M22 -to sram_oe -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_a[17] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_a[16] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_a[15] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_a[14] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_a[13] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_a[12] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_a[11] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_a[10] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_a[9] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_a[8] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_we -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_ub -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_oe -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_lb -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_d[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_d[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_d[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_d[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_d[4] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_d[5] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_d[6] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_d[7] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_d[8] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_d[9] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_d[10] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_d[11] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_d[12] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_d[13] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_d[14] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_d[15] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_d -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_ce -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_a[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_a[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_a[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_a[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_a[4] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_a[5] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_a[6] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_a[7] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_a -set_location_assignment PIN_AC9 -to sw[0] -set_location_assignment PIN_AE10 -to sw[1] -set_location_assignment PIN_AD13 -to sw[2] -set_location_assignment PIN_AC8 -to sw[3] -set_location_assignment PIN_W11 -to sw[4] -set_location_assignment PIN_AB10 -to sw[5] -set_location_assignment PIN_V10 -to sw[6] -set_location_assignment PIN_AC10 -to sw[7] -set_location_assignment PIN_Y11 -to sw[8] -set_location_assignment PIN_AE19 -to sw[9] -set_instance_assignment -name IO_STANDARD "1.2 V" -to sw[9] -set_instance_assignment -name IO_STANDARD "1.2 V" -to sw[0] -set_instance_assignment -name IO_STANDARD "1.2 V" -to sw[1] -set_instance_assignment -name IO_STANDARD "1.2 V" -to sw[2] -set_instance_assignment -name IO_STANDARD "1.2 V" -to sw[3] -set_instance_assignment -name IO_STANDARD "1.2 V" -to sw[4] -set_instance_assignment -name IO_STANDARD "1.2 V" -to sw[5] -set_instance_assignment -name IO_STANDARD "1.2 V" -to sw[6] -set_instance_assignment -name IO_STANDARD "1.2 V" -to sw[7] -set_instance_assignment -name IO_STANDARD "1.2 V" -to sw[8] -set_instance_assignment -name IO_STANDARD "1.2 V" -to sw -set_location_assignment PIN_F7 -to ledr[0] -set_location_assignment PIN_F6 -to ledr[1] -set_location_assignment PIN_G6 -to ledr[2] -set_location_assignment PIN_G7 -to ledr[3] -set_location_assignment PIN_J8 -to ledr[4] -set_location_assignment PIN_J7 -to ledr[5] -set_location_assignment PIN_K10 -to ledr[6] -set_location_assignment PIN_K8 -to ledr[7] -set_location_assignment PIN_H7 -to ledr[8] -set_location_assignment PIN_J10 -to ledr[9] -set_location_assignment PIN_L7 -to ledg[0] -set_location_assignment PIN_K6 -to ledg[1] -set_location_assignment PIN_D8 -to ledg[2] -set_location_assignment PIN_E9 -to ledg[3] -set_location_assignment PIN_A5 -to ledg[4] -set_location_assignment PIN_B6 -to ledg[5] -set_location_assignment PIN_H8 -to ledg[6] -set_location_assignment PIN_H9 -to ledg[7] -set_location_assignment PIN_K25 -to scl -set_location_assignment PIN_E26 -to sda -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to scl -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sda -set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" -set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON -set_global_assignment -name NUM_PARALLEL_PROCESSORS 2 -set_global_assignment -name CDF_FILE output_files/fpdpga6.cdf -set_global_assignment -name ENABLE_SIGNALTAP ON -set_global_assignment -name USE_SIGNALTAP_FILE output_files/test.stp -set_global_assignment -name SIGNALTAP_FILE output_files/test.stp -set_global_assignment -name VERILOG_FILE uart.v -set_location_assignment PIN_K26 -to rx -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to rx -set_location_assignment PIN_M26 -to tx -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to tx -set_global_assignment -name VERILOG_FILE ../apr.v -set_global_assignment -name VERILOG_FILE ../core161c.v -set_global_assignment -name VERILOG_FILE ../fast162.v -set_global_assignment -name VERILOG_FILE ../modules.v -set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/verilog/quartus/fpdpga6.sdc b/verilog/quartus/fpdpga6.sdc deleted file mode 100644 index 519e013..0000000 --- a/verilog/quartus/fpdpga6.sdc +++ /dev/null @@ -1,116 +0,0 @@ -## Generated SDC file "fpdpga6.sdc" - -## Copyright (C) 2016 Intel Corporation. All rights reserved. -## Your use of Intel Corporation's design tools, logic functions -## and other software and tools, and its AMPP partner logic -## functions, and any output files from any of the foregoing -## (including device programming or simulation files), and any -## associated documentation or information are expressly subject -## to the terms and conditions of the Intel Program License -## Subscription Agreement, the Intel Quartus Prime License Agreement, -## the Intel MegaCore Function License Agreement, or other -## applicable license agreement, including, without limitation, -## that your use is for the sole purpose of programming logic -## devices manufactured by Intel and sold by Intel or its -## authorized distributors. Please refer to the applicable -## agreement for further details. - - -## VENDOR "Altera" -## PROGRAM "Quartus Prime" -## VERSION "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition" - -## DATE "Fri Dec 02 10:55:33 2016" - -## -## DEVICE "5CGXFC5C6F27C7" -## - - -#************************************************************** -# Time Information -#************************************************************** - -set_time_format -unit ns -decimal_places 3 - - - -#************************************************************** -# Create Clock -#************************************************************** - -create_clock -name {clk} -period 20.000 -waveform { 0.000 10.000 } [get_ports {clk}] - - -#************************************************************** -# Create Generated Clock -#************************************************************** - - - -#************************************************************** -# Set Clock Latency -#************************************************************** - - - -#************************************************************** -# Set Clock Uncertainty -#************************************************************** - -set_clock_uncertainty -rise_from [get_clocks {clk}] -rise_to [get_clocks {clk}] -setup 0.100 -set_clock_uncertainty -rise_from [get_clocks {clk}] -rise_to [get_clocks {clk}] -hold 0.060 -set_clock_uncertainty -rise_from [get_clocks {clk}] -fall_to [get_clocks {clk}] -setup 0.100 -set_clock_uncertainty -rise_from [get_clocks {clk}] -fall_to [get_clocks {clk}] -hold 0.060 -set_clock_uncertainty -fall_from [get_clocks {clk}] -rise_to [get_clocks {clk}] -setup 0.100 -set_clock_uncertainty -fall_from [get_clocks {clk}] -rise_to [get_clocks {clk}] -hold 0.060 -set_clock_uncertainty -fall_from [get_clocks {clk}] -fall_to [get_clocks {clk}] -setup 0.100 -set_clock_uncertainty -fall_from [get_clocks {clk}] -fall_to [get_clocks {clk}] -hold 0.060 - - -#************************************************************** -# Set Input Delay -#************************************************************** - - - -#************************************************************** -# Set Output Delay -#************************************************************** - - - -#************************************************************** -# Set Clock Groups -#************************************************************** - - - -#************************************************************** -# Set False Path -#************************************************************** - - - -#************************************************************** -# Set Multicycle Path -#************************************************************** - - - -#************************************************************** -# Set Maximum Delay -#************************************************************** - - - -#************************************************************** -# Set Minimum Delay -#************************************************************** - - - -#************************************************************** -# Set Input Transition -#************************************************************** - diff --git a/verilog/quartus/fpdpga6.v b/verilog/quartus/fpdpga6.v deleted file mode 100644 index 586ded2..0000000 --- a/verilog/quartus/fpdpga6.v +++ /dev/null @@ -1,535 +0,0 @@ -`default_nettype none - -`define synthesis - -module fpdpga6( - input wire clk, - input wire [9:0] sw, - input wire [4:0] key, - output wire [7:0] ledg, - output wire [9:0] ledr, - - input wire rx, - output wire tx, - - output wire [17:0] sram_a, - inout wire [15:0] sram_d, - output wire sram_ce, - output wire sram_oe, - output wire sram_we, - output wire sram_lb, - output wire sram_ub, - - input wire scl, - inout wire sda -); - - // TODO: figure out what to do with this - wire reset = ~key[0]; - - wire ack; - reg ack0; - wire done = ~ack0 & ack; - wire [6:0] dev; - wire [7:0] in; - wire dir; - wire start, stop; - // hardcoded devices: - wire ok = panelok | coreok; - wire [7:0] out = panelok ? panelout : - coreok ? coreout : 8'b0; - - i2cslv slv(.clk(clk), .reset(reset), - .scl(scl), .sda(sda), - .dev(dev), .ok(ok), - .ack(ack), .dir(dir), - .in(in), .out(out), - .start(start), .stop(stop)); - always @(posedge clk) - ack0 <= ack; - - wire [17:0] core_sram_a; - wire core_sram_ce; - wire core_sram_oe; - wire core_sram_we; - wire core_sram_lb; - wire core_sram_ub; - wire [17:0] i2c_sram_a; - wire i2c_sram_ce; - wire i2c_sram_oe; - wire i2c_sram_we; - wire i2c_sram_lb; - wire i2c_sram_ub; - assign sram_a = core_sram_a | i2c_sram_a; - assign sram_ce = core_sram_ce & i2c_sram_ce; - assign sram_oe = core_sram_oe & i2c_sram_oe; - assign sram_we = core_sram_we & i2c_sram_we; - assign sram_lb = core_sram_lb & i2c_sram_lb; - assign sram_ub = core_sram_ub & i2c_sram_ub; - - // i2cdev core - wire coreok = dev == 7'h21; - wire [7:0] coreout; - i2c_core i2c_core0(.clk(clk), .reset(reset), - .start(start), .stop(stop), - .dir(dir), - .ok(coreok), - .done(done), - .in(in), - .out(coreout), - - .sram_a(i2c_sram_a), - .sram_d(sram_d), - .sram_ce(i2c_sram_ce), - .sram_oe(i2c_sram_oe), - .sram_we(i2c_sram_we), - .sram_lb(i2c_sram_lb), - .sram_ub(i2c_sram_ub)); - - // i2cdev panel - wire panelok = dev == 7'h26; - reg [1:0] state; - reg [7:0] addr; - reg [7:0] panelout; - - always @(posedge clk) if(panelok) begin - if(start) - state <= 0; - if(stop && dir == 1) - addr <= addr - 8'b1; // needed for consecutive reads - if(dir == 0) begin // WRITE - if(done) begin - case(state) - 0: begin // got device address - state <= 1; - end - 1: begin // got write address - state <= 2; - addr <= in; - end - 2: begin - case(addr) - 'h0: mas[18:25] <= in; - 'h1: mas[26:33] <= in; - 'h2: mas[34:35] <= in[7:6]; - - 'h3: datasw[0:7] <= in; - 'h4: datasw[8:15] <= in; - 'h5: datasw[16:23] <= in; - 'h6: datasw[24:31] <= in; - 'h7: datasw[32:35] <= in[7:4]; - - 'h8: { sw_repeat, sw_addr_stop, - sw_power, sw_mem_disable } <= in[7:4]; - - 'h9: { sw_rim_maint, sw_repeat_bypass, sw_art3_maint, - sw_sct_maint, sw_split_cyc } <= in[7:3]; - - 'hA: { key_start, - key_inst_cont, - key_inst_stop, - key_io_reset, - key_dep, - key_ex, - key_reader_off, - key_punch_feed } <= in; - - 'hB: { key_read_in, - key_mem_cont, - key_mem_stop, - key_exec, - key_dep_nxt, - key_ex_nxt, - key_reader_on, - key_reader_feed } <= in; - - endcase - addr <= addr + 8'b1; - end - endcase - end - end else if(dir == 1) begin - if(done) begin - if(sw_power) - case(addr) - 8'h0: panelout <= ir[0:7]; - 8'h1: panelout <= ir[8:15]; - 8'h2: panelout <= { ir[16:17], 6'b0 }; - 8'h3: panelout <= pc[18:25]; - 8'h4: panelout <= pc[26:33]; - 8'h5: panelout <= { pc[34:35], 6'b0 }; - 8'h6: panelout <= mi[0:7]; - 8'h7: panelout <= mi[8:15]; - 8'h8: panelout <= mi[16:23]; - 8'h9: panelout <= mi[24:31]; - 8'hA: panelout <= { mi[32:35], 4'b0 }; - 8'hB: panelout <= ma[18:25]; - 8'hC: panelout <= ma[26:33]; - 8'hD: panelout <= { ma[34:35], 6'b0 }; - 8'hE: panelout <= { run, pih }; - 8'hF: panelout <= { mc_stop, pir }; - 8'h10: panelout <= { pi_active, pio }; - 8'h11: panelout <= { sw_repeat, sw_addr_stop, - sw_power, sw_mem_disable, 4'b0 }; - - 8'h12: panelout <= mb[0:7]; - 8'h13: panelout <= mb[8:15]; - 8'h14: panelout <= mb[16:23]; - 8'h15: panelout <= mb[24:31]; - 8'h16: panelout <= { mb[32:35], 4'b0 }; - 8'h17: panelout <= ar[0:7]; - 8'h18: panelout <= ar[8:15]; - 8'h19: panelout <= ar[16:23]; - 8'h1A: panelout <= ar[24:31]; - 8'h1B: panelout <= { ar[32:35], 4'b0 }; - 8'h1C: panelout <= mq[0:7]; - 8'h1D: panelout <= mq[8:15]; - 8'h1E: panelout <= mq[16:23]; - 8'h1F: panelout <= mq[24:31]; - 8'h20: panelout <= { mq[32:35], 4'b0 }; - - 8'h21: panelout <= ff[0]; - 8'h22: panelout <= ff[1]; - 8'h23: panelout <= ff[2]; - 8'h24: panelout <= ff[3]; - 8'h25: panelout <= ff[4]; - 8'h26: panelout <= ff[5]; - 8'h27: panelout <= ff[6]; - 8'h28: panelout <= ff[7]; - 8'h29: panelout <= ff[8]; - 8'h2A: panelout <= ff[9]; - 8'h2B: panelout <= ff[10]; - 8'h2C: panelout <= ff[11]; - 8'h2D: panelout <= ff[12]; - 8'h2E: panelout <= ff[13]; - - 8'h2F: panelout <= pr; - 8'h30: panelout <= rlr; - 8'h31: panelout <= rla; - - 8'h32: panelout <= { 1'b0, tty_ind }; - 8'h33: panelout <= tti_ind; - default: panelout <= 8'hFF; - endcase - else - panelout <= 8'b0; - addr <= addr + 8'b1; - end - end - end - - - // front panel - reg [0:35] datasw; - reg [18:35] mas; - reg sw_repeat, sw_addr_stop; - reg sw_power, sw_mem_disable; - reg sw_rim_maint, sw_repeat_bypass; - reg sw_art3_maint, sw_sct_maint, sw_split_cyc; - reg key_start, key_read_in; - reg key_inst_cont, key_mem_cont; - reg key_inst_stop, key_mem_stop; - reg key_io_reset, key_exec; - reg key_dep, key_dep_nxt; - reg key_ex, key_ex_nxt; - reg key_reader_off, key_reader_on; - reg key_punch_feed, key_reader_feed; - - wire [0:17] ir; - wire [0:35] mi; - wire [0:35] ar; - wire [0:35] mb; - wire [0:35] mq; - wire [18:35] pc; - wire [18:35] ma; - wire run; - wire mc_stop; - wire pi_active; - wire [1:7] pih; - wire [1:7] pir; - wire [1:7] pio; - wire [18:25] pr; - wire [18:25] rlr; - wire [18:25] rla; - wire [0:7] ff[13:0]; - - - - - /* Mem bus */ - wire membus_wr_rs_p0; - wire membus_rq_cyc_p0; - wire membus_rd_rq_p0; - wire membus_wr_rq_p0; - wire [21:35] membus_ma_p0; - wire [18:21] membus_sel_p0; - wire membus_fmc_select_p0; - wire membus_addr_ack_p0; - wire membus_rd_rs_p0; - wire [0:35] membus_mb_in_p0; - - /* Out of apr0 */ - wire [0:35] membus_mb_out_p0_p; - - /* Out of fmem0 */ - wire [0:35] membus_mb_out_p0_0; - wire membus_addr_ack_p0_0; - wire membus_rd_rs_p0_0; - - /* Out of mem0 */ - wire [0:35] membus_mb_out_p0_1; - wire membus_addr_ack_p0_1; - wire membus_rd_rs_p0_1; - - /* IO bus */ - wire iobus_iob_poweron; - wire iobus_iob_reset; - wire iobus_datao_clear; - wire iobus_datao_set; - wire iobus_cono_clear; - wire iobus_cono_set; - wire iobus_iob_fm_datai; - wire iobus_iob_fm_status; - wire [3:9] iobus_ios; - wire [1:7] iobus_pi_req = tty_pi_req; - wire [0:35] iobus_iob_in = apr_iob_out | tty_iob_out; - - wire [0:35] apr_iob_out; - - assign membus_mb_in_p0 = membus_mb_out_p0_p | membus_mb_out_p0_0 | membus_mb_out_p0_1; - assign membus_addr_ack_p0 = membus_addr_ack_p0_0 | membus_addr_ack_p0_1; - assign membus_rd_rs_p0 = membus_rd_rs_p0_0 | membus_rd_rs_p0_1; - - apr apr0( - .clk(clk), - .reset(reset), - .key_start(key_start), - .key_read_in(key_read_in), - .key_inst_cont(key_inst_cont), - .key_mem_cont(key_mem_cont), - .key_inst_stop(key_inst_stop), - .key_mem_stop(key_mem_stop), - .key_io_reset(key_io_reset), - .key_exec(key_exec), - .key_dep(key_dep), - .key_dep_nxt(key_dep_nxt), - .key_ex(key_ex), - .key_ex_nxt(key_ex_nxt), - - .sw_repeat(sw_repeat), - .sw_addr_stop(sw_addr_stop), - .sw_power(sw_power), - .sw_mem_disable(sw_mem_disable), - .datasw(datasw), - .mas(mas), - - .sw_rim_maint(sw_rim_maint), - .sw_repeat_bypass(sw_repeat_bypass), - .sw_art3_maint(sw_art3_maint), - .sw_sct_maint(sw_sct_maint), - .sw_split_cyc(sw_split_cyc), - - .ir(ir), - .mi(mi), - .ar(ar), - .mb(mb), - .mq(mq), - .pc(pc), - .ma(ma), - .run(run), - .mc_stop(mc_stop), - .pi_active(pi_active), - .pih(pih), - .pir(pir), - .pio(pio), - .pr(pr), - .rlr(rlr), - .rla(rla), - .ff0(ff[0]), - .ff1(ff[1]), - .ff2(ff[2]), - .ff3(ff[3]), - .ff4(ff[4]), - .ff5(ff[5]), - .ff6(ff[6]), - .ff7(ff[7]), - .ff8(ff[8]), - .ff9(ff[9]), - .ff10(ff[10]), - .ff11(ff[11]), - .ff12(ff[12]), - .ff13(ff[13]), - - .membus_wr_rs(membus_wr_rs_p0), - .membus_rq_cyc(membus_rq_cyc_p0), - .membus_rd_rq(membus_rd_rq_p0), - .membus_wr_rq(membus_wr_rq_p0), - .membus_ma(membus_ma_p0), - .membus_sel(membus_sel_p0), - .membus_fmc_select(membus_fmc_select_p0), - .membus_mb_out(membus_mb_out_p0_p), - .membus_addr_ack(membus_addr_ack_p0), - .membus_rd_rs(membus_rd_rs_p0), - .membus_mb_in(membus_mb_in_p0), - - .iobus_iob_poweron(iobus_iob_poweron), - .iobus_iob_reset(iobus_iob_reset), - .iobus_datao_clear(iobus_datao_clear), - .iobus_datao_set(iobus_datao_set), - .iobus_cono_clear(iobus_cono_clear), - .iobus_cono_set(iobus_cono_set), - .iobus_iob_fm_datai(iobus_iob_fm_datai), - .iobus_iob_fm_status(iobus_iob_fm_status), - .iobus_ios(iobus_ios), - .iobus_iob_out(apr_iob_out), - .iobus_pi_req(iobus_pi_req), - .iobus_iob_in(iobus_iob_in) - ); - - reg mem0_sw_single_step = 0; - reg mem0_sw_restart = 0; - - fast162 fmem0( - .clk(clk), - .reset(reset), - .power(sw_power), - .sw_single_step(mem0_sw_single_step), - .sw_restart(mem0_sw_restart), - - .membus_wr_rs_p0(membus_wr_rs_p0), - .membus_rq_cyc_p0(membus_rq_cyc_p0), - .membus_rd_rq_p0(membus_rd_rq_p0), - .membus_wr_rq_p0(membus_wr_rq_p0), - .membus_ma_p0(membus_ma_p0), - .membus_sel_p0(membus_sel_p0), - .membus_fmc_select_p0(membus_fmc_select_p0), - .membus_mb_in_p0(membus_mb_in_p0), - .membus_addr_ack_p0(membus_addr_ack_p0_0), - .membus_rd_rs_p0(membus_rd_rs_p0_0), - .membus_mb_out_p0(membus_mb_out_p0_0), - - .membus_rq_cyc_p1(1'b0), - .membus_sel_p1(4'b0), - .membus_fmc_select_p1(1'b0), - - .membus_rq_cyc_p2(1'b0), - .membus_sel_p2(4'b0), - .membus_fmc_select_p2(1'b0), - - .membus_rq_cyc_p3(1'b0), - .membus_sel_p3(4'b0), - .membus_fmc_select_p3(1'b0) - ); - - core161c mem0( - .clk(clk), - .reset(reset), - .power(sw_power), - .sw_single_step(mem0_sw_single_step), - .sw_restart(mem0_sw_restart), - - .membus_wr_rs_p0(membus_wr_rs_p0), - .membus_rq_cyc_p0(membus_rq_cyc_p0), - .membus_rd_rq_p0(membus_rd_rq_p0), - .membus_wr_rq_p0(membus_wr_rq_p0), - .membus_ma_p0(membus_ma_p0), - .membus_sel_p0(membus_sel_p0), - .membus_fmc_select_p0(membus_fmc_select_p0), - .membus_mb_in_p0(membus_mb_in_p0), - .membus_addr_ack_p0(membus_addr_ack_p0_1), - .membus_rd_rs_p0(membus_rd_rs_p0_1), - .membus_mb_out_p0(membus_mb_out_p0_1), - - .membus_rq_cyc_p1(1'b0), - .membus_sel_p1(4'b0), - .membus_fmc_select_p1(1'b0), - - .membus_rq_cyc_p2(1'b0), - .membus_sel_p2(4'b0), - .membus_fmc_select_p2(1'b0), - - .membus_rq_cyc_p3(1'b0), - .membus_sel_p3(4'b0), - .membus_fmc_select_p3(1'b0), - - .sram_a(core_sram_a), - .sram_d(sram_d), - .sram_ce(core_sram_ce), - .sram_oe(core_sram_oe), - .sram_we(core_sram_we), - .sram_lb(core_sram_lb), - .sram_ub(core_sram_ub) - ); - - wire [7:0] tti_ind; - wire [6:0] tty_ind; - - wire [1:7] tty_pi_req; - wire [0:35] tty_iob_out; - - tty tty0( - .clk(clk), - .rx(rx), - .tx(tx), - - .tti_ind(tti_ind), - .status_ind(tty_ind), - - .iobus_iob_poweron(iobus_iob_poweron), - .iobus_iob_reset(iobus_iob_reset), - .iobus_datao_clear(iobus_datao_clear), - .iobus_datao_set(iobus_datao_set), - .iobus_cono_clear(iobus_cono_clear), - .iobus_cono_set(iobus_cono_set), - .iobus_iob_fm_datai(iobus_iob_fm_datai), - .iobus_iob_fm_status(iobus_iob_fm_status), - .iobus_ios(iobus_ios), - .iobus_iob_in(iobus_iob_in), - .iobus_pi_req(tty_pi_req), - .iobus_iob_out(tty_iob_out) - ); - - assign ledr = { run, 1'b0, tti_ind }; - assign ledg = { 1'b0, tty_ind }; -/* - assign ledr[7:0] = sw == 0 ? datasw[0:5] : - sw == 1 ? datasw[6:11] : - sw == 2 ? datasw[12:17] : - sw == 3 ? datasw[18:23] : - sw == 4 ? datasw[24:29] : - sw == 5 ? datasw[30:35] : - sw == 6 ? { 4'b0, sw_repeat, sw_addr_stop, sw_power, sw_mem_disable } : - sw == 7 ? { key_start, key_inst_cont, key_inst_stop, key_io_reset, key_dep, key_ex, key_reader_off, key_punch_feed } : - 6'b0; - assign ledg[7:0] = sw == 3 ? { 2'b0, mas[18:23] } : - sw == 4 ? { 2'b0, mas[24:29] } : - sw == 5 ? { 2'b0, mas[30:35] } : - sw == 6 ? { 3'b0, sw_rim_maint, sw_repeat_bypass, sw_art3_maint, sw_sct_maint, sw_split_cyc } : - sw == 7 ? { key_read_in, key_mem_cont, key_mem_stop, key_exec, key_dep_nxt, key_ex_nxt, key_reader_on, key_reader_feed } : - 6'b0; - - assign ledr[9:8] = 2'b0; - - assign ledr[5:0] = sw == 0 ? mb[0:5] : - sw == 1 ? mb[6:11] : - sw == 2 ? mb[12:17] : - sw == 3 ? mb[18:23] : - sw == 4 ? mb[24:29] : - sw == 5 ? mb[30:35] : - sw == 6 ? ar[0:5] : - sw == 7 ? ar[6:11] : - sw == 8 ? ar[12:17] : - sw == 9 ? ar[18:23] : - sw == 10 ? ar[24:29] : - sw == 11 ? ar[30:35] : - sw == 12 ? mq[0:5] : - sw == 13 ? mq[6:11] : - sw == 14 ? mq[12:17] : - sw == 15 ? mq[18:23] : - sw == 16 ? mq[24:29] : - sw == 17 ? mq[30:35] : 0; - assign ledr[9:6] = 0; - assign ledg = 0; -*/ - -endmodule diff --git a/verilog/quartus/i2c.v b/verilog/quartus/i2c.v deleted file mode 100644 index b49cb14..0000000 --- a/verilog/quartus/i2c.v +++ /dev/null @@ -1,113 +0,0 @@ -`default_nettype none - -module i2cslv( - input wire clk, - input wire reset, - input wire scl, - inout reg sda, - - output wire ack, - output reg dir, - output reg [6:0] dev, - input wire ok, - output wire [7:0] in, - input wire [7:0] out, - output wire start, - output wire stop -); - localparam IDLE = 0; - localparam ADDR = 1; - localparam RECV = 2; - localparam SENDACK = 3; - localparam SEND = 4; - localparam RECVACK = 5; - - localparam WRITE = 0; - localparam READ = 1; - - reg [2:0] state; - reg [2:0] n; - reg [7:0] b; - reg sda0, sda1, scl0, scl1; - - assign in = b; - assign ack = state == SENDACK || state == RECVACK; - - assign start = scl1 & scl0 & sda1 & ~sda0; - assign stop = scl1 & scl0 & ~sda1 & sda0; - wire scl_rise = ~scl1 & scl0; - wire scl_fall = scl1 & ~scl0; - - always @(posedge clk) begin - { sda1, sda0 } <= { sda0, sda }; - { scl1, scl0 } <= { scl0, scl }; - if(scl_rise) - n <= n + 3'b1; - if(start) begin - state <= ADDR; - n <= 0; - end - if(stop) - state <= IDLE; - case(state) - ADDR: begin - if(scl_rise) begin - if(n == 7) begin - dir <= sda; - if(ok) - state <= SENDACK; - else - state <= IDLE; - end else - dev <= { dev[5:0], sda }; - end - end - RECV: begin - if(scl_fall) - sda <= 1'bz; - if(scl_rise) begin - if(n == 7) - state <= SENDACK; - b <= { b[6:0], sda }; - end - end - SENDACK: begin - if(scl_fall) - sda <= 1'b0; - if(scl_rise) begin - if(dir == WRITE) - state <= RECV; - else begin - b <= out; - state <= SEND; - end - n <= 0; - end - end - SEND: begin - if(scl_fall) begin - if(b[7]) - sda <= 1'bz; - else - sda <= 1'b0; - b <= b << 1; - end - if(scl_rise & n == 7) - state <= RECVACK; - end - RECVACK: begin - if(scl_fall) - sda <= 1'bz; - if(scl_rise) begin - b <= out; - if(sda) - state <= IDLE; - else - state <= SEND; - n <= 0; - end - end - endcase - end - -endmodule diff --git a/verilog/quartus/i2c_core.v b/verilog/quartus/i2c_core.v deleted file mode 100644 index e14c4f9..0000000 --- a/verilog/quartus/i2c_core.v +++ /dev/null @@ -1,159 +0,0 @@ -module i2c_core( - input wire clk, - input wire reset, - - input wire start, - input wire stop, - input wire dir, - input wire ok, - input wire done, - input wire [7:0] in, - output reg [7:0] out, - - output reg [17:0] sram_a, - inout reg [15:0] sram_d, - output reg sram_ce, - output reg sram_oe, - output reg sram_we, - output reg sram_lb, - output reg sram_ub -); - localparam DEV = 0; - localparam ADDR = 1; - localparam DATA = 2; - - reg [17:0] caddr; // core address - reg [11:0] d; // a third of a word - reg [1:0] state; // major state - reg [1:0] n; // minor state - // memory controller - reg [1:0] memstate; - reg memdir; // 0: read, 1: write - reg memdone; - - initial begin - memstate <= 0; - memdone <= 0; - sram_a <= 0; - sram_d <= 16'bz; - sram_ce <= 1; - sram_oe <= 1; - sram_we <= 1; - sram_lb <= 1; - sram_ub <= 1; - end - - always @(posedge clk) if(ok) begin - if(memdone) - memdone <= 0; - if(start) begin - state <= DEV; - n <= 0; - end - - if(stop) - sram_a <= 0; - if(dir == 0 && done) // WRITE - case(state) - DEV: state <= ADDR; - ADDR: begin - caddr <= { caddr[11:0], in[5:0] }; - if(n == 2) begin - state <= DATA; - n <= 0; - end else - n <= n + 2'b1; - end - DATA: begin - d <= { d[5:0], in[5:0] }; - case(n) - 0: begin // first 6 bits, came from ADDR - sram_a <= (caddr << 1) + caddr; - n <= 2; - end - 1: n <= 2; // first 6 bits, else - 2: begin // read second 6 bits - n <= 1; - // start write - memdir <= 1; - memstate <= 1; - end - endcase - end - endcase - else if(done) // READ - case(state) - DEV: begin - state <= DATA; - sram_a <= (caddr << 1) + caddr; - // two dummy bytes - out <= 8'b0; - d <= 12'b0000; - end - DATA: begin - case(n) - 0: begin - out <= { 2'b0, d[5:0] }; - n <= 1; - // get a new 16 bit word - memdir <= 0; - memstate <= 1; - end - 1: begin - out <= { 2'b0, d[11:6] }; - n <= 0; - end - endcase - end - endcase - - // Talk to SRAM - if(memdir == 0) // read - case(memstate) - 1: begin - sram_ce <= 0; - sram_oe <= 0; - sram_lb <= 0; - sram_ub <= 0; - memstate <= 2; - end - 2: memstate <= 3; - 3: begin - sram_a <= sram_a + 18'b1; - d <= sram_d[15:4]; - sram_ce <= 1; - sram_oe <= 1; - sram_lb <= 1; - sram_ub <= 1; - memstate <= 0; - memdone <= 1; - end - endcase - else // write - case(memstate) - 1: begin - sram_d <= { d, 4'b0 }; - sram_ce <= 0; - sram_we <= 1; - sram_lb <= 0; - sram_ub <= 0; - memstate <= 2; - end - 2: begin - sram_we <= 0; - memstate <= 3; - end - 3: begin - sram_a <= sram_a + 18'b1; - sram_d <= 16'bz; - sram_ce <= 1; - sram_we <= 1; - sram_lb <= 1; - sram_ub <= 1; - memstate <= 0; - memdone <= 1; - end - endcase - end - -endmodule diff --git a/verilog/quartus/test.stp b/verilog/quartus/test.stp deleted file mode 100644 index 42c2ace..0000000 --- a/verilog/quartus/test.stp +++ /dev/null @@ -1,1081 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 'core161c:mem0|cmpc_p0_rq' == either edge - - - - - - 11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 - 11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 11111111111111111111111111111 - 11111111111111111111111111111 - - - - - - - - - - - - - - - - - - - 11000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000001000000000000000000000000000000000000000000001000000000000010000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000001000000000000000000000000000000100000000001000000001000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000010000000000000000001000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000010000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000001000000000000000000000000000000010100000000100000001000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000001000000000000000000100000000000000000000000000000000000000000000000000000000001000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000001000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000100000000000000000000000000000001010000000010000000100000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000100000000000000000010000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000101000000001000000010000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000010000000000000000001000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000100000000000000000010000000000000000000000000000000000000000 - B1B11B1B1B111B1B11B11B11B1B111B1B11B11B11B1B111B1B11B11B1B111B1B11B11B111 - - - - - - - - - - - - - - - - - diff --git a/verilog/tb/Makefile b/verilog/tb/Makefile new file mode 100644 index 0000000..30b0d59 --- /dev/null +++ b/verilog/tb/Makefile @@ -0,0 +1,29 @@ +DEP= +V=../clk.v ../memory.v ../arbiter.v ../memif.v ../membusif.v ../core161c.v \ + ../core164.v ../core32k.v ../fast162.v ../fast162_dp.v ../modules_50.v \ + ../dly_50.v ../onchip_ram.v ../memory_16.v ../memory_16k.v ../memory_32k.v \ + ../panel_6.v ../fakeapr.v ../ptr.v ../ptp.v + +tb_ptp: tb_ptp.v $(V) $(DEP) + iverilog -o $@ tb_ptp.v $(V) + +tb_ptr: tb_ptr.v $(V) $(DEP) + iverilog -o $@ tb_ptr.v $(V) + +tb_panel: tb_panel.v $(V) $(DEP) + iverilog -o $@ tb_panel.v $(V) + +tb_membusif_x: tb_membusif_x.v $(V) $(DEP) + iverilog -o $@ tb_membusif_x.v $(V) + +tb_membusif: tb_membusif.v $(V) $(DEP) + iverilog -o $@ tb_membusif.v $(V) + +tb_memif: tb_memif.v $(V) $(DEP) + iverilog -o $@ tb_memif.v $(V) + +tb_arbit: tb_arbit.v $(V) $(DEP) + iverilog -o $@ tb_arbit.v $(V) + +tb_mem: tb_mem.v $(V) $(DEP) + iverilog -o $@ tb_mem.v $(V) diff --git a/verilog/tb/tb_arbit.v b/verilog/tb/tb_arbit.v new file mode 100644 index 0000000..3049925 --- /dev/null +++ b/verilog/tb/tb_arbit.v @@ -0,0 +1,120 @@ +`default_nettype none +`timescale 1ns/1ns + +module tb_mem(); + + wire clk, reset; + clock clock(clk, reset); + + reg m0_write = 0; + reg m0_read = 0; + reg [35:0] m0_writedata = 0; + reg [17:0] m0_address = 0; + wire [35:0] m0_readdata; + wire m0_waitrequest; + reg m1_write = 0; + reg m1_read = 0; + reg [35:0] m1_writedata = 0; + reg [17:0] m1_address = 0; + wire [35:0] m1_readdata; + wire m1_waitrequest; + wire s_write, s_read, s_waitrequest; + wire [17:0] s_address; + wire [35:0] s_writedata, s_readdata; + + arbiter arb0(.clk(clk), .reset(reset), + .s0_address(m0_address), + .s0_write(m0_write), + .s0_read(m0_read), + .s0_writedata(m0_writedata), + .s0_readdata(m0_readdata), + .s0_waitrequest(m0_waitrequest), + .s1_address(m1_address), + .s1_write(m1_write), + .s1_read(m1_read), + .s1_writedata(m1_writedata), + .s1_readdata(m1_readdata), + .s1_waitrequest(m1_waitrequest), + .m_address(s_address), + .m_write(s_write), + .m_read(s_read), + .m_writedata(s_writedata), + .m_readdata(s_readdata), + .m_waitrequest(s_waitrequest)); + + testmem16k memory(.i_clk(clk), .i_reset_n(reset), + .i_address(s_address), .i_write(s_write), .i_read(s_read), + .i_writedata(s_writedata), + .o_readdata(s_readdata), + .o_waitrequest(s_waitrequest)); + + initial begin + $dumpfile("dump.vcd"); + $dumpvars(); + +// memory.mem[4] = 'o123; +// memory.mem[5] = 'o321; +// memory.mem[8] = 'o11111; + memory.ram.ram[4] = 'o123; + memory.ram.ram[5] = 'o321; + memory.ram.ram[6] = 'o444444; + memory.ram.ram[8] = 'o11111; + + #5; + + #200; + + + m0_address <= 'o4; +// m1_address <= 'o10; + m0_write <= 1; +// m1_write <= 1; + m0_writedata <= 'o1234; +// m1_writedata <= 'o4321; + + + @(negedge m0_write); + @(posedge clk); + m0_address <= 5; + m0_read <= 1; + + @(negedge m0_read); + @(posedge clk); + m0_address <= 6; + m0_read <= 1; + + @(negedge m0_read); + @(posedge clk); + m0_address <= 0; + m0_read <= 1; + + @(negedge m0_read); + @(posedge clk); + m0_address <= 4; + m0_read <= 1; + end + + initial begin + #40000; + $finish; + end + + reg [35:0] data0; + reg [35:0] data1; + always @(posedge clk) begin + + if(~m0_waitrequest & m0_write) + m0_write <= 0; + if(~m0_waitrequest & m0_read) begin + m0_read <= 0; + data0 <= m0_readdata; + end + if(~m1_waitrequest & m1_write) + m1_write <= 0; + if(~m1_waitrequest & m1_read) begin + m1_read <= 0; + data1 <= m1_readdata; + end + end + +endmodule diff --git a/verilog/tb/tb_dly.v b/verilog/tb/tb_dly.v new file mode 100644 index 0000000..e8c85bc --- /dev/null +++ b/verilog/tb/tb_dly.v @@ -0,0 +1,66 @@ +`default_nettype none +`timescale 1ns/1ns + +module tb_dly(); + + wire clk, reset; + clock clock(clk, reset); + + reg in; + wire start; + wire out50ns, out70ns, out100ns, out150ns; + wire out200ns, out250ns, out400ns, out800ns; + dly50ns dstart(clk, ~reset, in, start); + dly50ns d50ns(clk, ~reset, start, out50ns); + dly70ns d70ns(clk, ~reset, start, out70ns); + dly100ns d100ns(clk, ~reset, start, out100ns); + dly150ns d150ns(clk, ~reset, start, out150ns); + dly200ns d200ns(clk, ~reset, start, out200ns); + dly250ns d250ns(clk, ~reset, start, out250ns); + dly400ns d400ns(clk, ~reset, start, out400ns); + dly800ns d800ns(clk, ~reset, start, out800ns); + + wire out1us, out1_5us, out2us, out100us; + wire lv1us, lv1_5us, lv2us, lv100us; + ldly1us d1us(clk, ~reset, start, out1us, lv1us); + ldly1_5us d1_5us(clk, ~reset, start, out1_5us, lv1_5us); + ldly2us d2us(clk, ~reset, start, out2us, lv2us); + ldly100us d100us(clk, ~reset, start, out100us, lv100us); + + wire driveedge; + edgedet drive(clk, reset, iot_drive, driveedge); + + wire iot_t2, iot_t3, iot_t3a, iot_t4; + wire iot_init_setup, iot_final_setup, iot_reset, iot_restart; + ldly1us iot_dly1(clk, ~reset, start, iot_t2, iot_init_setup); + ldly1_5us iot_dly2(clk, ~reset, + iot_t2, + iot_t3a, + iot_final_setup); + ldly2us iot_dly3(clk, ~reset, + iot_t3a, + iot_t4, + iot_reset); + ldly1us iot_dly4(clk, ~reset, + iot_t2, + iot_t3, + iot_restart); + wire iot_drive = iot_init_setup | iot_final_setup | iot_t2; + + initial begin + $dumpfile("dump.vcd"); + $dumpvars(); + + in = 0; + + #110; + in = 1; + #20; + in = 0; + end + + initial begin + #40000; + $finish; + end +endmodule diff --git a/verilog/tb/tb_mem.v b/verilog/tb/tb_mem.v new file mode 100644 index 0000000..f550010 --- /dev/null +++ b/verilog/tb/tb_mem.v @@ -0,0 +1,54 @@ +`default_nettype none +`timescale 1ns/1ns + +module tb_mem(); + + wire clk, reset; + clock clock(clk, reset); + + reg write = 0; + reg read = 0; + reg [35:0] writedata = 0; + reg [17:0] address; + wire [35:0] readdata; + wire waitrequest; + dlymemory memory(.i_clk(clk), .i_reset_n(reset), + .i_address(address), .i_write(write), .i_read(read), + .i_writedata(writedata), + .o_readdata(readdata), + .o_waitrequest(waitrequest)); + + initial begin + $dumpfile("dump.vcd"); + $dumpvars(); + + memory.mem[4] = 123; + memory.mem[5] = 321; + + #5; + + address <= 4; + + #200; + write <= 1; + writedata <= 36'o44556677; + + @(negedge write); + @(posedge clk); + address <= 5; + read <= 1; + end + + initial begin + #40000; + $finish; + end + + always @(posedge clk) begin + if(~waitrequest & write) + write <= 0; + if(~waitrequest & read) + read <= 0; + end + +endmodule diff --git a/verilog/tb/tb_membusif b/verilog/tb/tb_membusif new file mode 100755 index 0000000..9accbb9 --- /dev/null +++ b/verilog/tb/tb_membusif @@ -0,0 +1,5042 @@ +#! /usr/bin/vvp +:ivl_version "10.3 (stable)" "(v10_3)"; +:ivl_delay_selection "TYPICAL"; +:vpi_time_precision - 9; +:vpi_module "system"; +:vpi_module "vhdl_sys"; +:vpi_module "v2005_math"; +:vpi_module "va_math"; +S_0x56148be2d130 .scope module, "arbiter" "arbiter" 2 1; + .timescale -9 -9; + .port_info 0 /INPUT 1 "i_clk" + .port_info 1 /INPUT 1 "i_reset_n" + .port_info 2 /INPUT 18 "i0_address" + .port_info 3 /INPUT 1 "i0_write" + .port_info 4 /INPUT 1 "i0_read" + .port_info 5 /INPUT 36 "i0_writedata" + .port_info 6 /OUTPUT 36 "o0_readdata" + .port_info 7 /OUTPUT 1 "o0_waitrequest" + .port_info 8 /INPUT 18 "i1_address" + .port_info 9 /INPUT 1 "i1_write" + .port_info 10 /INPUT 1 "i1_read" + .port_info 11 /INPUT 36 "i1_writedata" + .port_info 12 /OUTPUT 36 "o1_readdata" + .port_info 13 /OUTPUT 1 "o1_waitrequest" + .port_info 14 /OUTPUT 18 "o_address" + .port_info 15 /OUTPUT 1 "o_write" + .port_info 16 /OUTPUT 1 "o_read" + .port_info 17 /OUTPUT 36 "o_writedata" + .port_info 18 /INPUT 36 "i_readdata" + .port_info 19 /INPUT 1 "i_waitrequest" + .port_info 20 /NODIR 0 "unnamed" +o0x7ff4beabe0d8 .functor BUFZ 1, C4; HiZ drive +o0x7ff4beabe108 .functor BUFZ 1, C4; HiZ drive +L_0x56148bf0d630 .functor OR 1, o0x7ff4beabe0d8, o0x7ff4beabe108, C4<0>, C4<0>; +o0x7ff4beabe198 .functor BUFZ 1, C4; HiZ drive +o0x7ff4beabe1c8 .functor BUFZ 1, C4; HiZ drive +L_0x56148bf0d730 .functor OR 1, o0x7ff4beabe198, o0x7ff4beabe1c8, C4<0>, C4<0>; +L_0x56148bf0d830 .functor OR 1, v0x56148beaa460_0, v0x56148bea89b0_0, C4<0>, C4<0>; +v0x56148be1cf00_0 .net "connected", 0 0, L_0x56148bf0d830; 1 drivers +v0x56148be1d000_0 .net "cyc0", 0 0, L_0x56148bf0d630; 1 drivers +v0x56148be108e0_0 .net "cyc1", 0 0, L_0x56148bf0d730; 1 drivers +o0x7ff4beabe0a8 .functor BUFZ 18, C4; HiZ drive +v0x56148be10980_0 .net "i0_address", 17 0, o0x7ff4beabe0a8; 0 drivers +v0x56148be0ec20_0 .net "i0_read", 0 0, o0x7ff4beabe0d8; 0 drivers +v0x56148be0ed20_0 .net "i0_write", 0 0, o0x7ff4beabe108; 0 drivers +o0x7ff4beabe138 .functor BUFZ 36, C4; HiZ drive +v0x56148bd22a90_0 .net "i0_writedata", 35 0, o0x7ff4beabe138; 0 drivers +o0x7ff4beabe168 .functor BUFZ 18, C4; HiZ drive +v0x56148bea0390_0 .net "i1_address", 17 0, o0x7ff4beabe168; 0 drivers +v0x56148be8fc80_0 .net "i1_read", 0 0, o0x7ff4beabe198; 0 drivers +v0x56148be8fd40_0 .net "i1_write", 0 0, o0x7ff4beabe1c8; 0 drivers +o0x7ff4beabe1f8 .functor BUFZ 36, C4; HiZ drive +v0x56148be9ef40_0 .net "i1_writedata", 35 0, o0x7ff4beabe1f8; 0 drivers +o0x7ff4beabe228 .functor BUFZ 1, C4; HiZ drive +v0x56148be9f000_0 .net "i_clk", 0 0, o0x7ff4beabe228; 0 drivers +o0x7ff4beabe258 .functor BUFZ 36, C4; HiZ drive +v0x56148be9e060_0 .net "i_readdata", 35 0, o0x7ff4beabe258; 0 drivers +o0x7ff4beabe288 .functor BUFZ 1, C4; HiZ drive +v0x56148be9e120_0 .net "i_reset_n", 0 0, o0x7ff4beabe288; 0 drivers +o0x7ff4beabe2b8 .functor BUFZ 1, C4; HiZ drive +v0x56148be9d180_0 .net "i_waitrequest", 0 0, o0x7ff4beabe2b8; 0 drivers +v0x56148be9d220_0 .var "o0_readdata", 35 0; +v0x56148be9c2a0_0 .var "o0_waitrequest", 0 0; +v0x56148be9c340_0 .var "o1_readdata", 35 0; +v0x56148be9b330_0 .var "o1_waitrequest", 0 0; +v0x56148be9b3d0_0 .var "o_address", 17 0; +v0x56148beb2350_0 .var "o_read", 0 0; +v0x56148beb23f0_0 .var "o_write", 0 0; +v0x56148beaa380_0 .var "o_writedata", 35 0; +v0x56148beaa460_0 .var "sel0", 0 0; +v0x56148bea89b0_0 .var "sel1", 0 0; +E_0x56148bd0db00/0 .event edge, v0x56148beaa460_0, v0x56148be10980_0, v0x56148be0ed20_0, v0x56148be0ec20_0; +E_0x56148bd0db00/1 .event edge, v0x56148bd22a90_0, v0x56148be9e060_0, v0x56148be9d180_0, v0x56148bea89b0_0; +E_0x56148bd0db00/2 .event edge, v0x56148bea0390_0, v0x56148be8fd40_0, v0x56148be8fc80_0, v0x56148be9ef40_0; +E_0x56148bd0db00 .event/or E_0x56148bd0db00/0, E_0x56148bd0db00/1, E_0x56148bd0db00/2; +E_0x56148bd0e9b0/0 .event negedge, v0x56148be9e120_0; +E_0x56148bd0e9b0/1 .event posedge, v0x56148be9f000_0; +E_0x56148bd0e9b0 .event/or E_0x56148bd0e9b0/0, E_0x56148bd0e9b0/1; +S_0x56148bebe570 .scope module, "clk60hz" "clk60hz" 3 2; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /OUTPUT 1 "outclk" +v0x56148bea5250_0 .net *"_s0", 31 0, L_0x56148bf0d930; 1 drivers +L_0x7ff4bea75018 .functor BUFT 1, C4<0000000000>, C4<0>, C4<0>, C4<0>; +v0x56148beada10_0 .net *"_s3", 9 0, L_0x7ff4bea75018; 1 drivers +L_0x7ff4bea75060 .functor BUFT 1, C4<00000000000110010110111001101010>, C4<0>, C4<0>, C4<0>; +v0x56148beadaf0_0 .net/2u *"_s4", 31 0, L_0x7ff4bea75060; 1 drivers +o0x7ff4beabe918 .functor BUFZ 1, C4; HiZ drive +v0x56148beabd50_0 .net "clk", 0 0, o0x7ff4beabe918; 0 drivers +v0x56148beabe10_0 .var "cnt", 21 0; +v0x56148be453d0_0 .net "outclk", 0 0, L_0x56148bf1daa0; 1 drivers +E_0x56148bd0eac0 .event posedge, v0x56148beabd50_0; +L_0x56148bf0d930 .concat [ 22 10 0 0], v0x56148beabe10_0, L_0x7ff4bea75018; +L_0x56148bf1daa0 .cmp/eq 32, L_0x56148bf0d930, L_0x7ff4bea75060; +S_0x56148bec3ac0 .scope module, "dly100us" "dly100us" 3 273; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +v0x56148be43cb0_0 .net *"_s0", 31 0, L_0x56148bf1dbc0; 1 drivers +L_0x7ff4bea750a8 .functor BUFT 1, C4<0000000000000000>, C4<0>, C4<0>, C4<0>; +v0x56148be43db0_0 .net *"_s3", 15 0, L_0x7ff4bea750a8; 1 drivers +L_0x7ff4bea750f0 .functor BUFT 1, C4<00000000000000000010011100010010>, C4<0>, C4<0>, C4<0>; +v0x56148be39600_0 .net/2u *"_s4", 31 0, L_0x7ff4bea750f0; 1 drivers +o0x7ff4beabea98 .functor BUFZ 1, C4; HiZ drive +v0x56148be396c0_0 .net "clk", 0 0, o0x7ff4beabea98; 0 drivers +o0x7ff4beabeac8 .functor BUFZ 1, C4; HiZ drive +v0x56148be42630_0 .net "in", 0 0, o0x7ff4beabeac8; 0 drivers +v0x56148be42720_0 .net "p", 0 0, L_0x56148bf1dd10; 1 drivers +v0x56148be41010_0 .var "r", 15 0; +o0x7ff4beabeb58 .functor BUFZ 1, C4; HiZ drive +v0x56148be410f0_0 .net "reset", 0 0, o0x7ff4beabeb58; 0 drivers +E_0x56148bed0980 .event posedge, v0x56148be410f0_0, v0x56148be396c0_0; +L_0x56148bf1dbc0 .concat [ 16 16 0 0], v0x56148be41010_0, L_0x7ff4bea750a8; +L_0x56148bf1dd10 .cmp/eq 32, L_0x56148bf1dbc0, L_0x7ff4bea750f0; +S_0x56148beb5d40 .scope module, "dly150ns" "dly150ns" 3 117; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +v0x56148be3fa10_0 .net *"_s0", 31 0, L_0x56148bf1de80; 1 drivers +L_0x7ff4bea75138 .functor BUFT 1, C4<000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x56148be3d110_0 .net *"_s3", 26 0, L_0x7ff4bea75138; 1 drivers +L_0x7ff4bea75180 .functor BUFT 1, C4<00000000000000000000000000010001>, C4<0>, C4<0>, C4<0>; +v0x56148be3d1d0_0 .net/2u *"_s4", 31 0, L_0x7ff4bea75180; 1 drivers +o0x7ff4beabecd8 .functor BUFZ 1, C4; HiZ drive +v0x56148be3bd30_0 .net "clk", 0 0, o0x7ff4beabecd8; 0 drivers +o0x7ff4beabed08 .functor BUFZ 1, C4; HiZ drive +v0x56148be3bdd0_0 .net "in", 0 0, o0x7ff4beabed08; 0 drivers +v0x56148be3a970_0 .net "p", 0 0, L_0x56148bf1dff0; 1 drivers +v0x56148be3aa30_0 .var "r", 4 0; +o0x7ff4beabed98 .functor BUFZ 1, C4; HiZ drive +v0x56148be5eb80_0 .net "reset", 0 0, o0x7ff4beabed98; 0 drivers +E_0x56148bed0b90 .event posedge, v0x56148be5eb80_0, v0x56148be3bd30_0; +L_0x56148bf1de80 .concat [ 5 27 0 0], v0x56148be3aa30_0, L_0x7ff4bea75138; +L_0x56148bf1dff0 .cmp/eq 32, L_0x56148bf1de80, L_0x7ff4bea75180; +S_0x56148beb7af0 .scope module, "dly70ns" "dly70ns" 3 87; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +v0x56148be5bf80_0 .net *"_s0", 31 0, L_0x56148bf1e130; 1 drivers +L_0x7ff4bea751c8 .functor BUFT 1, C4<0000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x56148be5b280_0 .net *"_s3", 27 0, L_0x7ff4bea751c8; 1 drivers +L_0x7ff4bea75210 .functor BUFT 1, C4<00000000000000000000000000001001>, C4<0>, C4<0>, C4<0>; +v0x56148be5b360_0 .net/2u *"_s4", 31 0, L_0x7ff4bea75210; 1 drivers +o0x7ff4beabef18 .functor BUFZ 1, C4; HiZ drive +v0x56148be59720_0 .net "clk", 0 0, o0x7ff4beabef18; 0 drivers +o0x7ff4beabef48 .functor BUFZ 1, C4; HiZ drive +v0x56148be597e0_0 .net "in", 0 0, o0x7ff4beabef48; 0 drivers +v0x56148be503c0_0 .net "p", 0 0, L_0x56148bf1e250; 1 drivers +v0x56148be50460_0 .var "r", 3 0; +o0x7ff4beabefd8 .functor BUFZ 1, C4; HiZ drive +v0x56148be4a3e0_0 .net "reset", 0 0, o0x7ff4beabefd8; 0 drivers +E_0x56148be5ecc0 .event posedge, v0x56148be4a3e0_0, v0x56148be59720_0; +L_0x56148bf1e130 .concat [ 4 28 0 0], v0x56148be50460_0, L_0x7ff4bea751c8; +L_0x56148bf1e250 .cmp/eq 32, L_0x56148bf1e130, L_0x7ff4bea75210; +S_0x56148beb9590 .scope module, "dlymemory" "dlymemory" 4 36; + .timescale -9 -9; + .port_info 0 /INPUT 1 "i_clk" + .port_info 1 /INPUT 1 "i_reset_n" + .port_info 2 /INPUT 18 "i_address" + .port_info 3 /INPUT 1 "i_write" + .port_info 4 /INPUT 1 "i_read" + .port_info 5 /INPUT 36 "i_writedata" + .port_info 6 /OUTPUT 36 "o_readdata" + .port_info 7 /OUTPUT 1 "o_waitrequest" +L_0x56148bf1f410 .functor NOT 1, L_0x56148bf1ede0, C4<0>, C4<0>, C4<0>; +v0x56148be4ee20_0 .net *"_s1", 3 0, L_0x56148bf1e3c0; 1 drivers +v0x56148be4ef20_0 .net *"_s12", 35 0, L_0x56148bf1e8a0; 1 drivers +v0x56148be4d060_0 .net *"_s14", 15 0, L_0x56148bf1e940; 1 drivers +L_0x7ff4bea752e8 .functor BUFT 1, C4<00>, C4<0>, C4<0>, C4<0>; +v0x56148be4d120_0 .net *"_s17", 1 0, L_0x7ff4bea752e8; 1 drivers +L_0x7ff4bea75330 .functor BUFT 1, C4<000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x56148be4b600_0 .net/2u *"_s18", 35 0, L_0x7ff4bea75330; 1 drivers +v0x56148be24480_0 .net *"_s2", 31 0, L_0x56148bf1e460; 1 drivers +v0x56148be24560_0 .net *"_s22", 31 0, L_0x56148bf1eca0; 1 drivers +L_0x7ff4bea75378 .functor BUFT 1, C4<0000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x56148be23c00_0 .net *"_s25", 27 0, L_0x7ff4bea75378; 1 drivers +L_0x7ff4bea753c0 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x56148be23cc0_0 .net/2u *"_s26", 31 0, L_0x7ff4bea753c0; 1 drivers +L_0x7ff4bea75408 .functor BUFT 1, C4<000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x56148be1dd80_0 .net/2u *"_s30", 35 0, L_0x7ff4bea75408; 1 drivers +L_0x7ff4bea75258 .functor BUFT 1, C4<0000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x56148be1de60_0 .net *"_s5", 27 0, L_0x7ff4bea75258; 1 drivers +L_0x7ff4bea752a0 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x56148be1c6e0_0 .net/2u *"_s6", 31 0, L_0x7ff4bea752a0; 1 drivers +v0x56148be1c7c0_0 .net "addr", 13 0, L_0x56148bf1e780; 1 drivers +v0x56148be1b7d0_0 .net "addrok", 0 0, L_0x56148bf1e660; 1 drivers +v0x56148be1b890_0 .var "dly", 3 0; +o0x7ff4beabf6f8 .functor BUFZ 18, C4; HiZ drive +v0x56148be0bcb0_0 .net "i_address", 17 0, o0x7ff4beabf6f8; 0 drivers +o0x7ff4beabf0f8 .functor BUFZ 1, C4; HiZ drive +v0x56148be0bd70_0 .net "i_clk", 0 0, o0x7ff4beabf0f8; 0 drivers +o0x7ff4beabf338 .functor BUFZ 1, C4; HiZ drive +v0x56148be0e400_0 .net "i_read", 0 0, o0x7ff4beabf338; 0 drivers +o0x7ff4beabf188 .functor BUFZ 1, C4; HiZ drive +v0x56148be0e4a0_0 .net "i_reset_n", 0 0, o0x7ff4beabf188; 0 drivers +o0x7ff4beabf1b8 .functor BUFZ 1, C4; HiZ drive +v0x56148be0d480_0 .net "i_write", 0 0, o0x7ff4beabf1b8; 0 drivers +o0x7ff4beabf728 .functor BUFZ 36, C4; HiZ drive +v0x56148be0d520_0 .net "i_writedata", 35 0, o0x7ff4beabf728; 0 drivers +v0x56148becb530 .array "mem", 16383 0, 35 0; +v0x56148becb5f0_0 .net "memword", 35 0, L_0x56148bf1eb10; 1 drivers +v0x56148be8bd20_0 .net "o_readdata", 35 0, L_0x56148bf1f2c0; 1 drivers +v0x56148be8be00_0 .net "o_waitrequest", 0 0, L_0x56148bf1f410; 1 drivers +v0x56148beb0580_0 .net "read_edge", 0 0, L_0x56148bf1f160; 1 drivers +v0x56148beb0620_0 .net "ready", 0 0, L_0x56148bf1ede0; 1 drivers +v0x56148becc590_0 .net "write_edge", 0 0, L_0x56148bf1ef90; 1 drivers +L_0x56148bf1e3c0 .part o0x7ff4beabf6f8, 14, 4; +L_0x56148bf1e460 .concat [ 4 28 0 0], L_0x56148bf1e3c0, L_0x7ff4bea75258; +L_0x56148bf1e660 .cmp/eq 32, L_0x56148bf1e460, L_0x7ff4bea752a0; +L_0x56148bf1e780 .part o0x7ff4beabf6f8, 0, 14; +L_0x56148bf1e8a0 .array/port v0x56148becb530, L_0x56148bf1e940; +L_0x56148bf1e940 .concat [ 14 2 0 0], L_0x56148bf1e780, L_0x7ff4bea752e8; +L_0x56148bf1eb10 .functor MUXZ 36, L_0x7ff4bea75330, L_0x56148bf1e8a0, L_0x56148bf1e660, C4<>; +L_0x56148bf1eca0 .concat [ 4 28 0 0], v0x56148be1b890_0, L_0x7ff4bea75378; +L_0x56148bf1ede0 .cmp/eq 32, L_0x56148bf1eca0, L_0x7ff4bea753c0; +L_0x56148bf1f2c0 .functor MUXZ 36, L_0x7ff4bea75408, L_0x56148bf1eb10, o0x7ff4beabf338, C4<>; +S_0x56148be76390 .scope module, "e0" "edgedet" 4 61, 5 15 0, S_0x56148beb9590; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "signal" + .port_info 3 /OUTPUT 1 "p" +L_0x56148bf1ef20 .functor NOT 1, v0x56148be489e0_0, C4<0>, C4<0>, C4<0>; +L_0x56148bf1ef90 .functor AND 1, o0x7ff4beabf1b8, L_0x56148bf1ef20, C4<1>, C4<1>; +v0x56148be49b50_0 .net *"_s0", 0 0, L_0x56148bf1ef20; 1 drivers +v0x56148be48940_0 .net "clk", 0 0, o0x7ff4beabf0f8; alias, 0 drivers +v0x56148be489e0_0 .var "last", 0 0; +v0x56148be477b0_0 .net "p", 0 0, L_0x56148bf1ef90; alias, 1 drivers +v0x56148be47870_0 .net "reset", 0 0, o0x7ff4beabf188; alias, 0 drivers +v0x56148be46660_0 .net "signal", 0 0, o0x7ff4beabf1b8; alias, 0 drivers +E_0x56148be49ad0/0 .event negedge, v0x56148be47870_0; +E_0x56148be49ad0/1 .event posedge, v0x56148be48940_0; +E_0x56148be49ad0 .event/or E_0x56148be49ad0/0, E_0x56148be49ad0/1; +S_0x56148be77e90 .scope module, "e1" "edgedet" 4 62, 5 15 0, S_0x56148beb9590; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "signal" + .port_info 3 /OUTPUT 1 "p" +L_0x56148bf1f0f0 .functor NOT 1, v0x56148be54960_0, C4<0>, C4<0>, C4<0>; +L_0x56148bf1f160 .functor AND 1, o0x7ff4beabf338, L_0x56148bf1f0f0, C4<1>, C4<1>; +v0x56148be56340_0 .net *"_s0", 0 0, L_0x56148bf1f0f0; 1 drivers +v0x56148be548a0_0 .net "clk", 0 0, o0x7ff4beabf0f8; alias, 0 drivers +v0x56148be54960_0 .var "last", 0 0; +v0x56148be52ed0_0 .net "p", 0 0, L_0x56148bf1f160; alias, 1 drivers +v0x56148be52f70_0 .net "reset", 0 0, o0x7ff4beabf188; alias, 0 drivers +v0x56148be51210_0 .net "signal", 0 0, o0x7ff4beabf338; alias, 0 drivers +S_0x56148bebb030 .scope module, "ldly100us" "ldly100us" 3 288; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" + .port_info 4 /OUTPUT 1 "l" +L_0x56148bf1fd60 .functor AND 1, L_0x56148bf1f950, L_0x56148bf1fbb0, C4<1>, C4<1>; +v0x56148bd82510_0 .net *"_s0", 31 0, L_0x56148bf1f4d0; 1 drivers +L_0x7ff4bea754e0 .functor BUFT 1, C4<0000000000000000>, C4<0>, C4<0>, C4<0>; +v0x56148bd82610_0 .net *"_s11", 15 0, L_0x7ff4bea754e0; 1 drivers +L_0x7ff4bea75528 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x56148bd826f0_0 .net/2u *"_s12", 31 0, L_0x7ff4bea75528; 1 drivers +v0x56148bd827e0_0 .net *"_s14", 0 0, L_0x56148bf1f950; 1 drivers +v0x56148bd84850_0 .net *"_s16", 31 0, L_0x56148bf1fac0; 1 drivers +L_0x7ff4bea75570 .functor BUFT 1, C4<0000000000000000>, C4<0>, C4<0>, C4<0>; +v0x56148bd84930_0 .net *"_s19", 15 0, L_0x7ff4bea75570; 1 drivers +L_0x7ff4bea755b8 .functor BUFT 1, C4<00000000000000000010011100010010>, C4<0>, C4<0>, C4<0>; +v0x56148bd84a10_0 .net/2u *"_s20", 31 0, L_0x7ff4bea755b8; 1 drivers +v0x56148bd84af0_0 .net *"_s22", 0 0, L_0x56148bf1fbb0; 1 drivers +L_0x7ff4bea75450 .functor BUFT 1, C4<0000000000000000>, C4<0>, C4<0>, C4<0>; +v0x56148bd84bb0_0 .net *"_s3", 15 0, L_0x7ff4bea75450; 1 drivers +L_0x7ff4bea75498 .functor BUFT 1, C4<00000000000000000010011100010010>, C4<0>, C4<0>, C4<0>; +v0x56148bd7dbd0_0 .net/2u *"_s4", 31 0, L_0x7ff4bea75498; 1 drivers +v0x56148bd7dcb0_0 .net *"_s8", 31 0, L_0x56148bf1f810; 1 drivers +o0x7ff4beabfba8 .functor BUFZ 1, C4; HiZ drive +v0x56148bd7dd90_0 .net "clk", 0 0, o0x7ff4beabfba8; 0 drivers +o0x7ff4beabfbd8 .functor BUFZ 1, C4; HiZ drive +v0x56148bd7de50_0 .net "in", 0 0, o0x7ff4beabfbd8; 0 drivers +v0x56148bd7df10_0 .net "l", 0 0, L_0x56148bf1fd60; 1 drivers +v0x56148bcfb8b0_0 .net "p", 0 0, L_0x56148bf1f6d0; 1 drivers +v0x56148bcfb950_0 .var "r", 15 0; +o0x7ff4beabfc98 .functor BUFZ 1, C4; HiZ drive +v0x56148bcfba30_0 .net "reset", 0 0, o0x7ff4beabfc98; 0 drivers +E_0x56148becb690 .event posedge, v0x56148bcfba30_0, v0x56148bd7dd90_0; +L_0x56148bf1f4d0 .concat [ 16 16 0 0], v0x56148bcfb950_0, L_0x7ff4bea75450; +L_0x56148bf1f6d0 .cmp/eq 32, L_0x56148bf1f4d0, L_0x7ff4bea75498; +L_0x56148bf1f810 .concat [ 16 16 0 0], v0x56148bcfb950_0, L_0x7ff4bea754e0; +L_0x56148bf1f950 .cmp/ne 32, L_0x56148bf1f810, L_0x7ff4bea75528; +L_0x56148bf1fac0 .concat [ 16 16 0 0], v0x56148bcfb950_0, L_0x7ff4bea75570; +L_0x56148bf1fbb0 .cmp/gt 32, L_0x7ff4bea755b8, L_0x56148bf1fac0; +S_0x56148be328e0 .scope module, "ldly1_5us" "ldly1_5us" 3 229; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" + .port_info 4 /OUTPUT 1 "l" +v0x56148bd2d660_0 .net *"_s0", 31 0, L_0x56148bf1fe70; 1 drivers +L_0x7ff4bea75600 .functor BUFT 1, C4<000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x56148bd2d760_0 .net *"_s3", 23 0, L_0x7ff4bea75600; 1 drivers +L_0x7ff4bea75648 .functor BUFT 1, C4<00000000000000000000000010011000>, C4<0>, C4<0>, C4<0>; +v0x56148bd2d840_0 .net/2u *"_s4", 31 0, L_0x7ff4bea75648; 1 drivers +o0x7ff4beabfe48 .functor BUFZ 1, C4; HiZ drive +v0x56148bd2d900_0 .net "clk", 0 0, o0x7ff4beabfe48; 0 drivers +o0x7ff4beabfe78 .functor BUFZ 1, C4; HiZ drive +v0x56148bd2d9c0_0 .net "in", 0 0, o0x7ff4beabfe78; 0 drivers +v0x56148bd8b7b0_0 .var "l", 0 0; +v0x56148bd8b870_0 .net "p", 0 0, L_0x56148bf1ff60; 1 drivers +v0x56148bd8b930_0 .var "r", 7 0; +o0x7ff4beabff38 .functor BUFZ 1, C4; HiZ drive +v0x56148bd8ba10_0 .net "reset", 0 0, o0x7ff4beabff38; 0 drivers +E_0x56148bd7dfb0 .event posedge, v0x56148bd8ba10_0, v0x56148bd2d900_0; +L_0x56148bf1fe70 .concat [ 8 24 0 0], v0x56148bd8b930_0, L_0x7ff4bea75600; +L_0x56148bf1ff60 .cmp/eq 32, L_0x56148bf1fe70, L_0x7ff4bea75648; +S_0x56148bebcad0 .scope module, "ldly1us" "ldly1us" 3 207; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" + .port_info 4 /OUTPUT 1 "l" +v0x56148bda4d60_0 .net *"_s0", 31 0, L_0x56148bf200a0; 1 drivers +L_0x7ff4bea75690 .functor BUFT 1, C4<0000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x56148bda4e40_0 .net *"_s3", 24 0, L_0x7ff4bea75690; 1 drivers +L_0x7ff4bea756d8 .functor BUFT 1, C4<00000000000000000000000001100110>, C4<0>, C4<0>, C4<0>; +v0x56148bda4f20_0 .net/2u *"_s4", 31 0, L_0x7ff4bea756d8; 1 drivers +o0x7ff4beac00e8 .functor BUFZ 1, C4; HiZ drive +v0x56148bda4fe0_0 .net "clk", 0 0, o0x7ff4beac00e8; 0 drivers +o0x7ff4beac0118 .functor BUFZ 1, C4; HiZ drive +v0x56148bda50a0_0 .net "in", 0 0, o0x7ff4beac0118; 0 drivers +v0x56148bd8db50_0 .var "l", 0 0; +v0x56148bd8dbf0_0 .net "p", 0 0, L_0x56148bf201c0; 1 drivers +v0x56148bd8dcb0_0 .var "r", 6 0; +o0x7ff4beac01d8 .functor BUFZ 1, C4; HiZ drive +v0x56148bd8dd90_0 .net "reset", 0 0, o0x7ff4beac01d8; 0 drivers +E_0x56148be4b750 .event posedge, v0x56148bd8dd90_0, v0x56148bda4fe0_0; +L_0x56148bf200a0 .concat [ 7 25 0 0], v0x56148bd8dcb0_0, L_0x7ff4bea75690; +L_0x56148bf201c0 .cmp/eq 32, L_0x56148bf200a0, L_0x7ff4bea756d8; +S_0x56148be6f910 .scope module, "ldly2us" "ldly2us" 3 251; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" + .port_info 4 /OUTPUT 1 "l" +v0x56148bd98cb0_0 .net *"_s0", 31 0, L_0x56148bf20330; 1 drivers +L_0x7ff4bea75720 .functor BUFT 1, C4<000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x56148bd98db0_0 .net *"_s3", 23 0, L_0x7ff4bea75720; 1 drivers +L_0x7ff4bea75768 .functor BUFT 1, C4<00000000000000000000000011001010>, C4<0>, C4<0>, C4<0>; +v0x56148bd98e90_0 .net/2u *"_s4", 31 0, L_0x7ff4bea75768; 1 drivers +o0x7ff4beac0388 .functor BUFZ 1, C4; HiZ drive +v0x56148bd98f50_0 .net "clk", 0 0, o0x7ff4beac0388; 0 drivers +o0x7ff4beac03b8 .functor BUFZ 1, C4; HiZ drive +v0x56148bd99010_0 .net "in", 0 0, o0x7ff4beac03b8; 0 drivers +v0x56148bd8fec0_0 .var "l", 0 0; +v0x56148bd8ff80_0 .net "p", 0 0, L_0x56148bf20450; 1 drivers +v0x56148bd90040_0 .var "r", 7 0; +o0x7ff4beac0478 .functor BUFZ 1, C4; HiZ drive +v0x56148bd90120_0 .net "reset", 0 0, o0x7ff4beac0478; 0 drivers +E_0x56148bd8def0 .event posedge, v0x56148bd90120_0, v0x56148bd98f50_0; +L_0x56148bf20330 .concat [ 8 24 0 0], v0x56148bd90040_0, L_0x7ff4bea75720; +L_0x56148bf20450 .cmp/eq 32, L_0x56148bf20330, L_0x7ff4bea75768; +S_0x56148be713e0 .scope module, "memif" "memif" 6 1; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 2 "s_address" + .port_info 3 /INPUT 1 "s_write" + .port_info 4 /INPUT 1 "s_read" + .port_info 5 /INPUT 32 "s_writedata" + .port_info 6 /OUTPUT 32 "s_readdata" + .port_info 7 /OUTPUT 1 "s_waitrequest" + .port_info 8 /OUTPUT 18 "m_address" + .port_info 9 /OUTPUT 1 "m_write" + .port_info 10 /OUTPUT 1 "m_read" + .port_info 11 /OUTPUT 36 "m_writedata" + .port_info 12 /INPUT 36 "m_readdata" + .port_info 13 /INPUT 1 "m_waitrequest" +L_0x56148bf205c0 .functor BUFZ 18, v0x56148bd96920_0, C4<000000000000000000>, C4<000000000000000000>, C4<000000000000000000>; +L_0x56148bf20630 .functor BUFZ 36, v0x56148bda71c0_0, C4<000000000000000000000000000000000000>, C4<000000000000000000000000000000000000>, C4<000000000000000000000000000000000000>; +L_0x56148bf20b00 .functor OR 1, L_0x56148bf207d0, L_0x56148bf209a0, C4<0>, C4<0>; +L_0x56148bf20c60 .functor AND 1, L_0x56148bf20b00, L_0x56148bf20b70, C4<1>, C4<1>; +L_0x56148bf20da0 .functor OR 1, L_0x56148bf20c60, v0x56148bd5cba0_0, C4<0>, C4<0>; +v0x56148bd895a0_0 .net *"_s4", 0 0, L_0x56148bf20b00; 1 drivers +L_0x7ff4bea757b0 .functor BUFT 1, C4<10>, C4<0>, C4<0>, C4<0>; +v0x56148bd896a0_0 .net/2u *"_s6", 1 0, L_0x7ff4bea757b0; 1 drivers +v0x56148bd89780_0 .net *"_s8", 0 0, L_0x56148bf20b70; 1 drivers +v0x56148bd96920_0 .var "addr", 17 0; +o0x7ff4beac05c8 .functor BUFZ 1, C4; HiZ drive +v0x56148bd96a00_0 .net "clk", 0 0, o0x7ff4beac05c8; 0 drivers +v0x56148bd96b40_0 .net "m_address", 17 0, L_0x56148bf205c0; 1 drivers +v0x56148bd96c20_0 .var "m_read", 0 0; +o0x7ff4beac0a18 .functor BUFZ 36, C4; HiZ drive +v0x56148bd03560_0 .net "m_readdata", 35 0, o0x7ff4beac0a18; 0 drivers +o0x7ff4beac0a48 .functor BUFZ 1, C4; HiZ drive +v0x56148bd03640_0 .net "m_waitrequest", 0 0, o0x7ff4beac0a48; 0 drivers +v0x56148bd03790_0 .var "m_write", 0 0; +v0x56148bd03850_0 .net "m_writedata", 35 0, L_0x56148bf20630; 1 drivers +v0x56148bcfce40_0 .net "read_edge", 0 0, L_0x56148bf209a0; 1 drivers +v0x56148bcfcee0_0 .net "req", 0 0, L_0x56148bf20c60; 1 drivers +o0x7ff4beac0658 .functor BUFZ 1, C4; HiZ drive +v0x56148bcfcf80_0 .net "reset", 0 0, o0x7ff4beac0658; 0 drivers +o0x7ff4beac0b08 .functor BUFZ 2, C4; HiZ drive +v0x56148bcfd020_0 .net "s_address", 1 0, o0x7ff4beac0b08; 0 drivers +o0x7ff4beac0808 .functor BUFZ 1, C4; HiZ drive +v0x56148bcfd100_0 .net "s_read", 0 0, o0x7ff4beac0808; 0 drivers +v0x56148bcfd1a0_0 .var "s_readdata", 31 0; +v0x56148bd5c980_0 .net "s_waitrequest", 0 0, L_0x56148bf20da0; 1 drivers +o0x7ff4beac0688 .functor BUFZ 1, C4; HiZ drive +v0x56148bd5ca40_0 .net "s_write", 0 0, o0x7ff4beac0688; 0 drivers +o0x7ff4beac0b98 .functor BUFZ 32, C4; HiZ drive +v0x56148bd5cae0_0 .net "s_writedata", 31 0, o0x7ff4beac0b98; 0 drivers +v0x56148bd5cba0_0 .var "waiting", 0 0; +v0x56148bda71c0_0 .var "word", 35 0; +v0x56148bda72a0_0 .net "write_edge", 0 0, L_0x56148bf207d0; 1 drivers +E_0x56148bd90280 .event edge, v0x56148bcfd020_0, v0x56148bda71c0_0; +L_0x56148bf20b70 .cmp/eq 2, o0x7ff4beac0b08, L_0x7ff4bea757b0; +S_0x56148be79960 .scope module, "e0" "edgedet" 6 29, 5 15 0, S_0x56148be713e0; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "signal" + .port_info 3 /OUTPUT 1 "p" +L_0x56148bf20700 .functor NOT 1, v0x56148bd924b0_0, C4<0>, C4<0>, C4<0>; +L_0x56148bf207d0 .functor AND 1, o0x7ff4beac0688, L_0x56148bf20700, C4<1>, C4<1>; +v0x56148bd922f0_0 .net *"_s0", 0 0, L_0x56148bf20700; 1 drivers +v0x56148bd923f0_0 .net "clk", 0 0, o0x7ff4beac05c8; alias, 0 drivers +v0x56148bd924b0_0 .var "last", 0 0; +v0x56148bd92580_0 .net "p", 0 0, L_0x56148bf207d0; alias, 1 drivers +v0x56148bd945a0_0 .net "reset", 0 0, o0x7ff4beac0658; alias, 0 drivers +v0x56148bd946b0_0 .net "signal", 0 0, o0x7ff4beac0688; alias, 0 drivers +E_0x56148bd92270/0 .event negedge, v0x56148bd945a0_0; +E_0x56148bd92270/1 .event posedge, v0x56148bd923f0_0; +E_0x56148bd92270 .event/or E_0x56148bd92270/0, E_0x56148bd92270/1; +S_0x56148bd947f0 .scope module, "e1" "edgedet" 6 30, 5 15 0, S_0x56148be713e0; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "signal" + .port_info 3 /OUTPUT 1 "p" +L_0x56148bf20930 .functor NOT 1, v0x56148bd872c0_0, C4<0>, C4<0>, C4<0>; +L_0x56148bf209a0 .functor AND 1, o0x7ff4beac0808, L_0x56148bf20930, C4<1>, C4<1>; +v0x56148bd870f0_0 .net *"_s0", 0 0, L_0x56148bf20930; 1 drivers +v0x56148bd871d0_0 .net "clk", 0 0, o0x7ff4beac05c8; alias, 0 drivers +v0x56148bd872c0_0 .var "last", 0 0; +v0x56148bd87390_0 .net "p", 0 0, L_0x56148bf209a0; alias, 1 drivers +v0x56148bd87430_0 .net "reset", 0 0, o0x7ff4beac0658; alias, 0 drivers +v0x56148bd89490_0 .net "signal", 0 0, o0x7ff4beac0808; alias, 0 drivers +S_0x56148be72e50 .scope module, "memory" "memory" 4 1; + .timescale -9 -9; + .port_info 0 /INPUT 1 "i_clk" + .port_info 1 /INPUT 1 "i_reset_n" + .port_info 2 /INPUT 18 "i_address" + .port_info 3 /INPUT 1 "i_write" + .port_info 4 /INPUT 1 "i_read" + .port_info 5 /INPUT 36 "i_writedata" + .port_info 6 /OUTPUT 36 "o_readdata" + .port_info 7 /OUTPUT 1 "o_waitrequest" +v0x56148bd9e480_0 .net *"_s1", 3 0, L_0x56148bf20e60; 1 drivers +v0x56148bd9e560_0 .net *"_s12", 35 0, L_0x56148bf21330; 1 drivers +v0x56148bd9e640_0 .net *"_s14", 15 0, L_0x56148bf213d0; 1 drivers +L_0x7ff4bea75888 .functor BUFT 1, C4<00>, C4<0>, C4<0>, C4<0>; +v0x56148bd9e700_0 .net *"_s17", 1 0, L_0x7ff4bea75888; 1 drivers +L_0x7ff4bea758d0 .functor BUFT 1, C4<000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x56148bd9e7e0_0 .net/2u *"_s18", 35 0, L_0x7ff4bea758d0; 1 drivers +v0x56148bd9b010_0 .net *"_s2", 31 0, L_0x56148bf20f30; 1 drivers +L_0x7ff4bea75918 .functor BUFT 1, C4<000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x56148bd9b0f0_0 .net/2u *"_s22", 35 0, L_0x7ff4bea75918; 1 drivers +L_0x7ff4bea757f8 .functor BUFT 1, C4<0000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x56148bd9b1d0_0 .net *"_s5", 27 0, L_0x7ff4bea757f8; 1 drivers +L_0x7ff4bea75840 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x56148bd9b2b0_0 .net/2u *"_s6", 31 0, L_0x7ff4bea75840; 1 drivers +v0x56148bd9b390_0 .net "addr", 13 0, L_0x56148bf21210; 1 drivers +v0x56148bda18f0_0 .net "addrok", 0 0, L_0x56148bf210a0; 1 drivers +o0x7ff4beac10d8 .functor BUFZ 18, C4; HiZ drive +v0x56148bda19b0_0 .net "i_address", 17 0, o0x7ff4beac10d8; 0 drivers +o0x7ff4beac1108 .functor BUFZ 1, C4; HiZ drive +v0x56148bda1a90_0 .net "i_clk", 0 0, o0x7ff4beac1108; 0 drivers +o0x7ff4beac1138 .functor BUFZ 1, C4; HiZ drive +v0x56148bda1b50_0 .net "i_read", 0 0, o0x7ff4beac1138; 0 drivers +o0x7ff4beac1168 .functor BUFZ 1, C4; HiZ drive +v0x56148bda1c10_0 .net "i_reset_n", 0 0, o0x7ff4beac1168; 0 drivers +o0x7ff4beac1198 .functor BUFZ 1, C4; HiZ drive +v0x56148bd1efd0_0 .net "i_write", 0 0, o0x7ff4beac1198; 0 drivers +o0x7ff4beac11c8 .functor BUFZ 36, C4; HiZ drive +v0x56148bd1f090_0 .net "i_writedata", 35 0, o0x7ff4beac11c8; 0 drivers +v0x56148bd1f280 .array "mem", 16383 0, 35 0; +v0x56148bd1f340_0 .net "memword", 35 0, L_0x56148bf215a0; 1 drivers +v0x56148bd14eb0_0 .net "o_readdata", 35 0, L_0x56148bf21940; 1 drivers +L_0x7ff4bea75960 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +v0x56148bd14f90_0 .net "o_waitrequest", 0 0, L_0x7ff4bea75960; 1 drivers +E_0x56148bd89820/0 .event negedge, v0x56148bda1c10_0; +E_0x56148bd89820/1 .event posedge, v0x56148bda1a90_0; +E_0x56148bd89820 .event/or E_0x56148bd89820/0, E_0x56148bd89820/1; +L_0x56148bf20e60 .part o0x7ff4beac10d8, 14, 4; +L_0x56148bf20f30 .concat [ 4 28 0 0], L_0x56148bf20e60, L_0x7ff4bea757f8; +L_0x56148bf210a0 .cmp/eq 32, L_0x56148bf20f30, L_0x7ff4bea75840; +L_0x56148bf21210 .part o0x7ff4beac10d8, 0, 14; +L_0x56148bf21330 .array/port v0x56148bd1f280, L_0x56148bf213d0; +L_0x56148bf213d0 .concat [ 14 2 0 0], L_0x56148bf21210, L_0x7ff4bea75888; +L_0x56148bf215a0 .functor MUXZ 36, L_0x7ff4bea758d0, L_0x56148bf21330, L_0x56148bf210a0, C4<>; +L_0x56148bf21940 .functor MUXZ 36, L_0x7ff4bea75918, L_0x56148bf215a0, o0x7ff4beac1138, C4<>; +S_0x56148be748f0 .scope module, "tb_membusif" "tb_membusif" 7 4; + .timescale -9 -9; +L_0x56148bf21ad0 .functor OR 36, L_0x56148bf26f50, L_0x56148bf307f0, C4<000000000000000000000000000000000000>, C4<000000000000000000000000000000000000>; +L_0x56148bf21c30 .functor OR 1, L_0x56148bf25b40, L_0x56148bf30590, C4<0>, C4<0>; +L_0x56148bf21d90 .functor OR 1, L_0x56148bf26df0, L_0x56148bf306a0, C4<0>, C4<0>; +L_0x56148bf2e7c0 .functor NOT 1, v0x56148bcfeb70_0, C4<0>, C4<0>, C4<0>; +L_0x56148bf387b0 .functor NOT 1, v0x56148bcfeb70_0, C4<0>, C4<0>, C4<0>; +v0x56148bf06140_0 .var "a_address", 1 0; +v0x56148bf0c430_0 .var "a_read", 0 0; +v0x56148bf0c520_0 .net "a_readdata", 31 0, v0x56148bf0ba70_0; 1 drivers +v0x56148bf0c5c0_0 .net "a_waitrequest", 0 0, L_0x56148bf22a00; 1 drivers +v0x56148bf0c660_0 .var "a_write", 0 0; +v0x56148bf0c7a0_0 .var "a_writedata", 31 0; +v0x56148bf0c840_0 .net "b_addr_ack", 0 0, L_0x56148bf21c30; 1 drivers +v0x56148bf0c8e0_0 .net "b_addr_ack_0", 0 0, L_0x56148bf25b40; 1 drivers +v0x56148bf0c9b0_0 .net "b_addr_ack_1", 0 0, L_0x56148bf30590; 1 drivers +v0x56148bf0cb10_0 .net "b_fmc_select", 0 0, v0x56148bf0ac20_0; 1 drivers +v0x56148bf0cbb0_0 .net "b_ma", 21 35, L_0x56148bf21ef0; 1 drivers +v0x56148bf0cc50_0 .net "b_mb_read", 0 35, L_0x56148bf21ad0; 1 drivers +v0x56148bf0cd20_0 .net "b_mb_read_0", 0 35, L_0x56148bf26f50; 1 drivers +v0x56148bf0cdf0_0 .net "b_mb_read_1", 0 35, L_0x56148bf307f0; 1 drivers +v0x56148bf0cec0_0 .net "b_mb_write", 0 35, L_0x56148bf23cc0; 1 drivers +v0x56148bf0cf60_0 .net "b_rd_rq", 0 0, v0x56148bf0afc0_0; 1 drivers +v0x56148bf0d000_0 .net "b_rd_rs", 0 0, L_0x56148bf21d90; 1 drivers +v0x56148bf0d0d0_0 .net "b_rd_rs_0", 0 0, L_0x56148bf26df0; 1 drivers +v0x56148bf0d1a0_0 .net "b_rd_rs_1", 0 0, L_0x56148bf306a0; 1 drivers +v0x56148bf0d270_0 .net "b_rq_cyc", 0 0, v0x56148bf0b170_0; 1 drivers +v0x56148bf0d310_0 .net "b_sel", 18 21, L_0x56148bf21f90; 1 drivers +v0x56148bf0d3b0_0 .net "b_wr_rq", 0 0, v0x56148bf0b480_0; 1 drivers +v0x56148bf0d450_0 .net "b_wr_rs", 0 0, L_0x56148bf22d00; 1 drivers +v0x56148bf0d4f0_0 .net "clk", 0 0, v0x56148bd15230_0; 1 drivers +v0x56148bf0d590_0 .net "reset", 0 0, v0x56148bcfeb70_0; 1 drivers +E_0x56148bd15150 .event negedge, v0x56148bf07b70_0; +E_0x56148bd151d0 .event negedge, v0x56148bf07370_0; +S_0x56148bcfe930 .scope module, "clock" "clock" 7 7, 5 1 0, S_0x56148be748f0; + .timescale -9 -9; + .port_info 0 /OUTPUT 1 "clk" + .port_info 1 /OUTPUT 1 "reset" +v0x56148bd15230_0 .var "clk", 0 0; +v0x56148bcfeb70_0 .var "reset", 0 0; +S_0x56148bd810e0 .scope module, "cmem" "core161c" 7 58, 8 1 0, S_0x56148be748f0; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "power" + .port_info 3 /INPUT 1 "sw_single_step" + .port_info 4 /INPUT 1 "sw_restart" + .port_info 5 /INPUT 1 "membus_wr_rs_p0" + .port_info 6 /INPUT 1 "membus_rq_cyc_p0" + .port_info 7 /INPUT 1 "membus_rd_rq_p0" + .port_info 8 /INPUT 1 "membus_wr_rq_p0" + .port_info 9 /INPUT 15 "membus_ma_p0" + .port_info 10 /INPUT 4 "membus_sel_p0" + .port_info 11 /INPUT 1 "membus_fmc_select_p0" + .port_info 12 /INPUT 36 "membus_mb_in_p0" + .port_info 13 /OUTPUT 1 "membus_addr_ack_p0" + .port_info 14 /OUTPUT 1 "membus_rd_rs_p0" + .port_info 15 /OUTPUT 36 "membus_mb_out_p0" + .port_info 16 /INPUT 1 "membus_wr_rs_p1" + .port_info 17 /INPUT 1 "membus_rq_cyc_p1" + .port_info 18 /INPUT 1 "membus_rd_rq_p1" + .port_info 19 /INPUT 1 "membus_wr_rq_p1" + .port_info 20 /INPUT 15 "membus_ma_p1" + .port_info 21 /INPUT 4 "membus_sel_p1" + .port_info 22 /INPUT 1 "membus_fmc_select_p1" + .port_info 23 /INPUT 36 "membus_mb_in_p1" + .port_info 24 /OUTPUT 1 "membus_addr_ack_p1" + .port_info 25 /OUTPUT 1 "membus_rd_rs_p1" + .port_info 26 /OUTPUT 36 "membus_mb_out_p1" + .port_info 27 /INPUT 1 "membus_wr_rs_p2" + .port_info 28 /INPUT 1 "membus_rq_cyc_p2" + .port_info 29 /INPUT 1 "membus_rd_rq_p2" + .port_info 30 /INPUT 1 "membus_wr_rq_p2" + .port_info 31 /INPUT 15 "membus_ma_p2" + .port_info 32 /INPUT 4 "membus_sel_p2" + .port_info 33 /INPUT 1 "membus_fmc_select_p2" + .port_info 34 /INPUT 36 "membus_mb_in_p2" + .port_info 35 /OUTPUT 1 "membus_addr_ack_p2" + .port_info 36 /OUTPUT 1 "membus_rd_rs_p2" + .port_info 37 /OUTPUT 36 "membus_mb_out_p2" + .port_info 38 /INPUT 1 "membus_wr_rs_p3" + .port_info 39 /INPUT 1 "membus_rq_cyc_p3" + .port_info 40 /INPUT 1 "membus_rd_rq_p3" + .port_info 41 /INPUT 1 "membus_wr_rq_p3" + .port_info 42 /INPUT 15 "membus_ma_p3" + .port_info 43 /INPUT 4 "membus_sel_p3" + .port_info 44 /INPUT 1 "membus_fmc_select_p3" + .port_info 45 /INPUT 36 "membus_mb_in_p3" + .port_info 46 /OUTPUT 1 "membus_addr_ack_p3" + .port_info 47 /OUTPUT 1 "membus_rd_rs_p3" + .port_info 48 /OUTPUT 36 "membus_mb_out_p3" +P_0x56148bd812b0 .param/l "memsel_p0" 0 8 58, C4<0000>; +P_0x56148bd812f0 .param/l "memsel_p1" 0 8 59, C4<0000>; +P_0x56148bd81330 .param/l "memsel_p2" 0 8 60, C4<0000>; +P_0x56148bd81370 .param/l "memsel_p3" 0 8 61, C4<0000>; +L_0x56148bf23f20 .functor NOT 1, v0x56148bf0ac20_0, C4<0>, C4<0>, C4<0>; +L_0x56148bf24020 .functor AND 1, L_0x56148bf23e30, L_0x56148bf23f20, C4<1>, C4<1>; +L_0x56148bf240e0 .functor AND 1, L_0x56148bf24020, v0x56148bf0b170_0, C4<1>, C4<1>; +L_0x7ff4bea76f50 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x56148bf242d0 .functor NOT 1, L_0x7ff4bea76f50, C4<0>, C4<0>, C4<0>; +L_0x56148bf24340 .functor AND 1, L_0x56148bf24230, L_0x56148bf242d0, C4<1>, C4<1>; +L_0x7ff4bea76de8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x56148bf24450 .functor AND 1, L_0x56148bf24340, L_0x7ff4bea76de8, C4<1>, C4<1>; +L_0x7ff4bea77190 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x56148bf24640 .functor NOT 1, L_0x7ff4bea77190, C4<0>, C4<0>, C4<0>; +L_0x56148bf246b0 .functor AND 1, L_0x56148bf24550, L_0x56148bf24640, C4<1>, C4<1>; +L_0x7ff4bea77028 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x56148bf24810 .functor AND 1, L_0x56148bf246b0, L_0x7ff4bea77028, C4<1>, C4<1>; +L_0x7ff4bea773d0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x56148bf24a20 .functor NOT 1, L_0x7ff4bea773d0, C4<0>, C4<0>, C4<0>; +L_0x56148bf24b50 .functor AND 1, L_0x56148bf248d0, L_0x56148bf24a20, C4<1>, C4<1>; +L_0x7ff4bea77268 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x56148bf24c10 .functor AND 1, L_0x56148bf24b50, L_0x7ff4bea77268, C4<1>, C4<1>; +L_0x56148bf24d40 .functor AND 1, L_0x56148bf240e0, v0x56148beea1a0_0, C4<1>, C4<1>; +L_0x56148bf24e00 .functor AND 1, L_0x56148bf24450, v0x56148beea1a0_0, C4<1>, C4<1>; +L_0x56148bf24cd0 .functor AND 1, L_0x56148bf24810, v0x56148beea1a0_0, C4<1>, C4<1>; +L_0x56148bf25010 .functor AND 1, L_0x56148bf24c10, v0x56148beea1a0_0, C4<1>, C4<1>; +L_0x56148bf25b40 .functor AND 1, L_0x56148bf2b4a0, v0x56148beea520_0, C4<1>, C4<1>; +L_0x56148bf26df0 .functor AND 1, L_0x56148bf2b680, v0x56148beea520_0, C4<1>, C4<1>; +L_0x56148bf27040 .functor AND 1, L_0x56148bf2b4a0, v0x56148beea5e0_0, C4<1>, C4<1>; +L_0x56148bf270b0 .functor AND 1, L_0x56148bf2b680, v0x56148beea5e0_0, C4<1>, C4<1>; +L_0x56148bf274c0 .functor AND 1, L_0x56148bf2b4a0, v0x56148beeaab0_0, C4<1>, C4<1>; +L_0x56148bf27530 .functor AND 1, L_0x56148bf2b680, v0x56148beeaab0_0, C4<1>, C4<1>; +L_0x56148bf27870 .functor AND 1, L_0x56148bf2b4a0, v0x56148beeab70_0, C4<1>, C4<1>; +L_0x56148bf278e0 .functor AND 1, L_0x56148bf2b680, v0x56148beeab70_0, C4<1>, C4<1>; +L_0x7ff4bea76d58 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x56148bf285e0 .functor AND 1, L_0x7ff4bea76d58, v0x56148beeb2b0_0, C4<1>, C4<1>; +L_0x56148bf28a40 .functor OR 1, L_0x56148bf24d40, L_0x56148bf24e00, C4<0>, C4<0>; +L_0x56148bf27950 .functor OR 1, L_0x56148bf28a40, L_0x56148bf24cd0, C4<0>, C4<0>; +L_0x56148bf28c80 .functor OR 1, L_0x56148bf27950, L_0x56148bf25010, C4<0>, C4<0>; +L_0x56148bf29ff0 .functor AND 1, v0x56148beeadd0_0, v0x56148beeac30_0, C4<1>, C4<1>; +L_0x56148bf2a0b0 .functor OR 1, L_0x56148bf280f0, L_0x56148bf2dc90, C4<0>, C4<0>; +L_0x56148bf2a220 .functor NOT 1, v0x56148beeb2b0_0, C4<0>, C4<0>, C4<0>; +L_0x56148bf2a2e0 .functor AND 1, v0x56148bedf060_0, L_0x56148bf2a220, C4<1>, C4<1>; +L_0x56148bf2a4b0 .functor OR 1, L_0x56148bf2a2e0, v0x56148bedd380_0, C4<0>, C4<0>; +L_0x56148bf2a5c0 .functor OR 1, L_0x56148bf2a4b0, L_0x56148bf28480, C4<0>, C4<0>; +L_0x56148bf2a7a0 .functor NOT 1, v0x56148bee9f60_0, C4<0>, C4<0>, C4<0>; +L_0x56148bf2a810 .functor AND 1, L_0x56148bf2a7a0, L_0x56148bf2e3b0, C4<1>, C4<1>; +L_0x56148bf2a680 .functor OR 1, v0x56148bedfb60_0, L_0x56148bf2a810, C4<0>, C4<0>; +L_0x56148bf2aa50 .functor OR 1, L_0x56148bf2a680, L_0x56148bf29ab0, C4<0>, C4<0>; +L_0x56148bf2ac00 .functor AND 1, L_0x56148bf2e610, v0x56148bee9f60_0, C4<1>, C4<1>; +L_0x56148bf2ad10 .functor OR 1, L_0x56148bf28930, L_0x56148bf2ac00, C4<0>, C4<0>; +L_0x56148bf2aed0 .functor NOT 1, v0x56148bee9f60_0, C4<0>, C4<0>, C4<0>; +L_0x56148bf2af40 .functor AND 1, v0x56148bee2c70_0, L_0x56148bf2aed0, C4<1>, C4<1>; +L_0x56148bf2b1b0 .functor OR 1, L_0x56148bf2af40, L_0x56148bf29e90, C4<0>, C4<0>; +L_0x56148bf2b270 .functor AND 1, L_0x56148bf2def0, v0x56148bee9ea0_0, C4<1>, C4<1>; +L_0x56148bf2e750 .functor BUFZ 14, v0x56148bee9dc0_0, C4<00000000000000>, C4<00000000000000>, C4<00000000000000>; +L_0x7ff4bea75d08 .functor BUFT 1, C4<0000>, C4<0>, C4<0>, C4<0>; +v0x56148bee6fd0_0 .net/2u *"_s0", 3 0, L_0x7ff4bea75d08; 1 drivers +L_0x7ff4bea75d50 .functor BUFT 1, C4<0000>, C4<0>, C4<0>, C4<0>; +v0x56148bee70d0_0 .net/2u *"_s10", 3 0, L_0x7ff4bea75d50; 1 drivers +L_0x7ff4bea75f90 .functor BUFT 1, C4<000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x56148bee71b0_0 .net/2u *"_s102", 35 0, L_0x7ff4bea75f90; 1 drivers +L_0x7ff4bea75fd8 .functor BUFT 1, C4<000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x56148bee7270_0 .net/2u *"_s110", 35 0, L_0x7ff4bea75fd8; 1 drivers +L_0x7ff4bea76020 .functor BUFT 1, C4<000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x56148bee7350_0 .net/2u *"_s118", 35 0, L_0x7ff4bea76020; 1 drivers +v0x56148bee7480_0 .net *"_s12", 0 0, L_0x56148bf24230; 1 drivers +L_0x7ff4bea76068 .functor BUFT 1, C4<000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x56148bee7540_0 .net/2u *"_s126", 35 0, L_0x7ff4bea76068; 1 drivers +L_0x7ff4bea760b0 .functor BUFT 1, C4<000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x56148bee7620_0 .net/2u *"_s130", 35 0, L_0x7ff4bea760b0; 1 drivers +v0x56148bee7700_0 .net *"_s136", 0 0, L_0x56148bf28a40; 1 drivers +v0x56148bee77e0_0 .net *"_s138", 0 0, L_0x56148bf27950; 1 drivers +v0x56148bee78c0_0 .net *"_s14", 0 0, L_0x56148bf242d0; 1 drivers +v0x56148bee79a0_0 .net *"_s148", 0 0, L_0x56148bf2a220; 1 drivers +v0x56148bee7a80_0 .net *"_s150", 0 0, L_0x56148bf2a2e0; 1 drivers +v0x56148bee7b60_0 .net *"_s152", 0 0, L_0x56148bf2a4b0; 1 drivers +v0x56148bee7c40_0 .net *"_s156", 0 0, L_0x56148bf2a7a0; 1 drivers +v0x56148bee7d20_0 .net *"_s158", 0 0, L_0x56148bf2a810; 1 drivers +v0x56148bee7e00_0 .net *"_s16", 0 0, L_0x56148bf24340; 1 drivers +v0x56148bee7ee0_0 .net *"_s160", 0 0, L_0x56148bf2a680; 1 drivers +v0x56148bee7fc0_0 .net *"_s164", 0 0, L_0x56148bf2ac00; 1 drivers +v0x56148bee80a0_0 .net *"_s168", 0 0, L_0x56148bf2aed0; 1 drivers +v0x56148bee8180_0 .net *"_s170", 0 0, L_0x56148bf2af40; 1 drivers +v0x56148bee8260_0 .net *"_s2", 0 0, L_0x56148bf23e30; 1 drivers +L_0x7ff4bea75d98 .functor BUFT 1, C4<0000>, C4<0>, C4<0>, C4<0>; +v0x56148bee8320_0 .net/2u *"_s20", 3 0, L_0x7ff4bea75d98; 1 drivers +v0x56148bee8400_0 .net *"_s22", 0 0, L_0x56148bf24550; 1 drivers +v0x56148bee84c0_0 .net *"_s24", 0 0, L_0x56148bf24640; 1 drivers +v0x56148bee85a0_0 .net *"_s26", 0 0, L_0x56148bf246b0; 1 drivers +L_0x7ff4bea75de0 .functor BUFT 1, C4<0000>, C4<0>, C4<0>, C4<0>; +v0x56148bee8680_0 .net/2u *"_s30", 3 0, L_0x7ff4bea75de0; 1 drivers +v0x56148bee8760_0 .net *"_s32", 0 0, L_0x56148bf248d0; 1 drivers +v0x56148bee8820_0 .net *"_s34", 0 0, L_0x56148bf24a20; 1 drivers +v0x56148bee8900_0 .net *"_s36", 0 0, L_0x56148bf24b50; 1 drivers +v0x56148bee89e0_0 .net *"_s4", 0 0, L_0x56148bf23f20; 1 drivers +L_0x7ff4bea75e28 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +v0x56148bee8ac0_0 .net/2u *"_s48", 0 0, L_0x7ff4bea75e28; 1 drivers +v0x56148bee8ba0_0 .net *"_s50", 0 0, L_0x56148bf251f0; 1 drivers +v0x56148bee8c80_0 .net *"_s52", 0 0, L_0x56148bf252c0; 1 drivers +v0x56148bee8d60_0 .net *"_s54", 0 0, L_0x56148bf25420; 1 drivers +L_0x7ff4bea75e70 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +v0x56148bee8e40_0 .net/2u *"_s58", 0 0, L_0x7ff4bea75e70; 1 drivers +v0x56148bee8f20_0 .net *"_s6", 0 0, L_0x56148bf24020; 1 drivers +v0x56148bee9000_0 .net *"_s60", 0 0, L_0x56148bf25700; 1 drivers +v0x56148bee90e0_0 .net *"_s62", 0 0, L_0x56148bf25870; 1 drivers +v0x56148bee91c0_0 .net *"_s64", 0 0, L_0x56148bf25960; 1 drivers +L_0x7ff4bea75eb8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +v0x56148bee92a0_0 .net/2u *"_s68", 0 0, L_0x7ff4bea75eb8; 1 drivers +v0x56148bee9380_0 .net *"_s70", 0 0, L_0x56148bf25ce0; 1 drivers +v0x56148bee9460_0 .net *"_s72", 0 0, L_0x56148bf25d80; 1 drivers +v0x56148bee9540_0 .net *"_s74", 0 0, L_0x56148bf25f20; 1 drivers +L_0x7ff4bea75f00 .functor BUFT 1, C4<000000000000000>, C4<0>, C4<0>, C4<0>; +v0x56148bee9620_0 .net/2u *"_s78", 14 0, L_0x7ff4bea75f00; 1 drivers +v0x56148bee9700_0 .net *"_s80", 14 0, L_0x56148bf261f0; 1 drivers +v0x56148bee97e0_0 .net *"_s82", 14 0, L_0x56148bf26350; 1 drivers +v0x56148bee98c0_0 .net *"_s84", 14 0, L_0x56148bf264c0; 1 drivers +L_0x7ff4bea75f48 .functor BUFT 1, C4<000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x56148bee99a0_0 .net/2u *"_s88", 35 0, L_0x7ff4bea75f48; 1 drivers +v0x56148bee9a80_0 .net *"_s90", 35 0, L_0x56148bf263f0; 1 drivers +v0x56148bee9b60_0 .net *"_s92", 35 0, L_0x56148bf268b0; 1 drivers +v0x56148bee9c40_0 .net *"_s94", 35 0, L_0x56148bf26a90; 1 drivers +v0x56148bee9d20_0 .net "clk", 0 0, v0x56148bd15230_0; alias, 1 drivers +v0x56148bee9dc0_0 .var "cma", 22 35; +v0x56148bee9ea0_0 .var "cma_rd_rq", 0 0; +v0x56148bee9f60_0 .var "cma_wr_rq", 0 0; +v0x56148beea020_0 .var "cmb", 0 35; +v0x56148beea100_0 .net "cmc_addr_ack", 0 0, L_0x56148bf2b4a0; 1 drivers +v0x56148beea1a0_0 .var "cmc_await_rq", 0 0; +v0x56148beea240_0 .net "cmc_cmb_clr", 0 0, v0x56148bee0ce0_0; 1 drivers +v0x56148beea310_0 .var "cmc_inhibit", 0 0; +v0x56148beea3b0_0 .net "cmc_key_restart", 0 0, L_0x56148bf28480; 1 drivers +v0x56148beea480_0 .var "cmc_last_proc", 0 0; +v0x56148beea520_0 .var "cmc_p0_act", 0 0; +v0x56148beea5e0_0 .var "cmc_p1_act", 0 0; +v0x56148beeaab0_0 .var "cmc_p2_act", 0 0; +v0x56148beeab70_0 .var "cmc_p3_act", 0 0; +v0x56148beeac30_0 .var "cmc_proc_rs", 0 0; +v0x56148beead00_0 .net "cmc_proc_rs_P", 0 0, L_0x56148bf29ab0; 1 drivers +v0x56148beeadd0_0 .var "cmc_pse_sync", 0 0; +v0x56148beeae70_0 .net "cmc_pwr_clr", 0 0, L_0x56148bf280f0; 1 drivers +v0x56148beeaf10_0 .net "cmc_pwr_clr_D", 0 0, L_0x56148bf2c5c0; 1 drivers +v0x56148beeb000_0 .net "cmc_pwr_start", 0 0, v0x56148bedd380_0; 1 drivers +v0x56148beeb0a0_0 .var "cmc_rd", 0 0; +v0x56148beeb140_0 .net "cmc_rd_rs", 0 0, L_0x56148bf2b680; 1 drivers +v0x56148beeb1e0_0 .net "cmc_state_clr", 0 0, v0x56148bee0700_0; 1 drivers +v0x56148beeb2b0_0 .var "cmc_stop", 0 0; +v0x56148beeb350_0 .net "cmc_strb_sa", 0 0, v0x56148bedf5f0_0; 1 drivers +v0x56148beeb3f0_0 .net "cmc_strb_sa_D0", 0 0, L_0x56148bf2e150; 1 drivers +v0x56148beeb4e0_0 .net "cmc_strb_sa_D1", 0 0, L_0x56148bf2e3b0; 1 drivers +v0x56148beeb580_0 .net "cmc_strb_sa_D2", 0 0, L_0x56148bf2e610; 1 drivers +v0x56148beeb650_0 .net "cmc_t0", 0 0, L_0x56148bf28930; 1 drivers +v0x56148beeb740_0 .net "cmc_t0_D", 0 0, L_0x56148bf2ca20; 1 drivers +v0x56148beeb830_0 .net "cmc_t1", 0 0, v0x56148bee12f0_0; 1 drivers +v0x56148beeb8d0_0 .net "cmc_t10", 0 0, v0x56148bedfb60_0; 1 drivers +v0x56148beeb9c0_0 .net "cmc_t10_D", 0 0, L_0x56148bf2c7f0; 1 drivers +v0x56148beebab0_0 .net "cmc_t11", 0 0, v0x56148bee0160_0; 1 drivers +v0x56148beebb50_0 .net "cmc_t12", 0 0, v0x56148bedcd70_0; 1 drivers +v0x56148beebbf0_0 .net "cmc_t1_D", 0 0, L_0x56148bf2cc50; 1 drivers +v0x56148beebce0_0 .net "cmc_t2", 0 0, v0x56148bee1cd0_0; 1 drivers +v0x56148beebd80_0 .net "cmc_t2_D0", 0 0, L_0x56148bf2ce80; 1 drivers +v0x56148beebe70_0 .net "cmc_t2_D1", 0 0, L_0x56148bf2def0; 1 drivers +v0x56148beebf10_0 .net "cmc_t4", 0 0, v0x56148bee22a0_0; 1 drivers +v0x56148beec000_0 .net "cmc_t4_D", 0 0, L_0x56148bf2d0b0; 1 drivers +v0x56148beec0f0_0 .net "cmc_t5", 0 0, v0x56148bee2c70_0; 1 drivers +v0x56148beec190_0 .net "cmc_t6", 0 0, v0x56148bedd920_0; 1 drivers +v0x56148beec280_0 .net "cmc_t6_D", 0 0, L_0x56148bf2d310; 1 drivers +v0x56148beec370_0 .net "cmc_t7", 0 0, v0x56148beddf20_0; 1 drivers +v0x56148beec460_0 .net "cmc_t7_D", 0 0, L_0x56148bf2d570; 1 drivers +v0x56148beec550_0 .net "cmc_t8", 0 0, v0x56148bede4e0_0; 1 drivers +v0x56148beec640_0 .net "cmc_t8_D", 0 0, L_0x56148bf2d7d0; 1 drivers +v0x56148beec730_0 .net "cmc_t9", 0 0, v0x56148bedeaa0_0; 1 drivers +v0x56148beec820_0 .net "cmc_t9_D", 0 0, L_0x56148bf2da30; 1 drivers +v0x56148beec910_0 .net "cmc_t9a", 0 0, v0x56148bedf060_0; 1 drivers +v0x56148beeca00_0 .net "cmc_t9a_D", 0 0, L_0x56148bf2dc90; 1 drivers +v0x56148beecaa0_0 .var "cmc_wr", 0 0; +v0x56148beecb40_0 .net "cmc_wr_rs", 0 0, L_0x56148bf29e90; 1 drivers +v0x56148beecbe0_0 .net "cmpc_p0_rq", 0 0, L_0x56148bf24d40; 1 drivers +v0x56148beecc80_0 .net "cmpc_p1_rq", 0 0, L_0x56148bf24e00; 1 drivers +v0x56148beecd20_0 .net "cmpc_p2_rq", 0 0, L_0x56148bf24cd0; 1 drivers +v0x56148beecdc0_0 .net "cmpc_p3_rq", 0 0, L_0x56148bf25010; 1 drivers +v0x56148beece60_0 .net "cmpc_rs_strb", 0 0, L_0x56148bf296d0; 1 drivers +v0x56148beecf00 .array "core", 16383 0, 0 35; +v0x56148beecfa0_0 .net "core_addr", 13 0, L_0x56148bf2e750; 1 drivers +v0x56148beed040_0 .var "core_rd", 0 0; +v0x56148beed0e0_0 .var "core_wr", 0 0; +v0x56148beed180_0 .net "cyc_rq_p0", 0 0, L_0x56148bf240e0; 1 drivers +v0x56148beed220_0 .net "cyc_rq_p1", 0 0, L_0x56148bf24450; 1 drivers +v0x56148beed2e0_0 .net "cyc_rq_p2", 0 0, L_0x56148bf24810; 1 drivers +v0x56148beed3a0_0 .net "cyc_rq_p3", 0 0, L_0x56148bf24c10; 1 drivers +v0x56148beed460_0 .net "ma", 21 35, L_0x56148bf26620; 1 drivers +v0x56148beed540_0 .net "mb_in", 0 35, L_0x56148bf26bb0; 1 drivers +v0x56148beed620_0 .net "mb_out", 0 35, L_0x56148bf27d20; 1 drivers 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21 35, L_0x7ff4bea76ec0; 1 drivers +L_0x7ff4bea77100 .functor BUFT 1, C4<000000000000000>, C4<0>, C4<0>, C4<0>; +v0x56148beee710_0 .net "membus_ma_p2", 21 35, L_0x7ff4bea77100; 1 drivers +L_0x7ff4bea77340 .functor BUFT 1, C4<000000000000000>, C4<0>, C4<0>, C4<0>; +v0x56148beee7f0_0 .net "membus_ma_p3", 21 35, L_0x7ff4bea77340; 1 drivers +v0x56148beee8d0_0 .net "membus_mb_in_p0", 0 35, L_0x56148bf23cc0; alias, 1 drivers +L_0x7ff4bea76f98 .functor BUFT 1, C4<000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x56148beee9b0_0 .net "membus_mb_in_p1", 0 35, L_0x7ff4bea76f98; 1 drivers +L_0x7ff4bea771d8 .functor BUFT 1, C4<000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x56148beeea90_0 .net "membus_mb_in_p2", 0 35, L_0x7ff4bea771d8; 1 drivers +L_0x7ff4bea77418 .functor BUFT 1, C4<000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x56148beeeb70_0 .net "membus_mb_in_p3", 0 35, L_0x7ff4bea77418; 1 drivers +v0x56148beeec50_0 .net "membus_mb_out_p0", 0 35, L_0x56148bf26f50; alias, 1 drivers +v0x56148beeed30_0 .net "membus_mb_out_p1", 0 35, L_0x56148bf26eb0; 1 drivers +v0x56148beeee10_0 .net "membus_mb_out_p2", 0 35, L_0x56148bf27690; 1 drivers +v0x56148beeeef0_0 .net "membus_mb_out_p3", 0 35, L_0x56148bf27a50; 1 drivers +v0x56148beeefd0_0 .net "membus_rd_rq_p0", 0 0, v0x56148bf0afc0_0; alias, 1 drivers +L_0x7ff4bea76e30 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +v0x56148beef090_0 .net "membus_rd_rq_p1", 0 0, L_0x7ff4bea76e30; 1 drivers +L_0x7ff4bea77070 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +v0x56148beef150_0 .net "membus_rd_rq_p2", 0 0, L_0x7ff4bea77070; 1 drivers +L_0x7ff4bea772b0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +v0x56148beef210_0 .net "membus_rd_rq_p3", 0 0, L_0x7ff4bea772b0; 1 drivers +v0x56148beef2d0_0 .net "membus_rd_rs_p0", 0 0, L_0x56148bf26df0; alias, 1 drivers +v0x56148beef390_0 .net "membus_rd_rs_p1", 0 0, L_0x56148bf270b0; 1 drivers +v0x56148beef450_0 .net "membus_rd_rs_p2", 0 0, L_0x56148bf27530; 1 drivers +v0x56148beef510_0 .net "membus_rd_rs_p3", 0 0, L_0x56148bf278e0; 1 drivers +v0x56148beef5d0_0 .net "membus_rq_cyc_p0", 0 0, v0x56148bf0b170_0; alias, 1 drivers +v0x56148beef690_0 .net "membus_rq_cyc_p1", 0 0, L_0x7ff4bea76de8; 1 drivers +v0x56148beef750_0 .net "membus_rq_cyc_p2", 0 0, L_0x7ff4bea77028; 1 drivers +v0x56148beef810_0 .net "membus_rq_cyc_p3", 0 0, L_0x7ff4bea77268; 1 drivers +v0x56148beef8d0_0 .net "membus_sel_p0", 18 21, L_0x56148bf21f90; alias, 1 drivers +L_0x7ff4bea76f08 .functor BUFT 1, C4<0000>, C4<0>, C4<0>, C4<0>; +v0x56148beef9b0_0 .net "membus_sel_p1", 18 21, L_0x7ff4bea76f08; 1 drivers +L_0x7ff4bea77148 .functor BUFT 1, C4<0000>, C4<0>, C4<0>, C4<0>; +v0x56148beefa90_0 .net "membus_sel_p2", 18 21, L_0x7ff4bea77148; 1 drivers +L_0x7ff4bea77388 .functor BUFT 1, C4<0000>, C4<0>, C4<0>, C4<0>; +v0x56148beefb70_0 .net "membus_sel_p3", 18 21, L_0x7ff4bea77388; 1 drivers +v0x56148beefc50_0 .net "membus_wr_rq_p0", 0 0, v0x56148bf0b480_0; alias, 1 drivers +L_0x7ff4bea76e78 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +v0x56148beefd10_0 .net "membus_wr_rq_p1", 0 0, L_0x7ff4bea76e78; 1 drivers +L_0x7ff4bea770b8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +v0x56148beefdd0_0 .net "membus_wr_rq_p2", 0 0, L_0x7ff4bea770b8; 1 drivers +L_0x7ff4bea772f8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +v0x56148beefe90_0 .net "membus_wr_rq_p3", 0 0, L_0x7ff4bea772f8; 1 drivers +v0x56148beeff50_0 .net "membus_wr_rs_p0", 0 0, L_0x56148bf22d00; alias, 1 drivers +L_0x7ff4bea76da0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +v0x56148bef0010_0 .net "membus_wr_rs_p1", 0 0, L_0x7ff4bea76da0; 1 drivers +L_0x7ff4bea76fe0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +v0x56148bef00d0_0 .net "membus_wr_rs_p2", 0 0, L_0x7ff4bea76fe0; 1 drivers +L_0x7ff4bea77220 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +v0x56148bef0190_0 .net "membus_wr_rs_p3", 0 0, L_0x7ff4bea77220; 1 drivers +L_0x7ff4bea76cc8 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>; +v0x56148bef0250_0 .net "power", 0 0, L_0x7ff4bea76cc8; 1 drivers +v0x56148bef02f0_0 .net "rd_rq", 0 0, L_0x56148bf25aa0; 1 drivers +v0x56148bef0390_0 .net "reset", 0 0, L_0x56148bf2e7c0; 1 drivers +v0x56148bef0430_0 .var "sa", 0 35; +v0x56148bef0510_0 .net "sw_restart", 0 0, L_0x7ff4bea76d58; 1 drivers +L_0x7ff4bea76d10 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +v0x56148bef05d0_0 .net "sw_single_step", 0 0, L_0x7ff4bea76d10; 1 drivers +v0x56148bef0690_0 .net "wr_rq", 0 0, L_0x56148bf26040; 1 drivers +v0x56148bef0750_0 .net "wr_rs", 0 0, L_0x56148bf25570; 1 drivers +L_0x56148bf23e30 .cmp/eq 4, L_0x7ff4bea75d08, L_0x56148bf21f90; +L_0x56148bf24230 .cmp/eq 4, L_0x7ff4bea75d50, L_0x7ff4bea76f08; +L_0x56148bf24550 .cmp/eq 4, L_0x7ff4bea75d98, L_0x7ff4bea77148; +L_0x56148bf248d0 .cmp/eq 4, L_0x7ff4bea75de0, L_0x7ff4bea77388; +L_0x56148bf251f0 .functor MUXZ 1, L_0x7ff4bea75e28, L_0x7ff4bea77220, v0x56148beeab70_0, C4<>; +L_0x56148bf252c0 .functor MUXZ 1, L_0x56148bf251f0, L_0x7ff4bea76fe0, v0x56148beeaab0_0, C4<>; +L_0x56148bf25420 .functor MUXZ 1, L_0x56148bf252c0, L_0x7ff4bea76da0, v0x56148beea5e0_0, C4<>; +L_0x56148bf25570 .functor MUXZ 1, L_0x56148bf25420, L_0x56148bf22d00, v0x56148beea520_0, C4<>; +L_0x56148bf25700 .functor MUXZ 1, L_0x7ff4bea75e70, L_0x7ff4bea772b0, v0x56148beeab70_0, C4<>; +L_0x56148bf25870 .functor MUXZ 1, L_0x56148bf25700, L_0x7ff4bea77070, v0x56148beeaab0_0, C4<>; +L_0x56148bf25960 .functor MUXZ 1, L_0x56148bf25870, L_0x7ff4bea76e30, v0x56148beea5e0_0, C4<>; +L_0x56148bf25aa0 .functor MUXZ 1, L_0x56148bf25960, v0x56148bf0afc0_0, v0x56148beea520_0, C4<>; +L_0x56148bf25ce0 .functor MUXZ 1, L_0x7ff4bea75eb8, L_0x7ff4bea772f8, v0x56148beeab70_0, C4<>; +L_0x56148bf25d80 .functor MUXZ 1, L_0x56148bf25ce0, L_0x7ff4bea770b8, v0x56148beeaab0_0, C4<>; +L_0x56148bf25f20 .functor MUXZ 1, L_0x56148bf25d80, L_0x7ff4bea76e78, v0x56148beea5e0_0, C4<>; +L_0x56148bf26040 .functor MUXZ 1, L_0x56148bf25f20, v0x56148bf0b480_0, v0x56148beea520_0, C4<>; +L_0x56148bf261f0 .functor MUXZ 15, L_0x7ff4bea75f00, L_0x7ff4bea77340, v0x56148beeab70_0, C4<>; +L_0x56148bf26350 .functor MUXZ 15, L_0x56148bf261f0, L_0x7ff4bea77100, v0x56148beeaab0_0, C4<>; +L_0x56148bf264c0 .functor MUXZ 15, L_0x56148bf26350, L_0x7ff4bea76ec0, v0x56148beea5e0_0, C4<>; +L_0x56148bf26620 .functor MUXZ 15, L_0x56148bf264c0, L_0x56148bf21ef0, v0x56148beea520_0, C4<>; +L_0x56148bf263f0 .functor MUXZ 36, L_0x7ff4bea75f48, L_0x7ff4bea77418, v0x56148beeab70_0, C4<>; +L_0x56148bf268b0 .functor MUXZ 36, L_0x56148bf263f0, L_0x7ff4bea771d8, v0x56148beeaab0_0, C4<>; +L_0x56148bf26a90 .functor MUXZ 36, L_0x56148bf268b0, L_0x7ff4bea76f98, v0x56148beea5e0_0, C4<>; +L_0x56148bf26bb0 .functor MUXZ 36, L_0x56148bf26a90, L_0x56148bf23cc0, v0x56148beea520_0, C4<>; +L_0x56148bf26f50 .functor MUXZ 36, L_0x7ff4bea75f90, L_0x56148bf27d20, v0x56148beea520_0, C4<>; +L_0x56148bf26eb0 .functor MUXZ 36, L_0x7ff4bea75fd8, L_0x56148bf27d20, v0x56148beea5e0_0, C4<>; +L_0x56148bf27690 .functor MUXZ 36, L_0x7ff4bea76020, L_0x56148bf27d20, v0x56148beeaab0_0, C4<>; +L_0x56148bf27a50 .functor MUXZ 36, L_0x7ff4bea76068, L_0x56148bf27d20, v0x56148beeab70_0, C4<>; +L_0x56148bf27d20 .functor MUXZ 36, L_0x7ff4bea760b0, v0x56148bef0430_0, L_0x56148bf2c3c0, C4<>; +L_0x56148bf29260 .reduce/or L_0x56148bf26bb0; +S_0x56148bd7f380 .scope module, "cmc_bd0" "bd" 8 197, 3 39 0, S_0x56148bd810e0; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +v0x56148bd7f5d0_0 .net *"_s0", 31 0, L_0x56148bf2b050; 1 drivers +L_0x7ff4bea760f8 .functor BUFT 1, C4<00000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x56148bd7f6d0_0 .net *"_s3", 28 0, L_0x7ff4bea760f8; 1 drivers +L_0x7ff4bea76140 .functor BUFT 1, C4<00000000000000000000000000000100>, C4<0>, C4<0>, C4<0>; +v0x56148bcb8090_0 .net/2u *"_s4", 31 0, L_0x7ff4bea76140; 1 drivers +v0x56148bcb81a0_0 .net "clk", 0 0, v0x56148bd15230_0; alias, 1 drivers +v0x56148bcb8240_0 .net "in", 0 0, v0x56148bee12f0_0; alias, 1 drivers +v0x56148bcb8330_0 .net "p", 0 0, L_0x56148bf2b4a0; alias, 1 drivers +v0x56148bcb83f0_0 .var "r", 2 0; +v0x56148bd09d80_0 .net "reset", 0 0, L_0x56148bf2e7c0; alias, 1 drivers +E_0x56148bd7f550 .event posedge, v0x56148bd09d80_0, v0x56148bd15230_0; +L_0x56148bf2b050 .concat [ 3 29 0 0], v0x56148bcb83f0_0, L_0x7ff4bea760f8; +L_0x56148bf2b4a0 .cmp/eq 32, L_0x56148bf2b050, L_0x7ff4bea76140; +S_0x56148bd09ec0 .scope module, "cmc_bd1" "bd" 8 198, 3 39 0, S_0x56148bd810e0; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +v0x56148bd0a0b0_0 .net *"_s0", 31 0, L_0x56148bf2b590; 1 drivers +L_0x7ff4bea76188 .functor BUFT 1, C4<00000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x56148bed1950_0 .net *"_s3", 28 0, L_0x7ff4bea76188; 1 drivers +L_0x7ff4bea761d0 .functor BUFT 1, C4<00000000000000000000000000000100>, C4<0>, C4<0>, C4<0>; +v0x56148bed1a30_0 .net/2u *"_s4", 31 0, L_0x7ff4bea761d0; 1 drivers +v0x56148bed1b20_0 .net "clk", 0 0, v0x56148bd15230_0; alias, 1 drivers +v0x56148bed1c10_0 .net "in", 0 0, L_0x56148bf2e150; alias, 1 drivers +v0x56148bed1d20_0 .net "p", 0 0, L_0x56148bf2b680; alias, 1 drivers +v0x56148bed1de0_0 .var "r", 2 0; +v0x56148bed1ec0_0 .net "reset", 0 0, L_0x56148bf2e7c0; alias, 1 drivers +L_0x56148bf2b590 .concat [ 3 29 0 0], v0x56148bed1de0_0, L_0x7ff4bea76188; +L_0x56148bf2b680 .cmp/eq 32, L_0x56148bf2b590, L_0x7ff4bea761d0; +S_0x56148bed1fc0 .scope module, "cmc_bd2" "bd2" 8 199, 3 57 0, S_0x56148bd810e0; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +L_0x56148bf2bc70 .functor OR 1, L_0x56148bf2b8b0, L_0x56148bf2bb30, C4<0>, C4<0>; +L_0x56148bf2bff0 .functor OR 1, L_0x56148bf2bc70, L_0x56148bf2be70, C4<0>, C4<0>; +L_0x56148bf2c3c0 .functor OR 1, L_0x56148bf2bff0, L_0x56148bf2c230, C4<0>, C4<0>; +v0x56148bed21c0_0 .net *"_s0", 31 0, L_0x56148bf2b7c0; 1 drivers +L_0x7ff4bea762a8 .functor BUFT 1, C4<00000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x56148bed22a0_0 .net *"_s11", 28 0, L_0x7ff4bea762a8; 1 drivers +L_0x7ff4bea762f0 .functor BUFT 1, C4<00000000000000000000000000000101>, C4<0>, C4<0>, C4<0>; +v0x56148bed2380_0 .net/2u *"_s12", 31 0, L_0x7ff4bea762f0; 1 drivers +v0x56148bed2470_0 .net *"_s14", 0 0, L_0x56148bf2bb30; 1 drivers +v0x56148bed2530_0 .net *"_s16", 0 0, L_0x56148bf2bc70; 1 drivers +v0x56148bed2640_0 .net *"_s18", 31 0, L_0x56148bf2bd80; 1 drivers +L_0x7ff4bea76338 .functor BUFT 1, C4<00000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x56148bed2720_0 .net *"_s21", 28 0, L_0x7ff4bea76338; 1 drivers +L_0x7ff4bea76380 .functor BUFT 1, C4<00000000000000000000000000000110>, C4<0>, C4<0>, C4<0>; +v0x56148bed2800_0 .net/2u *"_s22", 31 0, L_0x7ff4bea76380; 1 drivers +v0x56148bed28e0_0 .net *"_s24", 0 0, L_0x56148bf2be70; 1 drivers +v0x56148bed29a0_0 .net *"_s26", 0 0, L_0x56148bf2bff0; 1 drivers +v0x56148bed2a60_0 .net *"_s28", 31 0, L_0x56148bf2c100; 1 drivers +L_0x7ff4bea76218 .functor BUFT 1, C4<00000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x56148bed2b40_0 .net *"_s3", 28 0, L_0x7ff4bea76218; 1 drivers +L_0x7ff4bea763c8 .functor BUFT 1, C4<00000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x56148bed2c20_0 .net *"_s31", 28 0, L_0x7ff4bea763c8; 1 drivers +L_0x7ff4bea76410 .functor BUFT 1, C4<00000000000000000000000000000111>, C4<0>, C4<0>, C4<0>; +v0x56148bed2d00_0 .net/2u *"_s32", 31 0, L_0x7ff4bea76410; 1 drivers +v0x56148bed2de0_0 .net *"_s34", 0 0, L_0x56148bf2c230; 1 drivers +L_0x7ff4bea76260 .functor BUFT 1, C4<00000000000000000000000000000100>, C4<0>, C4<0>, C4<0>; +v0x56148bed2ea0_0 .net/2u *"_s4", 31 0, L_0x7ff4bea76260; 1 drivers +v0x56148bed2f80_0 .net *"_s6", 0 0, L_0x56148bf2b8b0; 1 drivers +v0x56148bed3150_0 .net *"_s8", 31 0, L_0x56148bf2b9f0; 1 drivers +v0x56148bed3230_0 .net "clk", 0 0, v0x56148bd15230_0; alias, 1 drivers +v0x56148bed32d0_0 .net "in", 0 0, v0x56148bedf5f0_0; alias, 1 drivers +v0x56148bed3390_0 .net "p", 0 0, L_0x56148bf2c3c0; alias, 1 drivers +v0x56148bed3450_0 .var "r", 2 0; +v0x56148bed3530_0 .net "reset", 0 0, L_0x56148bf2e7c0; alias, 1 drivers +L_0x56148bf2b7c0 .concat [ 3 29 0 0], v0x56148bed3450_0, L_0x7ff4bea76218; +L_0x56148bf2b8b0 .cmp/eq 32, L_0x56148bf2b7c0, L_0x7ff4bea76260; +L_0x56148bf2b9f0 .concat [ 3 29 0 0], v0x56148bed3450_0, L_0x7ff4bea762a8; +L_0x56148bf2bb30 .cmp/eq 32, L_0x56148bf2b9f0, L_0x7ff4bea762f0; +L_0x56148bf2bd80 .concat [ 3 29 0 0], v0x56148bed3450_0, L_0x7ff4bea76338; +L_0x56148bf2be70 .cmp/eq 32, L_0x56148bf2bd80, L_0x7ff4bea76380; +L_0x56148bf2c100 .concat [ 3 29 0 0], v0x56148bed3450_0, L_0x7ff4bea763c8; +L_0x56148bf2c230 .cmp/eq 32, L_0x56148bf2c100, L_0x7ff4bea76410; +S_0x56148bed3650 .scope module, "cmc_dly0" "dly100ns" 8 205, 3 102 0, S_0x56148bd810e0; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +v0x56148bed3890_0 .net *"_s0", 31 0, L_0x56148bf2c4d0; 1 drivers +L_0x7ff4bea76458 .functor BUFT 1, C4<0000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x56148bed3990_0 .net *"_s3", 27 0, L_0x7ff4bea76458; 1 drivers +L_0x7ff4bea764a0 .functor BUFT 1, C4<00000000000000000000000000001100>, C4<0>, C4<0>, C4<0>; +v0x56148bed3a70_0 .net/2u *"_s4", 31 0, L_0x7ff4bea764a0; 1 drivers +v0x56148bed3b30_0 .net "clk", 0 0, v0x56148bd15230_0; alias, 1 drivers +v0x56148bed3bd0_0 .net "in", 0 0, L_0x56148bf280f0; alias, 1 drivers +v0x56148bed3c90_0 .net "p", 0 0, L_0x56148bf2c5c0; alias, 1 drivers +v0x56148bed3d50_0 .var "r", 3 0; +v0x56148bed3e30_0 .net "reset", 0 0, L_0x56148bf2e7c0; alias, 1 drivers +L_0x56148bf2c4d0 .concat [ 4 28 0 0], v0x56148bed3d50_0, L_0x7ff4bea76458; +L_0x56148bf2c5c0 .cmp/eq 32, L_0x56148bf2c4d0, L_0x7ff4bea764a0; +S_0x56148bed3f50 .scope module, "cmc_dly1" "dly100ns" 8 206, 3 102 0, S_0x56148bd810e0; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +v0x56148bed41e0_0 .net *"_s0", 31 0, L_0x56148bf2c700; 1 drivers +L_0x7ff4bea764e8 .functor BUFT 1, C4<0000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x56148bed42e0_0 .net *"_s3", 27 0, L_0x7ff4bea764e8; 1 drivers +L_0x7ff4bea76530 .functor BUFT 1, C4<00000000000000000000000000001100>, C4<0>, C4<0>, C4<0>; +v0x56148bed43c0_0 .net/2u *"_s4", 31 0, L_0x7ff4bea76530; 1 drivers +v0x56148bed4480_0 .net "clk", 0 0, v0x56148bd15230_0; alias, 1 drivers +v0x56148bed4520_0 .net "in", 0 0, v0x56148bedfb60_0; alias, 1 drivers +v0x56148bed4630_0 .net "p", 0 0, L_0x56148bf2c7f0; alias, 1 drivers +v0x56148bed46f0_0 .var "r", 3 0; +v0x56148bed47d0_0 .net "reset", 0 0, L_0x56148bf2e7c0; alias, 1 drivers +L_0x56148bf2c700 .concat [ 4 28 0 0], v0x56148bed46f0_0, L_0x7ff4bea764e8; +L_0x56148bf2c7f0 .cmp/eq 32, L_0x56148bf2c700, L_0x7ff4bea76530; +S_0x56148bed48f0 .scope module, "cmc_dly10" "dly200ns" 8 215, 3 132 0, S_0x56148bd810e0; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +v0x56148bed4ae0_0 .net *"_s0", 31 0, L_0x56148bf2db70; 1 drivers +L_0x7ff4bea769f8 .functor BUFT 1, C4<000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x56148bed4be0_0 .net *"_s3", 26 0, L_0x7ff4bea769f8; 1 drivers +L_0x7ff4bea76a40 .functor BUFT 1, C4<00000000000000000000000000010110>, C4<0>, C4<0>, C4<0>; +v0x56148bed4cc0_0 .net/2u *"_s4", 31 0, L_0x7ff4bea76a40; 1 drivers +v0x56148bed4db0_0 .net "clk", 0 0, v0x56148bd15230_0; alias, 1 drivers +v0x56148bed4e50_0 .net "in", 0 0, v0x56148bedf060_0; alias, 1 drivers +v0x56148bed4f60_0 .net "p", 0 0, L_0x56148bf2dc90; alias, 1 drivers +v0x56148bed5020_0 .var "r", 4 0; +v0x56148bed5100_0 .net "reset", 0 0, L_0x56148bf2e7c0; alias, 1 drivers +L_0x56148bf2db70 .concat [ 5 27 0 0], v0x56148bed5020_0, L_0x7ff4bea769f8; +L_0x56148bf2dc90 .cmp/eq 32, L_0x56148bf2db70, L_0x7ff4bea76a40; +S_0x56148bed5220 .scope module, "cmc_dly11" "dly800ns" 8 216, 3 177 0, S_0x56148bd810e0; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +v0x56148bed5460_0 .net *"_s0", 31 0, L_0x56148bf2ddd0; 1 drivers +L_0x7ff4bea76a88 .functor BUFT 1, C4<0000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x56148bed5560_0 .net *"_s3", 24 0, L_0x7ff4bea76a88; 1 drivers +L_0x7ff4bea76ad0 .functor BUFT 1, C4<00000000000000000000000001010010>, C4<0>, C4<0>, C4<0>; +v0x56148bed5640_0 .net/2u *"_s4", 31 0, L_0x7ff4bea76ad0; 1 drivers +v0x56148bed5730_0 .net "clk", 0 0, v0x56148bd15230_0; alias, 1 drivers +v0x56148bed57d0_0 .net "in", 0 0, v0x56148bee1cd0_0; alias, 1 drivers +v0x56148bed58e0_0 .net "p", 0 0, L_0x56148bf2def0; alias, 1 drivers +v0x56148bed59a0_0 .var "r", 6 0; +v0x56148bed5a80_0 .net "reset", 0 0, L_0x56148bf2e7c0; alias, 1 drivers +L_0x56148bf2ddd0 .concat [ 7 25 0 0], v0x56148bed59a0_0, L_0x7ff4bea76a88; +L_0x56148bf2def0 .cmp/eq 32, L_0x56148bf2ddd0, L_0x7ff4bea76ad0; +S_0x56148bed5ba0 .scope module, "cmc_dly12" "dly100ns" 8 217, 3 102 0, S_0x56148bd810e0; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +v0x56148bed5de0_0 .net *"_s0", 31 0, L_0x56148bf2e030; 1 drivers +L_0x7ff4bea76b18 .functor BUFT 1, C4<0000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x56148bed5ee0_0 .net *"_s3", 27 0, L_0x7ff4bea76b18; 1 drivers +L_0x7ff4bea76b60 .functor BUFT 1, C4<00000000000000000000000000001100>, C4<0>, C4<0>, C4<0>; +v0x56148bed5fc0_0 .net/2u *"_s4", 31 0, L_0x7ff4bea76b60; 1 drivers +v0x56148bed60b0_0 .net "clk", 0 0, v0x56148bd15230_0; alias, 1 drivers +v0x56148bed6260_0 .net "in", 0 0, v0x56148bedf5f0_0; alias, 1 drivers +v0x56148bed6350_0 .net "p", 0 0, L_0x56148bf2e150; alias, 1 drivers +v0x56148bed6420_0 .var "r", 3 0; +v0x56148bed64c0_0 .net "reset", 0 0, L_0x56148bf2e7c0; alias, 1 drivers +L_0x56148bf2e030 .concat [ 4 28 0 0], v0x56148bed6420_0, L_0x7ff4bea76b18; +L_0x56148bf2e150 .cmp/eq 32, L_0x56148bf2e030, L_0x7ff4bea76b60; +S_0x56148bed6610 .scope module, "cmc_dly13" "dly200ns" 8 219, 3 132 0, S_0x56148bd810e0; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +v0x56148bed6850_0 .net *"_s0", 31 0, L_0x56148bf2e290; 1 drivers +L_0x7ff4bea76ba8 .functor BUFT 1, C4<000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x56148bed6950_0 .net *"_s3", 26 0, L_0x7ff4bea76ba8; 1 drivers +L_0x7ff4bea76bf0 .functor BUFT 1, C4<00000000000000000000000000010110>, C4<0>, C4<0>, C4<0>; +v0x56148bed6a30_0 .net/2u *"_s4", 31 0, L_0x7ff4bea76bf0; 1 drivers +v0x56148bed6b20_0 .net "clk", 0 0, v0x56148bd15230_0; alias, 1 drivers +v0x56148bed6bc0_0 .net "in", 0 0, v0x56148bedf5f0_0; alias, 1 drivers +v0x56148bed6cb0_0 .net "p", 0 0, L_0x56148bf2e3b0; alias, 1 drivers +v0x56148bed6d70_0 .var "r", 4 0; +v0x56148bed6e50_0 .net "reset", 0 0, L_0x56148bf2e7c0; alias, 1 drivers +L_0x56148bf2e290 .concat [ 5 27 0 0], v0x56148bed6d70_0, L_0x7ff4bea76ba8; +L_0x56148bf2e3b0 .cmp/eq 32, L_0x56148bf2e290, L_0x7ff4bea76bf0; +S_0x56148bed7080 .scope module, "cmc_dly14" "dly250ns" 8 221, 3 147 0, S_0x56148bd810e0; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +v0x56148bed72c0_0 .net *"_s0", 31 0, L_0x56148bf2e4f0; 1 drivers +L_0x7ff4bea76c38 .functor BUFT 1, C4<000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x56148bed73c0_0 .net *"_s3", 26 0, L_0x7ff4bea76c38; 1 drivers +L_0x7ff4bea76c80 .functor BUFT 1, C4<00000000000000000000000000011011>, C4<0>, C4<0>, C4<0>; +v0x56148bed74a0_0 .net/2u *"_s4", 31 0, L_0x7ff4bea76c80; 1 drivers +v0x56148bed7560_0 .net "clk", 0 0, v0x56148bd15230_0; alias, 1 drivers +v0x56148bed7600_0 .net "in", 0 0, v0x56148bedf5f0_0; alias, 1 drivers +v0x56148bed76f0_0 .net "p", 0 0, L_0x56148bf2e610; alias, 1 drivers +v0x56148bed77b0_0 .var "r", 4 0; +v0x56148bed7890_0 .net "reset", 0 0, L_0x56148bf2e7c0; alias, 1 drivers +L_0x56148bf2e4f0 .concat [ 5 27 0 0], v0x56148bed77b0_0, L_0x7ff4bea76c38; +L_0x56148bf2e610 .cmp/eq 32, L_0x56148bf2e4f0, L_0x7ff4bea76c80; +S_0x56148bed79b0 .scope module, "cmc_dly2" "dly200ns" 8 207, 3 132 0, S_0x56148bd810e0; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +v0x56148bed7bf0_0 .net *"_s0", 31 0, L_0x56148bf2c930; 1 drivers +L_0x7ff4bea76578 .functor BUFT 1, C4<000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x56148bed7cf0_0 .net *"_s3", 26 0, L_0x7ff4bea76578; 1 drivers +L_0x7ff4bea765c0 .functor BUFT 1, C4<00000000000000000000000000010110>, C4<0>, C4<0>, C4<0>; +v0x56148bed7dd0_0 .net/2u *"_s4", 31 0, L_0x7ff4bea765c0; 1 drivers +v0x56148bed7ec0_0 .net "clk", 0 0, v0x56148bd15230_0; alias, 1 drivers +v0x56148bed7f60_0 .net "in", 0 0, L_0x56148bf28930; alias, 1 drivers +v0x56148bed8070_0 .net "p", 0 0, L_0x56148bf2ca20; alias, 1 drivers +v0x56148bed8130_0 .var "r", 4 0; +v0x56148bed8210_0 .net "reset", 0 0, L_0x56148bf2e7c0; alias, 1 drivers +L_0x56148bf2c930 .concat [ 5 27 0 0], v0x56148bed8130_0, L_0x7ff4bea76578; +L_0x56148bf2ca20 .cmp/eq 32, L_0x56148bf2c930, L_0x7ff4bea765c0; +S_0x56148bed8330 .scope module, "cmc_dly3" "dly1us" 8 208, 3 192 0, S_0x56148bd810e0; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +v0x56148bed8570_0 .net *"_s0", 31 0, L_0x56148bf2cb60; 1 drivers +L_0x7ff4bea76608 .functor BUFT 1, C4<0000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x56148bed8670_0 .net *"_s3", 24 0, L_0x7ff4bea76608; 1 drivers +L_0x7ff4bea76650 .functor BUFT 1, C4<00000000000000000000000001100110>, C4<0>, C4<0>, C4<0>; +v0x56148bed8750_0 .net/2u *"_s4", 31 0, L_0x7ff4bea76650; 1 drivers +v0x56148bed8840_0 .net "clk", 0 0, v0x56148bd15230_0; alias, 1 drivers +v0x56148bed88e0_0 .net "in", 0 0, v0x56148bee12f0_0; alias, 1 drivers +v0x56148bed89d0_0 .net "p", 0 0, L_0x56148bf2cc50; alias, 1 drivers +v0x56148bed8a70_0 .var "r", 6 0; +v0x56148bed8b50_0 .net "reset", 0 0, L_0x56148bf2e7c0; alias, 1 drivers +L_0x56148bf2cb60 .concat [ 7 25 0 0], v0x56148bed8a70_0, L_0x7ff4bea76608; +L_0x56148bf2cc50 .cmp/eq 32, L_0x56148bf2cb60, L_0x7ff4bea76650; +S_0x56148bed8ca0 .scope module, "cmc_dly4" "dly1us" 8 209, 3 192 0, S_0x56148bd810e0; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +v0x56148bed8ee0_0 .net *"_s0", 31 0, L_0x56148bf2cd90; 1 drivers +L_0x7ff4bea76698 .functor BUFT 1, C4<0000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x56148bed8fe0_0 .net *"_s3", 24 0, L_0x7ff4bea76698; 1 drivers +L_0x7ff4bea766e0 .functor BUFT 1, C4<00000000000000000000000001100110>, C4<0>, C4<0>, C4<0>; +v0x56148bed90c0_0 .net/2u *"_s4", 31 0, L_0x7ff4bea766e0; 1 drivers +v0x56148bed91b0_0 .net "clk", 0 0, v0x56148bd15230_0; alias, 1 drivers +v0x56148bed9250_0 .net "in", 0 0, v0x56148bee1cd0_0; alias, 1 drivers +v0x56148bed9340_0 .net "p", 0 0, L_0x56148bf2ce80; alias, 1 drivers +v0x56148bed93e0_0 .var "r", 6 0; +v0x56148bed94c0_0 .net "reset", 0 0, L_0x56148bf2e7c0; alias, 1 drivers +L_0x56148bf2cd90 .concat [ 7 25 0 0], v0x56148bed93e0_0, L_0x7ff4bea76698; +L_0x56148bf2ce80 .cmp/eq 32, L_0x56148bf2cd90, L_0x7ff4bea766e0; +S_0x56148bed9610 .scope module, "cmc_dly5" "dly200ns" 8 210, 3 132 0, S_0x56148bd810e0; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +v0x56148bed9850_0 .net *"_s0", 31 0, L_0x56148bf2cfc0; 1 drivers +L_0x7ff4bea76728 .functor BUFT 1, C4<000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x56148bed9950_0 .net *"_s3", 26 0, L_0x7ff4bea76728; 1 drivers +L_0x7ff4bea76770 .functor BUFT 1, C4<00000000000000000000000000010110>, C4<0>, C4<0>, C4<0>; +v0x56148bed9a30_0 .net/2u *"_s4", 31 0, L_0x7ff4bea76770; 1 drivers +v0x56148bed9b20_0 .net "clk", 0 0, v0x56148bd15230_0; alias, 1 drivers +v0x56148bed9bc0_0 .net "in", 0 0, v0x56148bee22a0_0; alias, 1 drivers +v0x56148bed9cd0_0 .net "p", 0 0, L_0x56148bf2d0b0; alias, 1 drivers +v0x56148bed9d90_0 .var "r", 4 0; +v0x56148bed9e70_0 .net "reset", 0 0, L_0x56148bf2e7c0; alias, 1 drivers +L_0x56148bf2cfc0 .concat [ 5 27 0 0], v0x56148bed9d90_0, L_0x7ff4bea76728; +L_0x56148bf2d0b0 .cmp/eq 32, L_0x56148bf2cfc0, L_0x7ff4bea76770; +S_0x56148bed9f90 .scope module, "cmc_dly6" "dly200ns" 8 211, 3 132 0, S_0x56148bd810e0; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +v0x56148beda1d0_0 .net *"_s0", 31 0, L_0x56148bf2d1f0; 1 drivers +L_0x7ff4bea767b8 .functor BUFT 1, C4<000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x56148beda2d0_0 .net *"_s3", 26 0, L_0x7ff4bea767b8; 1 drivers +L_0x7ff4bea76800 .functor BUFT 1, C4<00000000000000000000000000010110>, C4<0>, C4<0>, C4<0>; +v0x56148beda3b0_0 .net/2u *"_s4", 31 0, L_0x7ff4bea76800; 1 drivers +v0x56148beda4a0_0 .net "clk", 0 0, v0x56148bd15230_0; alias, 1 drivers +v0x56148beda540_0 .net "in", 0 0, v0x56148bedd920_0; alias, 1 drivers +v0x56148beda650_0 .net "p", 0 0, L_0x56148bf2d310; alias, 1 drivers +v0x56148beda710_0 .var "r", 4 0; +v0x56148beda7f0_0 .net "reset", 0 0, L_0x56148bf2e7c0; alias, 1 drivers +L_0x56148bf2d1f0 .concat [ 5 27 0 0], v0x56148beda710_0, L_0x7ff4bea767b8; +L_0x56148bf2d310 .cmp/eq 32, L_0x56148bf2d1f0, L_0x7ff4bea76800; +S_0x56148beda910 .scope module, "cmc_dly7" "dly200ns" 8 212, 3 132 0, S_0x56148bd810e0; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +v0x56148bedab50_0 .net *"_s0", 31 0, L_0x56148bf2d450; 1 drivers +L_0x7ff4bea76848 .functor BUFT 1, C4<000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x56148bedac50_0 .net *"_s3", 26 0, L_0x7ff4bea76848; 1 drivers +L_0x7ff4bea76890 .functor BUFT 1, C4<00000000000000000000000000010110>, C4<0>, C4<0>, C4<0>; +v0x56148bedad30_0 .net/2u *"_s4", 31 0, L_0x7ff4bea76890; 1 drivers +v0x56148bedae20_0 .net "clk", 0 0, v0x56148bd15230_0; alias, 1 drivers +v0x56148bedb0d0_0 .net "in", 0 0, v0x56148beddf20_0; alias, 1 drivers +v0x56148bedb1e0_0 .net "p", 0 0, L_0x56148bf2d570; alias, 1 drivers +v0x56148bedb2a0_0 .var "r", 4 0; +v0x56148bedb380_0 .net "reset", 0 0, L_0x56148bf2e7c0; alias, 1 drivers +L_0x56148bf2d450 .concat [ 5 27 0 0], v0x56148bedb2a0_0, L_0x7ff4bea76848; +L_0x56148bf2d570 .cmp/eq 32, L_0x56148bf2d450, L_0x7ff4bea76890; +S_0x56148bedb4a0 .scope module, "cmc_dly8" "dly1us" 8 213, 3 192 0, S_0x56148bd810e0; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +v0x56148bedb6e0_0 .net *"_s0", 31 0, L_0x56148bf2d6b0; 1 drivers +L_0x7ff4bea768d8 .functor BUFT 1, C4<0000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x56148bedb7e0_0 .net *"_s3", 24 0, L_0x7ff4bea768d8; 1 drivers +L_0x7ff4bea76920 .functor BUFT 1, C4<00000000000000000000000001100110>, C4<0>, C4<0>, C4<0>; +v0x56148bedb8c0_0 .net/2u *"_s4", 31 0, L_0x7ff4bea76920; 1 drivers +v0x56148bedb9b0_0 .net "clk", 0 0, v0x56148bd15230_0; alias, 1 drivers +v0x56148bedba50_0 .net "in", 0 0, v0x56148bede4e0_0; alias, 1 drivers +v0x56148bedbb60_0 .net "p", 0 0, L_0x56148bf2d7d0; alias, 1 drivers +v0x56148bedbc20_0 .var "r", 6 0; +v0x56148bedbd00_0 .net "reset", 0 0, L_0x56148bf2e7c0; alias, 1 drivers +L_0x56148bf2d6b0 .concat [ 7 25 0 0], v0x56148bedbc20_0, L_0x7ff4bea768d8; +L_0x56148bf2d7d0 .cmp/eq 32, L_0x56148bf2d6b0, L_0x7ff4bea76920; +S_0x56148bedc030 .scope module, "cmc_dly9" "dly400ns" 8 214, 3 162 0, S_0x56148bd810e0; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +v0x56148bedc270_0 .net *"_s0", 31 0, L_0x56148bf2d910; 1 drivers +L_0x7ff4bea76968 .functor BUFT 1, C4<00000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x56148bedc370_0 .net *"_s3", 25 0, L_0x7ff4bea76968; 1 drivers +L_0x7ff4bea769b0 .functor BUFT 1, C4<00000000000000000000000000101010>, C4<0>, C4<0>, C4<0>; +v0x56148bedc450_0 .net/2u *"_s4", 31 0, L_0x7ff4bea769b0; 1 drivers +v0x56148bedc540_0 .net "clk", 0 0, v0x56148bd15230_0; alias, 1 drivers +v0x56148bedc5e0_0 .net "in", 0 0, v0x56148bedeaa0_0; alias, 1 drivers +v0x56148bedc6f0_0 .net "p", 0 0, L_0x56148bf2da30; alias, 1 drivers +v0x56148bedc7b0_0 .var "r", 5 0; +v0x56148bedc890_0 .net "reset", 0 0, L_0x56148bf2e7c0; alias, 1 drivers +L_0x56148bf2d910 .concat [ 6 26 0 0], v0x56148bedc7b0_0, L_0x7ff4bea76968; +L_0x56148bf2da30 .cmp/eq 32, L_0x56148bf2d910, L_0x7ff4bea769b0; +S_0x56148bedc9b0 .scope module, "cmc_pa0" "pa" 8 169, 3 30 0, S_0x56148bd810e0; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +v0x56148bedcbf0_0 .net "clk", 0 0, v0x56148bd15230_0; alias, 1 drivers +v0x56148bedccb0_0 .net "in", 0 0, L_0x56148bf2a0b0; 1 drivers +v0x56148bedcd70_0 .var "p", 0 0; +v0x56148bedce40_0 .net "reset", 0 0, L_0x56148bf2e7c0; alias, 1 drivers +S_0x56148bedcf90 .scope module, "cmc_pa1" "pa" 8 170, 3 30 0, S_0x56148bd810e0; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +v0x56148bedd1d0_0 .net "clk", 0 0, v0x56148bd15230_0; alias, 1 drivers +v0x56148bedd290_0 .net "in", 0 0, L_0x56148bf2c5c0; alias, 1 drivers +v0x56148bedd380_0 .var "p", 0 0; +v0x56148bedd450_0 .net "reset", 0 0, L_0x56148bf2e7c0; alias, 1 drivers +S_0x56148bedd560 .scope module, "cmc_pa10" "pa" 8 185, 3 30 0, S_0x56148bd810e0; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +v0x56148bedd7a0_0 .net "clk", 0 0, v0x56148bd15230_0; alias, 1 drivers +v0x56148bedd860_0 .net "in", 0 0, L_0x56148bf2b1b0; 1 drivers +v0x56148bedd920_0 .var "p", 0 0; +v0x56148bedda20_0 .net "reset", 0 0, L_0x56148bf2e7c0; alias, 1 drivers +S_0x56148beddb30 .scope module, "cmc_pa11" "pa" 8 188, 3 30 0, S_0x56148bd810e0; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +v0x56148beddd70_0 .net "clk", 0 0, v0x56148bd15230_0; alias, 1 drivers +v0x56148bedde30_0 .net "in", 0 0, L_0x56148bf2d310; alias, 1 drivers +v0x56148beddf20_0 .var "p", 0 0; +v0x56148bede020_0 .net "reset", 0 0, L_0x56148bf2e7c0; alias, 1 drivers +S_0x56148bede0f0 .scope module, "cmc_pa12" "pa" 8 189, 3 30 0, S_0x56148bd810e0; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +v0x56148bede330_0 .net "clk", 0 0, v0x56148bd15230_0; alias, 1 drivers +v0x56148bede3f0_0 .net "in", 0 0, L_0x56148bf2d570; alias, 1 drivers +v0x56148bede4e0_0 .var "p", 0 0; +v0x56148bede5e0_0 .net "reset", 0 0, L_0x56148bf2e7c0; alias, 1 drivers +S_0x56148bede6b0 .scope module, "cmc_pa13" "pa" 8 190, 3 30 0, S_0x56148bd810e0; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +v0x56148bede8f0_0 .net "clk", 0 0, v0x56148bd15230_0; alias, 1 drivers +v0x56148bede9b0_0 .net "in", 0 0, L_0x56148bf2d7d0; alias, 1 drivers +v0x56148bedeaa0_0 .var "p", 0 0; +v0x56148bedeba0_0 .net "reset", 0 0, L_0x56148bf2e7c0; alias, 1 drivers +S_0x56148bedec70 .scope module, "cmc_pa14" "pa" 8 191, 3 30 0, S_0x56148bd810e0; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +v0x56148bedeeb0_0 .net "clk", 0 0, v0x56148bd15230_0; alias, 1 drivers +v0x56148bedef70_0 .net "in", 0 0, L_0x56148bf2da30; alias, 1 drivers +v0x56148bedf060_0 .var "p", 0 0; +v0x56148bedf160_0 .net "reset", 0 0, L_0x56148bf2e7c0; alias, 1 drivers +S_0x56148bedf230 .scope module, "cmc_pa15" "pa" 8 192, 3 30 0, S_0x56148bd810e0; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +v0x56148bedf470_0 .net "clk", 0 0, v0x56148bd15230_0; alias, 1 drivers +v0x56148bedf530_0 .net "in", 0 0, L_0x56148bf2b270; 1 drivers +v0x56148bedf5f0_0 .var "p", 0 0; +v0x56148bedf6c0_0 .net "reset", 0 0, L_0x56148bf2e7c0; alias, 1 drivers +S_0x56148bedf7f0 .scope module, "cmc_pa2" "pa" 8 171, 3 30 0, S_0x56148bd810e0; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +v0x56148bedf9e0_0 .net "clk", 0 0, v0x56148bd15230_0; alias, 1 drivers +v0x56148bedfaa0_0 .net "in", 0 0, L_0x56148bf2a5c0; 1 drivers +v0x56148bedfb60_0 .var "p", 0 0; +v0x56148bedfc60_0 .net "reset", 0 0, L_0x56148bf2e7c0; alias, 1 drivers +S_0x56148bedfd70 .scope module, "cmc_pa3" "pa" 8 174, 3 30 0, S_0x56148bd810e0; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +v0x56148bedffb0_0 .net "clk", 0 0, v0x56148bd15230_0; alias, 1 drivers +v0x56148bee0070_0 .net "in", 0 0, L_0x56148bf2c7f0; alias, 1 drivers +v0x56148bee0160_0 .var "p", 0 0; +v0x56148bee0230_0 .net "reset", 0 0, L_0x56148bf2e7c0; alias, 1 drivers +S_0x56148bee0340 .scope module, "cmc_pa4" "pa" 8 175, 3 30 0, S_0x56148bd810e0; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +v0x56148bee0580_0 .net "clk", 0 0, v0x56148bd15230_0; alias, 1 drivers +v0x56148bee0640_0 .net "in", 0 0, L_0x56148bf2aa50; 1 drivers +v0x56148bee0700_0 .var "p", 0 0; +v0x56148bee07d0_0 .net "reset", 0 0, L_0x56148bf2e7c0; alias, 1 drivers +S_0x56148bee0920 .scope module, "cmc_pa5" "pa" 8 178, 3 30 0, S_0x56148bd810e0; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +v0x56148bee0b60_0 .net "clk", 0 0, v0x56148bd15230_0; alias, 1 drivers +v0x56148bee0c20_0 .net "in", 0 0, L_0x56148bf2ad10; 1 drivers +v0x56148bee0ce0_0 .var "p", 0 0; +v0x56148bee0db0_0 .net "reset", 0 0, L_0x56148bf2e7c0; alias, 1 drivers +S_0x56148bee0f00 .scope module, "cmc_pa6" "pa" 8 181, 3 30 0, S_0x56148bd810e0; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +v0x56148bee1140_0 .net "clk", 0 0, v0x56148bd15230_0; alias, 1 drivers +v0x56148bee1200_0 .net "in", 0 0, L_0x56148bf2ca20; alias, 1 drivers +v0x56148bee12f0_0 .var "p", 0 0; +v0x56148bee1410_0 .net "reset", 0 0, L_0x56148bf2e7c0; alias, 1 drivers +S_0x56148bee14d0 .scope module, "cmc_pa7" "pa" 8 182, 3 30 0, S_0x56148bd810e0; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +v0x56148bee1710_0 .net "clk", 0 0, v0x56148bd15230_0; alias, 1 drivers +v0x56148bee1be0_0 .net "in", 0 0, L_0x56148bf2cc50; alias, 1 drivers +v0x56148bee1cd0_0 .var "p", 0 0; +v0x56148bee1df0_0 .net "reset", 0 0, L_0x56148bf2e7c0; alias, 1 drivers +S_0x56148bee1eb0 .scope module, "cmc_pa8" "pa" 8 183, 3 30 0, S_0x56148bd810e0; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +v0x56148bee20f0_0 .net "clk", 0 0, v0x56148bd15230_0; alias, 1 drivers +v0x56148bee21b0_0 .net "in", 0 0, L_0x56148bf2ce80; alias, 1 drivers +v0x56148bee22a0_0 .var "p", 0 0; +v0x56148bee23a0_0 .net "reset", 0 0, L_0x56148bf2e7c0; alias, 1 drivers +S_0x56148bee2880 .scope module, "cmc_pa9" "pa" 8 184, 3 30 0, S_0x56148bd810e0; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +v0x56148bee2ac0_0 .net "clk", 0 0, v0x56148bd15230_0; alias, 1 drivers +v0x56148bee2b80_0 .net "in", 0 0, L_0x56148bf2d0b0; alias, 1 drivers +v0x56148bee2c70_0 .var "p", 0 0; +v0x56148bee2d40_0 .net "reset", 0 0, L_0x56148bf2e7c0; alias, 1 drivers +S_0x56148bee2e50 .scope module, "cmc_pg0" "pg" 8 157, 3 15 0, S_0x56148bd810e0; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +L_0x56148bf280f0 .functor AND 1, L_0x56148bf27e10, L_0x56148bf28000, C4<1>, C4<1>; +v0x56148bee3090_0 .net *"_s1", 0 0, L_0x56148bf27e10; 1 drivers +v0x56148bee3190_0 .net *"_s3", 0 0, L_0x56148bf27ee0; 1 drivers +v0x56148bee3270_0 .net *"_s5", 0 0, L_0x56148bf28000; 1 drivers +v0x56148bee3340_0 .net "clk", 0 0, v0x56148bd15230_0; alias, 1 drivers +v0x56148bee33e0_0 .net "in", 0 0, L_0x7ff4bea76cc8; alias, 1 drivers +v0x56148bee34f0_0 .net "p", 0 0, L_0x56148bf280f0; alias, 1 drivers +v0x56148bee3590_0 .net "reset", 0 0, L_0x56148bf2e7c0; alias, 1 drivers +v0x56148bee3630_0 .var "x", 1 0; +L_0x56148bf27e10 .part v0x56148bee3630_0, 0, 1; +L_0x56148bf27ee0 .part v0x56148bee3630_0, 1, 1; +L_0x56148bf28000 .reduce/nor L_0x56148bf27ee0; +S_0x56148bee37a0 .scope module, "cmc_pg1" "pg" 8 158, 3 15 0, S_0x56148bd810e0; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +L_0x56148bf28480 .functor AND 1, L_0x56148bf28200, L_0x56148bf28390, C4<1>, C4<1>; +v0x56148bee39e0_0 .net *"_s1", 0 0, L_0x56148bf28200; 1 drivers +v0x56148bee3ae0_0 .net *"_s3", 0 0, L_0x56148bf282a0; 1 drivers +v0x56148bee3bc0_0 .net *"_s5", 0 0, L_0x56148bf28390; 1 drivers +v0x56148bee3c90_0 .net "clk", 0 0, v0x56148bd15230_0; alias, 1 drivers +v0x56148bee3d30_0 .net "in", 0 0, L_0x56148bf285e0; 1 drivers +v0x56148bee3e40_0 .net "p", 0 0, L_0x56148bf28480; alias, 1 drivers +v0x56148bee3f00_0 .net "reset", 0 0, L_0x56148bf2e7c0; alias, 1 drivers +v0x56148bee3fa0_0 .var "x", 1 0; +L_0x56148bf28200 .part v0x56148bee3fa0_0, 0, 1; +L_0x56148bf282a0 .part v0x56148bee3fa0_0, 1, 1; +L_0x56148bf28390 .reduce/nor L_0x56148bf282a0; +S_0x56148bee4100 .scope module, "cmc_pg2" "pg" 8 160, 3 15 0, S_0x56148bd810e0; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +L_0x56148bf28930 .functor AND 1, L_0x56148bf28650, L_0x56148bf28840, C4<1>, C4<1>; +v0x56148bee4340_0 .net *"_s1", 0 0, L_0x56148bf28650; 1 drivers +v0x56148bee4440_0 .net *"_s3", 0 0, L_0x56148bf28720; 1 drivers +v0x56148bee4520_0 .net *"_s5", 0 0, L_0x56148bf28840; 1 drivers +v0x56148bee45f0_0 .net "clk", 0 0, v0x56148bd15230_0; alias, 1 drivers +v0x56148bee4690_0 .net "in", 0 0, L_0x56148bf28c80; 1 drivers +v0x56148bee47a0_0 .net "p", 0 0, L_0x56148bf28930; alias, 1 drivers +v0x56148bee4840_0 .net "reset", 0 0, L_0x56148bf2e7c0; alias, 1 drivers +v0x56148bee48e0_0 .var "x", 1 0; +L_0x56148bf28650 .part v0x56148bee48e0_0, 0, 1; +L_0x56148bf28720 .part v0x56148bee48e0_0, 1, 1; +L_0x56148bf28840 .reduce/nor L_0x56148bf28720; +S_0x56148bee4a50 .scope module, "cmc_pg3" "pg" 8 163, 3 15 0, S_0x56148bd810e0; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +L_0x56148bf29100 .functor AND 1, L_0x56148bf28e80, L_0x56148bf29010, C4<1>, C4<1>; +v0x56148bee4c90_0 .net *"_s1", 0 0, L_0x56148bf28e80; 1 drivers +v0x56148bee4d90_0 .net *"_s3", 0 0, L_0x56148bf28f20; 1 drivers +v0x56148bee4e70_0 .net *"_s5", 0 0, L_0x56148bf29010; 1 drivers +v0x56148bee4f40_0 .net "clk", 0 0, v0x56148bd15230_0; alias, 1 drivers +v0x56148bee4fe0_0 .net "in", 0 0, L_0x56148bf29260; 1 drivers +v0x56148bee50f0_0 .net "p", 0 0, L_0x56148bf29100; alias, 1 drivers +v0x56148bee51b0_0 .net "reset", 0 0, L_0x56148bf2e7c0; alias, 1 drivers +v0x56148bee5250_0 .var "x", 1 0; +L_0x56148bf28e80 .part v0x56148bee5250_0, 0, 1; +L_0x56148bf28f20 .part v0x56148bee5250_0, 1, 1; +L_0x56148bf29010 .reduce/nor L_0x56148bf28f20; +S_0x56148bee53b0 .scope module, "cmc_pg4" "pg" 8 164, 3 15 0, S_0x56148bd810e0; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +L_0x56148bf296d0 .functor AND 1, L_0x56148bf29450, L_0x56148bf295e0, C4<1>, C4<1>; +v0x56148bee55f0_0 .net *"_s1", 0 0, L_0x56148bf29450; 1 drivers +v0x56148bee56f0_0 .net *"_s3", 0 0, L_0x56148bf294f0; 1 drivers +v0x56148bee57d0_0 .net *"_s5", 0 0, L_0x56148bf295e0; 1 drivers +v0x56148bee58a0_0 .net "clk", 0 0, v0x56148bd15230_0; alias, 1 drivers +v0x56148bee5940_0 .net "in", 0 0, L_0x56148bf25570; alias, 1 drivers +v0x56148bee5a50_0 .net "p", 0 0, L_0x56148bf296d0; alias, 1 drivers +v0x56148bee5b10_0 .net "reset", 0 0, L_0x56148bf2e7c0; alias, 1 drivers +v0x56148bee5bb0_0 .var "x", 1 0; +L_0x56148bf29450 .part v0x56148bee5bb0_0, 0, 1; +L_0x56148bf294f0 .part v0x56148bee5bb0_0, 1, 1; +L_0x56148bf295e0 .reduce/nor L_0x56148bf294f0; +S_0x56148bee5d10 .scope module, "cmc_pg5" "pg" 8 165, 3 15 0, S_0x56148bd810e0; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +L_0x56148bf29ab0 .functor AND 1, L_0x56148bf29830, L_0x56148bf299c0, C4<1>, C4<1>; +v0x56148bee5f50_0 .net *"_s1", 0 0, L_0x56148bf29830; 1 drivers +v0x56148bee6050_0 .net *"_s3", 0 0, L_0x56148bf298d0; 1 drivers +v0x56148bee6130_0 .net *"_s5", 0 0, L_0x56148bf299c0; 1 drivers +v0x56148bee6200_0 .net "clk", 0 0, v0x56148bd15230_0; alias, 1 drivers +v0x56148bee62a0_0 .net "in", 0 0, v0x56148beeac30_0; 1 drivers +v0x56148bee63b0_0 .net "p", 0 0, L_0x56148bf29ab0; alias, 1 drivers +v0x56148bee6470_0 .net "reset", 0 0, L_0x56148bf2e7c0; alias, 1 drivers +v0x56148bee6510_0 .var "x", 1 0; +L_0x56148bf29830 .part v0x56148bee6510_0, 0, 1; +L_0x56148bf298d0 .part v0x56148bee6510_0, 1, 1; +L_0x56148bf299c0 .reduce/nor L_0x56148bf298d0; +S_0x56148bee6670 .scope module, "cmc_pg6" "pg" 8 166, 3 15 0, S_0x56148bd810e0; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +L_0x56148bf29e90 .functor AND 1, L_0x56148bf29c10, L_0x56148bf29da0, C4<1>, C4<1>; +v0x56148bee68b0_0 .net *"_s1", 0 0, L_0x56148bf29c10; 1 drivers +v0x56148bee69b0_0 .net *"_s3", 0 0, L_0x56148bf29cb0; 1 drivers +v0x56148bee6a90_0 .net *"_s5", 0 0, L_0x56148bf29da0; 1 drivers +v0x56148bee6b60_0 .net "clk", 0 0, v0x56148bd15230_0; alias, 1 drivers +v0x56148bee6c00_0 .net "in", 0 0, L_0x56148bf29ff0; 1 drivers +v0x56148bee6d10_0 .net "p", 0 0, L_0x56148bf29e90; alias, 1 drivers +v0x56148bee6dd0_0 .net "reset", 0 0, L_0x56148bf2e7c0; alias, 1 drivers +v0x56148bee6e70_0 .var "x", 1 0; +L_0x56148bf29c10 .part v0x56148bee6e70_0, 0, 1; +L_0x56148bf29cb0 .part v0x56148bee6e70_0, 1, 1; +L_0x56148bf29da0 .reduce/nor L_0x56148bf29cb0; +S_0x56148bef0df0 .scope module, "fmem" "fast162" 7 108, 9 1 0, S_0x56148be748f0; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "power" + .port_info 3 /INPUT 1 "sw_single_step" + .port_info 4 /INPUT 1 "sw_restart" + .port_info 5 /INPUT 1 "membus_wr_rs_p0" + .port_info 6 /INPUT 1 "membus_rq_cyc_p0" + .port_info 7 /INPUT 1 "membus_rd_rq_p0" + .port_info 8 /INPUT 1 "membus_wr_rq_p0" + .port_info 9 /INPUT 15 "membus_ma_p0" + .port_info 10 /INPUT 4 "membus_sel_p0" + .port_info 11 /INPUT 1 "membus_fmc_select_p0" + .port_info 12 /INPUT 36 "membus_mb_in_p0" + .port_info 13 /OUTPUT 1 "membus_addr_ack_p0" + .port_info 14 /OUTPUT 1 "membus_rd_rs_p0" + .port_info 15 /OUTPUT 36 "membus_mb_out_p0" + .port_info 16 /INPUT 1 "membus_wr_rs_p1" + .port_info 17 /INPUT 1 "membus_rq_cyc_p1" + .port_info 18 /INPUT 1 "membus_rd_rq_p1" + .port_info 19 /INPUT 1 "membus_wr_rq_p1" + .port_info 20 /INPUT 15 "membus_ma_p1" + .port_info 21 /INPUT 4 "membus_sel_p1" + .port_info 22 /INPUT 1 "membus_fmc_select_p1" + .port_info 23 /INPUT 36 "membus_mb_in_p1" + .port_info 24 /OUTPUT 1 "membus_addr_ack_p1" + .port_info 25 /OUTPUT 1 "membus_rd_rs_p1" + .port_info 26 /OUTPUT 36 "membus_mb_out_p1" + .port_info 27 /INPUT 1 "membus_wr_rs_p2" + .port_info 28 /INPUT 1 "membus_rq_cyc_p2" + .port_info 29 /INPUT 1 "membus_rd_rq_p2" + .port_info 30 /INPUT 1 "membus_wr_rq_p2" + .port_info 31 /INPUT 15 "membus_ma_p2" + .port_info 32 /INPUT 4 "membus_sel_p2" + .port_info 33 /INPUT 1 "membus_fmc_select_p2" + .port_info 34 /INPUT 36 "membus_mb_in_p2" + .port_info 35 /OUTPUT 1 "membus_addr_ack_p2" + .port_info 36 /OUTPUT 1 "membus_rd_rs_p2" + .port_info 37 /OUTPUT 36 "membus_mb_out_p2" + .port_info 38 /INPUT 1 "membus_wr_rs_p3" + .port_info 39 /INPUT 1 "membus_rq_cyc_p3" + .port_info 40 /INPUT 1 "membus_rd_rq_p3" + .port_info 41 /INPUT 1 "membus_wr_rq_p3" + .port_info 42 /INPUT 15 "membus_ma_p3" + .port_info 43 /INPUT 4 "membus_sel_p3" + .port_info 44 /INPUT 1 "membus_fmc_select_p3" + .port_info 45 /INPUT 36 "membus_mb_in_p3" + .port_info 46 /OUTPUT 1 "membus_addr_ack_p3" + .port_info 47 /OUTPUT 1 "membus_rd_rs_p3" + .port_info 48 /OUTPUT 36 "membus_mb_out_p3" +P_0x56148bedbda0 .param/l "fmc_p0_sel" 0 9 62, C4<1>; +P_0x56148bedbde0 .param/l "fmc_p1_sel" 0 9 63, C4<0>; +P_0x56148bedbe20 .param/l "fmc_p2_sel" 0 9 64, C4<0>; +P_0x56148bedbe60 .param/l "fmc_p3_sel" 0 9 65, C4<0>; +P_0x56148bedbea0 .param/l "memsel_p0" 0 9 58, C4<0000>; +P_0x56148bedbee0 .param/l "memsel_p1" 0 9 59, C4<0000>; +P_0x56148bedbf20 .param/l "memsel_p2" 0 9 60, C4<0000>; +P_0x56148bedbf60 .param/l "memsel_p3" 0 9 61, C4<0000>; +L_0x56148bf2fa20 .functor OR 1, L_0x56148bf2f8e0, v0x56148bf019b0_0, C4<0>, C4<0>; +L_0x56148bf2fd60 .functor BUFZ 1, L_0x56148bf22d00, C4<0>, C4<0>, C4<0>; +L_0x56148bf2fe20 .functor BUFZ 1, v0x56148bf0afc0_0, C4<0>, C4<0>, C4<0>; +L_0x56148bf2fee0 .functor BUFZ 1, v0x56148bf0b480_0, C4<0>, C4<0>, C4<0>; +L_0x7ff4bea775c8 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>; +L_0x56148bf30590 .functor AND 1, L_0x56148bf376b0, L_0x7ff4bea775c8, C4<1>, C4<1>; +L_0x7ff4bea77610 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>; +L_0x56148bf306a0 .functor AND 1, L_0x56148bf37910, L_0x7ff4bea77610, C4<1>, C4<1>; +L_0x56148bf307f0 .functor BUFZ 36, L_0x56148bf30da0, C4<000000000000000000000000000000000000>, C4<000000000000000000000000000000000000>, C4<000000000000000000000000000000000000>; +L_0x7ff4bea77658 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x56148bf30860 .functor AND 1, L_0x56148bf376b0, L_0x7ff4bea77658, C4<1>, C4<1>; +L_0x7ff4bea776a0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x56148bf30970 .functor AND 1, L_0x56148bf37910, L_0x7ff4bea776a0, C4<1>, C4<1>; +L_0x7ff4bea77730 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x56148bf30a30 .functor AND 1, L_0x56148bf376b0, L_0x7ff4bea77730, C4<1>, C4<1>; +L_0x7ff4bea77778 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x56148bf30b00 .functor AND 1, L_0x56148bf37910, L_0x7ff4bea77778, C4<1>, C4<1>; +L_0x7ff4bea77808 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x56148bf30c00 .functor AND 1, L_0x56148bf376b0, L_0x7ff4bea77808, C4<1>, C4<1>; +L_0x7ff4bea77850 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x56148bf30ce0 .functor AND 1, L_0x56148bf37910, L_0x7ff4bea77850, C4<1>, C4<1>; +L_0x56148bf30f80 .functor NOT 1, v0x56148bf01f00_0, C4<0>, C4<0>, C4<0>; +L_0x7ff4bea77928 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>; +L_0x56148bf30c70 .functor AND 1, L_0x7ff4bea77928, L_0x56148bf30f80, C4<1>, C4<1>; +L_0x56148bf31110 .functor NOT 1, v0x56148bf01f00_0, C4<0>, C4<0>, C4<0>; +L_0x7ff4bea77970 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x56148bf31260 .functor AND 1, L_0x7ff4bea77970, L_0x56148bf31110, C4<1>, C4<1>; +L_0x56148bf31370 .functor NOT 1, v0x56148bf01f00_0, C4<0>, C4<0>, C4<0>; +L_0x7ff4bea779b8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x56148bf31480 .functor AND 1, L_0x7ff4bea779b8, L_0x56148bf31370, C4<1>, C4<1>; +L_0x56148bf31590 .functor NOT 1, v0x56148bf01f00_0, C4<0>, C4<0>, C4<0>; +L_0x7ff4bea77a00 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x56148bf316b0 .functor AND 1, L_0x7ff4bea77a00, L_0x56148bf31590, C4<1>, C4<1>; +L_0x7ff4bea77a48 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>; +L_0x56148bf31770 .functor AND 1, L_0x7ff4bea77a48, v0x56148bf011e0_0, C4<1>, C4<1>; +L_0x56148bf31940 .functor NOT 1, L_0x56148bf2fe20, C4<0>, C4<0>, C4<0>; +L_0x56148bf319b0 .functor AND 1, L_0x56148bf31770, L_0x56148bf31940, C4<1>, C4<1>; +L_0x7ff4bea77a90 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x56148bf31be0 .functor AND 1, L_0x7ff4bea77a90, v0x56148bf011e0_0, C4<1>, C4<1>; +L_0x56148bf31ca0 .functor NOT 1, L_0x56148bf2fe20, C4<0>, C4<0>, C4<0>; +L_0x56148bf31b10 .functor AND 1, L_0x56148bf31be0, L_0x56148bf31ca0, C4<1>, C4<1>; +L_0x7ff4bea77ad8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x56148bf31ed0 .functor AND 1, L_0x7ff4bea77ad8, v0x56148bf011e0_0, C4<1>, C4<1>; +L_0x56148bf32110 .functor NOT 1, L_0x56148bf2fe20, C4<0>, C4<0>, C4<0>; +L_0x56148bf32180 .functor AND 1, L_0x56148bf31ed0, L_0x56148bf32110, C4<1>, C4<1>; +L_0x7ff4bea77b20 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x56148bf32390 .functor AND 1, L_0x7ff4bea77b20, v0x56148bf011e0_0, C4<1>, C4<1>; +L_0x56148bf32450 .functor NOT 1, L_0x56148bf2fe20, C4<0>, C4<0>, C4<0>; +L_0x56148bf325d0 .functor AND 1, L_0x56148bf32390, L_0x56148bf32450, C4<1>, C4<1>; +L_0x56148bf327f0 .functor AND 1, L_0x56148bf30c70, L_0x56148bf313e0, C4<1>, C4<1>; +L_0x56148bf32a20 .functor AND 1, L_0x56148bf327f0, v0x56148bf0ac20_0, C4<1>, C4<1>; +L_0x56148bf32ae0 .functor AND 1, L_0x56148bf32a20, v0x56148bf0b170_0, C4<1>, C4<1>; +L_0x56148bf32cd0 .functor AND 1, L_0x56148bf31260, L_0x56148bf32900, C4<1>, C4<1>; +L_0x7ff4bea784b0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x56148bf32de0 .functor AND 1, L_0x56148bf32cd0, L_0x7ff4bea784b0, C4<1>, C4<1>; +L_0x7ff4bea78348 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x56148bf32fe0 .functor AND 1, L_0x56148bf32de0, L_0x7ff4bea78348, C4<1>, C4<1>; +L_0x56148bf32780 .functor AND 1, L_0x56148bf31480, L_0x56148bf330a0, C4<1>, C4<1>; +L_0x7ff4bea786f0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x56148bf33400 .functor AND 1, L_0x56148bf32780, L_0x7ff4bea786f0, C4<1>, C4<1>; +L_0x7ff4bea78588 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x56148bf334c0 .functor AND 1, L_0x56148bf33400, L_0x7ff4bea78588, C4<1>, C4<1>; +L_0x56148bf337d0 .functor AND 1, L_0x56148bf316b0, L_0x56148bf336e0, C4<1>, C4<1>; +L_0x7ff4bea78930 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x56148bf338e0 .functor AND 1, L_0x56148bf337d0, L_0x7ff4bea78930, C4<1>, C4<1>; +L_0x7ff4bea787c8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x56148bf33580 .functor AND 1, L_0x56148bf338e0, L_0x7ff4bea787c8, C4<1>, C4<1>; +L_0x7ff4bea782b8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x56148bf34260 .functor AND 1, L_0x7ff4bea782b8, v0x56148bf01f00_0, C4<1>, C4<1>; +L_0x56148bf354b0 .functor NOT 1, v0x56148bf01f00_0, C4<0>, C4<0>, C4<0>; +L_0x56148bf35520 .functor AND 1, v0x56148bef9bc0_0, L_0x56148bf354b0, C4<1>, C4<1>; +L_0x56148bf357c0 .functor OR 1, L_0x56148bf36cb0, L_0x56148bf35520, C4<0>, C4<0>; +L_0x56148bf358d0 .functor AND 1, L_0x56148bf346d0, L_0x56148bf2fe20, C4<1>, C4<1>; +L_0x56148bf35ef0 .functor NOT 1, L_0x56148bf2fe20, C4<0>, C4<0>, C4<0>; +L_0x56148bf35f60 .functor AND 1, L_0x56148bf346d0, L_0x56148bf35ef0, C4<1>, C4<1>; +L_0x56148bf361d0 .functor AND 1, L_0x56148bf35f60, L_0x56148bf2fee0, C4<1>, C4<1>; +L_0x56148bf362e0 .functor AND 1, L_0x56148bf371b0, L_0x56148bf2fee0, C4<1>, C4<1>; +L_0x56148bf36560 .functor OR 1, L_0x56148bf361d0, L_0x56148bf362e0, C4<0>, C4<0>; +L_0x56148bf36670 .functor NOT 1, L_0x56148bf2fee0, C4<0>, C4<0>, C4<0>; +L_0x56148bf368b0 .functor AND 1, L_0x56148bf371b0, L_0x56148bf36670, C4<1>, C4<1>; +L_0x56148bf36920 .functor OR 1, L_0x56148bf368b0, L_0x56148bf35350, C4<0>, C4<0>; +L_0x56148bf36df0 .functor OR 1, L_0x56148bf34100, L_0x56148bf33d20, C4<0>, C4<0>; +v0x56148befcff0_0 .net *"_s0", 31 0, L_0x56148bf24a90; 1 drivers +v0x56148befd0f0_0 .net *"_s10", 35 0, L_0x56148bf2fae0; 1 drivers +v0x56148befd1d0_0 .net/2u *"_s100", 0 0, L_0x7ff4bea77a00; 1 drivers +v0x56148befd290_0 .net *"_s102", 0 0, L_0x56148bf31590; 1 drivers +v0x56148befd370_0 .net/2u *"_s106", 0 0, L_0x7ff4bea77a48; 1 drivers +v0x56148befd4a0_0 .net *"_s108", 0 0, L_0x56148bf31770; 1 drivers +v0x56148befd580_0 .net *"_s110", 0 0, L_0x56148bf31940; 1 drivers +v0x56148befd660_0 .net/2u *"_s114", 0 0, L_0x7ff4bea77a90; 1 drivers +v0x56148befd740_0 .net *"_s116", 0 0, L_0x56148bf31be0; 1 drivers +v0x56148befd820_0 .net *"_s118", 0 0, L_0x56148bf31ca0; 1 drivers +L_0x7ff4bea774f0 .functor BUFT 1, C4<000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x56148befd900_0 .net/2u *"_s12", 35 0, L_0x7ff4bea774f0; 1 drivers +v0x56148befd9e0_0 .net/2u *"_s122", 0 0, L_0x7ff4bea77ad8; 1 drivers +v0x56148befdac0_0 .net *"_s124", 0 0, L_0x56148bf31ed0; 1 drivers +v0x56148befdba0_0 .net *"_s126", 0 0, L_0x56148bf32110; 1 drivers +v0x56148befdc80_0 .net/2u *"_s130", 0 0, L_0x7ff4bea77b20; 1 drivers +v0x56148befdd60_0 .net *"_s132", 0 0, L_0x56148bf32390; 1 drivers +v0x56148befde40_0 .net *"_s134", 0 0, L_0x56148bf32450; 1 drivers +L_0x7ff4bea77b68 .functor BUFT 1, C4<0000>, C4<0>, C4<0>, C4<0>; +v0x56148befdf20_0 .net/2u *"_s138", 3 0, L_0x7ff4bea77b68; 1 drivers +v0x56148befe000_0 .net *"_s140", 0 0, L_0x56148bf313e0; 1 drivers +v0x56148befe0c0_0 .net *"_s142", 0 0, L_0x56148bf327f0; 1 drivers +v0x56148befe1a0_0 .net *"_s144", 0 0, L_0x56148bf32a20; 1 drivers +L_0x7ff4bea77bb0 .functor BUFT 1, C4<0000>, C4<0>, C4<0>, C4<0>; +v0x56148befe280_0 .net/2u *"_s148", 3 0, L_0x7ff4bea77bb0; 1 drivers +v0x56148befe360_0 .net *"_s150", 0 0, L_0x56148bf32900; 1 drivers +v0x56148befe420_0 .net *"_s152", 0 0, L_0x56148bf32cd0; 1 drivers +v0x56148befe500_0 .net *"_s154", 0 0, L_0x56148bf32de0; 1 drivers +L_0x7ff4bea77bf8 .functor BUFT 1, C4<0000>, C4<0>, C4<0>, C4<0>; +v0x56148befe5e0_0 .net/2u *"_s158", 3 0, L_0x7ff4bea77bf8; 1 drivers +v0x56148befe6c0_0 .net *"_s160", 0 0, L_0x56148bf330a0; 1 drivers +v0x56148befe780_0 .net *"_s162", 0 0, L_0x56148bf32780; 1 drivers +v0x56148befe860_0 .net *"_s164", 0 0, L_0x56148bf33400; 1 drivers +L_0x7ff4bea77c40 .functor BUFT 1, C4<0000>, C4<0>, C4<0>, C4<0>; +v0x56148befe940_0 .net/2u *"_s168", 3 0, L_0x7ff4bea77c40; 1 drivers +v0x56148befea20_0 .net *"_s170", 0 0, L_0x56148bf336e0; 1 drivers +v0x56148befeae0_0 .net *"_s172", 0 0, L_0x56148bf337d0; 1 drivers +v0x56148befebc0_0 .net *"_s174", 0 0, L_0x56148bf338e0; 1 drivers +v0x56148befeeb0_0 .net *"_s182", 0 0, L_0x56148bf354b0; 1 drivers +v0x56148befef90_0 .net *"_s184", 0 0, L_0x56148bf35520; 1 drivers +v0x56148beff070_0 .net *"_s190", 0 0, L_0x56148bf35ef0; 1 drivers +v0x56148beff150_0 .net *"_s192", 0 0, L_0x56148bf35f60; 1 drivers +v0x56148beff230_0 .net *"_s194", 0 0, L_0x56148bf361d0; 1 drivers +v0x56148beff310_0 .net *"_s196", 0 0, L_0x56148bf362e0; 1 drivers +v0x56148beff3f0_0 .net *"_s200", 0 0, L_0x56148bf36670; 1 drivers +v0x56148beff4d0_0 .net *"_s202", 0 0, L_0x56148bf368b0; 1 drivers +v0x56148beff5b0_0 .net *"_s23", 3 0, L_0x56148bf2ff50; 1 drivers +L_0x7ff4bea77538 .functor BUFT 1, C4<00000000000>, C4<0>, C4<0>, C4<0>; +v0x56148beff690_0 .net *"_s27", 10 0, L_0x7ff4bea77538; 1 drivers +L_0x7ff4bea77580 .functor BUFT 1, C4<000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x56148beff770_0 .net/2u *"_s28", 35 0, L_0x7ff4bea77580; 1 drivers +L_0x7ff4bea77460 .functor BUFT 1, C4<00000000000000000>, C4<0>, C4<0>, C4<0>; +v0x56148beff850_0 .net *"_s3", 16 0, L_0x7ff4bea77460; 1 drivers +v0x56148beff930_0 .net *"_s30", 35 0, L_0x56148bf30170; 1 drivers +v0x56148beffa10_0 .net *"_s32", 35 0, L_0x56148bf30260; 1 drivers +v0x56148beffaf0_0 .net *"_s34", 35 0, L_0x56148bf303a0; 1 drivers +v0x56148beffbd0_0 .net/2u *"_s38", 0 0, L_0x7ff4bea775c8; 1 drivers +L_0x7ff4bea774a8 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x56148beffcb0_0 .net/2u *"_s4", 31 0, L_0x7ff4bea774a8; 1 drivers +v0x56148beffd90_0 .net/2u *"_s42", 0 0, L_0x7ff4bea77610; 1 drivers +v0x56148beffe70_0 .net/2u *"_s48", 0 0, L_0x7ff4bea77658; 1 drivers +v0x56148befff50_0 .net/2u *"_s52", 0 0, L_0x7ff4bea776a0; 1 drivers +v0x56148bf00030_0 .net/2u *"_s58", 0 0, L_0x7ff4bea77730; 1 drivers +v0x56148bf00110_0 .net *"_s6", 0 0, L_0x56148bf2f8e0; 1 drivers +v0x56148bf001d0_0 .net/2u *"_s62", 0 0, L_0x7ff4bea77778; 1 drivers +v0x56148bf002b0_0 .net/2u *"_s68", 0 0, L_0x7ff4bea77808; 1 drivers +v0x56148bf00390_0 .net/2u *"_s72", 0 0, L_0x7ff4bea77850; 1 drivers +L_0x7ff4bea778e0 .functor BUFT 1, C4<000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x56148bf00470_0 .net/2u *"_s78", 35 0, L_0x7ff4bea778e0; 1 drivers +v0x56148bf00550_0 .net *"_s8", 0 0, L_0x56148bf2fa20; 1 drivers +v0x56148bf00630_0 .net/2u *"_s82", 0 0, L_0x7ff4bea77928; 1 drivers +v0x56148bf00710_0 .net *"_s84", 0 0, L_0x56148bf30f80; 1 drivers +v0x56148bf007f0_0 .net/2u *"_s88", 0 0, L_0x7ff4bea77970; 1 drivers +v0x56148bf008d0_0 .net *"_s90", 0 0, L_0x56148bf31110; 1 drivers +v0x56148bf009b0_0 .net/2u *"_s94", 0 0, L_0x7ff4bea779b8; 1 drivers +v0x56148bf00a90_0 .net *"_s96", 0 0, L_0x56148bf31370; 1 drivers +v0x56148bf00b70_0 .net "clk", 0 0, v0x56148bd15230_0; alias, 1 drivers +v0x56148bf00c10 .array "ff", 16 0, 0 35; +v0x56148bf00cd0_0 .net "fm_clr", 0 0, v0x56148bef9050_0; 1 drivers +v0x56148bf00d70_0 .net "fm_out", 0 35, L_0x56148bf2fbd0; 1 drivers +v0x56148bf00e30_0 .net "fma", 21 35, L_0x56148bf2fff0; 1 drivers +v0x56148bf00f10_0 .net "fma_rd_rq", 0 0, L_0x56148bf2fe20; 1 drivers +v0x56148bf00fb0_0 .net "fma_rd_rq_D", 0 0, L_0x56148bf36f50; 1 drivers +v0x56148bf01050_0 .net "fma_rd_rq_P", 0 0, L_0x56148bf34a60; 1 drivers +v0x56148bf01140_0 .net "fma_wr_rq", 0 0, L_0x56148bf2fee0; 1 drivers +v0x56148bf011e0_0 .var "fmc_act", 0 0; +v0x56148bf01280_0 .net "fmc_addr_ack", 0 0, L_0x56148bf376b0; 1 drivers +v0x56148bf01320_0 .net "fmc_p0_sel1", 0 0, L_0x56148bf30c70; 1 drivers +v0x56148bf013c0_0 .net "fmc_p0_wr_sel", 0 0, L_0x56148bf319b0; 1 drivers +v0x56148bf01460_0 .net "fmc_p1_sel1", 0 0, L_0x56148bf31260; 1 drivers +v0x56148bf01520_0 .net "fmc_p1_wr_sel", 0 0, L_0x56148bf31b10; 1 drivers +v0x56148bf015e0_0 .net "fmc_p2_sel1", 0 0, L_0x56148bf31480; 1 drivers +v0x56148bf016a0_0 .net "fmc_p2_wr_sel", 0 0, L_0x56148bf32180; 1 drivers +v0x56148bf01760_0 .net "fmc_p3_sel1", 0 0, L_0x56148bf316b0; 1 drivers +v0x56148bf01820_0 .net "fmc_p3_wr_sel", 0 0, L_0x56148bf325d0; 1 drivers +v0x56148bf018e0_0 .net "fmc_pwr_on", 0 0, L_0x56148bf33d20; 1 drivers +v0x56148bf019b0_0 .var "fmc_rd0", 0 0; +v0x56148bf01a50_0 .net "fmc_rd0_set", 0 0, v0x56148bef8a80_0; 1 drivers +v0x56148bf01b20_0 .net "fmc_rd_rs", 0 0, L_0x56148bf37910; 1 drivers +v0x56148bf01bf0_0 .net "fmc_rd_strb", 0 0, L_0x56148bf386a0; 1 drivers +v0x56148bf01cc0_0 .net "fmc_restart", 0 0, L_0x56148bf34100; 1 drivers +v0x56148bf01d90_0 .var "fmc_rs", 0 0; +v0x56148bf01e30_0 .net "fmc_start", 0 0, L_0x56148bf36cb0; 1 drivers +v0x56148bf01f00_0 .var "fmc_stop", 0 0; +v0x56148bf01fa0_0 .var "fmc_wr", 0 0; +v0x56148bf02040_0 .net "fmc_wr_rs", 0 0, L_0x56148bf35350; 1 drivers +v0x56148bf02110_0 .net "fmc_wr_set", 0 0, v0x56148bef9620_0; 1 drivers +v0x56148bf021e0_0 .net "fmct0", 0 0, L_0x56148bf346d0; 1 drivers +v0x56148bf022d0_0 .net "fmct1", 0 0, v0x56148bef8490_0; 1 drivers +v0x56148bf02370_0 .net "fmct1_D", 0 0, L_0x56148bf371b0; 1 drivers +v0x56148bf02410_0 .net "fmct3", 0 0, L_0x56148bf35da0; 1 drivers +v0x56148bf024b0_0 .net "fmct3_D", 0 0, L_0x56148bf37450; 1 drivers +v0x56148bf02550_0 .net "fmct4", 0 0, v0x56148bef9bc0_0; 1 drivers +v0x56148bf025f0_0 .net "fmct5", 0 0, v0x56148bef7eb0_0; 1 drivers +v0x56148bf026c0_0 .net "fmpc_p0_rq", 0 0, L_0x56148bf32ae0; 1 drivers +v0x56148bf02760_0 .net "fmpc_p1_rq", 0 0, L_0x56148bf32fe0; 1 drivers +v0x56148bf02800_0 .net "fmpc_p2_rq", 0 0, L_0x56148bf334c0; 1 drivers +v0x56148bf028a0_0 .net "fmpc_p3_rq", 0 0, L_0x56148bf33580; 1 drivers +v0x56148bf02940_0 .net "mb_in", 0 35, L_0x56148bf30490; 1 drivers +v0x56148bf029e0_0 .net "mb_out", 0 35, L_0x56148bf30da0; 1 drivers +v0x56148bf02aa0_0 .net "mb_pulse_in", 0 0, L_0x56148bf34df0; 1 drivers +v0x56148bf02b70_0 .net "membus_addr_ack_p0", 0 0, L_0x56148bf30590; alias, 1 drivers +v0x56148bf02c10_0 .net "membus_addr_ack_p1", 0 0, L_0x56148bf30860; 1 drivers +v0x56148bf02cd0_0 .net "membus_addr_ack_p2", 0 0, L_0x56148bf30a30; 1 drivers +v0x56148bf02d90_0 .net "membus_addr_ack_p3", 0 0, L_0x56148bf30c00; 1 drivers +v0x56148bf02e50_0 .net "membus_fmc_select_p0", 0 0, v0x56148bf0ac20_0; alias, 1 drivers +v0x56148bf02f20_0 .net "membus_fmc_select_p1", 0 0, L_0x7ff4bea784b0; 1 drivers +v0x56148bf02fe0_0 .net "membus_fmc_select_p2", 0 0, L_0x7ff4bea786f0; 1 drivers +v0x56148bf030a0_0 .net "membus_fmc_select_p3", 0 0, L_0x7ff4bea78930; 1 drivers +v0x56148bf03160_0 .net "membus_ma_p0", 21 35, L_0x56148bf21ef0; alias, 1 drivers +L_0x7ff4bea78420 .functor BUFT 1, C4<000000000000000>, C4<0>, C4<0>, C4<0>; +v0x56148bf03220_0 .net "membus_ma_p1", 21 35, L_0x7ff4bea78420; 1 drivers +L_0x7ff4bea78660 .functor BUFT 1, C4<000000000000000>, C4<0>, C4<0>, C4<0>; +v0x56148bf032e0_0 .net "membus_ma_p2", 21 35, L_0x7ff4bea78660; 1 drivers +L_0x7ff4bea788a0 .functor BUFT 1, C4<000000000000000>, C4<0>, C4<0>, C4<0>; +v0x56148bf033c0_0 .net "membus_ma_p3", 21 35, L_0x7ff4bea788a0; 1 drivers +v0x56148bf034a0_0 .net "membus_mb_in_p0", 0 35, L_0x56148bf23cc0; alias, 1 drivers +L_0x7ff4bea784f8 .functor BUFT 1, C4<000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x56148bf03590_0 .net "membus_mb_in_p1", 0 35, L_0x7ff4bea784f8; 1 drivers +L_0x7ff4bea78738 .functor BUFT 1, C4<000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x56148bf03650_0 .net "membus_mb_in_p2", 0 35, L_0x7ff4bea78738; 1 drivers +L_0x7ff4bea78978 .functor BUFT 1, C4<000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x56148bf03730_0 .net "membus_mb_in_p3", 0 35, L_0x7ff4bea78978; 1 drivers +v0x56148bf03810_0 .net "membus_mb_out_p0", 0 35, L_0x56148bf307f0; alias, 1 drivers +L_0x7ff4bea776e8 .functor BUFT 1, C4<000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x56148bf038f0_0 .net "membus_mb_out_p1", 0 35, L_0x7ff4bea776e8; 1 drivers +L_0x7ff4bea777c0 .functor BUFT 1, C4<000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x56148bf041e0_0 .net "membus_mb_out_p2", 0 35, L_0x7ff4bea777c0; 1 drivers +L_0x7ff4bea77898 .functor BUFT 1, C4<000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x56148bf042c0_0 .net "membus_mb_out_p3", 0 35, L_0x7ff4bea77898; 1 drivers +v0x56148bf043a0_0 .net "membus_rd_rq_p0", 0 0, v0x56148bf0afc0_0; alias, 1 drivers +L_0x7ff4bea78390 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +v0x56148bf04470_0 .net "membus_rd_rq_p1", 0 0, L_0x7ff4bea78390; 1 drivers +L_0x7ff4bea785d0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +v0x56148bf04510_0 .net "membus_rd_rq_p2", 0 0, L_0x7ff4bea785d0; 1 drivers +L_0x7ff4bea78810 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +v0x56148bf045d0_0 .net "membus_rd_rq_p3", 0 0, L_0x7ff4bea78810; 1 drivers +v0x56148bf04690_0 .net "membus_rd_rs_p0", 0 0, L_0x56148bf306a0; alias, 1 drivers +v0x56148bf04750_0 .net "membus_rd_rs_p1", 0 0, L_0x56148bf30970; 1 drivers +v0x56148bf04810_0 .net "membus_rd_rs_p2", 0 0, L_0x56148bf30b00; 1 drivers +v0x56148bf048d0_0 .net "membus_rd_rs_p3", 0 0, L_0x56148bf30ce0; 1 drivers +v0x56148bf04990_0 .net "membus_rq_cyc_p0", 0 0, v0x56148bf0b170_0; alias, 1 drivers +v0x56148bf04a60_0 .net "membus_rq_cyc_p1", 0 0, L_0x7ff4bea78348; 1 drivers +v0x56148bf04b00_0 .net "membus_rq_cyc_p2", 0 0, L_0x7ff4bea78588; 1 drivers +v0x56148bf04bc0_0 .net "membus_rq_cyc_p3", 0 0, L_0x7ff4bea787c8; 1 drivers +v0x56148bf04c80_0 .net "membus_sel_p0", 18 21, L_0x56148bf21f90; alias, 1 drivers +L_0x7ff4bea78468 .functor BUFT 1, C4<0000>, C4<0>, C4<0>, C4<0>; +v0x56148bf04d70_0 .net "membus_sel_p1", 18 21, L_0x7ff4bea78468; 1 drivers +L_0x7ff4bea786a8 .functor BUFT 1, C4<0000>, C4<0>, C4<0>, C4<0>; +v0x56148bf04e30_0 .net "membus_sel_p2", 18 21, L_0x7ff4bea786a8; 1 drivers +L_0x7ff4bea788e8 .functor BUFT 1, C4<0000>, C4<0>, C4<0>, C4<0>; +v0x56148bf04f10_0 .net "membus_sel_p3", 18 21, L_0x7ff4bea788e8; 1 drivers +v0x56148bf04ff0_0 .net "membus_wr_rq_p0", 0 0, v0x56148bf0b480_0; alias, 1 drivers +L_0x7ff4bea783d8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +v0x56148bf050c0_0 .net "membus_wr_rq_p1", 0 0, L_0x7ff4bea783d8; 1 drivers +L_0x7ff4bea78618 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +v0x56148bf05160_0 .net "membus_wr_rq_p2", 0 0, L_0x7ff4bea78618; 1 drivers +L_0x7ff4bea78858 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +v0x56148bf05220_0 .net "membus_wr_rq_p3", 0 0, L_0x7ff4bea78858; 1 drivers +v0x56148bf052e0_0 .net "membus_wr_rs_p0", 0 0, L_0x56148bf22d00; alias, 1 drivers +L_0x7ff4bea78300 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +v0x56148bf053b0_0 .net "membus_wr_rs_p1", 0 0, L_0x7ff4bea78300; 1 drivers +L_0x7ff4bea78540 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +v0x56148bf05450_0 .net "membus_wr_rs_p2", 0 0, L_0x7ff4bea78540; 1 drivers +L_0x7ff4bea78780 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +v0x56148bf05510_0 .net "membus_wr_rs_p3", 0 0, L_0x7ff4bea78780; 1 drivers +L_0x7ff4bea78228 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>; +v0x56148bf055d0_0 .net "power", 0 0, L_0x7ff4bea78228; 1 drivers +v0x56148bf056a0_0 .net "reset", 0 0, L_0x56148bf387b0; 1 drivers +v0x56148bf05740_0 .net "sw_restart", 0 0, L_0x7ff4bea782b8; 1 drivers +L_0x7ff4bea78270 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +v0x56148bf057e0_0 .net "sw_single_step", 0 0, L_0x7ff4bea78270; 1 drivers +v0x56148bf058a0_0 .net "wr_rs", 0 0, L_0x56148bf2fd60; 1 drivers +E_0x56148bef1810 .event posedge, v0x56148bd15230_0; +L_0x56148bf24a90 .concat [ 15 17 0 0], L_0x56148bf2fff0, L_0x7ff4bea77460; +L_0x56148bf2f8e0 .cmp/ne 32, L_0x56148bf24a90, L_0x7ff4bea774a8; +L_0x56148bf2fae0 .array/port v0x56148bf00c10, L_0x56148bf2fff0; +L_0x56148bf2fbd0 .functor MUXZ 36, L_0x7ff4bea774f0, L_0x56148bf2fae0, L_0x56148bf2fa20, C4<>; +L_0x56148bf2ff50 .part L_0x56148bf21ef0, 0, 4; +L_0x56148bf2fff0 .concat [ 4 11 0 0], L_0x56148bf2ff50, L_0x7ff4bea77538; +L_0x56148bf30170 .functor MUXZ 36, L_0x7ff4bea77580, L_0x7ff4bea78978, L_0x56148bf325d0, C4<>; +L_0x56148bf30260 .functor MUXZ 36, L_0x56148bf30170, L_0x7ff4bea78738, L_0x56148bf32180, C4<>; +L_0x56148bf303a0 .functor MUXZ 36, L_0x56148bf30260, L_0x7ff4bea784f8, L_0x56148bf31b10, C4<>; +L_0x56148bf30490 .functor MUXZ 36, L_0x56148bf303a0, L_0x56148bf23cc0, L_0x56148bf319b0, C4<>; +L_0x56148bf30da0 .functor MUXZ 36, L_0x7ff4bea778e0, L_0x56148bf2fbd0, L_0x56148bf386a0, C4<>; +L_0x56148bf313e0 .cmp/eq 4, L_0x7ff4bea77b68, L_0x56148bf21f90; +L_0x56148bf32900 .cmp/eq 4, L_0x7ff4bea77bb0, L_0x7ff4bea78468; +L_0x56148bf330a0 .cmp/eq 4, L_0x7ff4bea77bf8, L_0x7ff4bea786a8; +L_0x56148bf336e0 .cmp/eq 4, L_0x7ff4bea77c40, L_0x7ff4bea788e8; +L_0x56148bf34f50 .reduce/or L_0x56148bf30490; +S_0x56148bef1870 .scope module, "cmc_pg4" "pg" 9 152, 3 15 0, S_0x56148bef0df0; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +L_0x56148bf34df0 .functor AND 1, L_0x56148bf34b70, L_0x56148bf34d00, C4<1>, C4<1>; +v0x56148bef1b80_0 .net *"_s1", 0 0, L_0x56148bf34b70; 1 drivers +v0x56148bef1c80_0 .net *"_s3", 0 0, L_0x56148bf34c10; 1 drivers +v0x56148bef1d60_0 .net *"_s5", 0 0, L_0x56148bf34d00; 1 drivers +v0x56148bef1e30_0 .net "clk", 0 0, v0x56148bd15230_0; alias, 1 drivers +v0x56148bef1ed0_0 .net "in", 0 0, L_0x56148bf34f50; 1 drivers +v0x56148bef1fe0_0 .net "p", 0 0, L_0x56148bf34df0; alias, 1 drivers +v0x56148bef20a0_0 .net "reset", 0 0, L_0x56148bf387b0; alias, 1 drivers +v0x56148bef2160_0 .var "x", 1 0; +E_0x56148bef1b00 .event posedge, v0x56148bef20a0_0, v0x56148bd15230_0; +L_0x56148bf34b70 .part v0x56148bef2160_0, 0, 1; +L_0x56148bf34c10 .part v0x56148bef2160_0, 1, 1; +L_0x56148bf34d00 .reduce/nor L_0x56148bf34c10; +S_0x56148bef22c0 .scope module, "cmc_pg5" "pg" 9 153, 3 15 0, S_0x56148bef0df0; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +L_0x56148bf35350 .functor AND 1, L_0x56148bf350d0, L_0x56148bf35260, C4<1>, C4<1>; +v0x56148bef2520_0 .net *"_s1", 0 0, L_0x56148bf350d0; 1 drivers +v0x56148bef2600_0 .net *"_s3", 0 0, L_0x56148bf35170; 1 drivers +v0x56148bef26e0_0 .net *"_s5", 0 0, L_0x56148bf35260; 1 drivers +v0x56148bef27b0_0 .net "clk", 0 0, v0x56148bd15230_0; alias, 1 drivers +v0x56148bef2850_0 .net "in", 0 0, L_0x56148bf2fd60; alias, 1 drivers +v0x56148bef2960_0 .net "p", 0 0, L_0x56148bf35350; alias, 1 drivers +v0x56148bef2a20_0 .net "reset", 0 0, L_0x56148bf387b0; alias, 1 drivers +v0x56148bef2ac0_0 .var "x", 1 0; +L_0x56148bf350d0 .part v0x56148bef2ac0_0, 0, 1; +L_0x56148bf35170 .part v0x56148bef2ac0_0, 1, 1; +L_0x56148bf35260 .reduce/nor L_0x56148bf35170; +S_0x56148bef2c30 .scope module, "fmc_bd0" "bd" 9 191, 3 39 0, S_0x56148bef0df0; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +v0x56148bef2ea0_0 .net *"_s0", 31 0, L_0x56148bf37590; 1 drivers +L_0x7ff4bea77ec8 .functor BUFT 1, C4<00000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x56148bef2f80_0 .net *"_s3", 28 0, L_0x7ff4bea77ec8; 1 drivers +L_0x7ff4bea77f10 .functor BUFT 1, C4<00000000000000000000000000000100>, C4<0>, C4<0>, C4<0>; +v0x56148bef3060_0 .net/2u *"_s4", 31 0, L_0x7ff4bea77f10; 1 drivers +v0x56148bef3150_0 .net "clk", 0 0, v0x56148bd15230_0; alias, 1 drivers +v0x56148bef31f0_0 .net "in", 0 0, L_0x56148bf346d0; alias, 1 drivers +v0x56148bef3300_0 .net "p", 0 0, L_0x56148bf376b0; alias, 1 drivers +v0x56148bef33c0_0 .var "r", 2 0; +v0x56148bef34a0_0 .net "reset", 0 0, L_0x56148bf387b0; alias, 1 drivers +L_0x56148bf37590 .concat [ 3 29 0 0], v0x56148bef33c0_0, L_0x7ff4bea77ec8; +L_0x56148bf376b0 .cmp/eq 32, L_0x56148bf37590, L_0x7ff4bea77f10; +S_0x56148bef3610 .scope module, "fmc_bd1" "bd" 9 192, 3 39 0, S_0x56148bef0df0; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +v0x56148bef3850_0 .net *"_s0", 31 0, L_0x56148bf377f0; 1 drivers +L_0x7ff4bea77f58 .functor BUFT 1, C4<00000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x56148bef3950_0 .net *"_s3", 28 0, L_0x7ff4bea77f58; 1 drivers +L_0x7ff4bea77fa0 .functor BUFT 1, C4<00000000000000000000000000000100>, C4<0>, C4<0>, C4<0>; +v0x56148bef3a30_0 .net/2u *"_s4", 31 0, L_0x7ff4bea77fa0; 1 drivers +v0x56148bef3af0_0 .net "clk", 0 0, v0x56148bd15230_0; alias, 1 drivers +v0x56148bef3b90_0 .net "in", 0 0, v0x56148bef8490_0; alias, 1 drivers +v0x56148bef3ca0_0 .net "p", 0 0, L_0x56148bf37910; alias, 1 drivers +v0x56148bef3d60_0 .var "r", 2 0; +v0x56148bef3e40_0 .net "reset", 0 0, L_0x56148bf387b0; alias, 1 drivers +L_0x56148bf377f0 .concat [ 3 29 0 0], v0x56148bef3d60_0, L_0x7ff4bea77f58; +L_0x56148bf37910 .cmp/eq 32, L_0x56148bf377f0, L_0x7ff4bea77fa0; +S_0x56148bef3f60 .scope module, "fmc_bd2" "bd2" 9 193, 3 57 0, S_0x56148bef0df0; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +L_0x56148bf37f90 .functor OR 1, L_0x56148bf37b70, L_0x56148bf37e20, C4<0>, C4<0>; +L_0x56148bf382d0 .functor OR 1, L_0x56148bf37f90, L_0x56148bf38190, C4<0>, C4<0>; +L_0x56148bf386a0 .functor OR 1, L_0x56148bf382d0, L_0x56148bf38510, C4<0>, C4<0>; +v0x56148bef41f0_0 .net *"_s0", 31 0, L_0x56148bf37a50; 1 drivers +L_0x7ff4bea78078 .functor BUFT 1, C4<00000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x56148bef42f0_0 .net *"_s11", 28 0, L_0x7ff4bea78078; 1 drivers +L_0x7ff4bea780c0 .functor BUFT 1, C4<00000000000000000000000000000101>, C4<0>, C4<0>, C4<0>; +v0x56148bef43d0_0 .net/2u *"_s12", 31 0, L_0x7ff4bea780c0; 1 drivers +v0x56148bef4490_0 .net *"_s14", 0 0, L_0x56148bf37e20; 1 drivers +v0x56148bef4550_0 .net *"_s16", 0 0, L_0x56148bf37f90; 1 drivers +v0x56148bef4660_0 .net *"_s18", 31 0, L_0x56148bf380a0; 1 drivers +L_0x7ff4bea78108 .functor BUFT 1, C4<00000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x56148bef4740_0 .net *"_s21", 28 0, L_0x7ff4bea78108; 1 drivers +L_0x7ff4bea78150 .functor BUFT 1, C4<00000000000000000000000000000110>, C4<0>, C4<0>, C4<0>; +v0x56148bef4820_0 .net/2u *"_s22", 31 0, L_0x7ff4bea78150; 1 drivers +v0x56148bef4900_0 .net *"_s24", 0 0, L_0x56148bf38190; 1 drivers +v0x56148bef49c0_0 .net *"_s26", 0 0, L_0x56148bf382d0; 1 drivers +v0x56148bef4a80_0 .net *"_s28", 31 0, L_0x56148bf383e0; 1 drivers +L_0x7ff4bea77fe8 .functor BUFT 1, C4<00000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x56148bef4b60_0 .net *"_s3", 28 0, L_0x7ff4bea77fe8; 1 drivers +L_0x7ff4bea78198 .functor BUFT 1, C4<00000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x56148bef4c40_0 .net *"_s31", 28 0, L_0x7ff4bea78198; 1 drivers +L_0x7ff4bea781e0 .functor BUFT 1, C4<00000000000000000000000000000111>, C4<0>, C4<0>, C4<0>; +v0x56148bef4d20_0 .net/2u *"_s32", 31 0, L_0x7ff4bea781e0; 1 drivers +v0x56148bef4e00_0 .net *"_s34", 0 0, L_0x56148bf38510; 1 drivers +L_0x7ff4bea78030 .functor BUFT 1, C4<00000000000000000000000000000100>, C4<0>, C4<0>, C4<0>; +v0x56148bef4ec0_0 .net/2u *"_s4", 31 0, L_0x7ff4bea78030; 1 drivers +v0x56148bef4fa0_0 .net *"_s6", 0 0, L_0x56148bf37b70; 1 drivers +v0x56148bef5060_0 .net *"_s8", 31 0, L_0x56148bf37ce0; 1 drivers +v0x56148bef5140_0 .net "clk", 0 0, v0x56148bd15230_0; alias, 1 drivers +v0x56148bef51e0_0 .net "in", 0 0, v0x56148bef8490_0; alias, 1 drivers +v0x56148bef5280_0 .net "p", 0 0, L_0x56148bf386a0; alias, 1 drivers +v0x56148bef5320_0 .var "r", 2 0; +v0x56148bef5400_0 .net "reset", 0 0, L_0x56148bf387b0; alias, 1 drivers +L_0x56148bf37a50 .concat [ 3 29 0 0], v0x56148bef5320_0, L_0x7ff4bea77fe8; +L_0x56148bf37b70 .cmp/eq 32, L_0x56148bf37a50, L_0x7ff4bea78030; +L_0x56148bf37ce0 .concat [ 3 29 0 0], v0x56148bef5320_0, L_0x7ff4bea78078; +L_0x56148bf37e20 .cmp/eq 32, L_0x56148bf37ce0, L_0x7ff4bea780c0; +L_0x56148bf380a0 .concat [ 3 29 0 0], v0x56148bef5320_0, L_0x7ff4bea78108; +L_0x56148bf38190 .cmp/eq 32, L_0x56148bf380a0, L_0x7ff4bea78150; +L_0x56148bf383e0 .concat [ 3 29 0 0], v0x56148bef5320_0, L_0x7ff4bea78198; +L_0x56148bf38510 .cmp/eq 32, L_0x56148bf383e0, L_0x7ff4bea781e0; +S_0x56148bef5550 .scope module, "fmc_dly0" "dly200ns" 9 178, 3 132 0, S_0x56148bef0df0; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +v0x56148bef5740_0 .net *"_s0", 31 0, L_0x56148bf36bc0; 1 drivers +L_0x7ff4bea77c88 .functor BUFT 1, C4<000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x56148bef5840_0 .net *"_s3", 26 0, L_0x7ff4bea77c88; 1 drivers +L_0x7ff4bea77cd0 .functor BUFT 1, C4<00000000000000000000000000010110>, C4<0>, C4<0>, C4<0>; +v0x56148bef5920_0 .net/2u *"_s4", 31 0, L_0x7ff4bea77cd0; 1 drivers +v0x56148bef5a10_0 .net "clk", 0 0, v0x56148bd15230_0; alias, 1 drivers +v0x56148bef5ab0_0 .net "in", 0 0, L_0x56148bf36df0; 1 drivers +v0x56148bef5b70_0 .net "p", 0 0, L_0x56148bf36cb0; alias, 1 drivers +v0x56148bef5c30_0 .var "r", 4 0; +v0x56148bef5d10_0 .net "reset", 0 0, L_0x56148bf387b0; alias, 1 drivers +L_0x56148bf36bc0 .concat [ 5 27 0 0], v0x56148bef5c30_0, L_0x7ff4bea77c88; +L_0x56148bf36cb0 .cmp/eq 32, L_0x56148bf36bc0, L_0x7ff4bea77cd0; +S_0x56148bef5e30 .scope module, "fmc_dly1" "dly50ns" 9 181, 3 72 0, S_0x56148bef0df0; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +v0x56148bef6070_0 .net *"_s0", 31 0, L_0x56148bf36e60; 1 drivers +L_0x7ff4bea77d18 .functor BUFT 1, C4<00000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x56148bef6170_0 .net *"_s3", 28 0, L_0x7ff4bea77d18; 1 drivers +L_0x7ff4bea77d60 .functor BUFT 1, C4<00000000000000000000000000000111>, C4<0>, C4<0>, C4<0>; +v0x56148bef6250_0 .net/2u *"_s4", 31 0, L_0x7ff4bea77d60; 1 drivers +v0x56148bef6340_0 .net "clk", 0 0, v0x56148bd15230_0; alias, 1 drivers +v0x56148bef63e0_0 .net "in", 0 0, L_0x56148bf34a60; alias, 1 drivers +v0x56148bef64f0_0 .net "p", 0 0, L_0x56148bf36f50; alias, 1 drivers +v0x56148bef65b0_0 .var "r", 2 0; +v0x56148bef6690_0 .net "reset", 0 0, L_0x56148bf387b0; alias, 1 drivers +L_0x56148bf36e60 .concat [ 3 29 0 0], v0x56148bef65b0_0, L_0x7ff4bea77d18; +L_0x56148bf36f50 .cmp/eq 32, L_0x56148bf36e60, L_0x7ff4bea77d60; +S_0x56148bef67b0 .scope module, "fmc_dly3" "dly100ns" 9 184, 3 102 0, S_0x56148bef0df0; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +v0x56148bef69f0_0 .net *"_s0", 31 0, L_0x56148bf37090; 1 drivers +L_0x7ff4bea77da8 .functor BUFT 1, C4<0000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x56148bef6af0_0 .net *"_s3", 27 0, L_0x7ff4bea77da8; 1 drivers +L_0x7ff4bea77df0 .functor BUFT 1, C4<00000000000000000000000000001100>, C4<0>, C4<0>, C4<0>; +v0x56148bef6bd0_0 .net/2u *"_s4", 31 0, L_0x7ff4bea77df0; 1 drivers +v0x56148bef6cc0_0 .net "clk", 0 0, v0x56148bd15230_0; alias, 1 drivers +v0x56148bef6d60_0 .net "in", 0 0, v0x56148bef8490_0; alias, 1 drivers +v0x56148bef6ea0_0 .net "p", 0 0, L_0x56148bf371b0; alias, 1 drivers +v0x56148bef6f60_0 .var "r", 3 0; +v0x56148bef7040_0 .net "reset", 0 0, L_0x56148bf387b0; alias, 1 drivers +L_0x56148bf37090 .concat [ 4 28 0 0], v0x56148bef6f60_0, L_0x7ff4bea77da8; +L_0x56148bf371b0 .cmp/eq 32, L_0x56148bf37090, L_0x7ff4bea77df0; +S_0x56148bef7160 .scope module, "fmc_dly4" "dly50ns" 9 187, 3 72 0, S_0x56148bef0df0; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +v0x56148bef7430_0 .net *"_s0", 31 0, L_0x56148bf37330; 1 drivers +L_0x7ff4bea77e38 .functor BUFT 1, C4<00000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x56148bef7530_0 .net *"_s3", 28 0, L_0x7ff4bea77e38; 1 drivers +L_0x7ff4bea77e80 .functor BUFT 1, C4<00000000000000000000000000000111>, C4<0>, C4<0>, C4<0>; +v0x56148bef7610_0 .net/2u *"_s4", 31 0, L_0x7ff4bea77e80; 1 drivers +v0x56148bef76d0_0 .net "clk", 0 0, v0x56148bd15230_0; alias, 1 drivers +v0x56148bef7770_0 .net "in", 0 0, L_0x56148bf35da0; alias, 1 drivers +v0x56148bef7830_0 .net "p", 0 0, L_0x56148bf37450; alias, 1 drivers +v0x56148bef78f0_0 .var "r", 2 0; +v0x56148bef79d0_0 .net "reset", 0 0, L_0x56148bf387b0; alias, 1 drivers +L_0x56148bf37330 .concat [ 3 29 0 0], v0x56148bef78f0_0, L_0x7ff4bea77e38; +L_0x56148bf37450 .cmp/eq 32, L_0x56148bf37330, L_0x7ff4bea77e80; +S_0x56148bef7af0 .scope module, "fmc_pa0" "pa" 9 155, 3 30 0, S_0x56148bef0df0; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +v0x56148bef7d30_0 .net "clk", 0 0, v0x56148bd15230_0; alias, 1 drivers +v0x56148bef7df0_0 .net "in", 0 0, L_0x56148bf357c0; 1 drivers +v0x56148bef7eb0_0 .var "p", 0 0; +v0x56148bef7f80_0 .net "reset", 0 0, L_0x56148bf387b0; alias, 1 drivers +S_0x56148bef80d0 .scope module, "fmc_pa1" "pa" 9 158, 3 30 0, S_0x56148bef0df0; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +v0x56148bef8310_0 .net "clk", 0 0, v0x56148bd15230_0; alias, 1 drivers +v0x56148bef83d0_0 .net "in", 0 0, L_0x56148bf358d0; 1 drivers +v0x56148bef8490_0 .var "p", 0 0; +v0x56148bef8560_0 .net "reset", 0 0, L_0x56148bf387b0; alias, 1 drivers +S_0x56148bef8690 .scope module, "fmc_pa2" "pa" 9 161, 3 30 0, S_0x56148bef0df0; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +v0x56148bef88d0_0 .net "clk", 0 0, v0x56148bd15230_0; alias, 1 drivers +v0x56148bef8990_0 .net "in", 0 0, L_0x56148bf36f50; alias, 1 drivers +v0x56148bef8a80_0 .var "p", 0 0; +v0x56148bef8b50_0 .net "reset", 0 0, L_0x56148bf387b0; alias, 1 drivers +S_0x56148bef8c60 .scope module, "fmc_pa3" "pa" 9 164, 3 30 0, S_0x56148bef0df0; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +v0x56148bef8ea0_0 .net "clk", 0 0, v0x56148bd15230_0; alias, 1 drivers +v0x56148bef8f60_0 .net "in", 0 0, L_0x56148bf35da0; alias, 1 drivers +v0x56148bef9050_0 .var "p", 0 0; +v0x56148bef9120_0 .net "reset", 0 0, L_0x56148bf387b0; alias, 1 drivers +S_0x56148bef9230 .scope module, "fmc_pa4" "pa" 9 167, 3 30 0, S_0x56148bef0df0; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +v0x56148bef9470_0 .net "clk", 0 0, v0x56148bd15230_0; alias, 1 drivers +v0x56148bef9530_0 .net "in", 0 0, L_0x56148bf37450; alias, 1 drivers +v0x56148bef9620_0 .var "p", 0 0; +v0x56148bef96f0_0 .net "reset", 0 0, L_0x56148bf387b0; alias, 1 drivers +S_0x56148bef9800 .scope module, "fmc_pa6" "pa" 9 174, 3 30 0, S_0x56148bef0df0; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +v0x56148bef9a40_0 .net "clk", 0 0, v0x56148bd15230_0; alias, 1 drivers +v0x56148bef9b00_0 .net "in", 0 0, L_0x56148bf36920; 1 drivers +v0x56148bef9bc0_0 .var "p", 0 0; +v0x56148bef9c90_0 .net "reset", 0 0, L_0x56148bf387b0; alias, 1 drivers +S_0x56148bef9de0 .scope module, "fmc_pg0" "pg" 9 147, 3 15 0, S_0x56148bef0df0; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +L_0x56148bf33d20 .functor AND 1, L_0x56148bf33640, L_0x56148bf33c30, C4<1>, C4<1>; +v0x56148befa020_0 .net *"_s1", 0 0, L_0x56148bf33640; 1 drivers +v0x56148befa120_0 .net *"_s3", 0 0, L_0x56148bf33b10; 1 drivers +v0x56148befa200_0 .net *"_s5", 0 0, L_0x56148bf33c30; 1 drivers +v0x56148befa2d0_0 .net "clk", 0 0, v0x56148bd15230_0; alias, 1 drivers +v0x56148befa370_0 .net "in", 0 0, L_0x7ff4bea78228; alias, 1 drivers +v0x56148befa480_0 .net "p", 0 0, L_0x56148bf33d20; alias, 1 drivers +v0x56148befa540_0 .net "reset", 0 0, L_0x56148bf387b0; alias, 1 drivers +v0x56148befa5e0_0 .var "x", 1 0; +L_0x56148bf33640 .part v0x56148befa5e0_0, 0, 1; +L_0x56148bf33b10 .part v0x56148befa5e0_0, 1, 1; +L_0x56148bf33c30 .reduce/nor L_0x56148bf33b10; +S_0x56148befa740 .scope module, "fmc_pg1" "pg" 9 148, 3 15 0, S_0x56148bef0df0; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +L_0x56148bf34100 .functor AND 1, L_0x56148bf33e80, L_0x56148bf34010, C4<1>, C4<1>; +v0x56148befaa90_0 .net *"_s1", 0 0, L_0x56148bf33e80; 1 drivers +v0x56148befab90_0 .net *"_s3", 0 0, L_0x56148bf33f20; 1 drivers +v0x56148befac70_0 .net *"_s5", 0 0, L_0x56148bf34010; 1 drivers +v0x56148befad40_0 .net "clk", 0 0, v0x56148bd15230_0; alias, 1 drivers +v0x56148befade0_0 .net "in", 0 0, L_0x56148bf34260; 1 drivers +v0x56148befaef0_0 .net "p", 0 0, L_0x56148bf34100; alias, 1 drivers +v0x56148befafb0_0 .net "reset", 0 0, L_0x56148bf387b0; alias, 1 drivers +v0x56148befb260_0 .var "x", 1 0; +L_0x56148bf33e80 .part v0x56148befb260_0, 0, 1; +L_0x56148bf33f20 .part v0x56148befb260_0, 1, 1; +L_0x56148bf34010 .reduce/nor L_0x56148bf33f20; +S_0x56148befb3c0 .scope module, "fmc_pg2" "pg" 9 150, 3 15 0, S_0x56148bef0df0; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +L_0x56148bf346d0 .functor AND 1, L_0x56148bf34450, L_0x56148bf345e0, C4<1>, C4<1>; +v0x56148befb600_0 .net *"_s1", 0 0, L_0x56148bf34450; 1 drivers +v0x56148befb700_0 .net *"_s3", 0 0, L_0x56148bf344f0; 1 drivers +v0x56148befb7e0_0 .net *"_s5", 0 0, L_0x56148bf345e0; 1 drivers +v0x56148befb8b0_0 .net "clk", 0 0, v0x56148bd15230_0; alias, 1 drivers +v0x56148befb950_0 .net "in", 0 0, v0x56148bf011e0_0; 1 drivers +v0x56148befba60_0 .net "p", 0 0, L_0x56148bf346d0; alias, 1 drivers +v0x56148befbb00_0 .net "reset", 0 0, L_0x56148bf387b0; alias, 1 drivers +v0x56148befbba0_0 .var "x", 1 0; +L_0x56148bf34450 .part v0x56148befbba0_0, 0, 1; +L_0x56148bf344f0 .part v0x56148befbba0_0, 1, 1; +L_0x56148bf345e0 .reduce/nor L_0x56148bf344f0; +S_0x56148befbd10 .scope module, "fmc_pg3" "pg" 9 151, 3 15 0, S_0x56148bef0df0; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +L_0x56148bf34a60 .functor AND 1, L_0x56148bf347e0, L_0x56148bf34970, C4<1>, C4<1>; +v0x56148befbf50_0 .net *"_s1", 0 0, L_0x56148bf347e0; 1 drivers +v0x56148befc050_0 .net *"_s3", 0 0, L_0x56148bf34880; 1 drivers +v0x56148befc130_0 .net *"_s5", 0 0, L_0x56148bf34970; 1 drivers +v0x56148befc200_0 .net "clk", 0 0, v0x56148bd15230_0; alias, 1 drivers +v0x56148befc2a0_0 .net "in", 0 0, L_0x56148bf2fe20; alias, 1 drivers +v0x56148befc3b0_0 .net "p", 0 0, L_0x56148bf34a60; alias, 1 drivers +v0x56148befc450_0 .net "reset", 0 0, L_0x56148bf387b0; alias, 1 drivers +v0x56148befc4f0_0 .var "x", 1 0; +L_0x56148bf347e0 .part v0x56148befc4f0_0, 0, 1; +L_0x56148bf34880 .part v0x56148befc4f0_0, 1, 1; +L_0x56148bf34970 .reduce/nor L_0x56148bf34880; +S_0x56148befc660 .scope module, "fmc_pg5" "pg" 9 170, 3 15 0, S_0x56148bef0df0; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +L_0x56148bf35da0 .functor AND 1, L_0x56148bf35b70, L_0x56148bf35cb0, C4<1>, C4<1>; +v0x56148befc8a0_0 .net *"_s1", 0 0, L_0x56148bf35b70; 1 drivers +v0x56148befc9a0_0 .net *"_s3", 0 0, L_0x56148bf35c10; 1 drivers +v0x56148befca80_0 .net *"_s5", 0 0, L_0x56148bf35cb0; 1 drivers +v0x56148befcb50_0 .net "clk", 0 0, v0x56148bd15230_0; alias, 1 drivers +v0x56148befcbf0_0 .net "in", 0 0, L_0x56148bf36560; 1 drivers +v0x56148befcd00_0 .net "p", 0 0, L_0x56148bf35da0; alias, 1 drivers +v0x56148befcdf0_0 .net "reset", 0 0, L_0x56148bf387b0; alias, 1 drivers +v0x56148befce90_0 .var "x", 1 0; +L_0x56148bf35b70 .part v0x56148befce90_0, 0, 1; +L_0x56148bf35c10 .part v0x56148befce90_0, 1, 1; +L_0x56148bf35cb0 .reduce/nor L_0x56148bf35c10; +S_0x56148bf05f70 .scope module, "membusif0" "membusif" 7 32, 10 1 0, S_0x56148be748f0; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 2 "s_address" + .port_info 3 /INPUT 1 "s_write" + .port_info 4 /INPUT 1 "s_read" + .port_info 5 /INPUT 32 "s_writedata" + .port_info 6 /OUTPUT 32 "s_readdata" + .port_info 7 /OUTPUT 1 "s_waitrequest" + .port_info 8 /OUTPUT 1 "m_rq_cyc" + .port_info 9 /OUTPUT 1 "m_rd_rq" + .port_info 10 /OUTPUT 1 "m_wr_rq" + .port_info 11 /OUTPUT 15 "m_ma" + .port_info 12 /OUTPUT 4 "m_sel" + .port_info 13 /OUTPUT 1 "m_fmc_select" + .port_info 14 /OUTPUT 36 "m_mb_write" + .port_info 15 /OUTPUT 1 "m_wr_rs" + .port_info 16 /INPUT 36 "m_mb_read" + .port_info 17 /INPUT 1 "m_addr_ack" + .port_info 18 /INPUT 1 "m_rd_rs" +L_0x56148bf225e0 .functor OR 1, L_0x56148bf22130, L_0x56148bf22260, C4<0>, C4<0>; +L_0x56148bf22790 .functor AND 1, L_0x56148bf225e0, L_0x56148bf22650, C4<1>, C4<1>; +L_0x56148bf228a0 .functor OR 1, L_0x56148bf22790, v0x56148bf0be30_0, C4<0>, C4<0>; +L_0x56148bf22a00 .functor OR 1, L_0x56148bf228a0, L_0x56148bf22960, C4<0>, C4<0>; +L_0x56148bf22b60 .functor AND 1, L_0x56148bf21c30, v0x56148bf0b480_0, C4<1>, C4<1>; +L_0x56148bf22e40 .functor NOT 1, v0x56148bcfeb70_0, C4<0>, C4<0>, C4<0>; +L_0x56148bf23c50 .functor NOT 1, v0x56148bcfeb70_0, C4<0>, C4<0>, C4<0>; +v0x56148bf0a490_0 .net *"_s10", 0 0, L_0x56148bf22650; 1 drivers +v0x56148bf0a570_0 .net *"_s14", 0 0, L_0x56148bf228a0; 1 drivers +v0x56148bf0a650_0 .net *"_s17", 0 0, L_0x56148bf22960; 1 drivers +L_0x7ff4bea75cc0 .functor BUFT 1, C4<000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x56148bf0a6f0_0 .net/2u *"_s26", 35 0, L_0x7ff4bea75cc0; 1 drivers +v0x56148bf0a7d0_0 .net *"_s6", 0 0, L_0x56148bf225e0; 1 drivers +L_0x7ff4bea759a8 .functor BUFT 1, C4<10>, C4<0>, C4<0>, C4<0>; +v0x56148bf0a900_0 .net/2u *"_s8", 1 0, L_0x7ff4bea759a8; 1 drivers +v0x56148bf0a9e0_0 .var "addr", 0 17; +v0x56148bf0aac0_0 .net "clk", 0 0, v0x56148bd15230_0; alias, 1 drivers +v0x56148bf0ab60_0 .net "m_addr_ack", 0 0, L_0x56148bf21c30; alias, 1 drivers +v0x56148bf0ac20_0 .var "m_fmc_select", 0 0; +v0x56148bf0acc0_0 .net "m_ma", 21 35, L_0x56148bf21ef0; alias, 1 drivers +v0x56148bf0add0_0 .net "m_mb_read", 0 35, L_0x56148bf21ad0; alias, 1 drivers +v0x56148bf0aeb0_0 .net "m_mb_write", 0 35, L_0x56148bf23cc0; alias, 1 drivers +v0x56148bf0afc0_0 .var "m_rd_rq", 0 0; +v0x56148bf0b0b0_0 .net "m_rd_rs", 0 0, L_0x56148bf21d90; alias, 1 drivers +v0x56148bf0b170_0 .var "m_rq_cyc", 0 0; +v0x56148bf0b260_0 .net "m_sel", 18 21, L_0x56148bf21f90; alias, 1 drivers +v0x56148bf0b480_0 .var "m_wr_rq", 0 0; +v0x56148bf0b570_0 .net "m_wr_rs", 0 0, L_0x56148bf22d00; alias, 1 drivers +v0x56148bf0b610_0 .net "mb_read_pulse", 0 0, L_0x56148bf223e0; 1 drivers +v0x56148bf0b6b0_0 .net "mb_write_pulse", 0 0, L_0x56148bf23af0; 1 drivers +v0x56148bf0b750_0 .net "read_edge", 0 0, L_0x56148bf22260; 1 drivers +v0x56148bf0b7f0_0 .net "req", 0 0, L_0x56148bf22790; 1 drivers +v0x56148bf0b890_0 .net "reset", 0 0, v0x56148bcfeb70_0; alias, 1 drivers +v0x56148bf0b930_0 .net "s_address", 1 0, v0x56148bf06140_0; 1 drivers +v0x56148bf0b9d0_0 .net "s_read", 0 0, v0x56148bf0c430_0; 1 drivers +v0x56148bf0ba70_0 .var "s_readdata", 31 0; +v0x56148bf0bb30_0 .net "s_waitrequest", 0 0, L_0x56148bf22a00; alias, 1 drivers +v0x56148bf0bbf0_0 .net "s_write", 0 0, v0x56148bf0c660_0; 1 drivers +v0x56148bf0bc90_0 .net "s_writedata", 31 0, v0x56148bf0c7a0_0; 1 drivers +v0x56148bf0bd50_0 .var "waitcyc", 7 0; +v0x56148bf0be30_0 .var "waiting", 0 0; +v0x56148bf0bef0_0 .var "word", 0 35; +v0x56148bf0bfd0_0 .net "wr_rs", 0 0, L_0x56148bf22b60; 1 drivers +v0x56148bf0c070_0 .net "write_edge", 0 0, L_0x56148bf22130; 1 drivers +E_0x56148bf063b0 .event edge, v0x56148bf0b930_0, v0x56148bf0bef0_0; +L_0x56148bf21ef0 .part v0x56148bf0a9e0_0, 0, 15; +L_0x56148bf21f90 .part v0x56148bf0a9e0_0, 14, 4; +L_0x56148bf224f0 .reduce/or L_0x56148bf21ad0; +L_0x56148bf22650 .cmp/eq 2, v0x56148bf06140_0, L_0x7ff4bea759a8; +L_0x56148bf22960 .reduce/or v0x56148bf0bd50_0; +L_0x56148bf23cc0 .functor MUXZ 36, L_0x7ff4bea75cc0, v0x56148bf0bef0_0, L_0x56148bf23af0, C4<>; +S_0x56148bf06430 .scope module, "e0" "edgedet" 10 33, 5 15 0, S_0x56148bf05f70; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "signal" + .port_info 3 /OUTPUT 1 "p" +L_0x56148bf220c0 .functor NOT 1, v0x56148bf07110_0, C4<0>, C4<0>, C4<0>; +L_0x56148bf22130 .functor AND 1, v0x56148bf0c660_0, L_0x56148bf220c0, C4<1>, C4<1>; +v0x56148bf06740_0 .net *"_s0", 0 0, L_0x56148bf220c0; 1 drivers +v0x56148bf06840_0 .net "clk", 0 0, v0x56148bd15230_0; alias, 1 drivers +v0x56148bf07110_0 .var "last", 0 0; +v0x56148bf071e0_0 .net "p", 0 0, L_0x56148bf22130; alias, 1 drivers +v0x56148bf07280_0 .net "reset", 0 0, v0x56148bcfeb70_0; alias, 1 drivers +v0x56148bf07370_0 .net "signal", 0 0, v0x56148bf0c660_0; alias, 1 drivers +E_0x56148bf066c0/0 .event negedge, v0x56148bcfeb70_0; +E_0x56148bf066c0/1 .event posedge, v0x56148bd15230_0; +E_0x56148bf066c0 .event/or E_0x56148bf066c0/0, E_0x56148bf066c0/1; +S_0x56148bf074c0 .scope module, "e1" "edgedet" 10 34, 5 15 0, S_0x56148bf05f70; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "signal" + .port_info 3 /OUTPUT 1 "p" +L_0x56148bf221f0 .functor NOT 1, v0x56148bf078c0_0, C4<0>, C4<0>, C4<0>; +L_0x56148bf22260 .functor AND 1, v0x56148bf0c430_0, L_0x56148bf221f0, C4<1>, C4<1>; +v0x56148bf07720_0 .net *"_s0", 0 0, L_0x56148bf221f0; 1 drivers +v0x56148bf07800_0 .net "clk", 0 0, v0x56148bd15230_0; alias, 1 drivers +v0x56148bf078c0_0 .var "last", 0 0; +v0x56148bf07990_0 .net "p", 0 0, L_0x56148bf22260; alias, 1 drivers +v0x56148bf07a30_0 .net "reset", 0 0, v0x56148bcfeb70_0; alias, 1 drivers +v0x56148bf07b70_0 .net "signal", 0 0, v0x56148bf0c430_0; alias, 1 drivers +S_0x56148bf07cb0 .scope module, "e2" "edgedet" 10 35, 5 15 0, S_0x56148bf05f70; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "signal" + .port_info 3 /OUTPUT 1 "p" +L_0x56148bf22370 .functor NOT 1, v0x56148bf08090_0, C4<0>, C4<0>, C4<0>; +L_0x56148bf223e0 .functor AND 1, L_0x56148bf224f0, L_0x56148bf22370, C4<1>, C4<1>; +v0x56148bf07ef0_0 .net *"_s0", 0 0, L_0x56148bf22370; 1 drivers +v0x56148bf07fd0_0 .net "clk", 0 0, v0x56148bd15230_0; alias, 1 drivers +v0x56148bf08090_0 .var "last", 0 0; +v0x56148bf08160_0 .net "p", 0 0, L_0x56148bf223e0; alias, 1 drivers +v0x56148bf08200_0 .net "reset", 0 0, v0x56148bcfeb70_0; alias, 1 drivers +v0x56148bf082f0_0 .net "signal", 0 0, L_0x56148bf224f0; 1 drivers +S_0x56148bf08430 .scope module, "mb_bd1" "bd2" 10 44, 3 57 0, S_0x56148bf05f70; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +L_0x56148bf233a0 .functor OR 1, L_0x56148bf22fe0, L_0x56148bf23260, C4<0>, C4<0>; +L_0x56148bf23720 .functor OR 1, L_0x56148bf233a0, L_0x56148bf235a0, C4<0>, C4<0>; +L_0x56148bf23af0 .functor OR 1, L_0x56148bf23720, L_0x56148bf23960, C4<0>, C4<0>; +v0x56148bf086f0_0 .net *"_s0", 31 0, L_0x56148bf22ef0; 1 drivers +L_0x7ff4bea75b10 .functor BUFT 1, C4<00000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x56148bf087f0_0 .net *"_s11", 28 0, L_0x7ff4bea75b10; 1 drivers +L_0x7ff4bea75b58 .functor BUFT 1, C4<00000000000000000000000000000101>, C4<0>, C4<0>, C4<0>; +v0x56148bf088d0_0 .net/2u *"_s12", 31 0, L_0x7ff4bea75b58; 1 drivers +v0x56148bf089c0_0 .net *"_s14", 0 0, L_0x56148bf23260; 1 drivers +v0x56148bf08a80_0 .net *"_s16", 0 0, L_0x56148bf233a0; 1 drivers +v0x56148bf08b90_0 .net *"_s18", 31 0, L_0x56148bf234b0; 1 drivers +L_0x7ff4bea75ba0 .functor BUFT 1, C4<00000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x56148bf08c70_0 .net *"_s21", 28 0, L_0x7ff4bea75ba0; 1 drivers +L_0x7ff4bea75be8 .functor BUFT 1, C4<00000000000000000000000000000110>, C4<0>, C4<0>, C4<0>; +v0x56148bf08d50_0 .net/2u *"_s22", 31 0, L_0x7ff4bea75be8; 1 drivers +v0x56148bf08e30_0 .net *"_s24", 0 0, L_0x56148bf235a0; 1 drivers +v0x56148bf08ef0_0 .net *"_s26", 0 0, L_0x56148bf23720; 1 drivers +v0x56148bf08fb0_0 .net *"_s28", 31 0, L_0x56148bf23830; 1 drivers +L_0x7ff4bea75a80 .functor BUFT 1, C4<00000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x56148bf09090_0 .net *"_s3", 28 0, L_0x7ff4bea75a80; 1 drivers +L_0x7ff4bea75c30 .functor BUFT 1, C4<00000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x56148bf09170_0 .net *"_s31", 28 0, L_0x7ff4bea75c30; 1 drivers +L_0x7ff4bea75c78 .functor BUFT 1, C4<00000000000000000000000000000111>, C4<0>, C4<0>, C4<0>; +v0x56148bf09250_0 .net/2u *"_s32", 31 0, L_0x7ff4bea75c78; 1 drivers +v0x56148bf09330_0 .net *"_s34", 0 0, L_0x56148bf23960; 1 drivers +L_0x7ff4bea75ac8 .functor BUFT 1, C4<00000000000000000000000000000100>, C4<0>, C4<0>, C4<0>; +v0x56148bf093f0_0 .net/2u *"_s4", 31 0, L_0x7ff4bea75ac8; 1 drivers +v0x56148bf094d0_0 .net *"_s6", 0 0, L_0x56148bf22fe0; 1 drivers +v0x56148bf09590_0 .net *"_s8", 31 0, L_0x56148bf23120; 1 drivers +v0x56148bf09670_0 .net "clk", 0 0, v0x56148bd15230_0; alias, 1 drivers +v0x56148bf09710_0 .net "in", 0 0, L_0x56148bf22b60; alias, 1 drivers +v0x56148bf097d0_0 .net "p", 0 0, L_0x56148bf23af0; alias, 1 drivers +v0x56148bf09890_0 .var "r", 2 0; +v0x56148bf09970_0 .net "reset", 0 0, L_0x56148bf23c50; 1 drivers +E_0x56148bf08670 .event posedge, v0x56148bf09970_0, v0x56148bd15230_0; +L_0x56148bf22ef0 .concat [ 3 29 0 0], v0x56148bf09890_0, L_0x7ff4bea75a80; +L_0x56148bf22fe0 .cmp/eq 32, L_0x56148bf22ef0, L_0x7ff4bea75ac8; +L_0x56148bf23120 .concat [ 3 29 0 0], v0x56148bf09890_0, L_0x7ff4bea75b10; +L_0x56148bf23260 .cmp/eq 32, L_0x56148bf23120, L_0x7ff4bea75b58; +L_0x56148bf234b0 .concat [ 3 29 0 0], v0x56148bf09890_0, L_0x7ff4bea75ba0; +L_0x56148bf235a0 .cmp/eq 32, L_0x56148bf234b0, L_0x7ff4bea75be8; +L_0x56148bf23830 .concat [ 3 29 0 0], v0x56148bf09890_0, L_0x7ff4bea75c30; +L_0x56148bf23960 .cmp/eq 32, L_0x56148bf23830, L_0x7ff4bea75c78; +S_0x56148bf09ab0 .scope module, "mc_bd0" "bd" 10 43, 3 39 0, S_0x56148bf05f70; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +v0x56148bf09d70_0 .net *"_s0", 31 0, L_0x56148bf22c60; 1 drivers +L_0x7ff4bea759f0 .functor BUFT 1, C4<00000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x56148bf09e70_0 .net *"_s3", 28 0, L_0x7ff4bea759f0; 1 drivers +L_0x7ff4bea75a38 .functor BUFT 1, C4<00000000000000000000000000000100>, C4<0>, C4<0>, C4<0>; +v0x56148bf09f50_0 .net/2u *"_s4", 31 0, L_0x7ff4bea75a38; 1 drivers +v0x56148bf0a010_0 .net "clk", 0 0, v0x56148bd15230_0; alias, 1 drivers +v0x56148bf0a0b0_0 .net "in", 0 0, L_0x56148bf22b60; alias, 1 drivers +v0x56148bf0a1a0_0 .net "p", 0 0, L_0x56148bf22d00; alias, 1 drivers +v0x56148bf0a290_0 .var "r", 2 0; +v0x56148bf0a350_0 .net "reset", 0 0, L_0x56148bf22e40; 1 drivers +E_0x56148bf09cf0 .event posedge, v0x56148bf0a350_0, v0x56148bd15230_0; +L_0x56148bf22c60 .concat [ 3 29 0 0], v0x56148bf0a290_0, L_0x7ff4bea759f0; +L_0x56148bf22d00 .cmp/eq 32, L_0x56148bf22c60, L_0x7ff4bea75a38; + .scope S_0x56148be2d130; +T_0 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x56148beaa460_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x56148bea89b0_0, 0, 1; + %end; + .thread T_0; + .scope S_0x56148be2d130; +T_1 ; + %wait E_0x56148bd0e9b0; + %load/vec4 v0x56148be9e120_0; + %inv; + %flag_set/vec4 8; + %jmp/0xz T_1.0, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x56148beaa460_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x56148bea89b0_0, 0; + %jmp T_1.1; +T_1.0 ; + %load/vec4 v0x56148beaa460_0; + %load/vec4 v0x56148be1d000_0; + %inv; + %and; + %load/vec4 v0x56148bea89b0_0; + %load/vec4 v0x56148be108e0_0; + %inv; + %and; + %or; + %flag_set/vec4 8; + %jmp/0xz T_1.2, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x56148beaa460_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x56148bea89b0_0, 0; + %jmp T_1.3; +T_1.2 ; + %load/vec4 v0x56148be1cf00_0; + %inv; + %flag_set/vec4 8; + %jmp/0xz T_1.4, 8; + %load/vec4 v0x56148be1d000_0; + %flag_set/vec4 8; + %jmp/0xz T_1.6, 8; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x56148beaa460_0, 0; + %jmp T_1.7; +T_1.6 ; + %load/vec4 v0x56148be108e0_0; + %flag_set/vec4 8; + %jmp/0xz T_1.8, 8; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x56148bea89b0_0, 0; +T_1.8 ; +T_1.7 ; +T_1.4 ; +T_1.3 ; +T_1.1 ; + %jmp T_1; + .thread T_1; + .scope S_0x56148be2d130; +T_2 ; + %wait E_0x56148bd0db00; + %load/vec4 v0x56148beaa460_0; + %flag_set/vec4 8; + %jmp/0xz T_2.0, 8; + %load/vec4 v0x56148be10980_0; + %assign/vec4 v0x56148be9b3d0_0, 0; + %load/vec4 v0x56148be0ed20_0; + %assign/vec4 v0x56148beb23f0_0, 0; + %load/vec4 v0x56148be0ec20_0; + %assign/vec4 v0x56148beb2350_0, 0; + %load/vec4 v0x56148bd22a90_0; + %assign/vec4 v0x56148beaa380_0, 0; + %load/vec4 v0x56148be9e060_0; + %assign/vec4 v0x56148be9d220_0, 0; + %load/vec4 v0x56148be9d180_0; + %assign/vec4 v0x56148be9c2a0_0, 0; + %pushi/vec4 0, 0, 36; + %assign/vec4 v0x56148be9c340_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x56148be9b330_0, 0; + %jmp T_2.1; +T_2.0 ; + %load/vec4 v0x56148bea89b0_0; + %flag_set/vec4 8; + %jmp/0xz T_2.2, 8; + %load/vec4 v0x56148bea0390_0; + %assign/vec4 v0x56148be9b3d0_0, 0; + %load/vec4 v0x56148be8fd40_0; + %assign/vec4 v0x56148beb23f0_0, 0; + %load/vec4 v0x56148be8fc80_0; + %assign/vec4 v0x56148beb2350_0, 0; + %load/vec4 v0x56148be9ef40_0; + %assign/vec4 v0x56148beaa380_0, 0; + %load/vec4 v0x56148be9e060_0; + %assign/vec4 v0x56148be9c340_0, 0; + %load/vec4 v0x56148be9d180_0; + %assign/vec4 v0x56148be9b330_0, 0; + %pushi/vec4 0, 0, 36; + %assign/vec4 v0x56148be9d220_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x56148be9c2a0_0, 0; + %jmp T_2.3; +T_2.2 ; + %pushi/vec4 0, 0, 18; + %assign/vec4 v0x56148be9b3d0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x56148beb23f0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x56148beb2350_0, 0; + %pushi/vec4 0, 0, 36; + %assign/vec4 v0x56148beaa380_0, 0; + %pushi/vec4 0, 0, 36; + %assign/vec4 v0x56148be9d220_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x56148be9c2a0_0, 0; + %pushi/vec4 0, 0, 36; + %assign/vec4 v0x56148be9c340_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x56148be9b330_0, 0; +T_2.3 ; +T_2.1 ; + %jmp T_2; + .thread T_2, $push; + .scope S_0x56148bebe570; +T_3 ; + %pushi/vec4 0, 0, 22; + %store/vec4 v0x56148beabe10_0, 0, 22; + %end; + .thread T_3; + .scope S_0x56148bebe570; +T_4 ; + %wait E_0x56148bd0eac0; + %load/vec4 v0x56148be453d0_0; + %flag_set/vec4 8; + %jmp/0xz T_4.0, 8; + %pushi/vec4 0, 0, 22; + %assign/vec4 v0x56148beabe10_0, 0; + %jmp T_4.1; +T_4.0 ; + %load/vec4 v0x56148beabe10_0; + %addi 1, 0, 22; + %assign/vec4 v0x56148beabe10_0, 0; +T_4.1 ; + %jmp T_4; + .thread T_4; + .scope S_0x56148bec3ac0; +T_5 ; + %wait E_0x56148bed0980; + %load/vec4 v0x56148be410f0_0; + %flag_set/vec4 8; + %jmp/0xz T_5.0, 8; + %pushi/vec4 0, 0, 16; + %assign/vec4 v0x56148be41010_0, 0; + %jmp T_5.1; +T_5.0 ; + %load/vec4 v0x56148be41010_0; + %cmpi/ne 0, 0, 16; + %jmp/0xz T_5.2, 4; + %load/vec4 v0x56148be41010_0; + %addi 1, 0, 16; + %assign/vec4 v0x56148be41010_0, 0; +T_5.2 ; + %load/vec4 v0x56148be42630_0; + %flag_set/vec4 8; + %jmp/0xz T_5.4, 8; + %pushi/vec4 1, 0, 16; + %assign/vec4 v0x56148be41010_0, 0; +T_5.4 ; +T_5.1 ; + %jmp T_5; + .thread T_5; + .scope S_0x56148beb5d40; +T_6 ; + %wait E_0x56148bed0b90; + %load/vec4 v0x56148be5eb80_0; + %flag_set/vec4 8; + %jmp/0xz T_6.0, 8; + %pushi/vec4 0, 0, 5; + %assign/vec4 v0x56148be3aa30_0, 0; + %jmp T_6.1; +T_6.0 ; + %load/vec4 v0x56148be3aa30_0; + %cmpi/ne 0, 0, 5; + %jmp/0xz T_6.2, 4; + %load/vec4 v0x56148be3aa30_0; + %addi 1, 0, 5; + %assign/vec4 v0x56148be3aa30_0, 0; +T_6.2 ; + %load/vec4 v0x56148be3bdd0_0; + %flag_set/vec4 8; + %jmp/0xz T_6.4, 8; + %pushi/vec4 1, 0, 5; + %assign/vec4 v0x56148be3aa30_0, 0; +T_6.4 ; +T_6.1 ; + %jmp T_6; + .thread T_6; + .scope S_0x56148beb7af0; +T_7 ; + %wait E_0x56148be5ecc0; + %load/vec4 v0x56148be4a3e0_0; + %flag_set/vec4 8; + %jmp/0xz T_7.0, 8; + %pushi/vec4 0, 0, 4; + %assign/vec4 v0x56148be50460_0, 0; + %jmp T_7.1; +T_7.0 ; + %load/vec4 v0x56148be50460_0; + %cmpi/ne 0, 0, 4; + %jmp/0xz T_7.2, 4; + %load/vec4 v0x56148be50460_0; + %addi 1, 0, 4; + %assign/vec4 v0x56148be50460_0, 0; +T_7.2 ; + %load/vec4 v0x56148be597e0_0; + %flag_set/vec4 8; + %jmp/0xz T_7.4, 8; + %pushi/vec4 1, 0, 4; + %assign/vec4 v0x56148be50460_0, 0; +T_7.4 ; +T_7.1 ; + %jmp T_7; + .thread T_7; + .scope S_0x56148be76390; +T_8 ; + %wait E_0x56148be49ad0; + %load/vec4 v0x56148be47870_0; + %inv; + %flag_set/vec4 8; + %jmp/0xz T_8.0, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x56148be489e0_0, 0; + %jmp T_8.1; +T_8.0 ; + %load/vec4 v0x56148be46660_0; + %assign/vec4 v0x56148be489e0_0, 0; +T_8.1 ; + %jmp T_8; + .thread T_8; + .scope S_0x56148be77e90; +T_9 ; + %wait E_0x56148be49ad0; + %load/vec4 v0x56148be52f70_0; + %inv; + %flag_set/vec4 8; + %jmp/0xz T_9.0, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x56148be54960_0, 0; + %jmp T_9.1; +T_9.0 ; + %load/vec4 v0x56148be51210_0; + %assign/vec4 v0x56148be54960_0, 0; +T_9.1 ; + %jmp T_9; + .thread T_9; + .scope S_0x56148beb9590; +T_10 ; + %wait E_0x56148be49ad0; + %load/vec4 v0x56148be0e4a0_0; + %inv; + %flag_set/vec4 8; + %jmp/0xz T_10.0, 8; + %pushi/vec4 4, 0, 4; + %assign/vec4 v0x56148be1b890_0, 0; + %jmp T_10.1; +T_10.0 ; + %load/vec4 v0x56148be0d480_0; + %load/vec4 v0x56148beb0620_0; + %and; + %load/vec4 v0x56148be1b7d0_0; + %and; + %flag_set/vec4 8; + %jmp/0xz T_10.2, 8; + %load/vec4 v0x56148be0d520_0; + %load/vec4 v0x56148be1c7c0_0; + %pad/u 16; + %ix/vec4 3; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x56148becb530, 0, 4; +T_10.2 ; + %load/vec4 v0x56148be0d480_0; + %load/vec4 v0x56148be0e400_0; + %or; + %inv; + %flag_set/vec4 8; + %jmp/0xz T_10.4, 8; + %pushi/vec4 4, 0, 4; + %assign/vec4 v0x56148be1b890_0, 0; + %jmp T_10.5; +T_10.4 ; + %load/vec4 v0x56148be1b890_0; + %cmpi/ne 0, 0, 4; + %jmp/0xz T_10.6, 4; + %load/vec4 v0x56148be1b890_0; + %subi 1, 0, 4; + %assign/vec4 v0x56148be1b890_0, 0; +T_10.6 ; +T_10.5 ; +T_10.1 ; + %jmp T_10; + .thread T_10; + .scope S_0x56148bebb030; +T_11 ; + %wait E_0x56148becb690; + %load/vec4 v0x56148bcfba30_0; + %flag_set/vec4 8; + %jmp/0xz T_11.0, 8; + %pushi/vec4 0, 0, 16; + %assign/vec4 v0x56148bcfb950_0, 0; + %jmp T_11.1; +T_11.0 ; + %load/vec4 v0x56148bcfb950_0; + %cmpi/ne 0, 0, 16; + %jmp/0xz T_11.2, 4; + %load/vec4 v0x56148bcfb950_0; + %addi 1, 0, 16; + %assign/vec4 v0x56148bcfb950_0, 0; +T_11.2 ; + %load/vec4 v0x56148bd7de50_0; + %flag_set/vec4 8; + %jmp/0xz T_11.4, 8; + %pushi/vec4 1, 0, 16; + %assign/vec4 v0x56148bcfb950_0, 0; +T_11.4 ; +T_11.1 ; + %jmp T_11; + .thread T_11; + .scope S_0x56148be328e0; +T_12 ; + %wait E_0x56148bd7dfb0; + %load/vec4 v0x56148bd8ba10_0; + %flag_set/vec4 8; + %jmp/0xz T_12.0, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x56148bd8b7b0_0, 0; + %pushi/vec4 0, 0, 8; + %assign/vec4 v0x56148bd8b930_0, 0; + %jmp T_12.1; +T_12.0 ; + %load/vec4 v0x56148bd8b930_0; + %cmpi/ne 0, 0, 8; + %jmp/0xz T_12.2, 4; + %load/vec4 v0x56148bd8b930_0; + %addi 1, 0, 8; + %assign/vec4 v0x56148bd8b930_0, 0; +T_12.2 ; + %load/vec4 v0x56148bd2d9c0_0; + %flag_set/vec4 8; + %jmp/0xz T_12.4, 8; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x56148bd8b7b0_0, 0; + %pushi/vec4 1, 0, 8; + %assign/vec4 v0x56148bd8b930_0, 0; +T_12.4 ; + %load/vec4 v0x56148bd8b930_0; + %pad/u 32; + %cmpi/e 151, 0, 32; + %jmp/0xz T_12.6, 4; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x56148bd8b7b0_0, 0; +T_12.6 ; +T_12.1 ; + %jmp T_12; + .thread T_12; + .scope S_0x56148bebcad0; +T_13 ; + %wait E_0x56148be4b750; + %load/vec4 v0x56148bd8dd90_0; + %flag_set/vec4 8; + %jmp/0xz T_13.0, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x56148bd8db50_0, 0; + %pushi/vec4 0, 0, 7; + %assign/vec4 v0x56148bd8dcb0_0, 0; + %jmp T_13.1; +T_13.0 ; + %load/vec4 v0x56148bd8dcb0_0; + %cmpi/ne 0, 0, 7; + %jmp/0xz T_13.2, 4; + %load/vec4 v0x56148bd8dcb0_0; + %addi 1, 0, 7; + %assign/vec4 v0x56148bd8dcb0_0, 0; +T_13.2 ; + %load/vec4 v0x56148bda50a0_0; + %flag_set/vec4 8; + %jmp/0xz T_13.4, 8; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x56148bd8db50_0, 0; + %pushi/vec4 1, 0, 7; + %assign/vec4 v0x56148bd8dcb0_0, 0; +T_13.4 ; + %load/vec4 v0x56148bd8dcb0_0; + %pad/u 32; + %cmpi/e 101, 0, 32; + %jmp/0xz T_13.6, 4; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x56148bd8db50_0, 0; +T_13.6 ; +T_13.1 ; + %jmp T_13; + .thread T_13; + .scope S_0x56148be6f910; +T_14 ; + %wait E_0x56148bd8def0; + %load/vec4 v0x56148bd90120_0; + %flag_set/vec4 8; + %jmp/0xz T_14.0, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x56148bd8fec0_0, 0; + %pushi/vec4 0, 0, 8; + %assign/vec4 v0x56148bd90040_0, 0; + %jmp T_14.1; +T_14.0 ; + %load/vec4 v0x56148bd90040_0; + %cmpi/ne 0, 0, 8; + %jmp/0xz T_14.2, 4; + %load/vec4 v0x56148bd90040_0; + %addi 1, 0, 8; + %assign/vec4 v0x56148bd90040_0, 0; +T_14.2 ; + %load/vec4 v0x56148bd99010_0; + %flag_set/vec4 8; + %jmp/0xz T_14.4, 8; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x56148bd8fec0_0, 0; + %pushi/vec4 1, 0, 8; + %assign/vec4 v0x56148bd90040_0, 0; +T_14.4 ; + %load/vec4 v0x56148bd90040_0; + %pad/u 32; + %cmpi/e 201, 0, 32; + %jmp/0xz T_14.6, 4; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x56148bd8fec0_0, 0; +T_14.6 ; +T_14.1 ; + %jmp T_14; + .thread T_14; + .scope S_0x56148be79960; +T_15 ; + %wait E_0x56148bd92270; + %load/vec4 v0x56148bd945a0_0; + %inv; + %flag_set/vec4 8; + %jmp/0xz T_15.0, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x56148bd924b0_0, 0; + %jmp T_15.1; +T_15.0 ; + %load/vec4 v0x56148bd946b0_0; + %assign/vec4 v0x56148bd924b0_0, 0; +T_15.1 ; + %jmp T_15; + .thread T_15; + .scope S_0x56148bd947f0; +T_16 ; + %wait E_0x56148bd92270; + %load/vec4 v0x56148bd87430_0; + %inv; + %flag_set/vec4 8; + %jmp/0xz T_16.0, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x56148bd872c0_0, 0; + %jmp T_16.1; +T_16.0 ; + %load/vec4 v0x56148bd89490_0; + %assign/vec4 v0x56148bd872c0_0, 0; +T_16.1 ; + %jmp T_16; + .thread T_16; + .scope S_0x56148be713e0; +T_17 ; + %wait E_0x56148bd92270; + %load/vec4 v0x56148bcfcf80_0; + %inv; + %flag_set/vec4 8; + %jmp/0xz T_17.0, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x56148bd03790_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x56148bd96c20_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x56148bd5cba0_0, 0; + %pushi/vec4 0, 0, 18; + %assign/vec4 v0x56148bd96920_0, 0; + %pushi/vec4 0, 0, 36; + %assign/vec4 v0x56148bda71c0_0, 0; + %jmp T_17.1; +T_17.0 ; + %load/vec4 v0x56148bda72a0_0; + %flag_set/vec4 8; + %jmp/0xz T_17.2, 8; + %load/vec4 v0x56148bcfd020_0; + %dup/vec4; + %pushi/vec4 0, 0, 2; + %cmp/u; + %jmp/1 T_17.4, 6; + %dup/vec4; + %pushi/vec4 1, 0, 2; + %cmp/u; + %jmp/1 T_17.5, 6; + %dup/vec4; + %pushi/vec4 2, 0, 2; + %cmp/u; + %jmp/1 T_17.6, 6; + %jmp T_17.7; +T_17.4 ; + %load/vec4 v0x56148bd5cae0_0; + %parti/s 18, 0, 2; + %assign/vec4 v0x56148bd96920_0, 0; + %jmp T_17.7; +T_17.5 ; + %load/vec4 v0x56148bd5cae0_0; + %parti/s 18, 0, 2; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x56148bda71c0_0, 4, 5; + %jmp T_17.7; +T_17.6 ; + %load/vec4 v0x56148bd5cae0_0; + %parti/s 18, 0, 2; + %ix/load 4, 18, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x56148bda71c0_0, 4, 5; + %jmp T_17.7; +T_17.7 ; + %pop/vec4 1; +T_17.2 ; + %load/vec4 v0x56148bcfcee0_0; + %flag_set/vec4 8; + %jmp/0xz T_17.8, 8; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x56148bd5cba0_0, 0; + %load/vec4 v0x56148bd5ca40_0; + %flag_set/vec4 8; + %jmp/0xz T_17.10, 8; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x56148bd03790_0, 0; + %jmp T_17.11; +T_17.10 ; + %load/vec4 v0x56148bcfd100_0; + %flag_set/vec4 8; + %jmp/0xz T_17.12, 8; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x56148bd96c20_0, 0; +T_17.12 ; +T_17.11 ; +T_17.8 ; + %load/vec4 v0x56148bd03790_0; + %load/vec4 v0x56148bd03640_0; + %inv; + %and; + %flag_set/vec4 8; + %jmp/0xz T_17.14, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x56148bd03790_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x56148bd5cba0_0, 0; +T_17.14 ; + %load/vec4 v0x56148bd96c20_0; + %load/vec4 v0x56148bd03640_0; + %inv; + %and; + %flag_set/vec4 8; + %jmp/0xz T_17.16, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x56148bd96c20_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x56148bd5cba0_0, 0; + %load/vec4 v0x56148bd03560_0; + %assign/vec4 v0x56148bda71c0_0, 0; +T_17.16 ; +T_17.1 ; + %jmp T_17; + .thread T_17; + .scope S_0x56148be713e0; +T_18 ; + %wait E_0x56148bd90280; + %load/vec4 v0x56148bcfd020_0; + %dup/vec4; + %pushi/vec4 1, 0, 2; + %cmp/u; + %jmp/1 T_18.0, 6; + %dup/vec4; + %pushi/vec4 2, 0, 2; + %cmp/u; + %jmp/1 T_18.1, 6; + %pushi/vec4 0, 0, 32; + %assign/vec4 v0x56148bcfd1a0_0, 0; + %jmp T_18.3; +T_18.0 ; + %pushi/vec4 0, 0, 14; + %load/vec4 v0x56148bda71c0_0; + %parti/s 18, 0, 2; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x56148bcfd1a0_0, 0; + %jmp T_18.3; +T_18.1 ; + %pushi/vec4 0, 0, 14; + %load/vec4 v0x56148bda71c0_0; + %parti/s 18, 18, 6; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x56148bcfd1a0_0, 0; + %jmp T_18.3; +T_18.3 ; + %pop/vec4 1; + %jmp T_18; + .thread T_18, $push; + .scope S_0x56148be72e50; +T_19 ; + %wait E_0x56148bd89820; + %load/vec4 v0x56148bda1c10_0; + %inv; + %flag_set/vec4 8; + %jmp/0xz T_19.0, 8; + %jmp T_19.1; +T_19.0 ; + %load/vec4 v0x56148bd1efd0_0; + %load/vec4 v0x56148bda18f0_0; + %and; + %flag_set/vec4 8; + %jmp/0xz T_19.2, 8; + %load/vec4 v0x56148bd1f090_0; + %load/vec4 v0x56148bd9b390_0; + %pad/u 16; + %ix/vec4 3; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x56148bd1f280, 0, 4; +T_19.2 ; +T_19.1 ; + %jmp T_19; + .thread T_19; + .scope S_0x56148bcfe930; +T_20 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x56148bd15230_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x56148bcfeb70_0, 0, 1; + %delay 50, 0; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x56148bcfeb70_0, 0, 1; + %end; + .thread T_20; + .scope S_0x56148bcfe930; +T_21 ; + %delay 5, 0; + %load/vec4 v0x56148bd15230_0; + %inv; + %store/vec4 v0x56148bd15230_0, 0, 1; + %jmp T_21; + .thread T_21; + .scope S_0x56148bf06430; +T_22 ; + %wait E_0x56148bf066c0; + %load/vec4 v0x56148bf07280_0; + %inv; + %flag_set/vec4 8; + %jmp/0xz T_22.0, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x56148bf07110_0, 0; + %jmp T_22.1; +T_22.0 ; + %load/vec4 v0x56148bf07370_0; + %assign/vec4 v0x56148bf07110_0, 0; +T_22.1 ; + %jmp T_22; + .thread T_22; + .scope S_0x56148bf074c0; +T_23 ; + %wait E_0x56148bf066c0; + %load/vec4 v0x56148bf07a30_0; + %inv; + %flag_set/vec4 8; + %jmp/0xz T_23.0, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x56148bf078c0_0, 0; + %jmp T_23.1; +T_23.0 ; + %load/vec4 v0x56148bf07b70_0; + %assign/vec4 v0x56148bf078c0_0, 0; +T_23.1 ; + %jmp T_23; + .thread T_23; + .scope S_0x56148bf07cb0; +T_24 ; + %wait E_0x56148bf066c0; + %load/vec4 v0x56148bf08200_0; + %inv; + %flag_set/vec4 8; + %jmp/0xz T_24.0, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x56148bf08090_0, 0; + %jmp T_24.1; +T_24.0 ; + %load/vec4 v0x56148bf082f0_0; + %assign/vec4 v0x56148bf08090_0, 0; +T_24.1 ; + %jmp T_24; + .thread T_24; + .scope S_0x56148bf09ab0; +T_25 ; + %wait E_0x56148bf09cf0; + %load/vec4 v0x56148bf0a350_0; + %flag_set/vec4 8; + %jmp/0xz T_25.0, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x56148bf0a290_0, 0; + %jmp T_25.1; +T_25.0 ; + %load/vec4 v0x56148bf0a290_0; + %cmpi/ne 0, 0, 3; + %jmp/0xz T_25.2, 4; + %load/vec4 v0x56148bf0a290_0; + %addi 1, 0, 3; + %assign/vec4 v0x56148bf0a290_0, 0; +T_25.2 ; + %load/vec4 v0x56148bf0a0b0_0; + %flag_set/vec4 8; + %jmp/0xz T_25.4, 8; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x56148bf0a290_0, 0; +T_25.4 ; +T_25.1 ; + %jmp T_25; + .thread T_25; + .scope S_0x56148bf08430; +T_26 ; + %wait E_0x56148bf08670; + %load/vec4 v0x56148bf09970_0; + %flag_set/vec4 8; + %jmp/0xz T_26.0, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x56148bf09890_0, 0; + %jmp T_26.1; +T_26.0 ; + %load/vec4 v0x56148bf09890_0; + %cmpi/ne 0, 0, 3; + %jmp/0xz T_26.2, 4; + %load/vec4 v0x56148bf09890_0; + %addi 1, 0, 3; + %assign/vec4 v0x56148bf09890_0, 0; +T_26.2 ; + %load/vec4 v0x56148bf09710_0; + %flag_set/vec4 8; + %jmp/0xz T_26.4, 8; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x56148bf09890_0, 0; +T_26.4 ; +T_26.1 ; + %jmp T_26; + .thread T_26; + .scope S_0x56148bf05f70; +T_27 ; + %wait E_0x56148bf066c0; + %load/vec4 v0x56148bf0b890_0; + %inv; + %flag_set/vec4 8; + %jmp/0xz T_27.0, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x56148bf0b170_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x56148bf0afc0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x56148bf0b480_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x56148bf0be30_0, 0; + %pushi/vec4 0, 0, 18; + %assign/vec4 v0x56148bf0a9e0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x56148bf0ac20_0, 0; + %pushi/vec4 0, 0, 36; + %assign/vec4 v0x56148bf0bef0_0, 0; + %pushi/vec4 0, 0, 8; + %assign/vec4 v0x56148bf0bd50_0, 0; + %jmp T_27.1; +T_27.0 ; + %load/vec4 v0x56148bf0c070_0; + %flag_set/vec4 8; + %jmp/0xz T_27.2, 8; + %load/vec4 v0x56148bf0b930_0; + %dup/vec4; + %pushi/vec4 0, 0, 2; + %cmp/u; + %jmp/1 T_27.4, 6; + %dup/vec4; + %pushi/vec4 1, 0, 2; + %cmp/u; + %jmp/1 T_27.5, 6; + %dup/vec4; + %pushi/vec4 2, 0, 2; + %cmp/u; + %jmp/1 T_27.6, 6; + %jmp T_27.7; +T_27.4 ; + %load/vec4 v0x56148bf0bc90_0; + %parti/s 18, 0, 2; + %assign/vec4 v0x56148bf0a9e0_0, 0; + %load/vec4 v0x56148bf0bc90_0; + %parti/s 1, 18, 6; + %assign/vec4 v0x56148bf0ac20_0, 0; + %jmp T_27.7; +T_27.5 ; + %load/vec4 v0x56148bf0bc90_0; + %parti/s 18, 0, 2; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x56148bf0bef0_0, 4, 5; + %jmp T_27.7; +T_27.6 ; + %load/vec4 v0x56148bf0bc90_0; + %parti/s 18, 0, 2; + %ix/load 4, 18, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x56148bf0bef0_0, 4, 5; + %jmp T_27.7; +T_27.7 ; + %pop/vec4 1; +T_27.2 ; + %load/vec4 v0x56148bf0b7f0_0; + %flag_set/vec4 8; + %jmp/0xz T_27.8, 8; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x56148bf0be30_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x56148bf0b170_0, 0; + %load/vec4 v0x56148bf0bbf0_0; + %flag_set/vec4 8; + %jmp/0xz T_27.10, 8; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x56148bf0b480_0, 0; + %jmp T_27.11; +T_27.10 ; + %load/vec4 v0x56148bf0b9d0_0; + %flag_set/vec4 8; + %jmp/0xz T_27.12, 8; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x56148bf0afc0_0, 0; +T_27.12 ; +T_27.11 ; +T_27.8 ; + %load/vec4 v0x56148bf0bd50_0; + %cmpi/ne 0, 0, 8; + %jmp/0xz T_27.14, 4; + %load/vec4 v0x56148bf0bd50_0; + %pad/u 32; + %cmpi/e 12, 0, 32; + %jmp/0xz T_27.16, 4; + %pushi/vec4 0, 0, 8; + %assign/vec4 v0x56148bf0bd50_0, 0; + %jmp T_27.17; +T_27.16 ; + %load/vec4 v0x56148bf0bd50_0; + %addi 1, 0, 8; + %assign/vec4 v0x56148bf0bd50_0, 0; +T_27.17 ; +T_27.14 ; + %load/vec4 v0x56148bf0b610_0; + %flag_set/vec4 8; + %jmp/0xz T_27.18, 8; + %load/vec4 v0x56148bf0add0_0; + %assign/vec4 v0x56148bf0bef0_0, 0; +T_27.18 ; + %load/vec4 v0x56148bf0ab60_0; + %flag_set/vec4 8; + %jmp/0xz T_27.20, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x56148bf0b170_0, 0; + %pushi/vec4 1, 0, 8; + %assign/vec4 v0x56148bf0bd50_0, 0; +T_27.20 ; + %load/vec4 v0x56148bf0b0b0_0; + %flag_set/vec4 8; + %jmp/0xz T_27.22, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x56148bf0afc0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x56148bf0be30_0, 0; +T_27.22 ; + %load/vec4 v0x56148bf0b570_0; + %flag_set/vec4 8; + %jmp/0xz T_27.24, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x56148bf0b480_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x56148bf0be30_0, 0; +T_27.24 ; +T_27.1 ; + %jmp T_27; + .thread T_27; + .scope S_0x56148bf05f70; +T_28 ; + %wait E_0x56148bf063b0; + %load/vec4 v0x56148bf0b930_0; + %dup/vec4; + %pushi/vec4 1, 0, 2; + %cmp/u; + %jmp/1 T_28.0, 6; + %dup/vec4; + %pushi/vec4 2, 0, 2; + %cmp/u; + %jmp/1 T_28.1, 6; + %pushi/vec4 0, 0, 32; + %assign/vec4 v0x56148bf0ba70_0, 0; + %jmp T_28.3; +T_28.0 ; + %pushi/vec4 0, 0, 14; + %load/vec4 v0x56148bf0bef0_0; + %parti/s 18, 0, 2; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x56148bf0ba70_0, 0; + %jmp T_28.3; +T_28.1 ; + %pushi/vec4 0, 0, 14; + %load/vec4 v0x56148bf0bef0_0; + %parti/s 18, 18, 6; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x56148bf0ba70_0, 0; + %jmp T_28.3; +T_28.3 ; + %pop/vec4 1; + %jmp T_28; + .thread T_28, $push; + .scope S_0x56148bee2e50; +T_29 ; + %wait E_0x56148bd7f550; + %load/vec4 v0x56148bee3590_0; + %flag_set/vec4 8; + %jmp/0xz T_29.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x56148bee3630_0, 0; + %jmp T_29.1; +T_29.0 ; + %load/vec4 v0x56148bee3630_0; + %parti/s 1, 0, 2; + %load/vec4 v0x56148bee33e0_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x56148bee3630_0, 0; +T_29.1 ; + %jmp T_29; + .thread T_29; + .scope S_0x56148bee37a0; +T_30 ; + %wait E_0x56148bd7f550; + %load/vec4 v0x56148bee3f00_0; + %flag_set/vec4 8; + %jmp/0xz T_30.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x56148bee3fa0_0, 0; + %jmp T_30.1; +T_30.0 ; + %load/vec4 v0x56148bee3fa0_0; + %parti/s 1, 0, 2; + %load/vec4 v0x56148bee3d30_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x56148bee3fa0_0, 0; +T_30.1 ; + %jmp T_30; + .thread T_30; + .scope S_0x56148bee4100; +T_31 ; + %wait E_0x56148bd7f550; + %load/vec4 v0x56148bee4840_0; + %flag_set/vec4 8; + %jmp/0xz T_31.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x56148bee48e0_0, 0; + %jmp T_31.1; +T_31.0 ; + %load/vec4 v0x56148bee48e0_0; + %parti/s 1, 0, 2; + %load/vec4 v0x56148bee4690_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x56148bee48e0_0, 0; +T_31.1 ; + %jmp T_31; + .thread T_31; + .scope S_0x56148bee4a50; +T_32 ; + %wait E_0x56148bd7f550; + %load/vec4 v0x56148bee51b0_0; + %flag_set/vec4 8; + %jmp/0xz T_32.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x56148bee5250_0, 0; + %jmp T_32.1; +T_32.0 ; + %load/vec4 v0x56148bee5250_0; + %parti/s 1, 0, 2; + %load/vec4 v0x56148bee4fe0_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x56148bee5250_0, 0; +T_32.1 ; + %jmp T_32; + .thread T_32; + .scope S_0x56148bee53b0; +T_33 ; + %wait E_0x56148bd7f550; + %load/vec4 v0x56148bee5b10_0; + %flag_set/vec4 8; + %jmp/0xz T_33.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x56148bee5bb0_0, 0; + %jmp T_33.1; +T_33.0 ; + %load/vec4 v0x56148bee5bb0_0; + %parti/s 1, 0, 2; + %load/vec4 v0x56148bee5940_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x56148bee5bb0_0, 0; +T_33.1 ; + %jmp T_33; + .thread T_33; + .scope S_0x56148bee5d10; +T_34 ; + %wait E_0x56148bd7f550; + %load/vec4 v0x56148bee6470_0; + %flag_set/vec4 8; + %jmp/0xz T_34.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x56148bee6510_0, 0; + %jmp T_34.1; +T_34.0 ; + %load/vec4 v0x56148bee6510_0; + %parti/s 1, 0, 2; + %load/vec4 v0x56148bee62a0_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x56148bee6510_0, 0; +T_34.1 ; + %jmp T_34; + .thread T_34; + .scope S_0x56148bee6670; +T_35 ; + %wait E_0x56148bd7f550; + %load/vec4 v0x56148bee6dd0_0; + %flag_set/vec4 8; + %jmp/0xz T_35.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x56148bee6e70_0, 0; + %jmp T_35.1; +T_35.0 ; + %load/vec4 v0x56148bee6e70_0; + %parti/s 1, 0, 2; + %load/vec4 v0x56148bee6c00_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x56148bee6e70_0, 0; +T_35.1 ; + %jmp T_35; + .thread T_35; + .scope S_0x56148bedc9b0; +T_36 ; + %wait E_0x56148bd7f550; + %load/vec4 v0x56148bedce40_0; + %flag_set/vec4 8; + %jmp/0xz T_36.0, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x56148bedcd70_0, 0; + %jmp T_36.1; +T_36.0 ; + %load/vec4 v0x56148bedccb0_0; + %assign/vec4 v0x56148bedcd70_0, 0; +T_36.1 ; + %jmp T_36; + .thread T_36; + .scope S_0x56148bedcf90; +T_37 ; + %wait E_0x56148bd7f550; + %load/vec4 v0x56148bedd450_0; + %flag_set/vec4 8; + %jmp/0xz T_37.0, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x56148bedd380_0, 0; + %jmp T_37.1; +T_37.0 ; + %load/vec4 v0x56148bedd290_0; + %assign/vec4 v0x56148bedd380_0, 0; +T_37.1 ; + %jmp T_37; + .thread T_37; + .scope S_0x56148bedf7f0; +T_38 ; + %wait E_0x56148bd7f550; + %load/vec4 v0x56148bedfc60_0; + %flag_set/vec4 8; + %jmp/0xz T_38.0, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x56148bedfb60_0, 0; + %jmp T_38.1; +T_38.0 ; + %load/vec4 v0x56148bedfaa0_0; + %assign/vec4 v0x56148bedfb60_0, 0; +T_38.1 ; + %jmp T_38; + .thread T_38; + .scope S_0x56148bedfd70; +T_39 ; + %wait E_0x56148bd7f550; + %load/vec4 v0x56148bee0230_0; + %flag_set/vec4 8; + %jmp/0xz T_39.0, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x56148bee0160_0, 0; + %jmp T_39.1; +T_39.0 ; + %load/vec4 v0x56148bee0070_0; + %assign/vec4 v0x56148bee0160_0, 0; +T_39.1 ; + %jmp T_39; + .thread T_39; + .scope S_0x56148bee0340; +T_40 ; + %wait E_0x56148bd7f550; + %load/vec4 v0x56148bee07d0_0; + %flag_set/vec4 8; + %jmp/0xz T_40.0, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x56148bee0700_0, 0; + %jmp T_40.1; +T_40.0 ; + %load/vec4 v0x56148bee0640_0; + %assign/vec4 v0x56148bee0700_0, 0; +T_40.1 ; + %jmp T_40; + .thread T_40; + .scope S_0x56148bee0920; +T_41 ; + %wait E_0x56148bd7f550; + %load/vec4 v0x56148bee0db0_0; + %flag_set/vec4 8; + %jmp/0xz T_41.0, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x56148bee0ce0_0, 0; + %jmp T_41.1; +T_41.0 ; + %load/vec4 v0x56148bee0c20_0; + %assign/vec4 v0x56148bee0ce0_0, 0; +T_41.1 ; + %jmp T_41; + .thread T_41; + .scope S_0x56148bee0f00; +T_42 ; + %wait E_0x56148bd7f550; + %load/vec4 v0x56148bee1410_0; + %flag_set/vec4 8; + %jmp/0xz T_42.0, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x56148bee12f0_0, 0; + %jmp T_42.1; +T_42.0 ; + %load/vec4 v0x56148bee1200_0; + %assign/vec4 v0x56148bee12f0_0, 0; +T_42.1 ; + %jmp T_42; + .thread T_42; + .scope S_0x56148bee14d0; +T_43 ; + %wait E_0x56148bd7f550; + %load/vec4 v0x56148bee1df0_0; + %flag_set/vec4 8; + %jmp/0xz T_43.0, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x56148bee1cd0_0, 0; + %jmp T_43.1; +T_43.0 ; + %load/vec4 v0x56148bee1be0_0; + %assign/vec4 v0x56148bee1cd0_0, 0; +T_43.1 ; + %jmp T_43; + .thread T_43; + .scope S_0x56148bee1eb0; +T_44 ; + %wait E_0x56148bd7f550; + %load/vec4 v0x56148bee23a0_0; + %flag_set/vec4 8; + %jmp/0xz T_44.0, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x56148bee22a0_0, 0; + %jmp T_44.1; +T_44.0 ; + %load/vec4 v0x56148bee21b0_0; + %assign/vec4 v0x56148bee22a0_0, 0; +T_44.1 ; + %jmp T_44; + .thread T_44; + .scope S_0x56148bee2880; +T_45 ; + %wait E_0x56148bd7f550; + %load/vec4 v0x56148bee2d40_0; + %flag_set/vec4 8; + %jmp/0xz T_45.0, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x56148bee2c70_0, 0; + %jmp T_45.1; +T_45.0 ; + %load/vec4 v0x56148bee2b80_0; + %assign/vec4 v0x56148bee2c70_0, 0; +T_45.1 ; + %jmp T_45; + .thread T_45; + .scope S_0x56148bedd560; +T_46 ; + %wait E_0x56148bd7f550; + %load/vec4 v0x56148bedda20_0; + %flag_set/vec4 8; + %jmp/0xz T_46.0, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x56148bedd920_0, 0; + %jmp T_46.1; +T_46.0 ; + %load/vec4 v0x56148bedd860_0; + %assign/vec4 v0x56148bedd920_0, 0; +T_46.1 ; + %jmp T_46; + .thread T_46; + .scope S_0x56148beddb30; +T_47 ; + %wait E_0x56148bd7f550; + %load/vec4 v0x56148bede020_0; + %flag_set/vec4 8; + %jmp/0xz T_47.0, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x56148beddf20_0, 0; + %jmp T_47.1; +T_47.0 ; + %load/vec4 v0x56148bedde30_0; + %assign/vec4 v0x56148beddf20_0, 0; +T_47.1 ; + %jmp T_47; + .thread T_47; + .scope S_0x56148bede0f0; +T_48 ; + %wait E_0x56148bd7f550; + %load/vec4 v0x56148bede5e0_0; + %flag_set/vec4 8; + %jmp/0xz T_48.0, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x56148bede4e0_0, 0; + %jmp T_48.1; +T_48.0 ; + %load/vec4 v0x56148bede3f0_0; + %assign/vec4 v0x56148bede4e0_0, 0; +T_48.1 ; + %jmp T_48; + .thread T_48; + .scope S_0x56148bede6b0; +T_49 ; + %wait E_0x56148bd7f550; + %load/vec4 v0x56148bedeba0_0; + %flag_set/vec4 8; + %jmp/0xz T_49.0, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x56148bedeaa0_0, 0; + %jmp T_49.1; +T_49.0 ; + %load/vec4 v0x56148bede9b0_0; + %assign/vec4 v0x56148bedeaa0_0, 0; +T_49.1 ; + %jmp T_49; + .thread T_49; + .scope S_0x56148bedec70; +T_50 ; + %wait E_0x56148bd7f550; + %load/vec4 v0x56148bedf160_0; + %flag_set/vec4 8; + %jmp/0xz T_50.0, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x56148bedf060_0, 0; + %jmp T_50.1; +T_50.0 ; + %load/vec4 v0x56148bedef70_0; + %assign/vec4 v0x56148bedf060_0, 0; +T_50.1 ; + %jmp T_50; + .thread T_50; + .scope S_0x56148bedf230; +T_51 ; + %wait E_0x56148bd7f550; + %load/vec4 v0x56148bedf6c0_0; + %flag_set/vec4 8; + %jmp/0xz T_51.0, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x56148bedf5f0_0, 0; + %jmp T_51.1; +T_51.0 ; + %load/vec4 v0x56148bedf530_0; + %assign/vec4 v0x56148bedf5f0_0, 0; +T_51.1 ; + %jmp T_51; + .thread T_51; + .scope S_0x56148bd7f380; +T_52 ; + %wait E_0x56148bd7f550; + %load/vec4 v0x56148bd09d80_0; + %flag_set/vec4 8; + %jmp/0xz T_52.0, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x56148bcb83f0_0, 0; + %jmp T_52.1; +T_52.0 ; + %load/vec4 v0x56148bcb83f0_0; + %cmpi/ne 0, 0, 3; + %jmp/0xz T_52.2, 4; + %load/vec4 v0x56148bcb83f0_0; + %addi 1, 0, 3; + %assign/vec4 v0x56148bcb83f0_0, 0; +T_52.2 ; + %load/vec4 v0x56148bcb8240_0; + %flag_set/vec4 8; + %jmp/0xz T_52.4, 8; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x56148bcb83f0_0, 0; +T_52.4 ; +T_52.1 ; + %jmp T_52; + .thread T_52; + .scope S_0x56148bd09ec0; +T_53 ; + %wait E_0x56148bd7f550; + %load/vec4 v0x56148bed1ec0_0; + %flag_set/vec4 8; + %jmp/0xz T_53.0, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x56148bed1de0_0, 0; + %jmp T_53.1; +T_53.0 ; + %load/vec4 v0x56148bed1de0_0; + %cmpi/ne 0, 0, 3; + %jmp/0xz T_53.2, 4; + %load/vec4 v0x56148bed1de0_0; + %addi 1, 0, 3; + %assign/vec4 v0x56148bed1de0_0, 0; +T_53.2 ; + %load/vec4 v0x56148bed1c10_0; + %flag_set/vec4 8; + %jmp/0xz T_53.4, 8; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x56148bed1de0_0, 0; +T_53.4 ; +T_53.1 ; + %jmp T_53; + .thread T_53; + .scope S_0x56148bed1fc0; +T_54 ; + %wait E_0x56148bd7f550; + %load/vec4 v0x56148bed3530_0; + %flag_set/vec4 8; + %jmp/0xz T_54.0, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x56148bed3450_0, 0; + %jmp T_54.1; +T_54.0 ; + %load/vec4 v0x56148bed3450_0; + %cmpi/ne 0, 0, 3; + %jmp/0xz T_54.2, 4; + %load/vec4 v0x56148bed3450_0; + %addi 1, 0, 3; + %assign/vec4 v0x56148bed3450_0, 0; +T_54.2 ; + %load/vec4 v0x56148bed32d0_0; + %flag_set/vec4 8; + %jmp/0xz T_54.4, 8; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x56148bed3450_0, 0; +T_54.4 ; +T_54.1 ; + %jmp T_54; + .thread T_54; + .scope S_0x56148bed3650; +T_55 ; + %wait E_0x56148bd7f550; + %load/vec4 v0x56148bed3e30_0; + %flag_set/vec4 8; + %jmp/0xz T_55.0, 8; + %pushi/vec4 0, 0, 4; + %assign/vec4 v0x56148bed3d50_0, 0; + %jmp T_55.1; +T_55.0 ; + %load/vec4 v0x56148bed3d50_0; + %cmpi/ne 0, 0, 4; + %jmp/0xz T_55.2, 4; + %load/vec4 v0x56148bed3d50_0; + %addi 1, 0, 4; + %assign/vec4 v0x56148bed3d50_0, 0; +T_55.2 ; + %load/vec4 v0x56148bed3bd0_0; + %flag_set/vec4 8; + %jmp/0xz T_55.4, 8; + %pushi/vec4 1, 0, 4; + %assign/vec4 v0x56148bed3d50_0, 0; +T_55.4 ; +T_55.1 ; + %jmp T_55; + .thread T_55; + .scope S_0x56148bed3f50; +T_56 ; + %wait E_0x56148bd7f550; + %load/vec4 v0x56148bed47d0_0; + %flag_set/vec4 8; + %jmp/0xz T_56.0, 8; + %pushi/vec4 0, 0, 4; + %assign/vec4 v0x56148bed46f0_0, 0; + %jmp T_56.1; +T_56.0 ; + %load/vec4 v0x56148bed46f0_0; + %cmpi/ne 0, 0, 4; + %jmp/0xz T_56.2, 4; + %load/vec4 v0x56148bed46f0_0; + %addi 1, 0, 4; + %assign/vec4 v0x56148bed46f0_0, 0; +T_56.2 ; + %load/vec4 v0x56148bed4520_0; + %flag_set/vec4 8; + %jmp/0xz T_56.4, 8; + %pushi/vec4 1, 0, 4; + %assign/vec4 v0x56148bed46f0_0, 0; +T_56.4 ; +T_56.1 ; + %jmp T_56; + .thread T_56; + .scope S_0x56148bed79b0; +T_57 ; + %wait E_0x56148bd7f550; + %load/vec4 v0x56148bed8210_0; + %flag_set/vec4 8; + %jmp/0xz T_57.0, 8; + %pushi/vec4 0, 0, 5; + %assign/vec4 v0x56148bed8130_0, 0; + %jmp T_57.1; +T_57.0 ; + %load/vec4 v0x56148bed8130_0; + %cmpi/ne 0, 0, 5; + %jmp/0xz T_57.2, 4; + %load/vec4 v0x56148bed8130_0; + %addi 1, 0, 5; + %assign/vec4 v0x56148bed8130_0, 0; +T_57.2 ; + %load/vec4 v0x56148bed7f60_0; + %flag_set/vec4 8; + %jmp/0xz T_57.4, 8; + %pushi/vec4 1, 0, 5; + %assign/vec4 v0x56148bed8130_0, 0; +T_57.4 ; +T_57.1 ; + %jmp T_57; + .thread T_57; + .scope S_0x56148bed8330; +T_58 ; + %wait E_0x56148bd7f550; + %load/vec4 v0x56148bed8b50_0; + %flag_set/vec4 8; + %jmp/0xz T_58.0, 8; + %pushi/vec4 0, 0, 7; + %assign/vec4 v0x56148bed8a70_0, 0; + %jmp T_58.1; +T_58.0 ; + %load/vec4 v0x56148bed8a70_0; + %cmpi/ne 0, 0, 7; + %jmp/0xz T_58.2, 4; + %load/vec4 v0x56148bed8a70_0; + %addi 1, 0, 7; + %assign/vec4 v0x56148bed8a70_0, 0; +T_58.2 ; + %load/vec4 v0x56148bed88e0_0; + %flag_set/vec4 8; + %jmp/0xz T_58.4, 8; + %pushi/vec4 1, 0, 7; + %assign/vec4 v0x56148bed8a70_0, 0; +T_58.4 ; +T_58.1 ; + %jmp T_58; + .thread T_58; + .scope S_0x56148bed8ca0; +T_59 ; + %wait E_0x56148bd7f550; + %load/vec4 v0x56148bed94c0_0; + %flag_set/vec4 8; + %jmp/0xz T_59.0, 8; + %pushi/vec4 0, 0, 7; + %assign/vec4 v0x56148bed93e0_0, 0; + %jmp T_59.1; +T_59.0 ; + %load/vec4 v0x56148bed93e0_0; + %cmpi/ne 0, 0, 7; + %jmp/0xz T_59.2, 4; + %load/vec4 v0x56148bed93e0_0; + %addi 1, 0, 7; + %assign/vec4 v0x56148bed93e0_0, 0; +T_59.2 ; + %load/vec4 v0x56148bed9250_0; + %flag_set/vec4 8; + %jmp/0xz T_59.4, 8; + %pushi/vec4 1, 0, 7; + %assign/vec4 v0x56148bed93e0_0, 0; +T_59.4 ; +T_59.1 ; + %jmp T_59; + .thread T_59; + .scope S_0x56148bed9610; +T_60 ; + %wait E_0x56148bd7f550; + %load/vec4 v0x56148bed9e70_0; + %flag_set/vec4 8; + %jmp/0xz T_60.0, 8; + %pushi/vec4 0, 0, 5; + %assign/vec4 v0x56148bed9d90_0, 0; + %jmp T_60.1; +T_60.0 ; + %load/vec4 v0x56148bed9d90_0; + %cmpi/ne 0, 0, 5; + %jmp/0xz T_60.2, 4; + %load/vec4 v0x56148bed9d90_0; + %addi 1, 0, 5; + %assign/vec4 v0x56148bed9d90_0, 0; +T_60.2 ; + %load/vec4 v0x56148bed9bc0_0; + %flag_set/vec4 8; + %jmp/0xz T_60.4, 8; + %pushi/vec4 1, 0, 5; + %assign/vec4 v0x56148bed9d90_0, 0; +T_60.4 ; +T_60.1 ; + %jmp T_60; + .thread T_60; + .scope S_0x56148bed9f90; +T_61 ; + %wait E_0x56148bd7f550; + %load/vec4 v0x56148beda7f0_0; + %flag_set/vec4 8; + %jmp/0xz T_61.0, 8; + %pushi/vec4 0, 0, 5; + %assign/vec4 v0x56148beda710_0, 0; + %jmp T_61.1; +T_61.0 ; + %load/vec4 v0x56148beda710_0; + %cmpi/ne 0, 0, 5; + %jmp/0xz T_61.2, 4; + %load/vec4 v0x56148beda710_0; + %addi 1, 0, 5; + %assign/vec4 v0x56148beda710_0, 0; +T_61.2 ; + %load/vec4 v0x56148beda540_0; + %flag_set/vec4 8; + %jmp/0xz T_61.4, 8; + %pushi/vec4 1, 0, 5; + %assign/vec4 v0x56148beda710_0, 0; +T_61.4 ; +T_61.1 ; + %jmp T_61; + .thread T_61; + .scope S_0x56148beda910; +T_62 ; + %wait E_0x56148bd7f550; + %load/vec4 v0x56148bedb380_0; + %flag_set/vec4 8; + %jmp/0xz T_62.0, 8; + %pushi/vec4 0, 0, 5; + %assign/vec4 v0x56148bedb2a0_0, 0; + %jmp T_62.1; +T_62.0 ; + %load/vec4 v0x56148bedb2a0_0; + %cmpi/ne 0, 0, 5; + %jmp/0xz T_62.2, 4; + %load/vec4 v0x56148bedb2a0_0; + %addi 1, 0, 5; + %assign/vec4 v0x56148bedb2a0_0, 0; +T_62.2 ; + %load/vec4 v0x56148bedb0d0_0; + %flag_set/vec4 8; + %jmp/0xz T_62.4, 8; + %pushi/vec4 1, 0, 5; + %assign/vec4 v0x56148bedb2a0_0, 0; +T_62.4 ; +T_62.1 ; + %jmp T_62; + .thread T_62; + .scope S_0x56148bedb4a0; +T_63 ; + %wait E_0x56148bd7f550; + %load/vec4 v0x56148bedbd00_0; + %flag_set/vec4 8; + %jmp/0xz T_63.0, 8; + %pushi/vec4 0, 0, 7; + %assign/vec4 v0x56148bedbc20_0, 0; + %jmp T_63.1; +T_63.0 ; + %load/vec4 v0x56148bedbc20_0; + %cmpi/ne 0, 0, 7; + %jmp/0xz T_63.2, 4; + %load/vec4 v0x56148bedbc20_0; + %addi 1, 0, 7; + %assign/vec4 v0x56148bedbc20_0, 0; +T_63.2 ; + %load/vec4 v0x56148bedba50_0; + %flag_set/vec4 8; + %jmp/0xz T_63.4, 8; + %pushi/vec4 1, 0, 7; + %assign/vec4 v0x56148bedbc20_0, 0; +T_63.4 ; +T_63.1 ; + %jmp T_63; + .thread T_63; + .scope S_0x56148bedc030; +T_64 ; + %wait E_0x56148bd7f550; + %load/vec4 v0x56148bedc890_0; + %flag_set/vec4 8; + %jmp/0xz T_64.0, 8; + %pushi/vec4 0, 0, 6; + %assign/vec4 v0x56148bedc7b0_0, 0; + %jmp T_64.1; +T_64.0 ; + %load/vec4 v0x56148bedc7b0_0; + %cmpi/ne 0, 0, 6; + %jmp/0xz T_64.2, 4; + %load/vec4 v0x56148bedc7b0_0; + %addi 1, 0, 6; + %assign/vec4 v0x56148bedc7b0_0, 0; +T_64.2 ; + %load/vec4 v0x56148bedc5e0_0; + %flag_set/vec4 8; + %jmp/0xz T_64.4, 8; + %pushi/vec4 1, 0, 6; + %assign/vec4 v0x56148bedc7b0_0, 0; +T_64.4 ; +T_64.1 ; + %jmp T_64; + .thread T_64; + .scope S_0x56148bed48f0; +T_65 ; + %wait E_0x56148bd7f550; + %load/vec4 v0x56148bed5100_0; + %flag_set/vec4 8; + %jmp/0xz T_65.0, 8; + %pushi/vec4 0, 0, 5; + %assign/vec4 v0x56148bed5020_0, 0; + %jmp T_65.1; +T_65.0 ; + %load/vec4 v0x56148bed5020_0; + %cmpi/ne 0, 0, 5; + %jmp/0xz T_65.2, 4; + %load/vec4 v0x56148bed5020_0; + %addi 1, 0, 5; + %assign/vec4 v0x56148bed5020_0, 0; +T_65.2 ; + %load/vec4 v0x56148bed4e50_0; + %flag_set/vec4 8; + %jmp/0xz T_65.4, 8; + %pushi/vec4 1, 0, 5; + %assign/vec4 v0x56148bed5020_0, 0; +T_65.4 ; +T_65.1 ; + %jmp T_65; + .thread T_65; + .scope S_0x56148bed5220; +T_66 ; + %wait E_0x56148bd7f550; + %load/vec4 v0x56148bed5a80_0; + %flag_set/vec4 8; + %jmp/0xz T_66.0, 8; + %pushi/vec4 0, 0, 7; + %assign/vec4 v0x56148bed59a0_0, 0; + %jmp T_66.1; +T_66.0 ; + %load/vec4 v0x56148bed59a0_0; + %cmpi/ne 0, 0, 7; + %jmp/0xz T_66.2, 4; + %load/vec4 v0x56148bed59a0_0; + %addi 1, 0, 7; + %assign/vec4 v0x56148bed59a0_0, 0; +T_66.2 ; + %load/vec4 v0x56148bed57d0_0; + %flag_set/vec4 8; + %jmp/0xz T_66.4, 8; + %pushi/vec4 1, 0, 7; + %assign/vec4 v0x56148bed59a0_0, 0; +T_66.4 ; +T_66.1 ; + %jmp T_66; + .thread T_66; + .scope S_0x56148bed5ba0; +T_67 ; + %wait E_0x56148bd7f550; + %load/vec4 v0x56148bed64c0_0; + %flag_set/vec4 8; + %jmp/0xz T_67.0, 8; + %pushi/vec4 0, 0, 4; + %assign/vec4 v0x56148bed6420_0, 0; + %jmp T_67.1; +T_67.0 ; + %load/vec4 v0x56148bed6420_0; + %cmpi/ne 0, 0, 4; + %jmp/0xz T_67.2, 4; + %load/vec4 v0x56148bed6420_0; + %addi 1, 0, 4; + %assign/vec4 v0x56148bed6420_0, 0; +T_67.2 ; + %load/vec4 v0x56148bed6260_0; + %flag_set/vec4 8; + %jmp/0xz T_67.4, 8; + %pushi/vec4 1, 0, 4; + %assign/vec4 v0x56148bed6420_0, 0; +T_67.4 ; +T_67.1 ; + %jmp T_67; + .thread T_67; + .scope S_0x56148bed6610; +T_68 ; + %wait E_0x56148bd7f550; + %load/vec4 v0x56148bed6e50_0; + %flag_set/vec4 8; + %jmp/0xz T_68.0, 8; + %pushi/vec4 0, 0, 5; + %assign/vec4 v0x56148bed6d70_0, 0; + %jmp T_68.1; +T_68.0 ; + %load/vec4 v0x56148bed6d70_0; + %cmpi/ne 0, 0, 5; + %jmp/0xz T_68.2, 4; + %load/vec4 v0x56148bed6d70_0; + %addi 1, 0, 5; + %assign/vec4 v0x56148bed6d70_0, 0; +T_68.2 ; + %load/vec4 v0x56148bed6bc0_0; + %flag_set/vec4 8; + %jmp/0xz T_68.4, 8; + %pushi/vec4 1, 0, 5; + %assign/vec4 v0x56148bed6d70_0, 0; +T_68.4 ; +T_68.1 ; + %jmp T_68; + .thread T_68; + .scope S_0x56148bed7080; +T_69 ; + %wait E_0x56148bd7f550; + %load/vec4 v0x56148bed7890_0; + %flag_set/vec4 8; + %jmp/0xz T_69.0, 8; + %pushi/vec4 0, 0, 5; + %assign/vec4 v0x56148bed77b0_0, 0; + %jmp T_69.1; +T_69.0 ; + %load/vec4 v0x56148bed77b0_0; + %cmpi/ne 0, 0, 5; + %jmp/0xz T_69.2, 4; + %load/vec4 v0x56148bed77b0_0; + %addi 1, 0, 5; + %assign/vec4 v0x56148bed77b0_0, 0; +T_69.2 ; + %load/vec4 v0x56148bed7600_0; + %flag_set/vec4 8; + %jmp/0xz T_69.4, 8; + %pushi/vec4 1, 0, 5; + %assign/vec4 v0x56148bed77b0_0, 0; +T_69.4 ; +T_69.1 ; + %jmp T_69; + .thread T_69; + .scope S_0x56148bd810e0; +T_70 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x56148beea1a0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x56148beeac30_0, 0, 1; + %end; + .thread T_70; + .scope S_0x56148bd810e0; +T_71 ; + %wait E_0x56148bd7f550; + %load/vec4 v0x56148bef0390_0; + %flag_set/vec4 8; + %jmp/0xz T_71.0, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x56148beea1a0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x56148beea480_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x56148beeac30_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x56148beed040_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x56148beed0e0_0, 0; + %pushi/vec4 0, 0, 36; + %assign/vec4 v0x56148bef0430_0, 0; + %jmp T_71.1; +T_71.0 ; + %load/vec4 v0x56148beed040_0; + %flag_set/vec4 8; + %jmp/0xz T_71.2, 8; + %load/vec4 v0x56148beecfa0_0; + %pad/u 16; + %ix/vec4 4; + %load/vec4a v0x56148beecf00, 4; + %assign/vec4 v0x56148bef0430_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x56148beed040_0, 0; + %jmp T_71.3; +T_71.2 ; + %load/vec4 v0x56148beed0e0_0; + %flag_set/vec4 8; + %jmp/0xz T_71.4, 8; + %load/vec4 v0x56148beea020_0; + %load/vec4 v0x56148beecfa0_0; + %pad/u 16; + %ix/vec4 3; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x56148beecf00, 0, 4; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x56148beed0e0_0, 0; +T_71.4 ; +T_71.3 ; + %load/vec4 v0x56148beeb1e0_0; + %flag_set/vec4 8; + %jmp/0xz T_71.6, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x56148beea520_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x56148beea5e0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x56148beeaab0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x56148beeab70_0, 0; +T_71.6 ; + %load/vec4 v0x56148beea240_0; + %flag_set/vec4 8; + %jmp/0xz T_71.8, 8; + %pushi/vec4 0, 0, 36; + %assign/vec4 v0x56148beea020_0, 0; +T_71.8 ; + %load/vec4 v0x56148beeb350_0; + %flag_set/vec4 8; + %jmp/0xz T_71.10, 8; + %load/vec4 v0x56148beea020_0; + %load/vec4 v0x56148bef0430_0; + %or; + %assign/vec4 v0x56148beea020_0, 0; +T_71.10 ; + %load/vec4 v0x56148beed700_0; + %flag_set/vec4 8; + %jmp/0xz T_71.12, 8; + %load/vec4 v0x56148beea020_0; + %load/vec4 v0x56148beed540_0; + %or; + %assign/vec4 v0x56148beea020_0, 0; +T_71.12 ; + %load/vec4 v0x56148beece60_0; + %flag_set/vec4 8; + %jmp/0xz T_71.14, 8; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x56148beeac30_0, 0; +T_71.14 ; + %load/vec4 v0x56148beeb650_0; + %flag_set/vec4 8; + %jmp/0xz T_71.16, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x56148beea1a0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x56148beeac30_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x56148beeadd0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x56148beeb2b0_0, 0; + %pushi/vec4 0, 0, 14; + %assign/vec4 v0x56148bee9dc0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x56148bee9ea0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x56148bee9f60_0, 0; + %load/vec4 v0x56148beecbe0_0; + %flag_set/vec4 8; + %jmp/0xz T_71.18, 8; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x56148beea520_0, 0; + %jmp T_71.19; +T_71.18 ; + %load/vec4 v0x56148beecc80_0; + %flag_set/vec4 8; + %jmp/0xz T_71.20, 8; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x56148beea5e0_0, 0; + %jmp T_71.21; +T_71.20 ; + %load/vec4 v0x56148beecd20_0; + %flag_set/vec4 8; + %jmp/0xz T_71.22, 8; + %load/vec4 v0x56148beecdc0_0; + %inv; + %load/vec4 v0x56148beea480_0; + %or; + %flag_set/vec4 8; + %jmp/0xz T_71.24, 8; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x56148beeaab0_0, 0; +T_71.24 ; + %jmp T_71.23; +T_71.22 ; + %load/vec4 v0x56148beecdc0_0; + %flag_set/vec4 8; + %jmp/0xz T_71.26, 8; + %load/vec4 v0x56148beecd20_0; + %inv; + %load/vec4 v0x56148beea480_0; + %inv; + %or; + %flag_set/vec4 8; + %jmp/0xz T_71.28, 8; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x56148beeab70_0, 0; +T_71.28 ; +T_71.26 ; +T_71.23 ; +T_71.21 ; +T_71.19 ; +T_71.16 ; + %load/vec4 v0x56148beeb830_0; + %flag_set/vec4 8; + %jmp/0xz T_71.30, 8; + %load/vec4 v0x56148bee9dc0_0; + %load/vec4 v0x56148beed460_0; + %parti/s 14, 0, 2; + %or; + %assign/vec4 v0x56148bee9dc0_0, 0; + %load/vec4 v0x56148bef02f0_0; + %flag_set/vec4 8; + %jmp/0xz T_71.32, 8; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x56148bee9ea0_0, 0; +T_71.32 ; + %load/vec4 v0x56148bef0690_0; + %flag_set/vec4 8; + %jmp/0xz T_71.34, 8; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x56148bee9f60_0, 0; +T_71.34 ; +T_71.30 ; + %load/vec4 v0x56148beebce0_0; + %flag_set/vec4 8; + %jmp/0xz T_71.36, 8; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x56148beeb0a0_0, 0; + %load/vec4 v0x56148beeaab0_0; + %flag_set/vec4 8; + %jmp/0xz T_71.38, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x56148beea480_0, 0; +T_71.38 ; + %load/vec4 v0x56148beeab70_0; + %flag_set/vec4 8; + %jmp/0xz T_71.40, 8; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x56148beea480_0, 0; +T_71.40 ; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x56148beed040_0, 0; + %pushi/vec4 0, 0, 36; + %assign/vec4 v0x56148bef0430_0, 0; +T_71.36 ; + %load/vec4 v0x56148beec0f0_0; + %flag_set/vec4 8; + %jmp/0xz T_71.42, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x56148beeb0a0_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x56148beeadd0_0, 0; +T_71.42 ; + %load/vec4 v0x56148beec370_0; + %flag_set/vec4 8; + %jmp/0xz T_71.44, 8; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x56148beea310_0, 0; + %load/vec4 v0x56148bef05d0_0; + %flag_set/vec4 8; + %jmp/0xz T_71.46, 8; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x56148beeb2b0_0, 0; +T_71.46 ; +T_71.44 ; + %load/vec4 v0x56148beec550_0; + %flag_set/vec4 8; + %jmp/0xz T_71.48, 8; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x56148beecaa0_0, 0; +T_71.48 ; + %load/vec4 v0x56148beec730_0; + %load/vec4 v0x56148beecaa0_0; + %and; + %flag_set/vec4 8; + %jmp/0xz T_71.50, 8; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x56148beed0e0_0, 0; +T_71.50 ; + %load/vec4 v0x56148beebab0_0; + %flag_set/vec4 8; + %jmp/0xz T_71.52, 8; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x56148beea1a0_0, 0; +T_71.52 ; + %load/vec4 v0x56148beebb50_0; + %flag_set/vec4 8; + %jmp/0xz T_71.54, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x56148beeb0a0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x56148beea310_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x56148beecaa0_0, 0; +T_71.54 ; +T_71.1 ; + %jmp T_71; + .thread T_71; + .scope S_0x56148bef9de0; +T_72 ; + %wait E_0x56148bef1b00; + %load/vec4 v0x56148befa540_0; + %flag_set/vec4 8; + %jmp/0xz T_72.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x56148befa5e0_0, 0; + %jmp T_72.1; +T_72.0 ; + %load/vec4 v0x56148befa5e0_0; + %parti/s 1, 0, 2; + %load/vec4 v0x56148befa370_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x56148befa5e0_0, 0; +T_72.1 ; + %jmp T_72; + .thread T_72; + .scope S_0x56148befa740; +T_73 ; + %wait E_0x56148bef1b00; + %load/vec4 v0x56148befafb0_0; + %flag_set/vec4 8; + %jmp/0xz T_73.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x56148befb260_0, 0; + %jmp T_73.1; +T_73.0 ; + %load/vec4 v0x56148befb260_0; + %parti/s 1, 0, 2; + %load/vec4 v0x56148befade0_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x56148befb260_0, 0; +T_73.1 ; + %jmp T_73; + .thread T_73; + .scope S_0x56148befb3c0; +T_74 ; + %wait E_0x56148bef1b00; + %load/vec4 v0x56148befbb00_0; + %flag_set/vec4 8; + %jmp/0xz T_74.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x56148befbba0_0, 0; + %jmp T_74.1; +T_74.0 ; + %load/vec4 v0x56148befbba0_0; + %parti/s 1, 0, 2; + %load/vec4 v0x56148befb950_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x56148befbba0_0, 0; +T_74.1 ; + %jmp T_74; + .thread T_74; + .scope S_0x56148befbd10; +T_75 ; + %wait E_0x56148bef1b00; + %load/vec4 v0x56148befc450_0; + %flag_set/vec4 8; + %jmp/0xz T_75.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x56148befc4f0_0, 0; + %jmp T_75.1; +T_75.0 ; + %load/vec4 v0x56148befc4f0_0; + %parti/s 1, 0, 2; + %load/vec4 v0x56148befc2a0_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x56148befc4f0_0, 0; +T_75.1 ; + %jmp T_75; + .thread T_75; + .scope S_0x56148bef1870; +T_76 ; + %wait E_0x56148bef1b00; + %load/vec4 v0x56148bef20a0_0; + %flag_set/vec4 8; + %jmp/0xz T_76.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x56148bef2160_0, 0; + %jmp T_76.1; +T_76.0 ; + %load/vec4 v0x56148bef2160_0; + %parti/s 1, 0, 2; + %load/vec4 v0x56148bef1ed0_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x56148bef2160_0, 0; +T_76.1 ; + %jmp T_76; + .thread T_76; + .scope S_0x56148bef22c0; +T_77 ; + %wait E_0x56148bef1b00; + %load/vec4 v0x56148bef2a20_0; + %flag_set/vec4 8; + %jmp/0xz T_77.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x56148bef2ac0_0, 0; + %jmp T_77.1; +T_77.0 ; + %load/vec4 v0x56148bef2ac0_0; + %parti/s 1, 0, 2; + %load/vec4 v0x56148bef2850_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x56148bef2ac0_0, 0; +T_77.1 ; + %jmp T_77; + .thread T_77; + .scope S_0x56148bef7af0; +T_78 ; + %wait E_0x56148bef1b00; + %load/vec4 v0x56148bef7f80_0; + %flag_set/vec4 8; + %jmp/0xz T_78.0, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x56148bef7eb0_0, 0; + %jmp T_78.1; +T_78.0 ; + %load/vec4 v0x56148bef7df0_0; + %assign/vec4 v0x56148bef7eb0_0, 0; +T_78.1 ; + %jmp T_78; + .thread T_78; + .scope S_0x56148bef80d0; +T_79 ; + %wait E_0x56148bef1b00; + %load/vec4 v0x56148bef8560_0; + %flag_set/vec4 8; + %jmp/0xz T_79.0, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x56148bef8490_0, 0; + %jmp T_79.1; +T_79.0 ; + %load/vec4 v0x56148bef83d0_0; + %assign/vec4 v0x56148bef8490_0, 0; +T_79.1 ; + %jmp T_79; + .thread T_79; + .scope S_0x56148bef8690; +T_80 ; + %wait E_0x56148bef1b00; + %load/vec4 v0x56148bef8b50_0; + %flag_set/vec4 8; + %jmp/0xz T_80.0, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x56148bef8a80_0, 0; + %jmp T_80.1; +T_80.0 ; + %load/vec4 v0x56148bef8990_0; + %assign/vec4 v0x56148bef8a80_0, 0; +T_80.1 ; + %jmp T_80; + .thread T_80; + .scope S_0x56148bef8c60; +T_81 ; + %wait E_0x56148bef1b00; + %load/vec4 v0x56148bef9120_0; + %flag_set/vec4 8; + %jmp/0xz T_81.0, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x56148bef9050_0, 0; + %jmp T_81.1; +T_81.0 ; + %load/vec4 v0x56148bef8f60_0; + %assign/vec4 v0x56148bef9050_0, 0; +T_81.1 ; + %jmp T_81; + .thread T_81; + .scope S_0x56148bef9230; +T_82 ; + %wait E_0x56148bef1b00; + %load/vec4 v0x56148bef96f0_0; + %flag_set/vec4 8; + %jmp/0xz T_82.0, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x56148bef9620_0, 0; + %jmp T_82.1; +T_82.0 ; + %load/vec4 v0x56148bef9530_0; + %assign/vec4 v0x56148bef9620_0, 0; +T_82.1 ; + %jmp T_82; + .thread T_82; + .scope S_0x56148befc660; +T_83 ; + %wait E_0x56148bef1b00; + %load/vec4 v0x56148befcdf0_0; + %flag_set/vec4 8; + %jmp/0xz T_83.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x56148befce90_0, 0; + %jmp T_83.1; +T_83.0 ; + %load/vec4 v0x56148befce90_0; + %parti/s 1, 0, 2; + %load/vec4 v0x56148befcbf0_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x56148befce90_0, 0; +T_83.1 ; + %jmp T_83; + .thread T_83; + .scope S_0x56148bef9800; +T_84 ; + %wait E_0x56148bef1b00; + %load/vec4 v0x56148bef9c90_0; + %flag_set/vec4 8; + %jmp/0xz T_84.0, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x56148bef9bc0_0, 0; + %jmp T_84.1; +T_84.0 ; + %load/vec4 v0x56148bef9b00_0; + %assign/vec4 v0x56148bef9bc0_0, 0; +T_84.1 ; + %jmp T_84; + .thread T_84; + .scope S_0x56148bef5550; +T_85 ; + %wait E_0x56148bef1b00; + %load/vec4 v0x56148bef5d10_0; + %flag_set/vec4 8; + %jmp/0xz T_85.0, 8; + %pushi/vec4 0, 0, 5; + %assign/vec4 v0x56148bef5c30_0, 0; + %jmp T_85.1; +T_85.0 ; + %load/vec4 v0x56148bef5c30_0; + %cmpi/ne 0, 0, 5; + %jmp/0xz T_85.2, 4; + %load/vec4 v0x56148bef5c30_0; + %addi 1, 0, 5; + %assign/vec4 v0x56148bef5c30_0, 0; +T_85.2 ; + %load/vec4 v0x56148bef5ab0_0; + %flag_set/vec4 8; + %jmp/0xz T_85.4, 8; + %pushi/vec4 1, 0, 5; + %assign/vec4 v0x56148bef5c30_0, 0; +T_85.4 ; +T_85.1 ; + %jmp T_85; + .thread T_85; + .scope S_0x56148bef5e30; +T_86 ; + %wait E_0x56148bef1b00; + %load/vec4 v0x56148bef6690_0; + %flag_set/vec4 8; + %jmp/0xz T_86.0, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x56148bef65b0_0, 0; + %jmp T_86.1; +T_86.0 ; + %load/vec4 v0x56148bef65b0_0; + %cmpi/ne 0, 0, 3; + %jmp/0xz T_86.2, 4; + %load/vec4 v0x56148bef65b0_0; + %addi 1, 0, 3; + %assign/vec4 v0x56148bef65b0_0, 0; +T_86.2 ; + %load/vec4 v0x56148bef63e0_0; + %flag_set/vec4 8; + %jmp/0xz T_86.4, 8; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x56148bef65b0_0, 0; +T_86.4 ; +T_86.1 ; + %jmp T_86; + .thread T_86; + .scope S_0x56148bef67b0; +T_87 ; + %wait E_0x56148bef1b00; + %load/vec4 v0x56148bef7040_0; + %flag_set/vec4 8; + %jmp/0xz T_87.0, 8; + %pushi/vec4 0, 0, 4; + %assign/vec4 v0x56148bef6f60_0, 0; + %jmp T_87.1; +T_87.0 ; + %load/vec4 v0x56148bef6f60_0; + %cmpi/ne 0, 0, 4; + %jmp/0xz T_87.2, 4; + %load/vec4 v0x56148bef6f60_0; + %addi 1, 0, 4; + %assign/vec4 v0x56148bef6f60_0, 0; +T_87.2 ; + %load/vec4 v0x56148bef6d60_0; + %flag_set/vec4 8; + %jmp/0xz T_87.4, 8; + %pushi/vec4 1, 0, 4; + %assign/vec4 v0x56148bef6f60_0, 0; +T_87.4 ; +T_87.1 ; + %jmp T_87; + .thread T_87; + .scope S_0x56148bef7160; +T_88 ; + %wait E_0x56148bef1b00; + %load/vec4 v0x56148bef79d0_0; + %flag_set/vec4 8; + %jmp/0xz T_88.0, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x56148bef78f0_0, 0; + %jmp T_88.1; +T_88.0 ; + %load/vec4 v0x56148bef78f0_0; + %cmpi/ne 0, 0, 3; + %jmp/0xz T_88.2, 4; + %load/vec4 v0x56148bef78f0_0; + %addi 1, 0, 3; + %assign/vec4 v0x56148bef78f0_0, 0; +T_88.2 ; + %load/vec4 v0x56148bef7770_0; + %flag_set/vec4 8; + %jmp/0xz T_88.4, 8; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x56148bef78f0_0, 0; +T_88.4 ; +T_88.1 ; + %jmp T_88; + .thread T_88; + .scope S_0x56148bef2c30; +T_89 ; + %wait E_0x56148bef1b00; + %load/vec4 v0x56148bef34a0_0; + %flag_set/vec4 8; + %jmp/0xz T_89.0, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x56148bef33c0_0, 0; + %jmp T_89.1; +T_89.0 ; + %load/vec4 v0x56148bef33c0_0; + %cmpi/ne 0, 0, 3; + %jmp/0xz T_89.2, 4; + %load/vec4 v0x56148bef33c0_0; + %addi 1, 0, 3; + %assign/vec4 v0x56148bef33c0_0, 0; +T_89.2 ; + %load/vec4 v0x56148bef31f0_0; + %flag_set/vec4 8; + %jmp/0xz T_89.4, 8; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x56148bef33c0_0, 0; +T_89.4 ; +T_89.1 ; + %jmp T_89; + .thread T_89; + .scope S_0x56148bef3610; +T_90 ; + %wait E_0x56148bef1b00; + %load/vec4 v0x56148bef3e40_0; + %flag_set/vec4 8; + %jmp/0xz T_90.0, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x56148bef3d60_0, 0; + %jmp T_90.1; +T_90.0 ; + %load/vec4 v0x56148bef3d60_0; + %cmpi/ne 0, 0, 3; + %jmp/0xz T_90.2, 4; + %load/vec4 v0x56148bef3d60_0; + %addi 1, 0, 3; + %assign/vec4 v0x56148bef3d60_0, 0; +T_90.2 ; + %load/vec4 v0x56148bef3b90_0; + %flag_set/vec4 8; + %jmp/0xz T_90.4, 8; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x56148bef3d60_0, 0; +T_90.4 ; +T_90.1 ; + %jmp T_90; + .thread T_90; + .scope S_0x56148bef3f60; +T_91 ; + %wait E_0x56148bef1b00; + %load/vec4 v0x56148bef5400_0; + %flag_set/vec4 8; + %jmp/0xz T_91.0, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x56148bef5320_0, 0; + %jmp T_91.1; +T_91.0 ; + %load/vec4 v0x56148bef5320_0; + %cmpi/ne 0, 0, 3; + %jmp/0xz T_91.2, 4; + %load/vec4 v0x56148bef5320_0; + %addi 1, 0, 3; + %assign/vec4 v0x56148bef5320_0, 0; +T_91.2 ; + %load/vec4 v0x56148bef51e0_0; + %flag_set/vec4 8; + %jmp/0xz T_91.4, 8; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x56148bef5320_0, 0; +T_91.4 ; +T_91.1 ; + %jmp T_91; + .thread T_91; + .scope S_0x56148bef0df0; +T_92 ; + %wait E_0x56148bef1810; + %load/vec4 v0x56148bf01cc0_0; + %load/vec4 v0x56148bf018e0_0; + %or; + %flag_set/vec4 8; + %jmp/0xz T_92.0, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x56148bf011e0_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x56148bf01f00_0, 0; +T_92.0 ; + %load/vec4 v0x56148bf026c0_0; + %load/vec4 v0x56148bf02760_0; + %or; + %load/vec4 v0x56148bf02800_0; + %or; + %load/vec4 v0x56148bf028a0_0; + %or; + %flag_set/vec4 8; + %jmp/0xz T_92.2, 8; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x56148bf011e0_0, 0; +T_92.2 ; + %load/vec4 v0x56148bf02040_0; + %flag_set/vec4 8; + %jmp/0xz T_92.4, 8; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x56148bf01d90_0, 0; +T_92.4 ; + %load/vec4 v0x56148bf00f10_0; + %inv; + %flag_set/vec4 8; + %jmp/0xz T_92.6, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x56148bf019b0_0, 0; +T_92.6 ; + %load/vec4 v0x56148bf01a50_0; + %flag_set/vec4 8; + %jmp/0xz T_92.8, 8; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x56148bf019b0_0, 0; +T_92.8 ; + %load/vec4 v0x56148bf02110_0; + %flag_set/vec4 8; + %jmp/0xz T_92.10, 8; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x56148bf01fa0_0, 0; +T_92.10 ; + %load/vec4 v0x56148bf00cd0_0; + %flag_set/vec4 8; + %jmp/0xz T_92.12, 8; + %pushi/vec4 0, 0, 36; + %ix/getv 3, v0x56148bf00e30_0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x56148bf00c10, 0, 4; +T_92.12 ; + %load/vec4 v0x56148bf02aa0_0; + %load/vec4 v0x56148bf01fa0_0; + %and; + %flag_set/vec4 8; + %jmp/0xz T_92.14, 8; + %ix/getv 4, v0x56148bf00e30_0; + %load/vec4a v0x56148bf00c10, 4; + %load/vec4 v0x56148bf02940_0; + %or; + %ix/getv 3, v0x56148bf00e30_0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x56148bf00c10, 0, 4; +T_92.14 ; + %load/vec4 v0x56148bf021e0_0; + %flag_set/vec4 8; + %jmp/0xz T_92.16, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x56148bf01d90_0, 0; + %load/vec4 v0x56148bf057e0_0; + %assign/vec4 v0x56148bf01f00_0, 0; +T_92.16 ; + %load/vec4 v0x56148bf02550_0; + %flag_set/vec4 8; + %jmp/0xz T_92.18, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x56148bf011e0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x56148bf019b0_0, 0; +T_92.18 ; + %load/vec4 v0x56148bf025f0_0; + %flag_set/vec4 8; + %jmp/0xz T_92.20, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x56148bf01f00_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x56148bf01fa0_0, 0; +T_92.20 ; + %jmp T_92; + .thread T_92; + .scope S_0x56148be748f0; +T_93 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x56148bf0c660_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x56148bf0c430_0, 0, 1; + %pushi/vec4 0, 0, 32; + %store/vec4 v0x56148bf0c7a0_0, 0, 32; + %end; + .thread T_93; + .scope S_0x56148be748f0; +T_94 ; + %vpi_call 7 156 "$dumpfile", "dump.vcd" {0 0 0}; + %vpi_call 7 157 "$dumpvars" {0 0 0}; + %pushi/vec4 123, 0, 36; + %ix/load 4, 4, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x56148beecf00, 4, 0; + %pushi/vec4 321, 0, 36; + %ix/load 4, 5, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x56148beecf00, 4, 0; + %pushi/vec4 2493223645, 0, 34; + %concati/vec4 2, 0, 2; + %ix/load 4, 83, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x56148beecf00, 4, 0; + %pushi/vec4 4294964955, 0, 32; + %concati/vec4 6, 0, 4; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x56148bf00c10, 4, 0; + %delay 5, 0; + %delay 200, 0; + %wait E_0x56148bef1810; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x56148bf06140_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x56148bf0c660_0, 0; + %pushi/vec4 83, 0, 32; + %assign/vec4 v0x56148bf0c7a0_0, 0; + %wait E_0x56148bd151d0; + %wait E_0x56148bef1810; + %pushi/vec4 2, 0, 2; + %assign/vec4 v0x56148bf06140_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x56148bf0c430_0, 0; + %wait E_0x56148bd15150; + %wait E_0x56148bef1810; + %pushi/vec4 1, 0, 2; + %assign/vec4 v0x56148bf06140_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x56148bf0c430_0, 0; + %wait E_0x56148bd15150; + %wait E_0x56148bef1810; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x56148bf06140_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x56148bf0c660_0, 0; + %pushi/vec4 84, 0, 32; + %assign/vec4 v0x56148bf0c7a0_0, 0; + %wait E_0x56148bd151d0; + %wait E_0x56148bef1810; + %pushi/vec4 2, 0, 2; + %assign/vec4 v0x56148bf06140_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x56148bf0c430_0, 0; + %wait E_0x56148bd15150; + %wait E_0x56148bef1810; + %pushi/vec4 1, 0, 2; + %assign/vec4 v0x56148bf06140_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x56148bf0c430_0, 0; + %wait E_0x56148bd15150; + %end; + .thread T_94; + .scope S_0x56148be748f0; +T_95 ; + %delay 40000, 0; + %vpi_call 7 222 "$finish" {0 0 0}; + %end; + .thread T_95; + .scope S_0x56148be748f0; +T_96 ; + %wait E_0x56148bef1810; + %load/vec4 v0x56148bf0c5c0_0; + %inv; + %load/vec4 v0x56148bf0c660_0; + %and; + %flag_set/vec4 8; + %jmp/0xz T_96.0, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x56148bf0c660_0, 0; +T_96.0 ; + %load/vec4 v0x56148bf0c5c0_0; + %inv; + %load/vec4 v0x56148bf0c430_0; + %and; + %flag_set/vec4 8; + %jmp/0xz T_96.2, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x56148bf0c430_0, 0; +T_96.2 ; + %jmp T_96; + .thread T_96; +# The file index is used to find the file name in the following table. +:file_names 11; + "N/A"; + ""; + "arbiter.v"; + "modules.v"; + "memory.v"; + "clk.v"; + "memif.v"; + "tb_membusif.v"; + "core161c.v"; + "fast162.v"; + "membusif.v"; diff --git a/verilog/tb/tb_membusif.v b/verilog/tb/tb_membusif.v new file mode 100644 index 0000000..cd5d479 --- /dev/null +++ b/verilog/tb/tb_membusif.v @@ -0,0 +1,232 @@ +`default_nettype none +`timescale 1ns/1ns + +module tb_membusif(); + + wire clk, reset; + clock clock(clk, reset); + + // avalon + reg a_write = 0; + reg a_read = 0; + reg [31:0] a_writedata = 0; + reg [1:0] a_address; + wire [31:0] a_readdata; + wire a_waitrequest; + + // membus + wire b_rq_cyc; + wire b_rd_rq; + wire b_wr_rq; + wire [21:35] b_ma; + wire [18:21] b_sel; + wire b_fmc_select; + wire [0:35] b_mb_write; + wire b_wr_rs; + + wire [0:35] b_mb_read = b_mb_read_0 | b_mb_read_1; + wire b_addr_ack = b_addr_ack_0 | b_addr_ack_1; + wire b_rd_rs = b_rd_rs_0 | b_rd_rs_1; + + + membusif membusif0( + .clk(clk), + .reset(reset), + + .s_address(a_address), + .s_write(a_write), + .s_read(a_read), + .s_writedata(a_writedata), + .s_readdata(a_readdata), + .s_waitrequest(a_waitrequest), + + .m_rq_cyc(b_rq_cyc), + .m_rd_rq(b_rd_rq), + .m_wr_rq(b_wr_rq), + .m_ma(b_ma), + .m_sel(b_sel), + .m_fmc_select(b_fmc_select), + .m_mb_write(b_mb_write), + .m_wr_rs(b_wr_rs), + .m_mb_read(b_mb_read), + .m_addr_ack(b_addr_ack), + .m_rd_rs(b_rd_rs)); + + wire [0:35] b_mb_read_0; + wire b_addr_ack_0; + wire b_rd_rs_0; + core161c cmem( + .clk(clk), + .reset(~reset), + .power(1'b1), + .sw_single_step(1'b0), + .sw_restart(1'b0), + + .membus_rq_cyc_p0(b_rq_cyc), + .membus_rd_rq_p0(b_rd_rq), + .membus_wr_rq_p0(b_wr_rq), + .membus_ma_p0(b_ma), + .membus_sel_p0(b_sel), + .membus_fmc_select_p0(b_fmc_select), + .membus_mb_in_p0(b_mb_write), + .membus_wr_rs_p0(b_wr_rs), + .membus_mb_out_p0(b_mb_read_0), + .membus_addr_ack_p0(b_addr_ack_0), + .membus_rd_rs_p0(b_rd_rs_0), + + .membus_wr_rs_p1(1'b0), + .membus_rq_cyc_p1(1'b0), + .membus_rd_rq_p1(1'b0), + .membus_wr_rq_p1(1'b0), + .membus_ma_p1(15'b0), + .membus_sel_p1(4'b0), + .membus_fmc_select_p1(1'b0), + .membus_mb_in_p1(36'b0), + + .membus_wr_rs_p2(1'b0), + .membus_rq_cyc_p2(1'b0), + .membus_rd_rq_p2(1'b0), + .membus_wr_rq_p2(1'b0), + .membus_ma_p2(15'b0), + .membus_sel_p2(4'b0), + .membus_fmc_select_p2(1'b0), + .membus_mb_in_p2(36'b0), + + .membus_wr_rs_p3(1'b0), + .membus_rq_cyc_p3(1'b0), + .membus_rd_rq_p3(1'b0), + .membus_wr_rq_p3(1'b0), + .membus_ma_p3(15'b0), + .membus_sel_p3(4'b0), + .membus_fmc_select_p3(1'b0), + .membus_mb_in_p3(36'b0) + ); + + wire [0:35] b_mb_read_1; + wire b_addr_ack_1; + wire b_rd_rs_1; + fast162 fmem( + .clk(clk), + .reset(~reset), + .power(1'b1), + .sw_single_step(1'b0), + .sw_restart(1'b0), + + .membus_rq_cyc_p0(b_rq_cyc), + .membus_rd_rq_p0(b_rd_rq), + .membus_wr_rq_p0(b_wr_rq), + .membus_ma_p0(b_ma), + .membus_sel_p0(b_sel), + .membus_fmc_select_p0(b_fmc_select), + .membus_mb_in_p0(b_mb_write), + .membus_wr_rs_p0(b_wr_rs), + .membus_mb_out_p0(b_mb_read_1), + .membus_addr_ack_p0(b_addr_ack_1), + .membus_rd_rs_p0(b_rd_rs_1), + + .membus_wr_rs_p1(1'b0), + .membus_rq_cyc_p1(1'b0), + .membus_rd_rq_p1(1'b0), + .membus_wr_rq_p1(1'b0), + .membus_ma_p1(15'b0), + .membus_sel_p1(4'b0), + .membus_fmc_select_p1(1'b0), + .membus_mb_in_p1(36'b0), + + .membus_wr_rs_p2(1'b0), + .membus_rq_cyc_p2(1'b0), + .membus_rd_rq_p2(1'b0), + .membus_wr_rq_p2(1'b0), + .membus_ma_p2(15'b0), + .membus_sel_p2(4'b0), + .membus_fmc_select_p2(1'b0), + .membus_mb_in_p2(36'b0), + + .membus_wr_rs_p3(1'b0), + .membus_rq_cyc_p3(1'b0), + .membus_rd_rq_p3(1'b0), + .membus_wr_rq_p3(1'b0), + .membus_ma_p3(15'b0), + .membus_sel_p3(4'b0), + .membus_fmc_select_p3(1'b0), + .membus_mb_in_p3(36'b0) + ); + + initial begin + $dumpfile("dump.vcd"); + $dumpvars(); + + cmem.core[4] = 123; + cmem.core[5] = 321; + cmem.core['o123] = 36'o112233445566; + fmem.ff[3] = 36'o777777666666; + + #5; + + #200; + + // write address + @(posedge clk); + a_address <= 0; + a_write <= 1; + a_writedata <= 32'o0000123; + @(negedge a_write); + + @(posedge clk); + a_address <= 2; + a_read <= 1; + @(negedge a_read); + + @(posedge clk); + a_address <= 1; + a_read <= 1; + @(negedge a_read); + + + // write address + @(posedge clk); + a_address <= 0; + a_write <= 1; + a_writedata <= 32'o0000124; + @(negedge a_write); + + @(posedge clk); + a_address <= 2; + a_read <= 1; + @(negedge a_read); + + @(posedge clk); + a_address <= 1; + a_read <= 1; + @(negedge a_read); + +/* + // write low word + @(posedge clk); + a_address <= 1; + a_write <= 1; + a_writedata <= 32'o111222; + @(negedge a_write); + + // write high word + @(posedge clk); + a_address <= 2; + a_write <= 1; + a_writedata <= 32'o333444; + @(negedge a_write); +*/ + end + + initial begin + #40000; + $finish; + end + + always @(posedge clk) begin + if(~a_waitrequest & a_write) + a_write <= 0; + if(~a_waitrequest & a_read) + a_read <= 0; + end + +endmodule diff --git a/verilog/tb/tb_membusif_x b/verilog/tb/tb_membusif_x new file mode 100755 index 0000000..58d4890 --- /dev/null +++ b/verilog/tb/tb_membusif_x @@ -0,0 +1,12324 @@ +#! /usr/bin/vvp +:ivl_version "10.3 (stable)" "(v10_3)"; +:ivl_delay_selection "TYPICAL"; +:vpi_time_precision - 9; +:vpi_module "system"; +:vpi_module "vhdl_sys"; +:vpi_module "v2005_math"; +:vpi_module "va_math"; +S_0x55dd3fa50bf0 .scope module, "arbiter" "arbiter" 2 1; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 18 "s0_address" + .port_info 3 /INPUT 1 "s0_write" + .port_info 4 /INPUT 1 "s0_read" + .port_info 5 /INPUT 36 "s0_writedata" + .port_info 6 /OUTPUT 36 "s0_readdata" + .port_info 7 /OUTPUT 1 "s0_waitrequest" + .port_info 8 /INPUT 18 "s1_address" + .port_info 9 /INPUT 1 "s1_write" + .port_info 10 /INPUT 1 "s1_read" + .port_info 11 /INPUT 36 "s1_writedata" + .port_info 12 /OUTPUT 36 "s1_readdata" + .port_info 13 /OUTPUT 1 "s1_waitrequest" + .port_info 14 /OUTPUT 18 "m_address" + .port_info 15 /OUTPUT 1 "m_write" + .port_info 16 /OUTPUT 1 "m_read" + .port_info 17 /OUTPUT 36 "m_writedata" + .port_info 18 /INPUT 36 "m_readdata" + .port_info 19 /INPUT 1 "m_waitrequest" +o0x7fc2ff371258 .functor BUFZ 1, C4; HiZ drive +o0x7fc2ff3712e8 .functor BUFZ 1, C4; HiZ drive +L_0x55dd3fb7c310 .functor OR 1, o0x7fc2ff371258, o0x7fc2ff3712e8, C4<0>, C4<0>; +o0x7fc2ff371378 .functor BUFZ 1, C4; HiZ drive +o0x7fc2ff371408 .functor BUFZ 1, C4; HiZ drive +L_0x55dd3fb7c410 .functor OR 1, o0x7fc2ff371378, o0x7fc2ff371408, C4<0>, C4<0>; +L_0x55dd3fb7c480 .functor OR 1, v0x55dd3faa68b0_0, v0x55dd3faa69b0_0, C4<0>, C4<0>; +o0x7fc2ff371018 .functor BUFZ 1, C4; HiZ drive +v0x55dd3f952320_0 .net "clk", 0 0, o0x7fc2ff371018; 0 drivers +v0x55dd3f952420_0 .net "connected", 0 0, L_0x55dd3fb7c480; 1 drivers +v0x55dd3f950880_0 .net "cyc0", 0 0, L_0x55dd3fb7c310; 1 drivers +v0x55dd3f950980_0 .net "cyc1", 0 0, L_0x55dd3fb7c410; 1 drivers +v0x55dd3f94edb0_0 .var "m_address", 17 0; +v0x55dd3f94eeb0_0 .var "m_read", 0 0; +o0x7fc2ff371138 .functor BUFZ 36, C4; HiZ drive +v0x55dd3f6cba40_0 .net "m_readdata", 35 0, o0x7fc2ff371138; 0 drivers +o0x7fc2ff371168 .functor BUFZ 1, C4; HiZ drive +v0x55dd3fafc2b0_0 .net "m_waitrequest", 0 0, o0x7fc2ff371168; 0 drivers +v0x55dd3fa17bf0_0 .var "m_write", 0 0; +v0x55dd3fabd980_0 .var "m_writedata", 35 0; +o0x7fc2ff3711f8 .functor BUFZ 1, C4; HiZ drive +v0x55dd3f958ef0_0 .net "reset", 0 0, o0x7fc2ff3711f8; 0 drivers +o0x7fc2ff371228 .functor BUFZ 18, C4; HiZ drive +v0x55dd3f957460_0 .net "s0_address", 17 0, o0x7fc2ff371228; 0 drivers +v0x55dd3fab08d0_0 .net "s0_read", 0 0, o0x7fc2ff371258; 0 drivers +v0x55dd3fab09d0_0 .var "s0_readdata", 35 0; +v0x55dd3faaef30_0 .var "s0_waitrequest", 0 0; +v0x55dd3faad370_0 .net "s0_write", 0 0, o0x7fc2ff3712e8; 0 drivers +o0x7fc2ff371318 .functor BUFZ 36, C4; HiZ drive +v0x55dd3faad470_0 .net "s0_writedata", 35 0, o0x7fc2ff371318; 0 drivers +o0x7fc2ff371348 .functor BUFZ 18, C4; HiZ drive +v0x55dd3faab8c0_0 .net "s1_address", 17 0, o0x7fc2ff371348; 0 drivers +v0x55dd3faab9c0_0 .net "s1_read", 0 0, o0x7fc2ff371378; 0 drivers +v0x55dd3faa9df0_0 .var "s1_readdata", 35 0; +v0x55dd3faa9ef0_0 .var "s1_waitrequest", 0 0; +v0x55dd3faa8350_0 .net "s1_write", 0 0, o0x7fc2ff371408; 0 drivers +o0x7fc2ff371438 .functor BUFZ 36, C4; HiZ drive +v0x55dd3faa8450_0 .net "s1_writedata", 35 0, o0x7fc2ff371438; 0 drivers +v0x55dd3faa68b0_0 .var "sel0", 0 0; +v0x55dd3faa69b0_0 .var "sel1", 0 0; +E_0x55dd3f6b5ad0/0 .event edge, v0x55dd3faa68b0_0, v0x55dd3f957460_0, v0x55dd3faad370_0, v0x55dd3fab08d0_0; +E_0x55dd3f6b5ad0/1 .event edge, v0x55dd3faad470_0, v0x55dd3f6cba40_0, v0x55dd3fafc2b0_0, v0x55dd3faa69b0_0; +E_0x55dd3f6b5ad0/2 .event edge, v0x55dd3faab8c0_0, v0x55dd3faa8350_0, v0x55dd3faab9c0_0, v0x55dd3faa8450_0; +E_0x55dd3f6b5ad0 .event/or E_0x55dd3f6b5ad0/0, E_0x55dd3f6b5ad0/1, E_0x55dd3f6b5ad0/2; +E_0x55dd3f6b7f80/0 .event negedge, v0x55dd3f958ef0_0; +E_0x55dd3f6b7f80/1 .event posedge, v0x55dd3f952320_0; +E_0x55dd3f6b7f80 .event/or E_0x55dd3f6b7f80/0, E_0x55dd3f6b7f80/1; +S_0x55dd3fafd030 .scope module, "clk60hz" "clk60hz" 3 2; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /OUTPUT 1 "outclk" +v0x55dd3fab3ea0_0 .net *"_s0", 31 0, L_0x55dd3fb7c520; 1 drivers +L_0x7fc2ff328018 .functor BUFT 1, C4<00>, C4<0>, C4<0>, C4<0>; +v0x55dd3fab3fa0_0 .net *"_s3", 1 0, L_0x7fc2ff328018; 1 drivers +L_0x7fc2ff328060 .functor BUFT 1, C4<00000000000011001011011100110101>, C4<0>, C4<0>, C4<0>; +v0x55dd3fab24a0_0 .net/2u *"_s4", 31 0, L_0x7fc2ff328060; 1 drivers +o0x7fc2ff371918 .functor BUFZ 1, C4; HiZ drive +v0x55dd3fa82400_0 .net "clk", 0 0, o0x7fc2ff371918; 0 drivers +v0x55dd3fa82500_0 .var "cnt", 29 0; +v0x55dd3fa80360_0 .net "outclk", 0 0, L_0x55dd3fb8c680; 1 drivers +E_0x55dd3f6b8090 .event posedge, v0x55dd3fa82400_0; +L_0x55dd3fb7c520 .concat [ 30 2 0 0], v0x55dd3fa82500_0, L_0x7fc2ff328018; +L_0x55dd3fb8c680 .cmp/eq 32, L_0x55dd3fb7c520, L_0x7fc2ff328060; +S_0x55dd3fafead0 .scope module, "core161c_x" "core161c_x" 4 1; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "power" + .port_info 3 /INPUT 1 "sw_single_step" + .port_info 4 /INPUT 1 "sw_restart" + .port_info 5 /INPUT 1 "membus_wr_rs_p0" + .port_info 6 /INPUT 1 "membus_rq_cyc_p0" + .port_info 7 /INPUT 1 "membus_rd_rq_p0" + .port_info 8 /INPUT 1 "membus_wr_rq_p0" + .port_info 9 /INPUT 15 "membus_ma_p0" + .port_info 10 /INPUT 4 "membus_sel_p0" + .port_info 11 /INPUT 1 "membus_fmc_select_p0" + .port_info 12 /INPUT 36 "membus_mb_in_p0" + .port_info 13 /OUTPUT 1 "membus_addr_ack_p0" + .port_info 14 /OUTPUT 1 "membus_rd_rs_p0" + .port_info 15 /OUTPUT 36 "membus_mb_out_p0" + .port_info 16 /INPUT 1 "membus_wr_rs_p1" + .port_info 17 /INPUT 1 "membus_rq_cyc_p1" + .port_info 18 /INPUT 1 "membus_rd_rq_p1" + .port_info 19 /INPUT 1 "membus_wr_rq_p1" + .port_info 20 /INPUT 15 "membus_ma_p1" + .port_info 21 /INPUT 4 "membus_sel_p1" + .port_info 22 /INPUT 1 "membus_fmc_select_p1" + .port_info 23 /INPUT 36 "membus_mb_in_p1" + .port_info 24 /OUTPUT 1 "membus_addr_ack_p1" + .port_info 25 /OUTPUT 1 "membus_rd_rs_p1" + .port_info 26 /OUTPUT 36 "membus_mb_out_p1" + .port_info 27 /INPUT 1 "membus_wr_rs_p2" + .port_info 28 /INPUT 1 "membus_rq_cyc_p2" + .port_info 29 /INPUT 1 "membus_rd_rq_p2" + .port_info 30 /INPUT 1 "membus_wr_rq_p2" + .port_info 31 /INPUT 15 "membus_ma_p2" + .port_info 32 /INPUT 4 "membus_sel_p2" + .port_info 33 /INPUT 1 "membus_fmc_select_p2" + .port_info 34 /INPUT 36 "membus_mb_in_p2" + .port_info 35 /OUTPUT 1 "membus_addr_ack_p2" + .port_info 36 /OUTPUT 1 "membus_rd_rs_p2" + .port_info 37 /OUTPUT 36 "membus_mb_out_p2" + .port_info 38 /INPUT 1 "membus_wr_rs_p3" + .port_info 39 /INPUT 1 "membus_rq_cyc_p3" + .port_info 40 /INPUT 1 "membus_rd_rq_p3" + .port_info 41 /INPUT 1 "membus_wr_rq_p3" + .port_info 42 /INPUT 15 "membus_ma_p3" + .port_info 43 /INPUT 4 "membus_sel_p3" + .port_info 44 /INPUT 1 "membus_fmc_select_p3" + .port_info 45 /INPUT 36 "membus_mb_in_p3" + .port_info 46 /OUTPUT 1 "membus_addr_ack_p3" + .port_info 47 /OUTPUT 1 "membus_rd_rs_p3" + .port_info 48 /OUTPUT 36 "membus_mb_out_p3" + .port_info 49 /OUTPUT 18 "m_address" + .port_info 50 /OUTPUT 1 "m_write" + .port_info 51 /OUTPUT 1 "m_read" + .port_info 52 /OUTPUT 36 "m_writedata" + .port_info 53 /INPUT 36 "m_readdata" + .port_info 54 /INPUT 1 "m_waitrequest" +P_0x55dd3fb0b820 .param/l "memsel_p0" 0 4 66, C4<0000>; +P_0x55dd3fb0b860 .param/l "memsel_p1" 0 4 67, C4<0000>; +P_0x55dd3fb0b8a0 .param/l "memsel_p2" 0 4 68, C4<0000>; +P_0x55dd3fb0b8e0 .param/l "memsel_p3" 0 4 69, C4<0000>; +o0x7fc2ff377108 .functor BUFZ 1, C4; HiZ drive +L_0x55dd3fb8c8e0 .functor NOT 1, o0x7fc2ff377108, C4<0>, C4<0>, C4<0>; +L_0x55dd3fb8c9b0 .functor AND 1, L_0x55dd3fb8c7f0, L_0x55dd3fb8c8e0, C4<1>, C4<1>; +o0x7fc2ff377588 .functor BUFZ 1, C4; HiZ drive +L_0x55dd3fb8cac0 .functor AND 1, L_0x55dd3fb8c9b0, o0x7fc2ff377588, C4<1>, C4<1>; +o0x7fc2ff377138 .functor BUFZ 1, C4; HiZ drive +L_0x55dd3fb8cca0 .functor NOT 1, o0x7fc2ff377138, C4<0>, C4<0>, C4<0>; +L_0x55dd3fb8cda0 .functor AND 1, L_0x55dd3fb8cb80, L_0x55dd3fb8cca0, C4<1>, C4<1>; +o0x7fc2ff3775b8 .functor BUFZ 1, C4; HiZ drive +L_0x55dd3fb8cee0 .functor AND 1, L_0x55dd3fb8cda0, o0x7fc2ff3775b8, C4<1>, C4<1>; +o0x7fc2ff377168 .functor BUFZ 1, C4; HiZ drive +L_0x55dd3fb8d120 .functor NOT 1, o0x7fc2ff377168, C4<0>, C4<0>, C4<0>; +L_0x55dd3fb8d1c0 .functor AND 1, L_0x55dd3fb8d030, L_0x55dd3fb8d120, C4<1>, C4<1>; +o0x7fc2ff3775e8 .functor BUFZ 1, C4; HiZ drive +L_0x55dd3fb8d320 .functor AND 1, L_0x55dd3fb8d1c0, o0x7fc2ff3775e8, C4<1>, C4<1>; +o0x7fc2ff377198 .functor BUFZ 1, C4; HiZ drive +L_0x55dd3fb8d500 .functor NOT 1, o0x7fc2ff377198, C4<0>, C4<0>, C4<0>; +L_0x55dd3fb8d630 .functor AND 1, L_0x55dd3fb8d3e0, L_0x55dd3fb8d500, C4<1>, C4<1>; +o0x7fc2ff377618 .functor BUFZ 1, C4; HiZ drive +L_0x55dd3fb8d720 .functor AND 1, L_0x55dd3fb8d630, o0x7fc2ff377618, C4<1>, C4<1>; +L_0x55dd3fb8d850 .functor AND 1, L_0x55dd3fb8cac0, v0x55dd3fb06110_0, C4<1>, C4<1>; +L_0x55dd3fb8d910 .functor AND 1, L_0x55dd3fb8cee0, v0x55dd3fb06110_0, C4<1>, C4<1>; +L_0x55dd3fb8d7e0 .functor AND 1, L_0x55dd3fb8d320, v0x55dd3fb06110_0, C4<1>, C4<1>; +L_0x55dd3fb8db20 .functor AND 1, L_0x55dd3fb8d720, v0x55dd3fb06110_0, C4<1>, C4<1>; +L_0x55dd3fb8e650 .functor AND 1, L_0x55dd3fb97630, v0x55dd3fb05360_0, C4<1>, C4<1>; +L_0x55dd3fb8f8d0 .functor AND 1, L_0x55dd3fb97810, v0x55dd3fb05360_0, C4<1>, C4<1>; +L_0x55dd3fb8fb20 .functor AND 1, L_0x55dd3fb97630, v0x55dd3fb05400_0, C4<1>, C4<1>; +L_0x55dd3fb8fbc0 .functor AND 1, L_0x55dd3fb97810, v0x55dd3fb05400_0, C4<1>, C4<1>; +L_0x55dd3fb90000 .functor AND 1, L_0x55dd3fb97630, v0x55dd3fabe3b0_0, C4<1>, C4<1>; +L_0x55dd3fb90070 .functor AND 1, L_0x55dd3fb97810, v0x55dd3fabe3b0_0, C4<1>, C4<1>; +L_0x55dd3fb90380 .functor AND 1, L_0x55dd3fb97630, v0x55dd3fabe470_0, C4<1>, C4<1>; +L_0x55dd3fb903f0 .functor AND 1, L_0x55dd3fb97810, v0x55dd3fabe470_0, C4<1>, C4<1>; +o0x7fc2ff3778e8 .functor BUFZ 1, C4; HiZ drive +L_0x55dd3fb910f0 .functor AND 1, o0x7fc2ff3778e8, v0x55dd3fac3840_0, C4<1>, C4<1>; +L_0x55dd3fb91550 .functor OR 1, L_0x55dd3fb8d850, L_0x55dd3fb8d910, C4<0>, C4<0>; +L_0x55dd3fb91740 .functor OR 1, L_0x55dd3fb91550, L_0x55dd3fb8d7e0, C4<0>, C4<0>; +L_0x55dd3fb91850 .functor OR 1, L_0x55dd3fb91740, L_0x55dd3fb8db20, C4<0>, C4<0>; +L_0x55dd3fb925f0 .functor AND 1, v0x55dd3fb04800_0, v0x55dd3fb05050_0, C4<1>, C4<1>; +L_0x55dd3fb92a90 .functor OR 1, L_0x55dd3fb90c00, L_0x55dd3fb993c0, C4<0>, C4<0>; +L_0x55dd3fb93370 .functor NOT 1, v0x55dd3fac3840_0, C4<0>, C4<0>, C4<0>; +L_0x55dd3fb93430 .functor AND 1, L_0x55dd3fb96f20, L_0x55dd3fb93370, C4<1>, C4<1>; +L_0x55dd3fb93600 .functor OR 1, L_0x55dd3fb93430, L_0x55dd3fb92e80, C4<0>, C4<0>; +L_0x55dd3fb936c0 .functor OR 1, L_0x55dd3fb93600, L_0x55dd3fb90f90, C4<0>, C4<0>; +L_0x55dd3fb94060 .functor NOT 1, v0x55dd3fb066f0_0, C4<0>, C4<0>, C4<0>; +L_0x55dd3fb940d0 .functor AND 1, L_0x55dd3fb99a50, L_0x55dd3fb94060, C4<1>, C4<1>; +L_0x55dd3fb93780 .functor OR 1, L_0x55dd3fb93260, L_0x55dd3fb940d0, C4<0>, C4<0>; +L_0x55dd3fb94310 .functor OR 1, L_0x55dd3fb93780, L_0x55dd3fb920b0, C4<0>, C4<0>; +L_0x55dd3fb948a0 .functor AND 1, L_0x55dd3fb99c80, v0x55dd3fb066f0_0, C4<1>, C4<1>; +L_0x55dd3fb949b0 .functor OR 1, L_0x55dd3fb91440, L_0x55dd3fb948a0, C4<0>, C4<0>; +L_0x55dd3fb95ea0 .functor NOT 1, v0x55dd3fb066f0_0, C4<0>, C4<0>, C4<0>; +L_0x55dd3fb95f10 .functor AND 1, L_0x55dd3fb959b0, L_0x55dd3fb95ea0, C4<1>, C4<1>; +L_0x55dd3fb96130 .functor OR 1, L_0x55dd3fb95f10, L_0x55dd3fb92490, C4<0>, C4<0>; +L_0x55dd3fb97400 .functor AND 1, L_0x55dd3fb995f0, v0x55dd3f84bfd0_0, C4<1>, C4<1>; +L_0x55dd3fb9a070 .functor BUFZ 36, v0x55dd3fb067b0_0, C4<000000000000000000000000000000000000>, C4<000000000000000000000000000000000000>, C4<000000000000000000000000000000000000>; +L_0x7fc2ff3280a8 .functor BUFT 1, C4<0000>, C4<0>, C4<0>, C4<0>; +v0x55dd3f9531a0_0 .net/2u *"_s0", 3 0, L_0x7fc2ff3280a8; 1 drivers +L_0x7fc2ff3280f0 .functor BUFT 1, C4<0000>, C4<0>, C4<0>, C4<0>; +v0x55dd3f951700_0 .net/2u *"_s10", 3 0, L_0x7fc2ff3280f0; 1 drivers +L_0x7fc2ff328330 .functor BUFT 1, C4<000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x55dd3f9517e0_0 .net/2u *"_s102", 35 0, L_0x7fc2ff328330; 1 drivers +L_0x7fc2ff328378 .functor BUFT 1, C4<000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x55dd3fac5170_0 .net/2u *"_s110", 35 0, L_0x7fc2ff328378; 1 drivers +L_0x7fc2ff3283c0 .functor BUFT 1, C4<000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x55dd3fac5250_0 .net/2u *"_s118", 35 0, L_0x7fc2ff3283c0; 1 drivers +v0x55dd3fa34910_0 .net *"_s12", 0 0, L_0x55dd3fb8cb80; 1 drivers +L_0x7fc2ff328408 .functor BUFT 1, C4<000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x55dd3fa349b0_0 .net/2u *"_s126", 35 0, L_0x7fc2ff328408; 1 drivers +L_0x7fc2ff328450 .functor BUFT 1, C4<000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x55dd3fa30e80_0 .net/2u *"_s130", 35 0, L_0x7fc2ff328450; 1 drivers +v0x55dd3fa30f60_0 .net *"_s136", 0 0, L_0x55dd3fb91550; 1 drivers +v0x55dd3facd5c0_0 .net *"_s138", 0 0, L_0x55dd3fb91740; 1 drivers +v0x55dd3facd6a0_0 .net *"_s14", 0 0, L_0x55dd3fb8cca0; 1 drivers +v0x55dd3fac9e70_0 .net *"_s146", 0 0, L_0x55dd3fb93370; 1 drivers +v0x55dd3fac9f50_0 .net *"_s148", 0 0, L_0x55dd3fb93430; 1 drivers +v0x55dd3fac9a50_0 .net *"_s150", 0 0, L_0x55dd3fb93600; 1 drivers +v0x55dd3fac9b30_0 .net *"_s154", 0 0, L_0x55dd3fb94060; 1 drivers +v0x55dd3fac9630_0 .net *"_s156", 0 0, L_0x55dd3fb940d0; 1 drivers +v0x55dd3fac9710_0 .net *"_s158", 0 0, L_0x55dd3fb93780; 1 drivers +v0x55dd3fab6840_0 .net *"_s16", 0 0, L_0x55dd3fb8cda0; 1 drivers +v0x55dd3fab6920_0 .net *"_s162", 0 0, L_0x55dd3fb948a0; 1 drivers +v0x55dd3fa87010_0 .net *"_s166", 0 0, L_0x55dd3fb95ea0; 1 drivers +v0x55dd3fa870f0_0 .net *"_s168", 0 0, L_0x55dd3fb95f10; 1 drivers +L_0x7fc2ff328eb8 .functor BUFT 1, C4<0000>, C4<0>, C4<0>, C4<0>; +v0x55dd3fa84d40_0 .net/2u *"_s176", 3 0, L_0x7fc2ff328eb8; 1 drivers +v0x55dd3fa84950_0 .net *"_s2", 0 0, L_0x55dd3fb8c7f0; 1 drivers +L_0x7fc2ff328138 .functor BUFT 1, C4<0000>, C4<0>, C4<0>, C4<0>; +v0x55dd3fa84a10_0 .net/2u *"_s20", 3 0, L_0x7fc2ff328138; 1 drivers +v0x55dd3fa373e0_0 .net *"_s22", 0 0, L_0x55dd3fb8d030; 1 drivers +v0x55dd3fa374a0_0 .net *"_s24", 0 0, L_0x55dd3fb8d120; 1 drivers +v0x55dd3fa37030_0 .net *"_s26", 0 0, L_0x55dd3fb8d1c0; 1 drivers +L_0x7fc2ff328180 .functor BUFT 1, C4<0000>, C4<0>, C4<0>, C4<0>; +v0x55dd3fa37110_0 .net/2u *"_s30", 3 0, L_0x7fc2ff328180; 1 drivers +v0x55dd3fa36ca0_0 .net *"_s32", 0 0, L_0x55dd3fb8d3e0; 1 drivers +v0x55dd3fa36d60_0 .net *"_s34", 0 0, L_0x55dd3fb8d500; 1 drivers +v0x55dd3fa25430_0 .net *"_s36", 0 0, L_0x55dd3fb8d630; 1 drivers +v0x55dd3fa25010_0 .net *"_s4", 0 0, L_0x55dd3fb8c8e0; 1 drivers +L_0x7fc2ff3281c8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +v0x55dd3fa250f0_0 .net/2u *"_s48", 0 0, L_0x7fc2ff3281c8; 1 drivers +v0x55dd3f9eaa40_0 .net *"_s50", 0 0, L_0x55dd3fb8dd00; 1 drivers +v0x55dd3f9eab20_0 .net *"_s52", 0 0, L_0x55dd3fb8ddd0; 1 drivers +v0x55dd3f9e7310_0 .net *"_s54", 0 0, L_0x55dd3fb8df00; 1 drivers +L_0x7fc2ff328210 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +v0x55dd3f9e6ed0_0 .net/2u *"_s58", 0 0, L_0x7fc2ff328210; 1 drivers +v0x55dd3f9e6fb0_0 .net *"_s6", 0 0, L_0x55dd3fb8c9b0; 1 drivers +v0x55dd3f9e6ab0_0 .net *"_s60", 0 0, L_0x55dd3fb8e210; 1 drivers +v0x55dd3f9e6b90_0 .net *"_s62", 0 0, L_0x55dd3fb8e380; 1 drivers +v0x55dd3f9dce80_0 .net *"_s64", 0 0, L_0x55dd3fb8e470; 1 drivers +L_0x7fc2ff328258 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +v0x55dd3f9dcf60_0 .net/2u *"_s68", 0 0, L_0x7fc2ff328258; 1 drivers +v0x55dd3f9cae80_0 .net *"_s70", 0 0, L_0x55dd3fb8e7f0; 1 drivers +v0x55dd3f99b610_0 .net *"_s72", 0 0, L_0x55dd3fb8e890; 1 drivers +v0x55dd3f99b6f0_0 .net *"_s74", 0 0, L_0x55dd3fb8ea30; 1 drivers +L_0x7fc2ff3282a0 .functor BUFT 1, C4<000000000000000>, C4<0>, C4<0>, C4<0>; +v0x55dd3f999300_0 .net/2u *"_s78", 14 0, L_0x7fc2ff3282a0; 1 drivers +v0x55dd3f9993e0_0 .net *"_s80", 14 0, L_0x55dd3fb8ed30; 1 drivers +v0x55dd3f998f70_0 .net *"_s82", 14 0, L_0x55dd3fb8ee90; 1 drivers +v0x55dd3f96a6e0_0 .net *"_s84", 14 0, L_0x55dd3fb8f000; 1 drivers +L_0x7fc2ff3282e8 .functor BUFT 1, C4<000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x55dd3f96a7c0_0 .net/2u *"_s88", 35 0, L_0x7fc2ff3282e8; 1 drivers +v0x55dd3f8fa0c0_0 .net *"_s90", 35 0, L_0x55dd3fb8ef30; 1 drivers +v0x55dd3f8fa1a0_0 .net *"_s92", 35 0, L_0x55dd3fb8f3c0; 1 drivers +v0x55dd3f89f3a0_0 .net *"_s94", 35 0, L_0x55dd3fb8f5a0; 1 drivers +o0x7fc2ff371a98 .functor BUFZ 1, C4; HiZ drive +v0x55dd3f89f480_0 .net "clk", 0 0, o0x7fc2ff371a98; 0 drivers +v0x55dd3f84bef0_0 .var "cma", 22 35; +v0x55dd3f84bfd0_0 .var "cma_rd_rq", 0 0; +v0x55dd3fb066f0_0 .var "cma_wr_rq", 0 0; +v0x55dd3fb067b0_0 .var "cmb", 0 35; +v0x55dd3fb06070_0 .net "cmc_addr_ack", 0 0, L_0x55dd3fb97630; 1 drivers +v0x55dd3fb06110_0 .var "cmc_await_rq", 0 0; +v0x55dd3fb05de0_0 .net "cmc_cmb_clr", 0 0, L_0x55dd3fb94740; 1 drivers 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drivers +v0x55dd3fac1ae0_0 .net "cmc_t4", 0 0, L_0x55dd3fb95620; 1 drivers +v0x55dd3fac1730_0 .net "cmc_t4_D", 0 0, L_0x55dd3fb988d0; 1 drivers +v0x55dd3fac1820_0 .net "cmc_t5", 0 0, L_0x55dd3fb959b0; 1 drivers +v0x55dd3fac1210_0 .net "cmc_t6", 0 0, L_0x55dd3fb95d90; 1 drivers +v0x55dd3fac1300_0 .net "cmc_t6_D", 0 0, L_0x55dd3fb98b00; 1 drivers +v0x55dd3fac0ed0_0 .net "cmc_t7", 0 0, L_0x55dd3fb96470; 1 drivers +v0x55dd3fac0fc0_0 .net "cmc_t7_D", 0 0, L_0x55dd3fb98d30; 1 drivers +v0x55dd3fac0bc0_0 .net "cmc_t8", 0 0, L_0x55dd3fb96800; 1 drivers +v0x55dd3fac0cb0_0 .net "cmc_t8_D", 0 0, L_0x55dd3fb98f60; 1 drivers +v0x55dd3fac0640_0 .net "cmc_t9", 0 0, L_0x55dd3fb96b90; 1 drivers +v0x55dd3fac0730_0 .net "cmc_t9_D", 0 0, L_0x55dd3fb99190; 1 drivers +v0x55dd3fac0380_0 .net "cmc_t9a", 0 0, L_0x55dd3fb96f20; 1 drivers +v0x55dd3fabff00_0 .net "cmc_t9a_D", 0 0, L_0x55dd3fb993c0; 1 drivers +v0x55dd3fabffa0_0 .var "cmc_wr", 0 0; +v0x55dd3fabfbf0_0 .net "cmc_wr_rs", 0 0, L_0x55dd3fb92490; 1 drivers +v0x55dd3fabfc90_0 .net "cmpc_p0_rq", 0 0, L_0x55dd3fb8d850; 1 drivers +v0x55dd3fabf8e0_0 .net "cmpc_p1_rq", 0 0, L_0x55dd3fb8d910; 1 drivers +v0x55dd3fabf980_0 .net "cmpc_p2_rq", 0 0, L_0x55dd3fb8d7e0; 1 drivers +v0x55dd3fabf650_0 .net "cmpc_p3_rq", 0 0, L_0x55dd3fb8db20; 1 drivers +v0x55dd3fabf6f0_0 .net "cmpc_rs_strb", 0 0, L_0x55dd3fb91cd0; 1 drivers +v0x55dd3fabf3d0_0 .net "core_addr", 13 0, v0x55dd3f84bef0_0; 1 drivers +v0x55dd3fabf470_0 .net "cyc_rq_p0", 0 0, L_0x55dd3fb8cac0; 1 drivers +v0x55dd3fabf150_0 .net "cyc_rq_p1", 0 0, L_0x55dd3fb8cee0; 1 drivers +v0x55dd3fabf210_0 .net "cyc_rq_p2", 0 0, L_0x55dd3fb8d320; 1 drivers +v0x55dd3fabea00_0 .net "cyc_rq_p3", 0 0, L_0x55dd3fb8d720; 1 drivers +v0x55dd3fabeac0_0 .net "m_address", 17 0, L_0x55dd3fb99e30; 1 drivers +v0x55dd3fb08c60_0 .var "m_read", 0 0; +o0x7fc2ff376ef8 .functor BUFZ 36, C4; HiZ drive +v0x55dd3fb08d20_0 .net "m_readdata", 35 0, o0x7fc2ff376ef8; 0 drivers +o0x7fc2ff376f28 .functor BUFZ 1, C4; HiZ drive +v0x55dd3fb08950_0 .net "m_waitrequest", 0 0, o0x7fc2ff376f28; 0 drivers +v0x55dd3fb08a10_0 .var "m_write", 0 0; +v0x55dd3fb08640_0 .net "m_writedata", 35 0, L_0x55dd3fb9a070; 1 drivers +v0x55dd3fb08700_0 .net "ma", 21 35, L_0x55dd3fb8f130; 1 drivers +v0x55dd3fb082d0_0 .net "mb_in", 0 35, L_0x55dd3fb8f690; 1 drivers +v0x55dd3fb083b0_0 .net "mb_out", 0 35, L_0x55dd3fb90830; 1 drivers +v0x55dd3fb07f90_0 .net "mb_pulse_out", 0 0, L_0x55dd3fb97a40; 1 drivers +v0x55dd3fb08030_0 .net "membus_addr_ack_p0", 0 0, L_0x55dd3fb8e650; 1 drivers +v0x55dd3fb07c50_0 .net "membus_addr_ack_p1", 0 0, L_0x55dd3fb8fb20; 1 drivers +v0x55dd3fb07d10_0 .net "membus_addr_ack_p2", 0 0, L_0x55dd3fb90000; 1 drivers +v0x55dd3fb079e0_0 .net "membus_addr_ack_p3", 0 0, L_0x55dd3fb90380; 1 drivers +v0x55dd3fb07aa0_0 .net "membus_fmc_select_p0", 0 0, o0x7fc2ff377108; 0 drivers +v0x55dd3fb076a0_0 .net "membus_fmc_select_p1", 0 0, o0x7fc2ff377138; 0 drivers +v0x55dd3fb07760_0 .net "membus_fmc_select_p2", 0 0, o0x7fc2ff377168; 0 drivers +v0x55dd3fabe6f0_0 .net "membus_fmc_select_p3", 0 0, o0x7fc2ff377198; 0 drivers +o0x7fc2ff3771c8 .functor BUFZ 15, C4; HiZ drive +v0x55dd3fabe7b0_0 .net "membus_ma_p0", 21 35, o0x7fc2ff3771c8; 0 drivers +o0x7fc2ff3771f8 .functor BUFZ 15, C4; HiZ drive +v0x55dd3fa579d0_0 .net "membus_ma_p1", 21 35, o0x7fc2ff3771f8; 0 drivers +o0x7fc2ff377228 .functor BUFZ 15, C4; HiZ drive +v0x55dd3fa57ab0_0 .net "membus_ma_p2", 21 35, o0x7fc2ff377228; 0 drivers +o0x7fc2ff377258 .functor BUFZ 15, C4; HiZ drive +v0x55dd3fa4f770_0 .net "membus_ma_p3", 21 35, o0x7fc2ff377258; 0 drivers +o0x7fc2ff377288 .functor BUFZ 36, C4; HiZ drive +v0x55dd3fa4f850_0 .net "membus_mb_in_p0", 0 35, o0x7fc2ff377288; 0 drivers +o0x7fc2ff3772b8 .functor BUFZ 36, C4; HiZ drive +v0x55dd3fa4ebe0_0 .net "membus_mb_in_p1", 0 35, o0x7fc2ff3772b8; 0 drivers +o0x7fc2ff3772e8 .functor BUFZ 36, C4; HiZ drive +v0x55dd3fa4ecc0_0 .net "membus_mb_in_p2", 0 35, o0x7fc2ff3772e8; 0 drivers +o0x7fc2ff377318 .functor BUFZ 36, C4; HiZ drive +v0x55dd3fa4d7d0_0 .net "membus_mb_in_p3", 0 35, o0x7fc2ff377318; 0 drivers +v0x55dd3fa4d890_0 .net "membus_mb_out_p0", 0 35, L_0x55dd3fb8fa30; 1 drivers +v0x55dd3fa4caf0_0 .net "membus_mb_out_p1", 0 35, L_0x55dd3fb8f990; 1 drivers +v0x55dd3fa4cbd0_0 .net "membus_mb_out_p2", 0 35, L_0x55dd3fb901a0; 1 drivers +v0x55dd3fad3bf0_0 .net "membus_mb_out_p3", 0 35, L_0x55dd3fb90590; 1 drivers +o0x7fc2ff377408 .functor BUFZ 1, C4; HiZ drive +v0x55dd3fad3cb0_0 .net "membus_rd_rq_p0", 0 0, o0x7fc2ff377408; 0 drivers +o0x7fc2ff377438 .functor BUFZ 1, C4; HiZ drive +v0x55dd3fad30d0_0 .net "membus_rd_rq_p1", 0 0, o0x7fc2ff377438; 0 drivers +o0x7fc2ff377468 .functor BUFZ 1, C4; HiZ drive +v0x55dd3fad3170_0 .net "membus_rd_rq_p2", 0 0, o0x7fc2ff377468; 0 drivers +o0x7fc2ff377498 .functor BUFZ 1, C4; HiZ drive +v0x55dd3fad25b0_0 .net "membus_rd_rq_p3", 0 0, o0x7fc2ff377498; 0 drivers +v0x55dd3fad2670_0 .net "membus_rd_rs_p0", 0 0, L_0x55dd3fb8f8d0; 1 drivers +v0x55dd3fad1a10_0 .net "membus_rd_rs_p1", 0 0, L_0x55dd3fb8fbc0; 1 drivers +v0x55dd3fad1ab0_0 .net "membus_rd_rs_p2", 0 0, L_0x55dd3fb90070; 1 drivers +v0x55dd3fad0c10_0 .net "membus_rd_rs_p3", 0 0, L_0x55dd3fb903f0; 1 drivers +v0x55dd3fad0cd0_0 .net "membus_rq_cyc_p0", 0 0, o0x7fc2ff377588; 0 drivers +v0x55dd3fad0470_0 .net "membus_rq_cyc_p1", 0 0, o0x7fc2ff3775b8; 0 drivers +v0x55dd3fad0510_0 .net "membus_rq_cyc_p2", 0 0, o0x7fc2ff3775e8; 0 drivers +v0x55dd3facf7c0_0 .net "membus_rq_cyc_p3", 0 0, o0x7fc2ff377618; 0 drivers +o0x7fc2ff377648 .functor BUFZ 4, C4; HiZ drive +v0x55dd3facf880_0 .net "membus_sel_p0", 18 21, o0x7fc2ff377648; 0 drivers +o0x7fc2ff377678 .functor BUFZ 4, C4; HiZ drive +v0x55dd3facf020_0 .net "membus_sel_p1", 18 21, o0x7fc2ff377678; 0 drivers +o0x7fc2ff3776a8 .functor BUFZ 4, C4; HiZ drive +v0x55dd3facf100_0 .net "membus_sel_p2", 18 21, o0x7fc2ff3776a8; 0 drivers +o0x7fc2ff3776d8 .functor BUFZ 4, C4; HiZ drive +v0x55dd3face370_0 .net "membus_sel_p3", 18 21, o0x7fc2ff3776d8; 0 drivers +o0x7fc2ff377708 .functor BUFZ 1, C4; HiZ drive +v0x55dd3face430_0 .net "membus_wr_rq_p0", 0 0, o0x7fc2ff377708; 0 drivers +o0x7fc2ff377738 .functor BUFZ 1, C4; HiZ drive +v0x55dd3facdbd0_0 .net "membus_wr_rq_p1", 0 0, o0x7fc2ff377738; 0 drivers +o0x7fc2ff377768 .functor BUFZ 1, C4; HiZ drive +v0x55dd3facdc70_0 .net "membus_wr_rq_p2", 0 0, o0x7fc2ff377768; 0 drivers +o0x7fc2ff377798 .functor BUFZ 1, C4; HiZ drive +v0x55dd3faccfe0_0 .net "membus_wr_rq_p3", 0 0, o0x7fc2ff377798; 0 drivers +o0x7fc2ff3777c8 .functor BUFZ 1, C4; HiZ drive +v0x55dd3facd0a0_0 .net "membus_wr_rs_p0", 0 0, o0x7fc2ff3777c8; 0 drivers +o0x7fc2ff3777f8 .functor BUFZ 1, C4; HiZ drive +v0x55dd3facc810_0 .net "membus_wr_rs_p1", 0 0, o0x7fc2ff3777f8; 0 drivers +o0x7fc2ff377828 .functor BUFZ 1, C4; HiZ drive +v0x55dd3facc8b0_0 .net "membus_wr_rs_p2", 0 0, o0x7fc2ff377828; 0 drivers +o0x7fc2ff377858 .functor BUFZ 1, C4; HiZ drive +v0x55dd3facbff0_0 .net "membus_wr_rs_p3", 0 0, o0x7fc2ff377858; 0 drivers +o0x7fc2ff3755d8 .functor BUFZ 1, C4; HiZ drive +v0x55dd3facc0b0_0 .net "power", 0 0, o0x7fc2ff3755d8; 0 drivers +v0x55dd3faca720_0 .net "rd_rq", 0 0, L_0x55dd3fb8e5b0; 1 drivers +o0x7fc2ff371b58 .functor BUFZ 1, C4; HiZ drive +v0x55dd3faca7c0_0 .net "reset", 0 0, o0x7fc2ff371b58; 0 drivers +v0x55dd3faf3a20_0 .var "sa", 0 35; +v0x55dd3faf3b00_0 .net "sw_restart", 0 0, o0x7fc2ff3778e8; 0 drivers +o0x7fc2ff377918 .functor BUFZ 1, C4; HiZ drive +v0x55dd3faf17a0_0 .net "sw_single_step", 0 0, o0x7fc2ff377918; 0 drivers +v0x55dd3faf1860_0 .net "wr_rq", 0 0, L_0x55dd3fb8eb50; 1 drivers +v0x55dd3fae8060_0 .net "wr_rs", 0 0, L_0x55dd3fb8e050; 1 drivers +L_0x55dd3fb8c7f0 .cmp/eq 4, L_0x7fc2ff3280a8, o0x7fc2ff377648; +L_0x55dd3fb8cb80 .cmp/eq 4, L_0x7fc2ff3280f0, o0x7fc2ff377678; +L_0x55dd3fb8d030 .cmp/eq 4, L_0x7fc2ff328138, o0x7fc2ff3776a8; +L_0x55dd3fb8d3e0 .cmp/eq 4, L_0x7fc2ff328180, o0x7fc2ff3776d8; +L_0x55dd3fb8dd00 .functor MUXZ 1, L_0x7fc2ff3281c8, o0x7fc2ff377858, v0x55dd3fabe470_0, C4<>; +L_0x55dd3fb8ddd0 .functor MUXZ 1, L_0x55dd3fb8dd00, o0x7fc2ff377828, v0x55dd3fabe3b0_0, C4<>; +L_0x55dd3fb8df00 .functor MUXZ 1, L_0x55dd3fb8ddd0, o0x7fc2ff3777f8, v0x55dd3fb05400_0, C4<>; +L_0x55dd3fb8e050 .functor MUXZ 1, L_0x55dd3fb8df00, o0x7fc2ff3777c8, v0x55dd3fb05360_0, C4<>; +L_0x55dd3fb8e210 .functor MUXZ 1, L_0x7fc2ff328210, o0x7fc2ff377498, v0x55dd3fabe470_0, C4<>; +L_0x55dd3fb8e380 .functor MUXZ 1, L_0x55dd3fb8e210, o0x7fc2ff377468, v0x55dd3fabe3b0_0, C4<>; +L_0x55dd3fb8e470 .functor MUXZ 1, L_0x55dd3fb8e380, o0x7fc2ff377438, v0x55dd3fb05400_0, C4<>; +L_0x55dd3fb8e5b0 .functor MUXZ 1, L_0x55dd3fb8e470, o0x7fc2ff377408, v0x55dd3fb05360_0, C4<>; +L_0x55dd3fb8e7f0 .functor MUXZ 1, L_0x7fc2ff328258, o0x7fc2ff377798, v0x55dd3fabe470_0, C4<>; +L_0x55dd3fb8e890 .functor MUXZ 1, L_0x55dd3fb8e7f0, o0x7fc2ff377768, v0x55dd3fabe3b0_0, C4<>; +L_0x55dd3fb8ea30 .functor MUXZ 1, L_0x55dd3fb8e890, o0x7fc2ff377738, v0x55dd3fb05400_0, C4<>; +L_0x55dd3fb8eb50 .functor MUXZ 1, L_0x55dd3fb8ea30, o0x7fc2ff377708, v0x55dd3fb05360_0, C4<>; +L_0x55dd3fb8ed30 .functor MUXZ 15, L_0x7fc2ff3282a0, o0x7fc2ff377258, v0x55dd3fabe470_0, C4<>; +L_0x55dd3fb8ee90 .functor MUXZ 15, L_0x55dd3fb8ed30, o0x7fc2ff377228, v0x55dd3fabe3b0_0, C4<>; +L_0x55dd3fb8f000 .functor MUXZ 15, L_0x55dd3fb8ee90, o0x7fc2ff3771f8, v0x55dd3fb05400_0, C4<>; +L_0x55dd3fb8f130 .functor MUXZ 15, L_0x55dd3fb8f000, o0x7fc2ff3771c8, v0x55dd3fb05360_0, C4<>; +L_0x55dd3fb8ef30 .functor MUXZ 36, L_0x7fc2ff3282e8, o0x7fc2ff377318, v0x55dd3fabe470_0, C4<>; +L_0x55dd3fb8f3c0 .functor MUXZ 36, L_0x55dd3fb8ef30, o0x7fc2ff3772e8, v0x55dd3fabe3b0_0, C4<>; +L_0x55dd3fb8f5a0 .functor MUXZ 36, L_0x55dd3fb8f3c0, o0x7fc2ff3772b8, v0x55dd3fb05400_0, C4<>; +L_0x55dd3fb8f690 .functor MUXZ 36, L_0x55dd3fb8f5a0, o0x7fc2ff377288, v0x55dd3fb05360_0, C4<>; +L_0x55dd3fb8fa30 .functor MUXZ 36, L_0x7fc2ff328330, L_0x55dd3fb90830, v0x55dd3fb05360_0, C4<>; +L_0x55dd3fb8f990 .functor MUXZ 36, L_0x7fc2ff328378, L_0x55dd3fb90830, v0x55dd3fb05400_0, C4<>; +L_0x55dd3fb901a0 .functor MUXZ 36, L_0x7fc2ff3283c0, L_0x55dd3fb90830, v0x55dd3fabe3b0_0, C4<>; +L_0x55dd3fb90590 .functor MUXZ 36, L_0x7fc2ff328408, L_0x55dd3fb90830, v0x55dd3fabe470_0, C4<>; +L_0x55dd3fb90830 .functor MUXZ 36, L_0x7fc2ff328450, v0x55dd3faf3a20_0, L_0x55dd3fb97a40, C4<>; +L_0x55dd3fb99e30 .concat [ 14 4 0 0], v0x55dd3f84bef0_0, L_0x7fc2ff328eb8; +S_0x55dd3fa7f190 .scope module, "cmc_bd0" "bd" 4 209, 3 49 0, S_0x55dd3fafead0; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +v0x55dd3fa16170_0 .net *"_s0", 31 0, L_0x55dd3fb95fd0; 1 drivers +L_0x7fc2ff328498 .functor BUFT 1, C4<00000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x55dd3fa27300_0 .net *"_s3", 28 0, L_0x7fc2ff328498; 1 drivers +L_0x7fc2ff3284e0 .functor BUFT 1, C4<00000000000000000000000000000100>, C4<0>, C4<0>, C4<0>; +v0x55dd3fa27220_0 .net/2u *"_s4", 31 0, L_0x7fc2ff3284e0; 1 drivers +v0x55dd3f9daff0_0 .net "clk", 0 0, o0x7fc2ff371a98; alias, 0 drivers +v0x55dd3f957360_0 .net "in", 0 0, L_0x55dd3fb94e80; alias, 1 drivers +v0x55dd3f955860_0 .net "p", 0 0, L_0x55dd3fb97630; alias, 1 drivers +v0x55dd3fa196b0_0 .var "r", 2 0; +v0x55dd3f9daef0_0 .net "reset", 0 0, o0x7fc2ff371b58; alias, 0 drivers +E_0x55dd3fb0e940 .event posedge, v0x55dd3f9daef0_0, v0x55dd3f9daff0_0; +L_0x55dd3fb95fd0 .concat [ 3 29 0 0], v0x55dd3fa196b0_0, L_0x7fc2ff328498; +L_0x55dd3fb97630 .cmp/eq 32, L_0x55dd3fb95fd0, L_0x7fc2ff3284e0; +S_0x55dd3fa81230 .scope module, "cmc_bd1" "bd" 4 210, 3 49 0, S_0x55dd3fafead0; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +v0x55dd3fa146b0_0 .net *"_s0", 31 0, L_0x55dd3fb97720; 1 drivers +L_0x7fc2ff328528 .functor BUFT 1, C4<00000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x55dd3fa127f0_0 .net *"_s3", 28 0, L_0x7fc2ff328528; 1 drivers +L_0x7fc2ff328570 .functor BUFT 1, C4<00000000000000000000000000000100>, C4<0>, C4<0>, C4<0>; +v0x55dd3fa1caf0_0 .net/2u *"_s4", 31 0, L_0x7fc2ff328570; 1 drivers +v0x55dd3fa1cbf0_0 .net "clk", 0 0, o0x7fc2ff371a98; alias, 0 drivers +v0x55dd3fa1b050_0 .net "in", 0 0, L_0x55dd3fb99820; alias, 1 drivers +v0x55dd3fa1b150_0 .net "p", 0 0, L_0x55dd3fb97810; alias, 1 drivers +v0x55dd3fa145b0_0 .var "r", 2 0; +v0x55dd3f9c4eb0_0 .net "reset", 0 0, o0x7fc2ff371b58; alias, 0 drivers +L_0x55dd3fb97720 .concat [ 3 29 0 0], v0x55dd3fa145b0_0, L_0x7fc2ff328528; +L_0x55dd3fb97810 .cmp/eq 32, L_0x55dd3fb97720, L_0x7fc2ff328570; +S_0x55dd3fab1780 .scope module, "cmc_bd2" "bd" 4 211, 3 49 0, S_0x55dd3fafead0; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +v0x55dd3f9c3430_0 .net *"_s0", 31 0, L_0x55dd3fb97950; 1 drivers +L_0x7fc2ff3285b8 .functor BUFT 1, C4<00000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x55dd3f9c3530_0 .net *"_s3", 28 0, L_0x7fc2ff3285b8; 1 drivers +L_0x7fc2ff328600 .functor BUFT 1, C4<00000000000000000000000000000100>, C4<0>, C4<0>, C4<0>; +v0x55dd3f9c1970_0 .net/2u *"_s4", 31 0, L_0x7fc2ff328600; 1 drivers +v0x55dd3f9c1a70_0 .net "clk", 0 0, o0x7fc2ff371a98; alias, 0 drivers +v0x55dd3f9bffc0_0 .net "in", 0 0, L_0x55dd3fb972f0; alias, 1 drivers +v0x55dd3f9be3f0_0 .net "p", 0 0, L_0x55dd3fb97a40; alias, 1 drivers +v0x55dd3f9be4f0_0 .var "r", 2 0; +v0x55dd3f9bc950_0 .net "reset", 0 0, o0x7fc2ff371b58; alias, 0 drivers +L_0x55dd3fb97950 .concat [ 3 29 0 0], v0x55dd3f9be4f0_0, L_0x7fc2ff3285b8; +L_0x55dd3fb97a40 .cmp/eq 32, L_0x55dd3fb97950, L_0x7fc2ff328600; +S_0x55dd3fab3280 .scope module, "cmc_dly0" "dly100ns" 4 217, 5 31 0, S_0x55dd3fafead0; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +v0x55dd3f9bafb0_0 .net *"_s0", 31 0, L_0x55dd3fb97b80; 1 drivers +L_0x7fc2ff328648 .functor BUFT 1, C4<00000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x55dd3f9b93e0_0 .net *"_s3", 28 0, L_0x7fc2ff328648; 1 drivers +L_0x7fc2ff328690 .functor BUFT 1, C4<00000000000000000000000000000101>, C4<0>, C4<0>, C4<0>; +v0x55dd3f9b94e0_0 .net/2u *"_s4", 31 0, L_0x7fc2ff328690; 1 drivers +v0x55dd3f9c9eb0_0 .net "clk", 0 0, o0x7fc2ff371a98; alias, 0 drivers +v0x55dd3f9c9fb0_0 .net "in", 0 0, L_0x55dd3fb90c00; alias, 1 drivers +v0x55dd3f9c84a0_0 .net "p", 0 0, L_0x55dd3fb97c70; alias, 1 drivers +v0x55dd3f9c85a0_0 .var "r", 2 0; +v0x55dd3f9c69a0_0 .net "reset", 0 0, o0x7fc2ff371b58; alias, 0 drivers +L_0x55dd3fb97b80 .concat [ 3 29 0 0], v0x55dd3f9c85a0_0, L_0x7fc2ff328648; +L_0x55dd3fb97c70 .cmp/eq 32, L_0x55dd3fb97b80, L_0x7fc2ff328690; +S_0x55dd3fab4cb0 .scope module, "cmc_dly1" "dly100ns" 4 218, 5 31 0, S_0x55dd3fafead0; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +v0x55dd3f996b00_0 .net *"_s0", 31 0, L_0x55dd3fb97db0; 1 drivers +L_0x7fc2ff3286d8 .functor BUFT 1, C4<00000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x55dd3f994960_0 .net *"_s3", 28 0, L_0x7fc2ff3286d8; 1 drivers +L_0x7fc2ff328720 .functor BUFT 1, C4<00000000000000000000000000000101>, C4<0>, C4<0>, C4<0>; +v0x55dd3f994a60_0 .net/2u *"_s4", 31 0, L_0x7fc2ff328720; 1 drivers +v0x55dd3f955960_0 .net "clk", 0 0, o0x7fc2ff371a98; alias, 0 drivers +v0x55dd3f9697a0_0 .net "in", 0 0, L_0x55dd3fb93260; alias, 1 drivers +v0x55dd3f9698a0_0 .net "p", 0 0, L_0x55dd3fb97ea0; alias, 1 drivers +v0x55dd3f958df0_0 .var "r", 2 0; +v0x55dd3f95f960_0 .net "reset", 0 0, o0x7fc2ff371b58; alias, 0 drivers +L_0x55dd3fb97db0 .concat [ 3 29 0 0], v0x55dd3f958df0_0, L_0x7fc2ff3286d8; +L_0x55dd3fb97ea0 .cmp/eq 32, L_0x55dd3fb97db0, L_0x7fc2ff328720; +S_0x55dd3faa41c0 .scope module, "cmc_dly10" "dly200ns" 4 227, 5 61 0, S_0x55dd3fafead0; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +v0x55dd3f95de60_0 .net *"_s0", 31 0, L_0x55dd3fb992d0; 1 drivers +L_0x7fc2ff328be8 .functor BUFT 1, C4<0000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x55dd3f95c2c0_0 .net *"_s3", 27 0, L_0x7fc2ff328be8; 1 drivers +L_0x7fc2ff328c30 .functor BUFT 1, C4<00000000000000000000000000001010>, C4<0>, C4<0>, C4<0>; +v0x55dd3f95c3c0_0 .net/2u *"_s4", 31 0, L_0x7fc2ff328c30; 1 drivers +v0x55dd3f95a840_0 .net "clk", 0 0, o0x7fc2ff371a98; alias, 0 drivers +v0x55dd3f95a920_0 .net "in", 0 0, L_0x55dd3fb96f20; alias, 1 drivers +v0x55dd3f961290_0 .net "p", 0 0, L_0x55dd3fb993c0; alias, 1 drivers +v0x55dd3f961390_0 .var "r", 3 0; +v0x55dd3f967d00_0 .net "reset", 0 0, o0x7fc2ff371b58; alias, 0 drivers +L_0x55dd3fb992d0 .concat [ 4 28 0 0], v0x55dd3f961390_0, L_0x7fc2ff328be8; +L_0x55dd3fb993c0 .cmp/eq 32, L_0x55dd3fb992d0, L_0x7fc2ff328c30; +S_0x55dd3fa306a0 .scope module, "cmc_dly11" "dly800ns" 4 228, 5 166 0, S_0x55dd3fafead0; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +v0x55dd3f966260_0 .net *"_s0", 31 0, L_0x55dd3fb99500; 1 drivers +L_0x7fc2ff328c78 .functor BUFT 1, C4<00000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x55dd3f966360_0 .net *"_s3", 25 0, L_0x7fc2ff328c78; 1 drivers +L_0x7fc2ff328cc0 .functor BUFT 1, C4<00000000000000000000000000101000>, C4<0>, C4<0>, C4<0>; +v0x55dd3f964830_0 .net/2u *"_s4", 31 0, L_0x7fc2ff328cc0; 1 drivers +v0x55dd3f964950_0 .net "clk", 0 0, o0x7fc2ff371a98; alias, 0 drivers +v0x55dd3f962d30_0 .net "in", 0 0, L_0x55dd3fb95250; alias, 1 drivers +v0x55dd3f953dc0_0 .net "p", 0 0, L_0x55dd3fb995f0; alias, 1 drivers +v0x55dd3f953ec0_0 .var "r", 5 0; +v0x55dd3f9d1f80_0 .net "reset", 0 0, o0x7fc2ff371b58; alias, 0 drivers +L_0x55dd3fb99500 .concat [ 6 26 0 0], v0x55dd3f953ec0_0, L_0x7fc2ff328c78; +L_0x55dd3fb995f0 .cmp/eq 32, L_0x55dd3fb99500, L_0x7fc2ff328cc0; +S_0x55dd3fa139b0 .scope module, "cmc_dly12" "dly100ns" 4 229, 5 31 0, S_0x55dd3fafead0; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +v0x55dd3fabef10_0 .net *"_s0", 31 0, L_0x55dd3fb99730; 1 drivers +L_0x7fc2ff328d08 .functor BUFT 1, C4<00000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x55dd3fac08b0_0 .net *"_s3", 28 0, L_0x7fc2ff328d08; 1 drivers +L_0x7fc2ff328d50 .functor BUFT 1, C4<00000000000000000000000000000101>, C4<0>, C4<0>, C4<0>; +v0x55dd3fac3060_0 .net/2u *"_s4", 31 0, L_0x7fc2ff328d50; 1 drivers +v0x55dd3fb03850_0 .net "clk", 0 0, o0x7fc2ff371a98; alias, 0 drivers +v0x55dd3fb04a80_0 .net "in", 0 0, L_0x55dd3fb972f0; alias, 1 drivers +v0x55dd3fb04d30_0 .net "p", 0 0, L_0x55dd3fb99820; alias, 1 drivers +v0x55dd3fb06390_0 .var "r", 2 0; +v0x55dd3fb07270_0 .net "reset", 0 0, o0x7fc2ff371b58; alias, 0 drivers +L_0x55dd3fb99730 .concat [ 3 29 0 0], v0x55dd3fb06390_0, L_0x7fc2ff328d08; +L_0x55dd3fb99820 .cmp/eq 32, L_0x55dd3fb99730, L_0x7fc2ff328d50; +S_0x55dd3fa15450 .scope module, "cmc_dly13" "dly200ns" 4 231, 5 61 0, S_0x55dd3fafead0; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +v0x55dd3fb0d3f0_0 .net *"_s0", 31 0, L_0x55dd3fb99960; 1 drivers +L_0x7fc2ff328d98 .functor BUFT 1, C4<0000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x55dd3f930070_0 .net *"_s3", 27 0, L_0x7fc2ff328d98; 1 drivers +L_0x7fc2ff328de0 .functor BUFT 1, C4<00000000000000000000000000001010>, C4<0>, C4<0>, C4<0>; +v0x55dd3f931dd0_0 .net/2u *"_s4", 31 0, L_0x7fc2ff328de0; 1 drivers +v0x55dd3f9429b0_0 .net "clk", 0 0, o0x7fc2ff371a98; alias, 0 drivers +v0x55dd3f942a50_0 .net "in", 0 0, L_0x55dd3fb972f0; alias, 1 drivers +v0x55dd3f946780_0 .net "p", 0 0, L_0x55dd3fb99a50; alias, 1 drivers +v0x55dd3f948180_0 .var "r", 3 0; +v0x55dd3f949b80_0 .net "reset", 0 0, o0x7fc2ff371b58; alias, 0 drivers +L_0x55dd3fb99960 .concat [ 4 28 0 0], v0x55dd3f948180_0, L_0x7fc2ff328d98; +L_0x55dd3fb99a50 .cmp/eq 32, L_0x55dd3fb99960, L_0x7fc2ff328de0; +S_0x55dd3fa16ef0 .scope module, "cmc_dly14" "dly250ns" 4 233, 5 76 0, S_0x55dd3fafead0; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +v0x55dd3f949c20_0 .net *"_s0", 31 0, L_0x55dd3fb99b90; 1 drivers +L_0x7fc2ff328e28 .functor BUFT 1, C4<0000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x55dd3f9337d0_0 .net *"_s3", 27 0, L_0x7fc2ff328e28; 1 drivers +L_0x7fc2ff328e70 .functor BUFT 1, C4<00000000000000000000000000001100>, C4<0>, C4<0>, C4<0>; +v0x55dd3f935f30_0 .net/2u *"_s4", 31 0, L_0x7fc2ff328e70; 1 drivers +v0x55dd3f937930_0 .net "clk", 0 0, o0x7fc2ff371a98; alias, 0 drivers +v0x55dd3f9379d0_0 .net "in", 0 0, L_0x55dd3fb972f0; alias, 1 drivers +v0x55dd3f93a0f0_0 .net "p", 0 0, L_0x55dd3fb99c80; alias, 1 drivers +v0x55dd3f93c1b0_0 .var "r", 3 0; +v0x55dd3f93dbb0_0 .net "reset", 0 0, o0x7fc2ff371b58; alias, 0 drivers +L_0x55dd3fb99b90 .concat [ 4 28 0 0], v0x55dd3f93c1b0_0, L_0x7fc2ff328e28; +L_0x55dd3fb99c80 .cmp/eq 32, L_0x55dd3fb99b90, L_0x7fc2ff328e70; +S_0x55dd3fa1f840 .scope module, "cmc_dly2" "dly200ns" 4 219, 5 61 0, S_0x55dd3fafead0; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +v0x55dd3f93f5b0_0 .net *"_s0", 31 0, L_0x55dd3fb97fe0; 1 drivers +L_0x7fc2ff328768 .functor BUFT 1, C4<0000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x55dd3f940fb0_0 .net *"_s3", 27 0, L_0x7fc2ff328768; 1 drivers +L_0x7fc2ff3287b0 .functor BUFT 1, C4<00000000000000000000000000001010>, C4<0>, C4<0>, C4<0>; +v0x55dd3f9252d0_0 .net/2u *"_s4", 31 0, L_0x7fc2ff3287b0; 1 drivers +v0x55dd3f926d30_0 .net "clk", 0 0, o0x7fc2ff371a98; alias, 0 drivers +v0x55dd3f926dd0_0 .net "in", 0 0, L_0x55dd3fb91440; alias, 1 drivers +v0x55dd3f928af0_0 .net "p", 0 0, L_0x55dd3fb98080; alias, 1 drivers +v0x55dd3f92aee0_0 .var "r", 3 0; +v0x55dd3f92c8b0_0 .net "reset", 0 0, o0x7fc2ff371b58; alias, 0 drivers +L_0x55dd3fb97fe0 .concat [ 4 28 0 0], v0x55dd3f92aee0_0, L_0x7fc2ff328768; +L_0x55dd3fb98080 .cmp/eq 32, L_0x55dd3fb97fe0, L_0x7fc2ff3287b0; +S_0x55dd3fa21940 .scope module, "cmc_dly3" "dly1us" 4 220, 5 182 0, S_0x55dd3fafead0; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +v0x55dd3f92e2e0_0 .net *"_s0", 31 0, L_0x55dd3fb98170; 1 drivers +L_0x7fc2ff3287f8 .functor BUFT 1, C4<00000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x55dd3f985f60_0 .net *"_s3", 25 0, L_0x7fc2ff3287f8; 1 drivers +L_0x7fc2ff328840 .functor BUFT 1, C4<00000000000000000000000000110010>, C4<0>, C4<0>, C4<0>; +v0x55dd3f987c90_0 .net/2u *"_s4", 31 0, L_0x7fc2ff328840; 1 drivers +v0x55dd3f9899c0_0 .net "clk", 0 0, o0x7fc2ff371a98; alias, 0 drivers +v0x55dd3f989a60_0 .net "in", 0 0, L_0x55dd3fb94e80; alias, 1 drivers +v0x55dd3f998510_0 .net "p", 0 0, L_0x55dd3fb98260; alias, 1 drivers +v0x55dd3f99d0e0_0 .var "r", 5 0; +v0x55dd3f9aeac0_0 .net "reset", 0 0, o0x7fc2ff371b58; alias, 0 drivers +L_0x55dd3fb98170 .concat [ 6 26 0 0], v0x55dd3f99d0e0_0, L_0x7fc2ff3287f8; +L_0x55dd3fb98260 .cmp/eq 32, L_0x55dd3fb98170, L_0x7fc2ff328840; +S_0x55dd3fa239e0 .scope module, "cmc_dly4" "dly1us" 4 221, 5 182 0, S_0x55dd3fafead0; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +v0x55dd3f9b04c0_0 .net *"_s0", 31 0, L_0x55dd3fb983a0; 1 drivers +L_0x7fc2ff328888 .functor BUFT 1, C4<00000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x55dd3f9b21f0_0 .net *"_s3", 25 0, L_0x7fc2ff328888; 1 drivers +L_0x7fc2ff3288d0 .functor BUFT 1, C4<00000000000000000000000000110010>, C4<0>, C4<0>, C4<0>; +v0x55dd3f9b3b90_0 .net/2u *"_s4", 31 0, L_0x7fc2ff3288d0; 1 drivers +v0x55dd3f9b5ff0_0 .net "clk", 0 0, o0x7fc2ff371a98; alias, 0 drivers +v0x55dd3f9b6090_0 .net "in", 0 0, L_0x55dd3fb95250; alias, 1 drivers +v0x55dd3f9b7990_0 .net "p", 0 0, L_0x55dd3fb98490; alias, 1 drivers +v0x55dd3f9b7a30_0 .var "r", 5 0; +v0x55dd3f99f4d0_0 .net "reset", 0 0, o0x7fc2ff371b58; alias, 0 drivers +L_0x55dd3fb983a0 .concat [ 6 26 0 0], v0x55dd3f9b7a30_0, L_0x7fc2ff328888; +L_0x55dd3fb98490 .cmp/eq 32, L_0x55dd3fb983a0, L_0x7fc2ff3288d0; +S_0x55dd3fa2c5d0 .scope module, "cmc_dly5" "dly200ns" 4 222, 5 61 0, S_0x55dd3fafead0; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +v0x55dd3f9a1230_0 .net *"_s0", 31 0, L_0x55dd3fb985d0; 1 drivers +L_0x7fc2ff328918 .functor BUFT 1, C4<0000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x55dd3f9a2f90_0 .net *"_s3", 27 0, L_0x7fc2ff328918; 1 drivers +L_0x7fc2ff328960 .functor BUFT 1, C4<00000000000000000000000000001010>, C4<0>, C4<0>, C4<0>; +v0x55dd3f9a4cf0_0 .net/2u *"_s4", 31 0, L_0x7fc2ff328960; 1 drivers +v0x55dd3f9a74e0_0 .net "clk", 0 0, o0x7fc2ff371a98; alias, 0 drivers +v0x55dd3f9a7580_0 .net "in", 0 0, L_0x55dd3fb95620; alias, 1 drivers +v0x55dd3f9a92a0_0 .net "p", 0 0, L_0x55dd3fb988d0; alias, 1 drivers +v0x55dd3f9a9340_0 .var "r", 3 0; +v0x55dd3f9aac70_0 .net "reset", 0 0, o0x7fc2ff371b58; alias, 0 drivers +L_0x55dd3fb985d0 .concat [ 4 28 0 0], v0x55dd3f9a9340_0, L_0x7fc2ff328918; +L_0x55dd3fb988d0 .cmp/eq 32, L_0x55dd3fb985d0, L_0x7fc2ff328960; +S_0x55dd3fa11c00 .scope module, "cmc_dly6" "dly200ns" 4 223, 5 61 0, S_0x55dd3fafead0; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +v0x55dd3f9ac640_0 .net *"_s0", 31 0, L_0x55dd3fb98a10; 1 drivers +L_0x7fc2ff3289a8 .functor BUFT 1, C4<0000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x55dd3f992950_0 .net *"_s3", 27 0, L_0x7fc2ff3289a8; 1 drivers +L_0x7fc2ff3289f0 .functor BUFT 1, C4<00000000000000000000000000001010>, C4<0>, C4<0>, C4<0>; +v0x55dd3f9dcbb0_0 .net/2u *"_s4", 31 0, L_0x7fc2ff3289f0; 1 drivers +v0x55dd3fa04a40_0 .net "clk", 0 0, o0x7fc2ff371a98; alias, 0 drivers +v0x55dd3fa04ae0_0 .net "in", 0 0, L_0x55dd3fb95d90; alias, 1 drivers +v0x55dd3fa06e70_0 .net "p", 0 0, L_0x55dd3fb98b00; alias, 1 drivers +v0x55dd3fa08ba0_0 .var "r", 3 0; +v0x55dd3fa0a5a0_0 .net "reset", 0 0, o0x7fc2ff371b58; alias, 0 drivers +L_0x55dd3fb98a10 .concat [ 4 28 0 0], v0x55dd3fa08ba0_0, L_0x7fc2ff3289a8; +L_0x55dd3fb98b00 .cmp/eq 32, L_0x55dd3fb98a10, L_0x7fc2ff3289f0; +S_0x55dd3f9d4800 .scope module, "cmc_dly7" "dly200ns" 4 224, 5 61 0, S_0x55dd3fafead0; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +v0x55dd3fa0bfa0_0 .net *"_s0", 31 0, L_0x55dd3fb98c40; 1 drivers +L_0x7fc2ff328a38 .functor BUFT 1, C4<0000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x55dd3fa10430_0 .net *"_s3", 27 0, L_0x7fc2ff328a38; 1 drivers +L_0x7fc2ff328a80 .functor BUFT 1, C4<00000000000000000000000000001010>, C4<0>, C4<0>, C4<0>; +v0x55dd3f9fc510_0 .net/2u *"_s4", 31 0, L_0x7fc2ff328a80; 1 drivers +v0x55dd3f9fdf70_0 .net "clk", 0 0, o0x7fc2ff371a98; alias, 0 drivers +v0x55dd3f9fe010_0 .net "in", 0 0, L_0x55dd3fb96470; alias, 1 drivers +v0x55dd3f9ffcd0_0 .net "p", 0 0, L_0x55dd3fb98d30; alias, 1 drivers +v0x55dd3f9ffd70_0 .var "r", 3 0; +v0x55dd3fa016a0_0 .net "reset", 0 0, o0x7fc2ff371b58; alias, 0 drivers +L_0x55dd3fb98c40 .concat [ 4 28 0 0], v0x55dd3f9ffd70_0, L_0x7fc2ff328a38; +L_0x55dd3fb98d30 .cmp/eq 32, L_0x55dd3fb98c40, L_0x7fc2ff328a80; +S_0x55dd3f9d8e70 .scope module, "cmc_dly8" "dly1us" 4 225, 5 182 0, S_0x55dd3fafead0; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +v0x55dd3fa71960_0 .net *"_s0", 31 0, L_0x55dd3fb98e70; 1 drivers +L_0x7fc2ff328ac8 .functor BUFT 1, C4<00000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x55dd3fa73690_0 .net *"_s3", 25 0, L_0x7fc2ff328ac8; 1 drivers +L_0x7fc2ff328b10 .functor BUFT 1, C4<00000000000000000000000000110010>, C4<0>, C4<0>, C4<0>; +v0x55dd3fa753c0_0 .net/2u *"_s4", 31 0, L_0x7fc2ff328b10; 1 drivers +v0x55dd3fa83f10_0 .net "clk", 0 0, o0x7fc2ff371a98; alias, 0 drivers +v0x55dd3fa83fb0_0 .net "in", 0 0, L_0x55dd3fb96800; alias, 1 drivers +v0x55dd3f7b14a0_0 .net "p", 0 0, L_0x55dd3fb98f60; alias, 1 drivers +v0x55dd3f7b1560_0 .var "r", 5 0; +v0x55dd3fa88ae0_0 .net "reset", 0 0, o0x7fc2ff371b58; alias, 0 drivers +L_0x55dd3fb98e70 .concat [ 6 26 0 0], v0x55dd3f7b1560_0, L_0x7fc2ff328ac8; +L_0x55dd3fb98f60 .cmp/eq 32, L_0x55dd3fb98e70, L_0x7fc2ff328b10; +S_0x55dd3f9db690 .scope module, "cmc_dly9" "dly400ns" 4 226, 5 106 0, S_0x55dd3fafead0; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +v0x55dd3fa88b80_0 .net *"_s0", 31 0, L_0x55dd3fb990a0; 1 drivers +L_0x7fc2ff328b58 .functor BUFT 1, C4<000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x55dd3fa9a4c0_0 .net *"_s3", 26 0, L_0x7fc2ff328b58; 1 drivers +L_0x7fc2ff328ba0 .functor BUFT 1, C4<00000000000000000000000000010100>, C4<0>, C4<0>, C4<0>; +v0x55dd3fa9bec0_0 .net/2u *"_s4", 31 0, L_0x7fc2ff328ba0; 1 drivers +v0x55dd3fa9dbf0_0 .net "clk", 0 0, o0x7fc2ff371a98; alias, 0 drivers +v0x55dd3fa9dc90_0 .net "in", 0 0, L_0x55dd3fb96b90; alias, 1 drivers +v0x55dd3fa9f590_0 .net "p", 0 0, L_0x55dd3fb99190; alias, 1 drivers +v0x55dd3fa9f630_0 .var "r", 4 0; +v0x55dd3faa19f0_0 .net "reset", 0 0, o0x7fc2ff371b58; alias, 0 drivers +L_0x55dd3fb990a0 .concat [ 5 27 0 0], v0x55dd3fa9f630_0, L_0x7fc2ff328b58; +L_0x55dd3fb99190 .cmp/eq 32, L_0x55dd3fb990a0, L_0x7fc2ff328ba0; +S_0x55dd3f9d6650 .scope module, "cmc_pa0" "pa" 4 176, 3 31 0, S_0x55dd3fafead0; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +L_0x55dd3fb92930 .functor AND 1, L_0x55dd3fb926b0, L_0x55dd3fb92840, C4<1>, C4<1>; +v0x55dd3faa3390_0 .net *"_s1", 0 0, L_0x55dd3fb926b0; 1 drivers +v0x55dd3fa8aed0_0 .net *"_s3", 0 0, L_0x55dd3fb92750; 1 drivers +v0x55dd3fa8cc30_0 .net *"_s5", 0 0, L_0x55dd3fb92840; 1 drivers +v0x55dd3fa8e990_0 .net "clk", 0 0, o0x7fc2ff371a98; alias, 0 drivers +v0x55dd3fa8ea30_0 .net "in", 0 0, L_0x55dd3fb92a90; 1 drivers +v0x55dd3fa906f0_0 .net "p", 0 0, L_0x55dd3fb92930; alias, 1 drivers +v0x55dd3fa92ee0_0 .net "reset", 0 0, o0x7fc2ff371b58; alias, 0 drivers +v0x55dd3fa92f80_0 .var "x", 1 0; +L_0x55dd3fb926b0 .part v0x55dd3fa92f80_0, 0, 1; +L_0x55dd3fb92750 .part v0x55dd3fa92f80_0, 1, 1; +L_0x55dd3fb92840 .reduce/nor L_0x55dd3fb92750; +S_0x55dd3fa18990 .scope module, "cmc_pa1" "pa" 4 177, 3 31 0, S_0x55dd3fafead0; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +L_0x55dd3fb92e80 .functor AND 1, L_0x55dd3fb92c00, L_0x55dd3fb92d90, C4<1>, C4<1>; +v0x55dd3fa94ca0_0 .net *"_s1", 0 0, L_0x55dd3fb92c00; 1 drivers +v0x55dd3fa96670_0 .net *"_s3", 0 0, L_0x55dd3fb92ca0; 1 drivers +v0x55dd3fa98040_0 .net *"_s5", 0 0, L_0x55dd3fb92d90; 1 drivers +v0x55dd3fa7e350_0 .net "clk", 0 0, o0x7fc2ff371a98; alias, 0 drivers +v0x55dd3fa7e3f0_0 .net "in", 0 0, L_0x55dd3fb97c70; alias, 1 drivers +v0x55dd3fae75c0_0 .net "p", 0 0, L_0x55dd3fb92e80; alias, 1 drivers +v0x55dd3fae99f0_0 .net "reset", 0 0, o0x7fc2ff371b58; alias, 0 drivers +v0x55dd3fae9a90_0 .var "x", 1 0; +L_0x55dd3fb92c00 .part v0x55dd3fae9a90_0, 0, 1; +L_0x55dd3fb92ca0 .part v0x55dd3fae9a90_0, 1, 1; +L_0x55dd3fb92d90 .reduce/nor L_0x55dd3fb92ca0; +S_0x55dd3fa1a430 .scope module, "cmc_pa10" "pa" 4 197, 3 31 0, S_0x55dd3fafead0; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +L_0x55dd3fb95d90 .functor AND 1, L_0x55dd3fb95b10, L_0x55dd3fb95ca0, C4<1>, C4<1>; +v0x55dd3faeb720_0 .net *"_s1", 0 0, L_0x55dd3fb95b10; 1 drivers +v0x55dd3faed120_0 .net *"_s3", 0 0, L_0x55dd3fb95bb0; 1 drivers +v0x55dd3faeeb20_0 .net *"_s5", 0 0, L_0x55dd3fb95ca0; 1 drivers +v0x55dd3faf2fb0_0 .net "clk", 0 0, o0x7fc2ff371a98; alias, 0 drivers +v0x55dd3faf3050_0 .net "in", 0 0, L_0x55dd3fb96130; 1 drivers +v0x55dd3fadf090_0 .net "p", 0 0, L_0x55dd3fb95d90; alias, 1 drivers +v0x55dd3fadf130_0 .net "reset", 0 0, o0x7fc2ff371b58; alias, 0 drivers +v0x55dd3fae0af0_0 .var "x", 1 0; +L_0x55dd3fb95b10 .part v0x55dd3fae0af0_0, 0, 1; +L_0x55dd3fb95bb0 .part v0x55dd3fae0af0_0, 1, 1; +L_0x55dd3fb95ca0 .reduce/nor L_0x55dd3fb95bb0; +S_0x55dd3fa1bed0 .scope module, "cmc_pa11" "pa" 4 200, 3 31 0, S_0x55dd3fafead0; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +L_0x55dd3fb96470 .functor AND 1, L_0x55dd3fb961f0, L_0x55dd3fb96380, C4<1>, C4<1>; +v0x55dd3fae2850_0 .net *"_s1", 0 0, L_0x55dd3fb961f0; 1 drivers +v0x55dd3fae4220_0 .net *"_s3", 0 0, L_0x55dd3fb96290; 1 drivers +v0x55dd3faf0520_0 .net *"_s5", 0 0, L_0x55dd3fb96380; 1 drivers +v0x55dd3fb03af0_0 .net "clk", 0 0, o0x7fc2ff371a98; alias, 0 drivers +v0x55dd3fb03b90_0 .net "in", 0 0, L_0x55dd3fb98b00; alias, 1 drivers +v0x55dd3fb06a40_0 .net "p", 0 0, L_0x55dd3fb96470; alias, 1 drivers +v0x55dd3fb045c0_0 .net "reset", 0 0, o0x7fc2ff371b58; alias, 0 drivers +v0x55dd3fb04660_0 .var "x", 1 0; +L_0x55dd3fb961f0 .part v0x55dd3fb04660_0, 0, 1; +L_0x55dd3fb96290 .part v0x55dd3fb04660_0, 1, 1; +L_0x55dd3fb96380 .reduce/nor L_0x55dd3fb96290; +S_0x55dd3f9d2d50 .scope module, "cmc_pa12" "pa" 4 201, 3 31 0, S_0x55dd3fafead0; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +L_0x55dd3fb96800 .functor AND 1, L_0x55dd3fb96580, L_0x55dd3fb96710, C4<1>, C4<1>; +v0x55dd3fb06f60_0 .net *"_s1", 0 0, L_0x55dd3fb96580; 1 drivers +v0x55dd3fa4b8c0_0 .net *"_s3", 0 0, L_0x55dd3fb96620; 1 drivers +v0x55dd3fb05670_0 .net *"_s5", 0 0, L_0x55dd3fb96710; 1 drivers +v0x55dd3fad11c0_0 .net "clk", 0 0, o0x7fc2ff371a98; alias, 0 drivers +v0x55dd3fad1260_0 .net "in", 0 0, L_0x55dd3fb98d30; alias, 1 drivers +v0x55dd3facfd70_0 .net "p", 0 0, L_0x55dd3fb96800; alias, 1 drivers +v0x55dd3face920_0 .net "reset", 0 0, o0x7fc2ff371b58; alias, 0 drivers +v0x55dd3face9c0_0 .var "x", 1 0; +L_0x55dd3fb96580 .part v0x55dd3face9c0_0, 0, 1; +L_0x55dd3fb96620 .part v0x55dd3face9c0_0, 1, 1; +L_0x55dd3fb96710 .reduce/nor L_0x55dd3fb96620; +S_0x55dd3f9ba290 .scope module, "cmc_pa13" "pa" 4 202, 3 31 0, S_0x55dd3fafead0; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +L_0x55dd3fb96b90 .functor AND 1, L_0x55dd3fb96910, L_0x55dd3fb96aa0, C4<1>, C4<1>; +v0x55dd3faf57a0_0 .net *"_s1", 0 0, L_0x55dd3fb96910; 1 drivers +v0x55dd3fae9d50_0 .net *"_s3", 0 0, L_0x55dd3fb969b0; 1 drivers +v0x55dd3fae0e50_0 .net *"_s5", 0 0, L_0x55dd3fb96aa0; 1 drivers +v0x55dd3fa9c220_0 .net "clk", 0 0, o0x7fc2ff371a98; alias, 0 drivers +v0x55dd3fa9c2c0_0 .net "in", 0 0, L_0x55dd3fb98f60; alias, 1 drivers +v0x55dd3fa93240_0 .net "p", 0 0, L_0x55dd3fb96b90; alias, 1 drivers +v0x55dd3fa8ecf0_0 .net "reset", 0 0, o0x7fc2ff371b58; alias, 0 drivers +v0x55dd3fa8ed90_0 .var "x", 1 0; +L_0x55dd3fb96910 .part v0x55dd3fa8ed90_0, 0, 1; +L_0x55dd3fb969b0 .part v0x55dd3fa8ed90_0, 1, 1; +L_0x55dd3fb96aa0 .reduce/nor L_0x55dd3fb969b0; +S_0x55dd3f9bbd30 .scope module, "cmc_pa14" "pa" 4 203, 3 31 0, S_0x55dd3fafead0; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +L_0x55dd3fb96f20 .functor AND 1, L_0x55dd3fb96ca0, L_0x55dd3fb96e30, C4<1>, C4<1>; +v0x55dd3fa8cf90_0 .net *"_s1", 0 0, L_0x55dd3fb96ca0; 1 drivers +v0x55dd3fa8b230_0 .net *"_s3", 0 0, L_0x55dd3fb96d40; 1 drivers +v0x55dd3fa75720_0 .net *"_s5", 0 0, L_0x55dd3fb96e30; 1 drivers +v0x55dd3fa739f0_0 .net "clk", 0 0, o0x7fc2ff371a98; alias, 0 drivers +v0x55dd3fa73a90_0 .net "in", 0 0, L_0x55dd3fb99190; alias, 1 drivers +v0x55dd3fa71cc0_0 .net "p", 0 0, L_0x55dd3fb96f20; alias, 1 drivers +v0x55dd3fa6ff60_0 .net "reset", 0 0, o0x7fc2ff371b58; alias, 0 drivers +v0x55dd3fa70000_0 .var "x", 1 0; +L_0x55dd3fb96ca0 .part v0x55dd3fa70000_0, 0, 1; +L_0x55dd3fb96d40 .part v0x55dd3fa70000_0, 1, 1; +L_0x55dd3fb96e30 .reduce/nor L_0x55dd3fb96d40; +S_0x55dd3f9bd7d0 .scope module, "cmc_pa15" "pa" 4 204, 3 31 0, S_0x55dd3fafead0; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +L_0x55dd3fb972f0 .functor AND 1, L_0x55dd3fb97070, L_0x55dd3fb97200, C4<1>, C4<1>; +v0x55dd3f9ee640_0 .net *"_s1", 0 0, L_0x55dd3fb97070; 1 drivers +v0x55dd3f9ed1f0_0 .net *"_s3", 0 0, L_0x55dd3fb97110; 1 drivers +v0x55dd3f9ebda0_0 .net *"_s5", 0 0, L_0x55dd3fb97200; 1 drivers +v0x55dd3fa12ba0_0 .net "clk", 0 0, o0x7fc2ff371a98; alias, 0 drivers +v0x55dd3fa12c40_0 .net "in", 0 0, L_0x55dd3fb97400; 1 drivers +v0x55dd3fa071d0_0 .net "p", 0 0, L_0x55dd3fb972f0; alias, 1 drivers +v0x55dd3fa07270_0 .net "reset", 0 0, o0x7fc2ff371b58; alias, 0 drivers +v0x55dd3f9fe2d0_0 .var "x", 1 0; +L_0x55dd3fb97070 .part v0x55dd3f9fe2d0_0, 0, 1; +L_0x55dd3fb97110 .part v0x55dd3f9fe2d0_0, 1, 1; +L_0x55dd3fb97200 .reduce/nor L_0x55dd3fb97110; +S_0x55dd3f9bf2a0 .scope module, "cmc_pa2" "pa" 4 178, 3 31 0, S_0x55dd3fafead0; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +L_0x55dd3fb93260 .functor AND 1, L_0x55dd3fb92fe0, L_0x55dd3fb93170, C4<1>, C4<1>; +v0x55dd3f9b0820_0 .net *"_s1", 0 0, L_0x55dd3fb92fe0; 1 drivers +v0x55dd3f9a7840_0 .net *"_s3", 0 0, L_0x55dd3fb93080; 1 drivers +v0x55dd3f9a32f0_0 .net *"_s5", 0 0, L_0x55dd3fb93170; 1 drivers +v0x55dd3f9a1590_0 .net "clk", 0 0, o0x7fc2ff371a98; alias, 0 drivers +v0x55dd3f9a1630_0 .net "in", 0 0, L_0x55dd3fb936c0; 1 drivers +v0x55dd3f99f830_0 .net "p", 0 0, L_0x55dd3fb93260; alias, 1 drivers +v0x55dd3f99f8d0_0 .net "reset", 0 0, o0x7fc2ff371b58; alias, 0 drivers +v0x55dd3f989d20_0 .var "x", 1 0; +L_0x55dd3fb92fe0 .part v0x55dd3f989d20_0, 0, 1; +L_0x55dd3fb93080 .part v0x55dd3f989d20_0, 1, 1; +L_0x55dd3fb93170 .reduce/nor L_0x55dd3fb93080; +S_0x55dd3f9c0d70 .scope module, "cmc_pa3" "pa" 4 183, 3 31 0, S_0x55dd3fafead0; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +L_0x55dd3fb93b20 .functor AND 1, L_0x55dd3fb938a0, L_0x55dd3fb93a30, C4<1>, C4<1>; +v0x55dd3f987ff0_0 .net *"_s1", 0 0, L_0x55dd3fb938a0; 1 drivers +v0x55dd3f9862c0_0 .net *"_s3", 0 0, L_0x55dd3fb93940; 1 drivers +v0x55dd3f984560_0 .net *"_s5", 0 0, L_0x55dd3fb93a30; 1 drivers +v0x55dd3f94b8b0_0 .net "clk", 0 0, o0x7fc2ff371a98; alias, 0 drivers +v0x55dd3f94b950_0 .net "in", 0 0, L_0x55dd3fb97ea0; alias, 1 drivers +v0x55dd3f9303d0_0 .net "p", 0 0, L_0x55dd3fb93b20; alias, 1 drivers +v0x55dd3f92e640_0 .net "reset", 0 0, o0x7fc2ff371b58; alias, 0 drivers +v0x55dd3f92e6e0_0 .var "x", 1 0; +L_0x55dd3fb938a0 .part v0x55dd3f92e6e0_0, 0, 1; +L_0x55dd3fb93940 .part v0x55dd3f92e6e0_0, 1, 1; +L_0x55dd3fb93a30 .reduce/nor L_0x55dd3fb93940; +S_0x55dd3f9c2810 .scope module, "cmc_pa4" "pa" 4 184, 3 31 0, S_0x55dd3fafead0; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +L_0x55dd3fb93f00 .functor AND 1, L_0x55dd3fb93c80, L_0x55dd3fb93e10, C4<1>, C4<1>; +v0x55dd3f927090_0 .net *"_s1", 0 0, L_0x55dd3fb93c80; 1 drivers +v0x55dd3fab5e50_0 .net *"_s3", 0 0, L_0x55dd3fb93d20; 1 drivers +v0x55dd3fa84270_0 .net *"_s5", 0 0, L_0x55dd3fb93e10; 1 drivers +v0x55dd3fa84310_0 .net "clk", 0 0, o0x7fc2ff371a98; alias, 0 drivers +v0x55dd3f9ca450_0 .net "in", 0 0, L_0x55dd3fb94310; 1 drivers +v0x55dd3f998870_0 .net "p", 0 0, L_0x55dd3fb93f00; alias, 1 drivers +v0x55dd3f969cf0_0 .net "reset", 0 0, o0x7fc2ff371b58; alias, 0 drivers +v0x55dd3f969d90_0 .var "x", 1 0; +L_0x55dd3fb93c80 .part v0x55dd3f969d90_0, 0, 1; +L_0x55dd3fb93d20 .part v0x55dd3f969d90_0, 1, 1; +L_0x55dd3fb93e10 .reduce/nor L_0x55dd3fb93d20; +S_0x55dd3f9c42b0 .scope module, "cmc_pa5" "pa" 4 189, 3 31 0, S_0x55dd3fafead0; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +L_0x55dd3fb94740 .functor AND 1, L_0x55dd3fb944c0, L_0x55dd3fb94650, C4<1>, C4<1>; +v0x55dd3fab64d0_0 .net *"_s1", 0 0, L_0x55dd3fb944c0; 1 drivers +v0x55dd3fa76690_0 .net *"_s3", 0 0, L_0x55dd3fb94560; 1 drivers +v0x55dd3fa76250_0 .net *"_s5", 0 0, L_0x55dd3fb94650; 1 drivers +v0x55dd3fa75e10_0 .net "clk", 0 0, o0x7fc2ff371a98; alias, 0 drivers +v0x55dd3fa75eb0_0 .net "in", 0 0, L_0x55dd3fb949b0; 1 drivers +v0x55dd3fa37650_0 .net "p", 0 0, L_0x55dd3fb94740; alias, 1 drivers +v0x55dd3fa37710_0 .net "reset", 0 0, o0x7fc2ff371b58; alias, 0 drivers +v0x55dd3fa2eb40_0 .var "x", 1 0; +L_0x55dd3fb944c0 .part v0x55dd3fa2eb40_0, 0, 1; +L_0x55dd3fb94560 .part v0x55dd3fa2eb40_0, 1, 1; +L_0x55dd3fb94650 .reduce/nor L_0x55dd3fb94560; +S_0x55dd3f9b87c0 .scope module, "cmc_pa6" "pa" 4 193, 3 31 0, S_0x55dd3fafead0; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +L_0x55dd3fb94e80 .functor AND 1, L_0x55dd3fb94c00, L_0x55dd3fb94d90, C4<1>, C4<1>; +v0x55dd3fa2ce70_0 .net *"_s1", 0 0, L_0x55dd3fb94c00; 1 drivers +v0x55dd3fa28500_0 .net *"_s3", 0 0, L_0x55dd3fb94ca0; 1 drivers +v0x55dd3f9ddf50_0 .net *"_s5", 0 0, L_0x55dd3fb94d90; 1 drivers +v0x55dd3f9e4540_0 .net "clk", 0 0, o0x7fc2ff371a98; alias, 0 drivers +v0x55dd3f9e45e0_0 .net "in", 0 0, L_0x55dd3fb98080; alias, 1 drivers +v0x55dd3f9ddab0_0 .net "p", 0 0, L_0x55dd3fb94e80; alias, 1 drivers +v0x55dd3f9e4180_0 .net "reset", 0 0, o0x7fc2ff371b58; alias, 0 drivers +v0x55dd3f9e4220_0 .var "x", 1 0; +L_0x55dd3fb94c00 .part v0x55dd3f9e4220_0, 0, 1; +L_0x55dd3fb94ca0 .part v0x55dd3f9e4220_0, 1, 1; +L_0x55dd3fb94d90 .reduce/nor L_0x55dd3fb94ca0; +S_0x55dd3f95ec40 .scope module, "cmc_pa7" "pa" 4 194, 3 31 0, S_0x55dd3fafead0; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +L_0x55dd3fb95250 .functor AND 1, L_0x55dd3fb94fd0, L_0x55dd3fb95160, C4<1>, C4<1>; +v0x55dd3f9e3dc0_0 .net *"_s1", 0 0, L_0x55dd3fb94fd0; 1 drivers +v0x55dd3f9e3e80_0 .net *"_s3", 0 0, L_0x55dd3fb95070; 1 drivers +v0x55dd3f9e3a00_0 .net *"_s5", 0 0, L_0x55dd3fb95160; 1 drivers +v0x55dd3f9e3640_0 .net "clk", 0 0, o0x7fc2ff371a98; alias, 0 drivers +v0x55dd3f9e36e0_0 .net "in", 0 0, L_0x55dd3fb98260; alias, 1 drivers +v0x55dd3f9e3280_0 .net "p", 0 0, L_0x55dd3fb95250; alias, 1 drivers +v0x55dd3f9e2ec0_0 .net "reset", 0 0, o0x7fc2ff371b58; alias, 0 drivers +v0x55dd3f9e2f60_0 .var "x", 1 0; +L_0x55dd3fb94fd0 .part v0x55dd3f9e2f60_0, 0, 1; +L_0x55dd3fb95070 .part v0x55dd3f9e2f60_0, 1, 1; +L_0x55dd3fb95160 .reduce/nor L_0x55dd3fb95070; +S_0x55dd3f960670 .scope module, "cmc_pa8" "pa" 4 195, 3 31 0, S_0x55dd3fafead0; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +L_0x55dd3fb95620 .functor AND 1, L_0x55dd3fb953a0, L_0x55dd3fb95530, C4<1>, C4<1>; +v0x55dd3f6a5190_0 .net *"_s1", 0 0, L_0x55dd3fb953a0; 1 drivers +v0x55dd3f6a5290_0 .net *"_s3", 0 0, L_0x55dd3fb95440; 1 drivers +v0x55dd3f9e2b40_0 .net *"_s5", 0 0, L_0x55dd3fb95530; 1 drivers +v0x55dd3f9e2740_0 .net "clk", 0 0, o0x7fc2ff371a98; alias, 0 drivers +v0x55dd3f9e27e0_0 .net "in", 0 0, L_0x55dd3fb98490; alias, 1 drivers +v0x55dd3f9e2380_0 .net "p", 0 0, L_0x55dd3fb95620; alias, 1 drivers +v0x55dd3f9e1fc0_0 .net "reset", 0 0, o0x7fc2ff371b58; alias, 0 drivers +v0x55dd3f9e2060_0 .var "x", 1 0; +L_0x55dd3fb953a0 .part v0x55dd3f9e2060_0, 0, 1; +L_0x55dd3fb95440 .part v0x55dd3f9e2060_0, 1, 1; +L_0x55dd3fb95530 .reduce/nor L_0x55dd3fb95440; +S_0x55dd3f993790 .scope module, "cmc_pa9" "pa" 4 196, 3 31 0, S_0x55dd3fafead0; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +L_0x55dd3fb959b0 .functor AND 1, L_0x55dd3fb95730, L_0x55dd3fb958c0, C4<1>, C4<1>; +v0x55dd3f9dd6d0_0 .net *"_s1", 0 0, L_0x55dd3fb95730; 1 drivers +v0x55dd3f9e1c40_0 .net *"_s3", 0 0, L_0x55dd3fb957d0; 1 drivers +v0x55dd3f9e1840_0 .net *"_s5", 0 0, L_0x55dd3fb958c0; 1 drivers +v0x55dd3f9e1480_0 .net "clk", 0 0, o0x7fc2ff371a98; alias, 0 drivers +v0x55dd3f9e1520_0 .net "in", 0 0, L_0x55dd3fb988d0; alias, 1 drivers +v0x55dd3f9e10c0_0 .net "p", 0 0, L_0x55dd3fb959b0; alias, 1 drivers +v0x55dd3f9e1160_0 .net "reset", 0 0, o0x7fc2ff371b58; alias, 0 drivers +v0x55dd3f9e0d00_0 .var "x", 1 0; +L_0x55dd3fb95730 .part v0x55dd3f9e0d00_0, 0, 1; +L_0x55dd3fb957d0 .part v0x55dd3f9e0d00_0, 1, 1; +L_0x55dd3fb958c0 .reduce/nor L_0x55dd3fb957d0; +S_0x55dd3f995830 .scope module, "cmc_pg0" "pg" 4 165, 3 15 0, S_0x55dd3fafead0; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +L_0x55dd3fb90c00 .functor AND 1, L_0x55dd3fb90920, L_0x55dd3fb90b10, C4<1>, C4<1>; +v0x55dd3f9e0a00_0 .net *"_s1", 0 0, L_0x55dd3fb90920; 1 drivers +v0x55dd3f9e0580_0 .net *"_s3", 0 0, L_0x55dd3fb909f0; 1 drivers +v0x55dd3f9e0640_0 .net *"_s5", 0 0, L_0x55dd3fb90b10; 1 drivers +v0x55dd3f9e01f0_0 .net "clk", 0 0, o0x7fc2ff371a98; alias, 0 drivers +v0x55dd3f9dfe00_0 .net "in", 0 0, o0x7fc2ff3755d8; alias, 0 drivers +v0x55dd3f9dfa50_0 .net "p", 0 0, L_0x55dd3fb90c00; alias, 1 drivers +v0x55dd3f9dfaf0_0 .net "reset", 0 0, o0x7fc2ff371b58; alias, 0 drivers +v0x55dd3f9dd170_0 .var "x", 1 0; +L_0x55dd3fb90920 .part v0x55dd3f9dd170_0, 0, 1; +L_0x55dd3fb909f0 .part v0x55dd3f9dd170_0, 1, 1; +L_0x55dd3fb90b10 .reduce/nor L_0x55dd3fb909f0; +S_0x55dd3f9c5d80 .scope module, "cmc_pg1" "pg" 4 166, 3 15 0, S_0x55dd3fafead0; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +L_0x55dd3fb90f90 .functor AND 1, L_0x55dd3fb90d10, L_0x55dd3fb90ea0, C4<1>, C4<1>; +v0x55dd3f9debf0_0 .net *"_s1", 0 0, L_0x55dd3fb90d10; 1 drivers +v0x55dd3f9decb0_0 .net *"_s3", 0 0, L_0x55dd3fb90db0; 1 drivers +v0x55dd3f9de830_0 .net *"_s5", 0 0, L_0x55dd3fb90ea0; 1 drivers +v0x55dd3f9de3f0_0 .net "clk", 0 0, o0x7fc2ff371a98; alias, 0 drivers +v0x55dd3f9de490_0 .net "in", 0 0, L_0x55dd3fb910f0; 1 drivers +v0x55dd3f9dbac0_0 .net "p", 0 0, L_0x55dd3fb90f90; alias, 1 drivers +v0x55dd3f9dbb80_0 .net "reset", 0 0, o0x7fc2ff371b58; alias, 0 drivers +v0x55dd3f9d6e80_0 .var "x", 1 0; +L_0x55dd3fb90d10 .part v0x55dd3f9d6e80_0, 0, 1; +L_0x55dd3fb90db0 .part v0x55dd3f9d6e80_0, 1, 1; +L_0x55dd3fb90ea0 .reduce/nor L_0x55dd3fb90db0; +S_0x55dd3f9c7880 .scope module, "cmc_pg2" "pg" 4 168, 3 15 0, S_0x55dd3fafead0; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +L_0x55dd3fb91440 .functor AND 1, L_0x55dd3fb91160, L_0x55dd3fb91350, C4<1>, C4<1>; +v0x55dd3f9cab20_0 .net *"_s1", 0 0, L_0x55dd3fb91160; 1 drivers +v0x55dd3f98acf0_0 .net *"_s3", 0 0, L_0x55dd3fb91230; 1 drivers +v0x55dd3f98a850_0 .net *"_s5", 0 0, L_0x55dd3fb91350; 1 drivers +v0x55dd3f98a410_0 .net "clk", 0 0, o0x7fc2ff371a98; alias, 0 drivers +v0x55dd3f98a4b0_0 .net "in", 0 0, L_0x55dd3fb91850; 1 drivers +v0x55dd3f96fc70_0 .net "p", 0 0, L_0x55dd3fb91440; alias, 1 drivers +v0x55dd3f96fd10_0 .net "reset", 0 0, o0x7fc2ff371b58; alias, 0 drivers +v0x55dd3f91eab0_0 .var "x", 1 0; +L_0x55dd3fb91160 .part v0x55dd3f91eab0_0, 0, 1; +L_0x55dd3fb91230 .part v0x55dd3f91eab0_0, 1, 1; +L_0x55dd3fb91350 .reduce/nor L_0x55dd3fb91230; +S_0x55dd3f9c92b0 .scope module, "cmc_pg4" "pg" 4 171, 3 15 0, S_0x55dd3fafead0; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +L_0x55dd3fb91cd0 .functor AND 1, L_0x55dd3fb91a50, L_0x55dd3fb91be0, C4<1>, C4<1>; +v0x55dd3f9175b0_0 .net *"_s1", 0 0, L_0x55dd3fb91a50; 1 drivers +v0x55dd3f9170b0_0 .net *"_s3", 0 0, L_0x55dd3fb91af0; 1 drivers +v0x55dd3f916c70_0 .net *"_s5", 0 0, L_0x55dd3fb91be0; 1 drivers +v0x55dd3f916d10_0 .net "clk", 0 0, o0x7fc2ff371a98; alias, 0 drivers +v0x55dd3f9167d0_0 .net "in", 0 0, L_0x55dd3fb8e050; alias, 1 drivers +v0x55dd3f96a300_0 .net "p", 0 0, L_0x55dd3fb91cd0; alias, 1 drivers +v0x55dd3f96a3c0_0 .net "reset", 0 0, o0x7fc2ff371b58; alias, 0 drivers +v0x55dd3f922430_0 .var "x", 1 0; +L_0x55dd3fb91a50 .part v0x55dd3f922430_0, 0, 1; +L_0x55dd3fb91af0 .part v0x55dd3f922430_0, 1, 1; +L_0x55dd3fb91be0 .reduce/nor L_0x55dd3fb91af0; +S_0x55dd3f95d140 .scope module, "cmc_pg5" "pg" 4 172, 3 15 0, S_0x55dd3fafead0; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +L_0x55dd3fb920b0 .functor AND 1, L_0x55dd3fb91e30, L_0x55dd3fb91fc0, C4<1>, C4<1>; +v0x55dd3f921ff0_0 .net *"_s1", 0 0, L_0x55dd3fb91e30; 1 drivers +v0x55dd3f9212a0_0 .net *"_s3", 0 0, L_0x55dd3fb91ed0; 1 drivers +v0x55dd3f920e60_0 .net *"_s5", 0 0, L_0x55dd3fb91fc0; 1 drivers +v0x55dd3f920110_0 .net "clk", 0 0, o0x7fc2ff371a98; alias, 0 drivers +v0x55dd3f9201b0_0 .net "in", 0 0, v0x55dd3fb05050_0; 1 drivers +v0x55dd3f91fcd0_0 .net "p", 0 0, L_0x55dd3fb920b0; alias, 1 drivers +v0x55dd3f91fd90_0 .net "reset", 0 0, o0x7fc2ff371b58; alias, 0 drivers +v0x55dd3f91ef20_0 .var "x", 1 0; +L_0x55dd3fb91e30 .part v0x55dd3f91ef20_0, 0, 1; +L_0x55dd3fb91ed0 .part v0x55dd3f91ef20_0, 1, 1; +L_0x55dd3fb91fc0 .reduce/nor L_0x55dd3fb91ed0; +S_0x55dd3f9670e0 .scope module, "cmc_pg6" "pg" 4 173, 3 15 0, S_0x55dd3fafead0; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +L_0x55dd3fb92490 .functor AND 1, L_0x55dd3fb92210, L_0x55dd3fb923a0, C4<1>, C4<1>; +v0x55dd3fa4df60_0 .net *"_s1", 0 0, L_0x55dd3fb92210; 1 drivers +v0x55dd3fa845c0_0 .net *"_s3", 0 0, L_0x55dd3fb922b0; 1 drivers +v0x55dd3f998bc0_0 .net *"_s5", 0 0, L_0x55dd3fb923a0; 1 drivers +v0x55dd3f998c60_0 .net "clk", 0 0, o0x7fc2ff371a98; alias, 0 drivers +v0x55dd3f965640_0 .net "in", 0 0, L_0x55dd3fb925f0; 1 drivers +v0x55dd3f963c10_0 .net "p", 0 0, L_0x55dd3fb92490; alias, 1 drivers +v0x55dd3f963cd0_0 .net "reset", 0 0, o0x7fc2ff371b58; alias, 0 drivers +v0x55dd3f962110_0 .var "x", 1 0; +L_0x55dd3fb92210 .part v0x55dd3f962110_0, 0, 1; +L_0x55dd3fb922b0 .part v0x55dd3f962110_0, 1, 1; +L_0x55dd3fb923a0 .reduce/nor L_0x55dd3fb922b0; +S_0x55dd3faf4800 .scope module, "core164" "core164" 6 1; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "power" + .port_info 3 /INPUT 1 "sw_single_step" + .port_info 4 /INPUT 1 "sw_restart" + .port_info 5 /INPUT 1 "membus_wr_rs_p0" + .port_info 6 /INPUT 1 "membus_rq_cyc_p0" + .port_info 7 /INPUT 1 "membus_rd_rq_p0" + .port_info 8 /INPUT 1 "membus_wr_rq_p0" + .port_info 9 /INPUT 15 "membus_ma_p0" + .port_info 10 /INPUT 4 "membus_sel_p0" + .port_info 11 /INPUT 1 "membus_fmc_select_p0" + .port_info 12 /INPUT 36 "membus_mb_in_p0" + .port_info 13 /OUTPUT 1 "membus_addr_ack_p0" + .port_info 14 /OUTPUT 1 "membus_rd_rs_p0" + .port_info 15 /OUTPUT 36 "membus_mb_out_p0" + .port_info 16 /INPUT 1 "membus_wr_rs_p1" + .port_info 17 /INPUT 1 "membus_rq_cyc_p1" + .port_info 18 /INPUT 1 "membus_rd_rq_p1" + .port_info 19 /INPUT 1 "membus_wr_rq_p1" + .port_info 20 /INPUT 15 "membus_ma_p1" + .port_info 21 /INPUT 4 "membus_sel_p1" + .port_info 22 /INPUT 1 "membus_fmc_select_p1" + .port_info 23 /INPUT 36 "membus_mb_in_p1" + .port_info 24 /OUTPUT 1 "membus_addr_ack_p1" + .port_info 25 /OUTPUT 1 "membus_rd_rs_p1" + .port_info 26 /OUTPUT 36 "membus_mb_out_p1" + .port_info 27 /INPUT 1 "membus_wr_rs_p2" + .port_info 28 /INPUT 1 "membus_rq_cyc_p2" + .port_info 29 /INPUT 1 "membus_rd_rq_p2" + .port_info 30 /INPUT 1 "membus_wr_rq_p2" + .port_info 31 /INPUT 15 "membus_ma_p2" + .port_info 32 /INPUT 4 "membus_sel_p2" + .port_info 33 /INPUT 1 "membus_fmc_select_p2" + .port_info 34 /INPUT 36 "membus_mb_in_p2" + .port_info 35 /OUTPUT 1 "membus_addr_ack_p2" + .port_info 36 /OUTPUT 1 "membus_rd_rs_p2" + .port_info 37 /OUTPUT 36 "membus_mb_out_p2" + .port_info 38 /INPUT 1 "membus_wr_rs_p3" + .port_info 39 /INPUT 1 "membus_rq_cyc_p3" + .port_info 40 /INPUT 1 "membus_rd_rq_p3" + .port_info 41 /INPUT 1 "membus_wr_rq_p3" + .port_info 42 /INPUT 15 "membus_ma_p3" + .port_info 43 /INPUT 4 "membus_sel_p3" + .port_info 44 /INPUT 1 "membus_fmc_select_p3" + .port_info 45 /INPUT 36 "membus_mb_in_p3" + .port_info 46 /OUTPUT 1 "membus_addr_ack_p3" + .port_info 47 /OUTPUT 1 "membus_rd_rs_p3" + .port_info 48 /OUTPUT 36 "membus_mb_out_p3" + .port_info 49 /OUTPUT 18 "m_address" + .port_info 50 /OUTPUT 1 "m_write" + .port_info 51 /OUTPUT 1 "m_read" + .port_info 52 /OUTPUT 36 "m_writedata" + .port_info 53 /INPUT 36 "m_readdata" + .port_info 54 /INPUT 1 "m_waitrequest" +P_0x55dd3fb04490 .param/l "memsel_p0" 0 6 65, C4<0000>; +P_0x55dd3fb044d0 .param/l "memsel_p1" 0 6 66, C4<0000>; +P_0x55dd3fb04510 .param/l "memsel_p2" 0 6 67, C4<0000>; +P_0x55dd3fb04550 .param/l "memsel_p3" 0 6 68, C4<0000>; +o0x7fc2ff37d9a8 .functor BUFZ 1, C4; HiZ drive +L_0x55dd3fb9a350 .functor NOT 1, o0x7fc2ff37d9a8, C4<0>, C4<0>, C4<0>; +L_0x55dd3fb9a3c0 .functor AND 1, L_0x55dd3fb9a260, L_0x55dd3fb9a350, C4<1>, C4<1>; +o0x7fc2ff37de28 .functor BUFZ 1, C4; HiZ drive +L_0x55dd3fb9a500 .functor AND 1, L_0x55dd3fb9a3c0, o0x7fc2ff37de28, C4<1>, C4<1>; +L_0x55dd3fb9a5c0 .functor AND 1, L_0x55dd3fb9a500, v0x55dd3f6a6710_0, C4<1>, C4<1>; +o0x7fc2ff37d9d8 .functor BUFZ 1, C4; HiZ drive +L_0x55dd3fb9a800 .functor NOT 1, o0x7fc2ff37d9d8, C4<0>, C4<0>, C4<0>; +L_0x55dd3fb9a8a0 .functor AND 1, L_0x55dd3fb9a6b0, L_0x55dd3fb9a800, C4<1>, C4<1>; +o0x7fc2ff37de58 .functor BUFZ 1, C4; HiZ drive +L_0x55dd3fb9aa20 .functor AND 1, L_0x55dd3fb9a8a0, o0x7fc2ff37de58, C4<1>, C4<1>; +L_0x55dd3fb9aae0 .functor AND 1, L_0x55dd3fb9aa20, v0x55dd3f6a6710_0, C4<1>, C4<1>; +o0x7fc2ff37da08 .functor BUFZ 1, C4; HiZ drive +L_0x55dd3fb9ad30 .functor NOT 1, o0x7fc2ff37da08, C4<0>, C4<0>, C4<0>; +L_0x55dd3fb9add0 .functor AND 1, L_0x55dd3fb9ac40, L_0x55dd3fb9ad30, C4<1>, C4<1>; +o0x7fc2ff37de88 .functor BUFZ 1, C4; HiZ drive +L_0x55dd3fb9af70 .functor AND 1, L_0x55dd3fb9add0, o0x7fc2ff37de88, C4<1>, C4<1>; +L_0x55dd3fb9afe0 .functor AND 1, L_0x55dd3fb9af70, v0x55dd3f6a6710_0, C4<1>, C4<1>; +o0x7fc2ff37da38 .functor BUFZ 1, C4; HiZ drive +L_0x55dd3fb9b290 .functor NOT 1, o0x7fc2ff37da38, C4<0>, C4<0>, C4<0>; +L_0x55dd3fb9b330 .functor AND 1, L_0x55dd3fb9b110, L_0x55dd3fb9b290, C4<1>, C4<1>; +o0x7fc2ff37deb8 .functor BUFZ 1, C4; HiZ drive +L_0x55dd3fb9b0a0 .functor AND 1, L_0x55dd3fb9b330, o0x7fc2ff37deb8, C4<1>, C4<1>; +L_0x55dd3fb9b540 .functor AND 1, L_0x55dd3fb9b0a0, v0x55dd3f6a6710_0, C4<1>, C4<1>; +o0x7fc2ff37da68 .functor BUFZ 15, C4; HiZ drive +L_0x55dd3fb9b8f0 .functor AND 15, L_0x55dd3fb9b7c0, o0x7fc2ff37da68, C4<111111111111111>, C4<111111111111111>; +o0x7fc2ff37da98 .functor BUFZ 15, C4; HiZ drive +L_0x55dd3fb9bd20 .functor AND 15, L_0x55dd3fb9bbe0, o0x7fc2ff37da98, C4<111111111111111>, C4<111111111111111>; +L_0x55dd3fb9be80 .functor OR 15, L_0x55dd3fb9b8f0, L_0x55dd3fb9bd20, C4<000000000000000>, C4<000000000000000>; +o0x7fc2ff37dac8 .functor BUFZ 15, C4; HiZ drive +L_0x55dd3fb9c260 .functor AND 15, L_0x55dd3fb9c1c0, o0x7fc2ff37dac8, C4<111111111111111>, C4<111111111111111>; +L_0x55dd3fb9c3d0 .functor OR 15, L_0x55dd3fb9be80, L_0x55dd3fb9c260, C4<000000000000000>, C4<000000000000000>; +o0x7fc2ff37daf8 .functor BUFZ 15, C4; HiZ drive +L_0x55dd3fb9c850 .functor AND 15, L_0x55dd3fb9c6f0, o0x7fc2ff37daf8, C4<111111111111111>, C4<111111111111111>; +L_0x55dd3fb9c9d0 .functor OR 15, L_0x55dd3fb9c3d0, L_0x55dd3fb9c850, C4<000000000000000>, C4<000000000000000>; +o0x7fc2ff37dca8 .functor BUFZ 1, C4; HiZ drive +L_0x55dd3fb9cc00 .functor AND 1, L_0x55dd3fba5b70, o0x7fc2ff37dca8, C4<1>, C4<1>; +o0x7fc2ff37dcd8 .functor BUFZ 1, C4; HiZ drive +L_0x55dd3fb9cd40 .functor AND 1, L_0x55dd3fba5e10, o0x7fc2ff37dcd8, C4<1>, C4<1>; +L_0x55dd3fb9ce10 .functor OR 1, L_0x55dd3fb9cc00, L_0x55dd3fb9cd40, C4<0>, C4<0>; +o0x7fc2ff37dd08 .functor BUFZ 1, C4; HiZ drive +L_0x55dd3fb9d030 .functor AND 1, L_0x55dd3fba5e80, o0x7fc2ff37dd08, C4<1>, C4<1>; +L_0x55dd3fb9d0a0 .functor OR 1, L_0x55dd3fb9ce10, L_0x55dd3fb9d030, C4<0>, C4<0>; +o0x7fc2ff37dd38 .functor BUFZ 1, C4; HiZ drive +L_0x55dd3fb9d2d0 .functor AND 1, L_0x55dd3fba6130, o0x7fc2ff37dd38, C4<1>, C4<1>; +L_0x55dd3fb9d340 .functor OR 1, L_0x55dd3fb9d0a0, L_0x55dd3fb9d2d0, C4<0>, C4<0>; +o0x7fc2ff37dfa8 .functor BUFZ 1, C4; HiZ drive +L_0x55dd3fb9d550 .functor AND 1, L_0x55dd3fba5b70, o0x7fc2ff37dfa8, C4<1>, C4<1>; +o0x7fc2ff37dfd8 .functor BUFZ 1, C4; HiZ drive +L_0x55dd3fb9d7d0 .functor AND 1, L_0x55dd3fba5e10, o0x7fc2ff37dfd8, C4<1>, C4<1>; +L_0x55dd3fb9dbc0 .functor OR 1, L_0x55dd3fb9d550, L_0x55dd3fb9d7d0, C4<0>, C4<0>; +o0x7fc2ff37e008 .functor BUFZ 1, C4; HiZ drive +L_0x55dd3fb9dd00 .functor AND 1, L_0x55dd3fba5e80, o0x7fc2ff37e008, C4<1>, C4<1>; +L_0x55dd3fb9e0a0 .functor OR 1, L_0x55dd3fb9dbc0, L_0x55dd3fb9dd00, C4<0>, C4<0>; +o0x7fc2ff37e038 .functor BUFZ 1, C4; HiZ drive +L_0x55dd3fb9e1e0 .functor AND 1, L_0x55dd3fba6130, o0x7fc2ff37e038, C4<1>, C4<1>; +L_0x55dd3fb9df80 .functor OR 1, L_0x55dd3fb9e0a0, L_0x55dd3fb9e1e0, C4<0>, C4<0>; +o0x7fc2ff37db28 .functor BUFZ 36, C4; HiZ drive +L_0x55dd3fb9c790 .functor AND 36, L_0x55dd3fb9e5e0, o0x7fc2ff37db28, C4<111111111111111111111111111111111111>, C4<111111111111111111111111111111111111>; +o0x7fc2ff37db58 .functor BUFZ 36, C4; HiZ drive +L_0x55dd3fb9ed40 .functor AND 36, L_0x55dd3fb9e890, o0x7fc2ff37db58, C4<111111111111111111111111111111111111>, C4<111111111111111111111111111111111111>; +L_0x55dd3fb9edb0 .functor OR 36, L_0x55dd3fb9c790, L_0x55dd3fb9ed40, C4<000000000000000000000000000000000000>, C4<000000000000000000000000000000000000>; +o0x7fc2ff37db88 .functor BUFZ 36, C4; HiZ drive +L_0x55dd3fb9f4b0 .functor AND 36, L_0x55dd3fb9ef70, o0x7fc2ff37db88, C4<111111111111111111111111111111111111>, C4<111111111111111111111111111111111111>; +L_0x55dd3fb9f570 .functor OR 36, L_0x55dd3fb9edb0, L_0x55dd3fb9f4b0, C4<000000000000000000000000000000000000>, C4<000000000000000000000000000000000000>; +o0x7fc2ff37dbb8 .functor BUFZ 36, C4; HiZ drive +L_0x55dd3fb9fdc0 .functor AND 36, L_0x55dd3fb9f7e0, o0x7fc2ff37dbb8, C4<111111111111111111111111111111111111>, C4<111111111111111111111111111111111111>; +L_0x55dd3fb9feb0 .functor OR 36, L_0x55dd3fb9f570, L_0x55dd3fb9fdc0, C4<000000000000000000000000000000000000>, C4<000000000000000000000000000000000000>; +L_0x55dd3fba0450 .functor AND 1, L_0x55dd3fbaa160, L_0x55dd3fba5b70, C4<1>, C4<1>; +L_0x55dd3fba08a0 .functor AND 1, L_0x55dd3fbaa160, L_0x55dd3fba5e10, C4<1>, C4<1>; +L_0x55dd3fba0e20 .functor AND 1, L_0x55dd3fbaa160, L_0x55dd3fba5e80, C4<1>, C4<1>; +L_0x55dd3fba1270 .functor AND 1, L_0x55dd3fbaa160, L_0x55dd3fba6130, C4<1>, C4<1>; +L_0x55dd3fba1470 .functor AND 1, L_0x55dd3fbac0c0, L_0x55dd3fba5b70, C4<1>, C4<1>; +L_0x55dd3fba1530 .functor AND 1, L_0x55dd3fbac0c0, L_0x55dd3fba5e10, C4<1>, C4<1>; +L_0x55dd3fba1740 .functor AND 1, L_0x55dd3fbac0c0, L_0x55dd3fba5e80, C4<1>, C4<1>; +L_0x55dd3fba17b0 .functor AND 1, L_0x55dd3fbac0c0, L_0x55dd3fba6130, C4<1>, C4<1>; +L_0x55dd3fba19d0 .functor AND 1, L_0x55dd3fbabc20, L_0x55dd3fba5b70, C4<1>, C4<1>; +L_0x55dd3fba2180 .functor AND 36, v0x55dd3fb13600_0, L_0x55dd3fba1a40, C4<111111111111111111111111111111111111>, C4<111111111111111111111111111111111111>; +L_0x55dd3fba23e0 .functor AND 1, L_0x55dd3fbabc20, L_0x55dd3fba5e10, C4<1>, C4<1>; +L_0x55dd3fba2a60 .functor AND 36, v0x55dd3fb13600_0, L_0x55dd3fba2450, C4<111111111111111111111111111111111111>, C4<111111111111111111111111111111111111>; +L_0x55dd3fba2cf0 .functor AND 1, L_0x55dd3fbabc20, L_0x55dd3fba5e80, C4<1>, C4<1>; +L_0x55dd3fba3440 .functor AND 36, v0x55dd3fb13600_0, L_0x55dd3fba2d60, C4<111111111111111111111111111111111111>, C4<111111111111111111111111111111111111>; +L_0x55dd3fba3690 .functor AND 1, L_0x55dd3fbabc20, L_0x55dd3fba6130, C4<1>, C4<1>; +L_0x55dd3fba3cc0 .functor AND 36, v0x55dd3fb13600_0, L_0x55dd3fba20e0, C4<111111111111111111111111111111111111>, C4<111111111111111111111111111111111111>; +o0x7fc2ff37e068 .functor BUFZ 1, C4; HiZ drive +L_0x55dd3fba3f20 .functor AND 1, o0x7fc2ff37e068, L_0x55dd3fba5b70, C4<1>, C4<1>; +o0x7fc2ff37e098 .functor BUFZ 1, C4; HiZ drive +L_0x55dd3fba3fc0 .functor AND 1, o0x7fc2ff37e098, L_0x55dd3fba5e10, C4<1>, C4<1>; +L_0x55dd3fba4290 .functor OR 1, L_0x55dd3fba3f20, L_0x55dd3fba3fc0, C4<0>, C4<0>; +o0x7fc2ff37e0c8 .functor BUFZ 1, C4; HiZ drive +L_0x55dd3fba4380 .functor AND 1, o0x7fc2ff37e0c8, L_0x55dd3fba5e80, C4<1>, C4<1>; +L_0x55dd3fba4600 .functor OR 1, L_0x55dd3fba4290, L_0x55dd3fba4380, C4<0>, C4<0>; +o0x7fc2ff37e0f8 .functor BUFZ 1, C4; HiZ drive +L_0x55dd3fba4740 .functor AND 1, o0x7fc2ff37e0f8, L_0x55dd3fba6130, C4<1>, C4<1>; +L_0x55dd3fba49d0 .functor OR 1, L_0x55dd3fba4600, L_0x55dd3fba4740, C4<0>, C4<0>; +L_0x55dd3fba5b70 .functor BUFZ 1, v0x55dd3f766320_0, C4<0>, C4<0>, C4<0>; +L_0x55dd3fba5e10 .functor BUFZ 1, v0x55dd3f7664a0_0, C4<0>, C4<0>, C4<0>; +L_0x55dd3fba5e80 .functor BUFZ 1, v0x55dd3f766620_0, C4<0>, C4<0>, C4<0>; +L_0x55dd3fba6130 .functor BUFZ 1, v0x55dd3f787190_0, C4<0>, C4<0>, C4<0>; +L_0x55dd3fba61a0 .functor OR 1, v0x55dd3f766320_0, v0x55dd3f7664a0_0, C4<0>, C4<0>; +L_0x55dd3fba6530 .functor OR 1, L_0x55dd3fba61a0, v0x55dd3f766620_0, C4<0>, C4<0>; +L_0x55dd3fba6640 .functor OR 1, L_0x55dd3fba6530, v0x55dd3f787190_0, C4<0>, C4<0>; +L_0x55dd3fba69b0 .functor NOT 1, L_0x55dd3fba6640, C4<0>, C4<0>, C4<0>; +L_0x55dd3fba6a70 .functor AND 1, L_0x55dd3fbad860, L_0x55dd3fba69b0, C4<1>, C4<1>; +L_0x7fc2ff328f00 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x55dd3fba6df0 .functor NOT 1, L_0x7fc2ff328f00, C4<0>, C4<0>, C4<0>; +L_0x55dd3fba6eb0 .functor AND 1, L_0x55dd3fbad860, L_0x55dd3fba6df0, C4<1>, C4<1>; +L_0x55dd3fba71f0 .functor AND 1, L_0x55dd3fba6eb0, L_0x55dd3fba6640, C4<1>, C4<1>; +L_0x55dd3fba72b0 .functor BUFZ 1, L_0x55dd3fbaa160, C4<0>, C4<0>, C4<0>; +L_0x55dd3fba7940 .functor OR 1, L_0x55dd3fb9a5c0, L_0x55dd3fb9aae0, C4<0>, C4<0>; +L_0x55dd3fba7a50 .functor OR 1, L_0x55dd3fba7940, L_0x55dd3fb9afe0, C4<0>, C4<0>; +L_0x55dd3fba7e00 .functor OR 1, L_0x55dd3fba7a50, L_0x55dd3fb9b540, C4<0>, C4<0>; +L_0x55dd3fba82f0 .functor OR 1, L_0x55dd3fbad3e0, L_0x55dd3fba5a10, C4<0>, C4<0>; +L_0x55dd3fba8a40 .functor OR 1, L_0x55dd3fba8190, L_0x55dd3fbae8e0, C4<0>, C4<0>; +L_0x55dd3fba8e90 .functor OR 1, L_0x55dd3fba8190, L_0x55dd3fbaeb10, C4<0>, C4<0>; +L_0x55dd3fba9630 .functor NOT 1, v0x55dd3f6a64b0_0, C4<0>, C4<0>, C4<0>; +L_0x55dd3fba96a0 .functor AND 1, L_0x55dd3fbac450, L_0x55dd3fba9630, C4<1>, C4<1>; +L_0x55dd3fba9a30 .functor OR 1, L_0x55dd3fba8190, L_0x55dd3fba96a0, C4<0>, C4<0>; +L_0x55dd3fba9af0 .functor OR 1, L_0x55dd3fba9a30, L_0x55dd3fbad050, C4<0>, C4<0>; +L_0x55dd3fbaa270 .functor AND 1, v0x55dd3f7d4aa0_0, v0x55dd3f819c00_0, C4<1>, C4<1>; +L_0x55dd3fbaade0 .functor AND 1, L_0x55dd3fbae430, v0x55dd3f6acee0_0, C4<1>, C4<1>; +L_0x55dd3fbab190 .functor AND 1, L_0x55dd3fbaade0, v0x55dd3f6a64b0_0, C4<1>, C4<1>; +L_0x55dd3fbab2a0 .functor OR 1, L_0x55dd3fbaa160, L_0x55dd3fbab190, C4<0>, C4<0>; +L_0x55dd3fbabd30 .functor AND 1, L_0x55dd3fbae200, v0x55dd3f6acee0_0, C4<1>, C4<1>; +L_0x55dd3fbac560 .functor NOT 1, v0x55dd3f6a64b0_0, C4<0>, C4<0>, C4<0>; +L_0x55dd3fbac8e0 .functor OR 1, v0x55dd3f7873d0_0, L_0x55dd3fbac560, C4<0>, C4<0>; +L_0x55dd3fbac9f0 .functor AND 1, v0x55dd3f7dd8b0_0, L_0x55dd3fbac8e0, C4<1>, C4<1>; +L_0x55dd3fbaf140 .functor BUFZ 36, v0x55dd3f6a6570_0, C4<000000000000000000000000000000000000>, C4<000000000000000000000000000000000000>, C4<000000000000000000000000000000000000>; +v0x55dd3fb008e0_0 .net *"_s10", 0 0, L_0x55dd3fb9a500; 1 drivers +v0x55dd3fb009c0_0 .net *"_s100", 0 0, L_0x55dd3fb9d2d0; 1 drivers +v0x55dd3fac5e30_0 .net *"_s104", 0 0, L_0x55dd3fb9d550; 1 drivers +v0x55dd3fac5ef0_0 .net *"_s106", 0 0, L_0x55dd3fb9d7d0; 1 drivers +v0x55dd3fa355d0_0 .net *"_s108", 0 0, L_0x55dd3fb9dbc0; 1 drivers +v0x55dd3fa35700_0 .net *"_s110", 0 0, L_0x55dd3fb9dd00; 1 drivers +v0x55dd3fa31b40_0 .net *"_s112", 0 0, L_0x55dd3fb9e0a0; 1 drivers +v0x55dd3fa31c00_0 .net *"_s114", 0 0, L_0x55dd3fb9e1e0; 1 drivers +v0x55dd3f97ad30_0 .net *"_s118", 35 0, L_0x55dd3fb9e5e0; 1 drivers +v0x55dd3f97ae10_0 .net *"_s120", 35 0, L_0x55dd3fb9c790; 1 drivers +v0x55dd3f705e80_0 .net *"_s122", 35 0, L_0x55dd3fb9e890; 1 drivers +v0x55dd3f705f60_0 .net *"_s124", 35 0, L_0x55dd3fb9ed40; 1 drivers +v0x55dd3f706040_0 .net *"_s126", 35 0, L_0x55dd3fb9edb0; 1 drivers +v0x55dd3f706120_0 .net *"_s128", 35 0, L_0x55dd3fb9ef70; 1 drivers +v0x55dd3f706200_0 .net *"_s130", 35 0, L_0x55dd3fb9f4b0; 1 drivers +v0x55dd3f735960_0 .net *"_s132", 35 0, L_0x55dd3fb9f570; 1 drivers +v0x55dd3f735a20_0 .net *"_s134", 35 0, L_0x55dd3fb9f7e0; 1 drivers +v0x55dd3f735b00_0 .net *"_s136", 35 0, L_0x55dd3fb9fdc0; 1 drivers +L_0x7fc2ff328f90 .functor BUFT 1, C4<0000>, C4<0>, C4<0>, C4<0>; +v0x55dd3f735be0_0 .net/2u *"_s14", 3 0, L_0x7fc2ff328f90; 1 drivers +v0x55dd3f735cc0_0 .net *"_s156", 0 0, L_0x55dd3fba19d0; 1 drivers +v0x55dd3f7b8340_0 .net *"_s158", 35 0, L_0x55dd3fba1a40; 1 drivers +v0x55dd3f7b8420_0 .net *"_s16", 0 0, L_0x55dd3fb9a6b0; 1 drivers +v0x55dd3f7b84e0_0 .net *"_s162", 0 0, L_0x55dd3fba23e0; 1 drivers +v0x55dd3f7b85c0_0 .net *"_s164", 35 0, L_0x55dd3fba2450; 1 drivers +v0x55dd3f7b86a0_0 .net *"_s168", 0 0, L_0x55dd3fba2cf0; 1 drivers +v0x55dd3f7db340_0 .net *"_s170", 35 0, L_0x55dd3fba2d60; 1 drivers +v0x55dd3f7db400_0 .net *"_s174", 0 0, L_0x55dd3fba3690; 1 drivers +v0x55dd3f7db4e0_0 .net *"_s176", 35 0, L_0x55dd3fba20e0; 1 drivers +v0x55dd3f7db5c0_0 .net *"_s18", 0 0, L_0x55dd3fb9a800; 1 drivers +v0x55dd3f7db6a0_0 .net *"_s180", 0 0, L_0x55dd3fba3f20; 1 drivers +v0x55dd3f7ba770_0 .net *"_s182", 0 0, L_0x55dd3fba3fc0; 1 drivers +v0x55dd3f7ba850_0 .net *"_s184", 0 0, L_0x55dd3fba4290; 1 drivers +v0x55dd3f7ba930_0 .net *"_s186", 0 0, L_0x55dd3fba4380; 1 drivers +v0x55dd3f7baa10_0 .net *"_s188", 0 0, L_0x55dd3fba4600; 1 drivers +v0x55dd3f7baaf0_0 .net *"_s190", 0 0, L_0x55dd3fba4740; 1 drivers +L_0x7fc2ff328f48 .functor BUFT 1, C4<0000>, C4<0>, C4<0>, C4<0>; +v0x55dd3f7ced70_0 .net/2u *"_s2", 3 0, L_0x7fc2ff328f48; 1 drivers +v0x55dd3f7cee50_0 .net *"_s20", 0 0, L_0x55dd3fb9a8a0; 1 drivers +v0x55dd3f7cef30_0 .net *"_s202", 0 0, L_0x55dd3fba61a0; 1 drivers +v0x55dd3f7cf010_0 .net *"_s204", 0 0, L_0x55dd3fba6530; 1 drivers +v0x55dd3f7cf0f0_0 .net *"_s208", 0 0, L_0x55dd3fba69b0; 1 drivers +v0x55dd3f7bcba0_0 .net *"_s212", 0 0, L_0x55dd3fba6df0; 1 drivers +v0x55dd3f7bcc60_0 .net *"_s214", 0 0, L_0x55dd3fba6eb0; 1 drivers +v0x55dd3f7bcd40_0 .net *"_s22", 0 0, L_0x55dd3fb9aa20; 1 drivers +v0x55dd3f7bce20_0 .net *"_s220", 0 0, L_0x55dd3fba7940; 1 drivers +v0x55dd3f7bcf00_0 .net *"_s222", 0 0, L_0x55dd3fba7a50; 1 drivers +v0x55dd3f7bf020_0 .net *"_s232", 0 0, L_0x55dd3fba9630; 1 drivers +v0x55dd3f7bf100_0 .net *"_s234", 0 0, L_0x55dd3fba96a0; 1 drivers +v0x55dd3f7bf1e0_0 .net *"_s236", 0 0, L_0x55dd3fba9a30; 1 drivers +v0x55dd3f7bf2c0_0 .net *"_s242", 0 0, L_0x55dd3fbaade0; 1 drivers +v0x55dd3f7c1430_0 .net *"_s244", 0 0, L_0x55dd3fbab190; 1 drivers +v0x55dd3f7c1510_0 .net *"_s250", 0 0, L_0x55dd3fbac560; 1 drivers +v0x55dd3f7c15f0_0 .net *"_s252", 0 0, L_0x55dd3fbac8e0; 1 drivers +L_0x7fc2ff3298d8 .functor BUFT 1, C4<0000>, C4<0>, C4<0>, C4<0>; +v0x55dd3f7c16d0_0 .net/2u *"_s258", 3 0, L_0x7fc2ff3298d8; 1 drivers +L_0x7fc2ff328fd8 .functor BUFT 1, C4<0000>, C4<0>, C4<0>, C4<0>; +v0x55dd3f7c17b0_0 .net/2u *"_s26", 3 0, L_0x7fc2ff328fd8; 1 drivers +v0x55dd3f7c3860_0 .net *"_s28", 0 0, L_0x55dd3fb9ac40; 1 drivers +v0x55dd3f7c3920_0 .net *"_s30", 0 0, L_0x55dd3fb9ad30; 1 drivers +v0x55dd3f7c3a00_0 .net *"_s32", 0 0, L_0x55dd3fb9add0; 1 drivers +v0x55dd3f7c3ae0_0 .net *"_s34", 0 0, L_0x55dd3fb9af70; 1 drivers +L_0x7fc2ff329020 .functor BUFT 1, C4<0000>, C4<0>, C4<0>, C4<0>; +v0x55dd3f7c3bc0_0 .net/2u *"_s38", 3 0, L_0x7fc2ff329020; 1 drivers +v0x55dd3f7c5c90_0 .net *"_s4", 0 0, L_0x55dd3fb9a260; 1 drivers +v0x55dd3f7c5d30_0 .net *"_s40", 0 0, L_0x55dd3fb9b110; 1 drivers +v0x55dd3f7c5df0_0 .net *"_s42", 0 0, L_0x55dd3fb9b290; 1 drivers +v0x55dd3f7c5ed0_0 .net *"_s44", 0 0, L_0x55dd3fb9b330; 1 drivers +v0x55dd3f7c5fb0_0 .net *"_s46", 0 0, L_0x55dd3fb9b0a0; 1 drivers +v0x55dd3f7b3ae0_0 .net *"_s50", 13 0, L_0x55dd3fb9b690; 1 drivers +v0x55dd3f7b3ba0_0 .net *"_s52", 14 0, L_0x55dd3fb9b7c0; 1 drivers +L_0x7fc2ff329068 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +v0x55dd3f7b3c80_0 .net *"_s55", 0 0, L_0x7fc2ff329068; 1 drivers +v0x55dd3f7b3d60_0 .net *"_s56", 14 0, L_0x55dd3fb9b8f0; 1 drivers +v0x55dd3f7b3e40_0 .net *"_s58", 13 0, L_0x55dd3fb9b9b0; 1 drivers +v0x55dd3f7c80e0_0 .net *"_s6", 0 0, L_0x55dd3fb9a350; 1 drivers +v0x55dd3f7c81c0_0 .net *"_s60", 14 0, L_0x55dd3fb9bbe0; 1 drivers +L_0x7fc2ff3290b0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +v0x55dd3f7c82a0_0 .net *"_s63", 0 0, L_0x7fc2ff3290b0; 1 drivers +v0x55dd3f7c8380_0 .net *"_s64", 14 0, L_0x55dd3fb9bd20; 1 drivers +v0x55dd3f7b5f10_0 .net *"_s66", 14 0, L_0x55dd3fb9be80; 1 drivers +v0x55dd3f7b5ff0_0 .net *"_s68", 13 0, L_0x55dd3fb9bfc0; 1 drivers +v0x55dd3f7b60d0_0 .net *"_s70", 14 0, L_0x55dd3fb9c1c0; 1 drivers +L_0x7fc2ff3290f8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +v0x55dd3f7b61b0_0 .net *"_s73", 0 0, L_0x7fc2ff3290f8; 1 drivers +v0x55dd3f7b6290_0 .net *"_s74", 14 0, L_0x55dd3fb9c260; 1 drivers +v0x55dd3f7ca4f0_0 .net *"_s76", 14 0, L_0x55dd3fb9c3d0; 1 drivers +v0x55dd3f7ca5d0_0 .net *"_s78", 13 0, L_0x55dd3fb9bde0; 1 drivers +v0x55dd3f7ca6b0_0 .net *"_s8", 0 0, L_0x55dd3fb9a3c0; 1 drivers +v0x55dd3f7ca790_0 .net *"_s80", 14 0, L_0x55dd3fb9c6f0; 1 drivers +L_0x7fc2ff329140 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +v0x55dd3f7ca870_0 .net *"_s83", 0 0, L_0x7fc2ff329140; 1 drivers +v0x55dd3f7cc930_0 .net *"_s84", 14 0, L_0x55dd3fb9c850; 1 drivers +v0x55dd3f7cca10_0 .net *"_s86", 14 0, L_0x55dd3fb9c9d0; 1 drivers +v0x55dd3f7ccaf0_0 .net *"_s90", 0 0, L_0x55dd3fb9cc00; 1 drivers +v0x55dd3f7ccbd0_0 .net *"_s92", 0 0, L_0x55dd3fb9cd40; 1 drivers +v0x55dd3f7cccb0_0 .net *"_s94", 0 0, L_0x55dd3fb9ce10; 1 drivers +v0x55dd3f6acba0_0 .net *"_s96", 0 0, L_0x55dd3fb9d030; 1 drivers +v0x55dd3f6acc80_0 .net *"_s98", 0 0, L_0x55dd3fb9d0a0; 1 drivers +o0x7fc2ff378458 .functor BUFZ 1, C4; HiZ drive +v0x55dd3f6acd60_0 .net "clk", 0 0, o0x7fc2ff378458; 0 drivers +v0x55dd3f6ace00_0 .var "cma", 22 35; +v0x55dd3f6acee0_0 .var "cma_rd_rq", 0 0; +v0x55dd3f6a64b0_0 .var "cma_wr_rq", 0 0; +v0x55dd3f6a6570_0 .var "cmb", 0 35; +v0x55dd3f6a6650_0 .net "cmc_aw_rq_set", 0 0, L_0x55dd3fba6a70; 1 drivers +v0x55dd3f6a6710_0 .var "cmc_await_rq", 0 0; +v0x55dd3f6a67d0_0 .net "cmc_await_rq_reset", 0 0, v0x55dd3fa63330_0; 1 drivers +v0x55dd3f819b30_0 .net "cmc_cmb_clr", 0 0, L_0x55dd3fbaac80; 1 drivers +v0x55dd3f819c00_0 .var "cmc_cyc_done", 0 0; +v0x55dd3f819ca0_0 .var "cmc_inh", 0 0; +v0x55dd3f819d60_0 .net "cmc_jam_cma", 0 0, L_0x55dd3fba72b0; 1 drivers +v0x55dd3f819e20_0 .var "cmc_last_proc", 0 0; +v0x55dd3f766320_0 .var "cmc_p0_act", 0 0; +v0x55dd3f7663e0_0 .net "cmc_p0_sel", 0 0, L_0x55dd3fba5b70; 1 drivers +v0x55dd3f7664a0_0 .var "cmc_p1_act", 0 0; +v0x55dd3f766560_0 .net "cmc_p1_sel", 0 0, L_0x55dd3fba5e10; 1 drivers +v0x55dd3f766620_0 .var "cmc_p2_act", 0 0; +v0x55dd3f7870d0_0 .net "cmc_p2_sel", 0 0, L_0x55dd3fba5e80; 1 drivers +v0x55dd3f787190_0 .var "cmc_p3_act", 0 0; +v0x55dd3f787250_0 .net "cmc_p3_sel", 0 0, L_0x55dd3fba6130; 1 drivers +v0x55dd3f787310_0 .net "cmc_pn_act", 0 0, L_0x55dd3fba6640; 1 drivers +v0x55dd3f7873d0_0 .var "cmc_proc_rs", 0 0; +v0x55dd3f7dd7e0_0 .net "cmc_proc_rs_pulse", 0 0, L_0x55dd3fbad050; 1 drivers +v0x55dd3f7dd8b0_0 .var "cmc_pse_sync", 0 0; +v0x55dd3f7dd950_0 .net "cmc_pse_sync_set", 0 0, L_0x55dd3fbadf80; 1 drivers +v0x55dd3f7dda20_0 .net "cmc_pwr_clr", 0 0, v0x55dd3fa91680_0; 1 drivers +v0x55dd3f7ddaf0_0 .net "cmc_pwr_start", 0 0, L_0x55dd3fba5a10; 1 drivers +v0x55dd3f7d4790_0 .net "cmc_rd_rs", 0 0, L_0x55dd3fbac0c0; 1 drivers +v0x55dd3f7d4860_0 .var "cmc_read", 0 0; +v0x55dd3f7d4900_0 .net "cmc_read_off", 0 0, L_0x55dd3fbadd00; 1 drivers +v0x55dd3f7d49d0_0 .net "cmc_restart", 0 0, L_0x55dd3fbad3e0; 1 drivers +v0x55dd3f7d4aa0_0 .var "cmc_rq_sync", 0 0; +v0x55dd3f7d11b0_0 .net "cmc_rq_sync_set", 0 0, L_0x55dd3fba71f0; 1 drivers +v0x55dd3f7d1250_0 .net "cmc_sp", 0 0, L_0x7fc2ff328f00; 1 drivers +v0x55dd3f7d12f0_0 .net "cmc_start", 0 0, L_0x55dd3fba8190; 1 drivers +v0x55dd3f7d13c0_0 .net "cmc_state_clr", 0 0, L_0x55dd3fba94d0; 1 drivers +v0x55dd3f7d1490_0 .var "cmc_stop", 0 0; +v0x55dd3f7d1530_0 .net "cmc_t0", 0 0, L_0x55dd3fba7830; 1 drivers +v0x55dd3f7d7d80_0 .net "cmc_t0_D", 0 0, L_0x55dd3fbad860; 1 drivers +v0x55dd3f7d7e20_0 .net "cmc_t1a", 0 0, L_0x55dd3fbaa8f0; 1 drivers +v0x55dd3f7d7ec0_0 .net "cmc_t1a_D1", 0 0, L_0x55dd3fbadad0; 1 drivers +v0x55dd3f7d7f60_0 .net "cmc_t1b", 0 0, L_0x55dd3fbaa160; 1 drivers +v0x55dd3f7d8050_0 .net "cmc_t1b_D", 0 0, L_0x55dd3fbaa560; 1 drivers +v0x55dd3f6c7f80_0 .net "cmc_t2", 0 0, L_0x55dd3fbab8e0; 1 drivers +v0x55dd3f6c8020_0 .net "cmc_t2_D1", 0 0, L_0x55dd3fbae200; 1 drivers +v0x55dd3f6c80c0_0 .net "cmc_t2_D2", 0 0, L_0x55dd3fbae430; 1 drivers +v0x55dd3f6c8160_0 .net "cmc_t3", 0 0, L_0x55dd3fbac450; 1 drivers +v0x55dd3f6c8200_0 .net "cmc_t3_D1", 0 0, L_0x55dd3fbae8e0; 1 drivers +v0x55dd3f6c82a0_0 .net "cmc_t3_D2", 0 0, L_0x55dd3fbaeb10; 1 drivers +v0x55dd3f6bde60_0 .net "cmc_t4", 0 0, L_0x55dd3fbae660; 1 drivers +v0x55dd3f6bdf00_0 .net "cmc_t5", 0 0, L_0x55dd3fba88e0; 1 drivers +v0x55dd3f6bdfd0_0 .net "cmc_t6", 0 0, L_0x55dd3fbad5e0; 1 drivers +v0x55dd3f6be0a0_0 .net "cmc_t6p", 0 0, L_0x55dd3fba8d80; 1 drivers +v0x55dd3f6be140_0 .var "cmc_write", 0 0; +v0x55dd3f6be1e0_0 .net "cmpc_p0_rq", 0 0, L_0x55dd3fb9a5c0; 1 drivers +v0x55dd3f6a7f80_0 .net "cmpc_p1_rq", 0 0, L_0x55dd3fb9aae0; 1 drivers +v0x55dd3f6a8020_0 .net "cmpc_p2_rq", 0 0, L_0x55dd3fb9afe0; 1 drivers +v0x55dd3f6a80c0_0 .net "cmpc_p3_rq", 0 0, L_0x55dd3fb9b540; 1 drivers +v0x55dd3f6a8160_0 .net "cmpc_rs_set", 0 0, L_0x55dd3fba49d0; 1 drivers +v0x55dd3f6a8200_0 .net "cmpc_rs_set_D", 0 0, L_0x55dd3fbaed40; 1 drivers +v0x55dd3f6a82a0_0 .net "core_addr", 13 0, v0x55dd3f6ace00_0; 1 drivers +v0x55dd3f7e3f70_0 .net "m_address", 17 0, L_0x55dd3fbaef40; 1 drivers +v0x55dd3f7e4010_0 .var "m_read", 0 0; +o0x7fc2ff37d888 .functor BUFZ 36, C4; HiZ drive +v0x55dd3f7e40b0_0 .net "m_readdata", 35 0, o0x7fc2ff37d888; 0 drivers +o0x7fc2ff37d8b8 .functor BUFZ 1, C4; HiZ drive +v0x55dd3f7e4150_0 .net "m_waitrequest", 0 0, o0x7fc2ff37d8b8; 0 drivers +v0x55dd3f7e41f0_0 .var "m_write", 0 0; +v0x55dd3f7e42b0_0 .net "m_writedata", 35 0, L_0x55dd3fbaf140; 1 drivers +v0x55dd3f7e8700_0 .net "ma_in", 22 35, L_0x55dd3fb9cb10; 1 drivers +v0x55dd3f7e87e0_0 .net "mb_in", 0 35, L_0x55dd3fb9feb0; 1 drivers +v0x55dd3f7e88c0_0 .net "membus_addr_ack_p0", 0 0, L_0x55dd3fba02f0; 1 drivers +v0x55dd3f7e8990_0 .net "membus_addr_ack_p1", 0 0, L_0x55dd3fba0740; 1 drivers +v0x55dd3f7e8a60_0 .net "membus_addr_ack_p2", 0 0, L_0x55dd3fba0cc0; 1 drivers +v0x55dd3f7ecf30_0 .net "membus_addr_ack_p3", 0 0, L_0x55dd3fba1110; 1 drivers +v0x55dd3f7ed000_0 .net "membus_fmc_select_p0", 0 0, o0x7fc2ff37d9a8; 0 drivers +v0x55dd3f7ed0a0_0 .net "membus_fmc_select_p1", 0 0, o0x7fc2ff37d9d8; 0 drivers +v0x55dd3f7ed140_0 .net "membus_fmc_select_p2", 0 0, o0x7fc2ff37da08; 0 drivers +v0x55dd3f7ed1e0_0 .net "membus_fmc_select_p3", 0 0, o0x7fc2ff37da38; 0 drivers +v0x55dd3f7ed280_0 .net "membus_ma_p0", 21 35, o0x7fc2ff37da68; 0 drivers +v0x55dd3f7e0e30_0 .net "membus_ma_p1", 21 35, o0x7fc2ff37da98; 0 drivers +v0x55dd3f7e0ef0_0 .net "membus_ma_p2", 21 35, o0x7fc2ff37dac8; 0 drivers +v0x55dd3f7e0fd0_0 .net "membus_ma_p3", 21 35, o0x7fc2ff37daf8; 0 drivers +v0x55dd3f7e10b0_0 .net "membus_mb_in_p0", 0 35, o0x7fc2ff37db28; 0 drivers +v0x55dd3f7e1190_0 .net "membus_mb_in_p1", 0 35, o0x7fc2ff37db58; 0 drivers +v0x55dd3f6b3360_0 .net "membus_mb_in_p2", 0 35, o0x7fc2ff37db88; 0 drivers +v0x55dd3f6b3420_0 .net "membus_mb_in_p3", 0 35, o0x7fc2ff37dbb8; 0 drivers +v0x55dd3f6b3500_0 .net "membus_mb_out_p0", 0 35, L_0x55dd3fba2180; 1 drivers +v0x55dd3f6b35e0_0 .net "membus_mb_out_p1", 0 35, L_0x55dd3fba2a60; 1 drivers +v0x55dd3f6b36c0_0 .net "membus_mb_out_p2", 0 35, L_0x55dd3fba3440; 1 drivers +v0x55dd3fb12000_0 .net "membus_mb_out_p3", 0 35, L_0x55dd3fba3cc0; 1 drivers +v0x55dd3fb120a0_0 .net "membus_rd_rq_p0", 0 0, o0x7fc2ff37dca8; 0 drivers +v0x55dd3fb12140_0 .net "membus_rd_rq_p1", 0 0, o0x7fc2ff37dcd8; 0 drivers +v0x55dd3fb121e0_0 .net "membus_rd_rq_p2", 0 0, o0x7fc2ff37dd08; 0 drivers +v0x55dd3fb12280_0 .net "membus_rd_rq_p3", 0 0, o0x7fc2ff37dd38; 0 drivers +v0x55dd3fb12320_0 .net "membus_rd_rs_p0", 0 0, L_0x55dd3fba1470; 1 drivers +v0x55dd3fb123c0_0 .net "membus_rd_rs_p1", 0 0, L_0x55dd3fba1530; 1 drivers +v0x55dd3fb12460_0 .net "membus_rd_rs_p2", 0 0, L_0x55dd3fba1740; 1 drivers +v0x55dd3fb12500_0 .net "membus_rd_rs_p3", 0 0, L_0x55dd3fba17b0; 1 drivers +v0x55dd3fb125a0_0 .net "membus_rq_cyc_p0", 0 0, o0x7fc2ff37de28; 0 drivers +v0x55dd3fb12640_0 .net "membus_rq_cyc_p1", 0 0, o0x7fc2ff37de58; 0 drivers +v0x55dd3fb126e0_0 .net "membus_rq_cyc_p2", 0 0, o0x7fc2ff37de88; 0 drivers +v0x55dd3fb12780_0 .net "membus_rq_cyc_p3", 0 0, o0x7fc2ff37deb8; 0 drivers +o0x7fc2ff37dee8 .functor BUFZ 4, C4; HiZ drive +v0x55dd3fb12820_0 .net "membus_sel_p0", 18 21, o0x7fc2ff37dee8; 0 drivers +o0x7fc2ff37df18 .functor BUFZ 4, C4; HiZ drive +v0x55dd3fb128c0_0 .net "membus_sel_p1", 18 21, o0x7fc2ff37df18; 0 drivers +o0x7fc2ff37df48 .functor BUFZ 4, C4; HiZ drive +v0x55dd3fb12960_0 .net "membus_sel_p2", 18 21, o0x7fc2ff37df48; 0 drivers +o0x7fc2ff37df78 .functor BUFZ 4, C4; HiZ drive +v0x55dd3fb12a40_0 .net "membus_sel_p3", 18 21, o0x7fc2ff37df78; 0 drivers +v0x55dd3fb12b20_0 .net "membus_wr_rq_p0", 0 0, o0x7fc2ff37dfa8; 0 drivers +v0x55dd3fb12be0_0 .net "membus_wr_rq_p1", 0 0, o0x7fc2ff37dfd8; 0 drivers +v0x55dd3fb12ca0_0 .net "membus_wr_rq_p2", 0 0, o0x7fc2ff37e008; 0 drivers +v0x55dd3fb12d60_0 .net "membus_wr_rq_p3", 0 0, o0x7fc2ff37e038; 0 drivers +v0x55dd3fb12e20_0 .net "membus_wr_rs_p0", 0 0, o0x7fc2ff37e068; 0 drivers +v0x55dd3fb12ee0_0 .net "membus_wr_rs_p1", 0 0, o0x7fc2ff37e098; 0 drivers +v0x55dd3fb12fa0_0 .net "membus_wr_rs_p2", 0 0, o0x7fc2ff37e0c8; 0 drivers +v0x55dd3fb13060_0 .net "membus_wr_rs_p3", 0 0, o0x7fc2ff37e0f8; 0 drivers +o0x7fc2ff37c058 .functor BUFZ 1, C4; HiZ drive +v0x55dd3fb13120_0 .net "power", 0 0, o0x7fc2ff37c058; 0 drivers +v0x55dd3fb131f0_0 .net "pwr_t1", 0 0, L_0x55dd3fba4db0; 1 drivers +v0x55dd3fb132e0_0 .net "pwr_t2", 0 0, L_0x55dd3fba4fb0; 1 drivers +v0x55dd3fb133d0_0 .net "pwr_t3", 0 0, L_0x55dd3fba5620; 1 drivers +v0x55dd3fb134c0_0 .net "rd_rq_in", 0 0, L_0x55dd3fb9d340; 1 drivers +o0x7fc2ff3784e8 .functor BUFZ 1, C4; HiZ drive +v0x55dd3fb13560_0 .net "reset", 0 0, o0x7fc2ff3784e8; 0 drivers +v0x55dd3fb13600_0 .var "sa", 0 35; +v0x55dd3fb136e0_0 .net "strobe_sense", 0 0, L_0x55dd3fbabc20; 1 drivers +o0x7fc2ff37b038 .functor BUFZ 1, C4; HiZ drive +v0x55dd3fb137d0_0 .net "sw_restart", 0 0, o0x7fc2ff37b038; 0 drivers +o0x7fc2ff37e188 .functor BUFZ 1, C4; HiZ drive +v0x55dd3fb13870_0 .net "sw_single_step", 0 0, o0x7fc2ff37e188; 0 drivers +v0x55dd3fb13910_0 .net "wr_rq_in", 0 0, L_0x55dd3fb9df80; 1 drivers +L_0x55dd3fb9a260 .cmp/eq 4, o0x7fc2ff37dee8, L_0x7fc2ff328f48; +L_0x55dd3fb9a6b0 .cmp/eq 4, o0x7fc2ff37df18, L_0x7fc2ff328f90; +L_0x55dd3fb9ac40 .cmp/eq 4, o0x7fc2ff37df48, L_0x7fc2ff328fd8; +L_0x55dd3fb9b110 .cmp/eq 4, o0x7fc2ff37df78, L_0x7fc2ff329020; +LS_0x55dd3fb9b690_0_0 .concat [ 1 1 1 1], L_0x55dd3fba5b70, L_0x55dd3fba5b70, L_0x55dd3fba5b70, L_0x55dd3fba5b70; +LS_0x55dd3fb9b690_0_4 .concat [ 1 1 1 1], L_0x55dd3fba5b70, L_0x55dd3fba5b70, L_0x55dd3fba5b70, L_0x55dd3fba5b70; +LS_0x55dd3fb9b690_0_8 .concat [ 1 1 1 1], L_0x55dd3fba5b70, L_0x55dd3fba5b70, L_0x55dd3fba5b70, L_0x55dd3fba5b70; +LS_0x55dd3fb9b690_0_12 .concat [ 1 1 0 0], L_0x55dd3fba5b70, L_0x55dd3fba5b70; +L_0x55dd3fb9b690 .concat [ 4 4 4 2], LS_0x55dd3fb9b690_0_0, LS_0x55dd3fb9b690_0_4, LS_0x55dd3fb9b690_0_8, LS_0x55dd3fb9b690_0_12; +L_0x55dd3fb9b7c0 .concat [ 14 1 0 0], L_0x55dd3fb9b690, L_0x7fc2ff329068; +LS_0x55dd3fb9b9b0_0_0 .concat [ 1 1 1 1], L_0x55dd3fba5e10, L_0x55dd3fba5e10, L_0x55dd3fba5e10, L_0x55dd3fba5e10; +LS_0x55dd3fb9b9b0_0_4 .concat [ 1 1 1 1], L_0x55dd3fba5e10, L_0x55dd3fba5e10, L_0x55dd3fba5e10, L_0x55dd3fba5e10; +LS_0x55dd3fb9b9b0_0_8 .concat [ 1 1 1 1], L_0x55dd3fba5e10, L_0x55dd3fba5e10, L_0x55dd3fba5e10, L_0x55dd3fba5e10; +LS_0x55dd3fb9b9b0_0_12 .concat [ 1 1 0 0], L_0x55dd3fba5e10, L_0x55dd3fba5e10; +L_0x55dd3fb9b9b0 .concat [ 4 4 4 2], LS_0x55dd3fb9b9b0_0_0, LS_0x55dd3fb9b9b0_0_4, LS_0x55dd3fb9b9b0_0_8, LS_0x55dd3fb9b9b0_0_12; +L_0x55dd3fb9bbe0 .concat [ 14 1 0 0], L_0x55dd3fb9b9b0, L_0x7fc2ff3290b0; +LS_0x55dd3fb9bfc0_0_0 .concat [ 1 1 1 1], L_0x55dd3fba5e80, L_0x55dd3fba5e80, L_0x55dd3fba5e80, L_0x55dd3fba5e80; +LS_0x55dd3fb9bfc0_0_4 .concat [ 1 1 1 1], L_0x55dd3fba5e80, L_0x55dd3fba5e80, L_0x55dd3fba5e80, L_0x55dd3fba5e80; +LS_0x55dd3fb9bfc0_0_8 .concat [ 1 1 1 1], L_0x55dd3fba5e80, L_0x55dd3fba5e80, L_0x55dd3fba5e80, L_0x55dd3fba5e80; +LS_0x55dd3fb9bfc0_0_12 .concat [ 1 1 0 0], L_0x55dd3fba5e80, L_0x55dd3fba5e80; +L_0x55dd3fb9bfc0 .concat [ 4 4 4 2], LS_0x55dd3fb9bfc0_0_0, LS_0x55dd3fb9bfc0_0_4, LS_0x55dd3fb9bfc0_0_8, LS_0x55dd3fb9bfc0_0_12; +L_0x55dd3fb9c1c0 .concat [ 14 1 0 0], L_0x55dd3fb9bfc0, L_0x7fc2ff3290f8; +LS_0x55dd3fb9bde0_0_0 .concat [ 1 1 1 1], L_0x55dd3fba6130, L_0x55dd3fba6130, L_0x55dd3fba6130, L_0x55dd3fba6130; +LS_0x55dd3fb9bde0_0_4 .concat [ 1 1 1 1], L_0x55dd3fba6130, L_0x55dd3fba6130, L_0x55dd3fba6130, L_0x55dd3fba6130; +LS_0x55dd3fb9bde0_0_8 .concat [ 1 1 1 1], L_0x55dd3fba6130, L_0x55dd3fba6130, L_0x55dd3fba6130, L_0x55dd3fba6130; +LS_0x55dd3fb9bde0_0_12 .concat [ 1 1 0 0], L_0x55dd3fba6130, L_0x55dd3fba6130; +L_0x55dd3fb9bde0 .concat [ 4 4 4 2], LS_0x55dd3fb9bde0_0_0, LS_0x55dd3fb9bde0_0_4, LS_0x55dd3fb9bde0_0_8, LS_0x55dd3fb9bde0_0_12; +L_0x55dd3fb9c6f0 .concat [ 14 1 0 0], L_0x55dd3fb9bde0, L_0x7fc2ff329140; +L_0x55dd3fb9cb10 .part L_0x55dd3fb9c9d0, 0, 14; +LS_0x55dd3fb9e5e0_0_0 .concat [ 1 1 1 1], L_0x55dd3fba5b70, L_0x55dd3fba5b70, L_0x55dd3fba5b70, L_0x55dd3fba5b70; +LS_0x55dd3fb9e5e0_0_4 .concat [ 1 1 1 1], L_0x55dd3fba5b70, L_0x55dd3fba5b70, L_0x55dd3fba5b70, L_0x55dd3fba5b70; +LS_0x55dd3fb9e5e0_0_8 .concat [ 1 1 1 1], L_0x55dd3fba5b70, L_0x55dd3fba5b70, L_0x55dd3fba5b70, L_0x55dd3fba5b70; +LS_0x55dd3fb9e5e0_0_12 .concat [ 1 1 1 1], L_0x55dd3fba5b70, L_0x55dd3fba5b70, L_0x55dd3fba5b70, L_0x55dd3fba5b70; +LS_0x55dd3fb9e5e0_0_16 .concat [ 1 1 1 1], L_0x55dd3fba5b70, L_0x55dd3fba5b70, L_0x55dd3fba5b70, L_0x55dd3fba5b70; +LS_0x55dd3fb9e5e0_0_20 .concat [ 1 1 1 1], L_0x55dd3fba5b70, L_0x55dd3fba5b70, L_0x55dd3fba5b70, L_0x55dd3fba5b70; +LS_0x55dd3fb9e5e0_0_24 .concat [ 1 1 1 1], L_0x55dd3fba5b70, L_0x55dd3fba5b70, L_0x55dd3fba5b70, L_0x55dd3fba5b70; +LS_0x55dd3fb9e5e0_0_28 .concat [ 1 1 1 1], L_0x55dd3fba5b70, L_0x55dd3fba5b70, L_0x55dd3fba5b70, L_0x55dd3fba5b70; +LS_0x55dd3fb9e5e0_0_32 .concat [ 1 1 1 1], L_0x55dd3fba5b70, L_0x55dd3fba5b70, L_0x55dd3fba5b70, L_0x55dd3fba5b70; +LS_0x55dd3fb9e5e0_1_0 .concat [ 4 4 4 4], LS_0x55dd3fb9e5e0_0_0, LS_0x55dd3fb9e5e0_0_4, LS_0x55dd3fb9e5e0_0_8, LS_0x55dd3fb9e5e0_0_12; +LS_0x55dd3fb9e5e0_1_4 .concat [ 4 4 4 4], LS_0x55dd3fb9e5e0_0_16, LS_0x55dd3fb9e5e0_0_20, LS_0x55dd3fb9e5e0_0_24, LS_0x55dd3fb9e5e0_0_28; +LS_0x55dd3fb9e5e0_1_8 .concat [ 4 0 0 0], LS_0x55dd3fb9e5e0_0_32; +L_0x55dd3fb9e5e0 .concat [ 16 16 4 0], LS_0x55dd3fb9e5e0_1_0, LS_0x55dd3fb9e5e0_1_4, LS_0x55dd3fb9e5e0_1_8; +LS_0x55dd3fb9e890_0_0 .concat [ 1 1 1 1], L_0x55dd3fba5e10, L_0x55dd3fba5e10, L_0x55dd3fba5e10, L_0x55dd3fba5e10; +LS_0x55dd3fb9e890_0_4 .concat [ 1 1 1 1], L_0x55dd3fba5e10, L_0x55dd3fba5e10, L_0x55dd3fba5e10, L_0x55dd3fba5e10; +LS_0x55dd3fb9e890_0_8 .concat [ 1 1 1 1], L_0x55dd3fba5e10, L_0x55dd3fba5e10, L_0x55dd3fba5e10, L_0x55dd3fba5e10; +LS_0x55dd3fb9e890_0_12 .concat [ 1 1 1 1], L_0x55dd3fba5e10, L_0x55dd3fba5e10, L_0x55dd3fba5e10, L_0x55dd3fba5e10; +LS_0x55dd3fb9e890_0_16 .concat [ 1 1 1 1], L_0x55dd3fba5e10, L_0x55dd3fba5e10, L_0x55dd3fba5e10, L_0x55dd3fba5e10; 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L_0x55dd3fba5e80, L_0x55dd3fba5e80; +LS_0x55dd3fb9ef70_0_4 .concat [ 1 1 1 1], L_0x55dd3fba5e80, L_0x55dd3fba5e80, L_0x55dd3fba5e80, L_0x55dd3fba5e80; +LS_0x55dd3fb9ef70_0_8 .concat [ 1 1 1 1], L_0x55dd3fba5e80, L_0x55dd3fba5e80, L_0x55dd3fba5e80, L_0x55dd3fba5e80; +LS_0x55dd3fb9ef70_0_12 .concat [ 1 1 1 1], L_0x55dd3fba5e80, L_0x55dd3fba5e80, L_0x55dd3fba5e80, L_0x55dd3fba5e80; +LS_0x55dd3fb9ef70_0_16 .concat [ 1 1 1 1], L_0x55dd3fba5e80, L_0x55dd3fba5e80, L_0x55dd3fba5e80, L_0x55dd3fba5e80; +LS_0x55dd3fb9ef70_0_20 .concat [ 1 1 1 1], L_0x55dd3fba5e80, L_0x55dd3fba5e80, L_0x55dd3fba5e80, L_0x55dd3fba5e80; +LS_0x55dd3fb9ef70_0_24 .concat [ 1 1 1 1], L_0x55dd3fba5e80, L_0x55dd3fba5e80, L_0x55dd3fba5e80, L_0x55dd3fba5e80; +LS_0x55dd3fb9ef70_0_28 .concat [ 1 1 1 1], L_0x55dd3fba5e80, L_0x55dd3fba5e80, L_0x55dd3fba5e80, L_0x55dd3fba5e80; +LS_0x55dd3fb9ef70_0_32 .concat [ 1 1 1 1], L_0x55dd3fba5e80, L_0x55dd3fba5e80, L_0x55dd3fba5e80, L_0x55dd3fba5e80; +LS_0x55dd3fb9ef70_1_0 .concat [ 4 4 4 4], LS_0x55dd3fb9ef70_0_0, LS_0x55dd3fb9ef70_0_4, LS_0x55dd3fb9ef70_0_8, LS_0x55dd3fb9ef70_0_12; +LS_0x55dd3fb9ef70_1_4 .concat [ 4 4 4 4], LS_0x55dd3fb9ef70_0_16, LS_0x55dd3fb9ef70_0_20, LS_0x55dd3fb9ef70_0_24, LS_0x55dd3fb9ef70_0_28; +LS_0x55dd3fb9ef70_1_8 .concat [ 4 0 0 0], LS_0x55dd3fb9ef70_0_32; +L_0x55dd3fb9ef70 .concat [ 16 16 4 0], LS_0x55dd3fb9ef70_1_0, LS_0x55dd3fb9ef70_1_4, LS_0x55dd3fb9ef70_1_8; +LS_0x55dd3fb9f7e0_0_0 .concat [ 1 1 1 1], L_0x55dd3fba6130, L_0x55dd3fba6130, L_0x55dd3fba6130, L_0x55dd3fba6130; +LS_0x55dd3fb9f7e0_0_4 .concat [ 1 1 1 1], L_0x55dd3fba6130, L_0x55dd3fba6130, L_0x55dd3fba6130, L_0x55dd3fba6130; +LS_0x55dd3fb9f7e0_0_8 .concat [ 1 1 1 1], L_0x55dd3fba6130, L_0x55dd3fba6130, L_0x55dd3fba6130, L_0x55dd3fba6130; +LS_0x55dd3fb9f7e0_0_12 .concat [ 1 1 1 1], L_0x55dd3fba6130, L_0x55dd3fba6130, L_0x55dd3fba6130, L_0x55dd3fba6130; +LS_0x55dd3fb9f7e0_0_16 .concat [ 1 1 1 1], L_0x55dd3fba6130, L_0x55dd3fba6130, L_0x55dd3fba6130, L_0x55dd3fba6130; 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L_0x55dd3fba19d0, L_0x55dd3fba19d0; +LS_0x55dd3fba1a40_0_4 .concat [ 1 1 1 1], L_0x55dd3fba19d0, L_0x55dd3fba19d0, L_0x55dd3fba19d0, L_0x55dd3fba19d0; +LS_0x55dd3fba1a40_0_8 .concat [ 1 1 1 1], L_0x55dd3fba19d0, L_0x55dd3fba19d0, L_0x55dd3fba19d0, L_0x55dd3fba19d0; +LS_0x55dd3fba1a40_0_12 .concat [ 1 1 1 1], L_0x55dd3fba19d0, L_0x55dd3fba19d0, L_0x55dd3fba19d0, L_0x55dd3fba19d0; +LS_0x55dd3fba1a40_0_16 .concat [ 1 1 1 1], L_0x55dd3fba19d0, L_0x55dd3fba19d0, L_0x55dd3fba19d0, L_0x55dd3fba19d0; +LS_0x55dd3fba1a40_0_20 .concat [ 1 1 1 1], L_0x55dd3fba19d0, L_0x55dd3fba19d0, L_0x55dd3fba19d0, L_0x55dd3fba19d0; +LS_0x55dd3fba1a40_0_24 .concat [ 1 1 1 1], L_0x55dd3fba19d0, L_0x55dd3fba19d0, L_0x55dd3fba19d0, L_0x55dd3fba19d0; +LS_0x55dd3fba1a40_0_28 .concat [ 1 1 1 1], L_0x55dd3fba19d0, L_0x55dd3fba19d0, L_0x55dd3fba19d0, L_0x55dd3fba19d0; +LS_0x55dd3fba1a40_0_32 .concat [ 1 1 1 1], L_0x55dd3fba19d0, L_0x55dd3fba19d0, L_0x55dd3fba19d0, L_0x55dd3fba19d0; +LS_0x55dd3fba1a40_1_0 .concat [ 4 4 4 4], LS_0x55dd3fba1a40_0_0, LS_0x55dd3fba1a40_0_4, LS_0x55dd3fba1a40_0_8, LS_0x55dd3fba1a40_0_12; +LS_0x55dd3fba1a40_1_4 .concat [ 4 4 4 4], LS_0x55dd3fba1a40_0_16, LS_0x55dd3fba1a40_0_20, LS_0x55dd3fba1a40_0_24, LS_0x55dd3fba1a40_0_28; +LS_0x55dd3fba1a40_1_8 .concat [ 4 0 0 0], LS_0x55dd3fba1a40_0_32; +L_0x55dd3fba1a40 .concat [ 16 16 4 0], LS_0x55dd3fba1a40_1_0, LS_0x55dd3fba1a40_1_4, LS_0x55dd3fba1a40_1_8; +LS_0x55dd3fba2450_0_0 .concat [ 1 1 1 1], L_0x55dd3fba23e0, L_0x55dd3fba23e0, L_0x55dd3fba23e0, L_0x55dd3fba23e0; +LS_0x55dd3fba2450_0_4 .concat [ 1 1 1 1], L_0x55dd3fba23e0, L_0x55dd3fba23e0, L_0x55dd3fba23e0, L_0x55dd3fba23e0; +LS_0x55dd3fba2450_0_8 .concat [ 1 1 1 1], L_0x55dd3fba23e0, L_0x55dd3fba23e0, L_0x55dd3fba23e0, L_0x55dd3fba23e0; +LS_0x55dd3fba2450_0_12 .concat [ 1 1 1 1], L_0x55dd3fba23e0, L_0x55dd3fba23e0, L_0x55dd3fba23e0, L_0x55dd3fba23e0; +LS_0x55dd3fba2450_0_16 .concat [ 1 1 1 1], L_0x55dd3fba23e0, L_0x55dd3fba23e0, L_0x55dd3fba23e0, L_0x55dd3fba23e0; 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L_0x55dd3fba2cf0, L_0x55dd3fba2cf0; +LS_0x55dd3fba2d60_0_4 .concat [ 1 1 1 1], L_0x55dd3fba2cf0, L_0x55dd3fba2cf0, L_0x55dd3fba2cf0, L_0x55dd3fba2cf0; +LS_0x55dd3fba2d60_0_8 .concat [ 1 1 1 1], L_0x55dd3fba2cf0, L_0x55dd3fba2cf0, L_0x55dd3fba2cf0, L_0x55dd3fba2cf0; +LS_0x55dd3fba2d60_0_12 .concat [ 1 1 1 1], L_0x55dd3fba2cf0, L_0x55dd3fba2cf0, L_0x55dd3fba2cf0, L_0x55dd3fba2cf0; +LS_0x55dd3fba2d60_0_16 .concat [ 1 1 1 1], L_0x55dd3fba2cf0, L_0x55dd3fba2cf0, L_0x55dd3fba2cf0, L_0x55dd3fba2cf0; +LS_0x55dd3fba2d60_0_20 .concat [ 1 1 1 1], L_0x55dd3fba2cf0, L_0x55dd3fba2cf0, L_0x55dd3fba2cf0, L_0x55dd3fba2cf0; +LS_0x55dd3fba2d60_0_24 .concat [ 1 1 1 1], L_0x55dd3fba2cf0, L_0x55dd3fba2cf0, L_0x55dd3fba2cf0, L_0x55dd3fba2cf0; +LS_0x55dd3fba2d60_0_28 .concat [ 1 1 1 1], L_0x55dd3fba2cf0, L_0x55dd3fba2cf0, L_0x55dd3fba2cf0, L_0x55dd3fba2cf0; +LS_0x55dd3fba2d60_0_32 .concat [ 1 1 1 1], L_0x55dd3fba2cf0, L_0x55dd3fba2cf0, L_0x55dd3fba2cf0, L_0x55dd3fba2cf0; +LS_0x55dd3fba2d60_1_0 .concat [ 4 4 4 4], LS_0x55dd3fba2d60_0_0, LS_0x55dd3fba2d60_0_4, LS_0x55dd3fba2d60_0_8, LS_0x55dd3fba2d60_0_12; +LS_0x55dd3fba2d60_1_4 .concat [ 4 4 4 4], LS_0x55dd3fba2d60_0_16, LS_0x55dd3fba2d60_0_20, LS_0x55dd3fba2d60_0_24, LS_0x55dd3fba2d60_0_28; +LS_0x55dd3fba2d60_1_8 .concat [ 4 0 0 0], LS_0x55dd3fba2d60_0_32; +L_0x55dd3fba2d60 .concat [ 16 16 4 0], LS_0x55dd3fba2d60_1_0, LS_0x55dd3fba2d60_1_4, LS_0x55dd3fba2d60_1_8; +LS_0x55dd3fba20e0_0_0 .concat [ 1 1 1 1], L_0x55dd3fba3690, L_0x55dd3fba3690, L_0x55dd3fba3690, L_0x55dd3fba3690; +LS_0x55dd3fba20e0_0_4 .concat [ 1 1 1 1], L_0x55dd3fba3690, L_0x55dd3fba3690, L_0x55dd3fba3690, L_0x55dd3fba3690; +LS_0x55dd3fba20e0_0_8 .concat [ 1 1 1 1], L_0x55dd3fba3690, L_0x55dd3fba3690, L_0x55dd3fba3690, L_0x55dd3fba3690; +LS_0x55dd3fba20e0_0_12 .concat [ 1 1 1 1], L_0x55dd3fba3690, L_0x55dd3fba3690, L_0x55dd3fba3690, L_0x55dd3fba3690; +LS_0x55dd3fba20e0_0_16 .concat [ 1 1 1 1], L_0x55dd3fba3690, L_0x55dd3fba3690, L_0x55dd3fba3690, L_0x55dd3fba3690; +LS_0x55dd3fba20e0_0_20 .concat [ 1 1 1 1], L_0x55dd3fba3690, L_0x55dd3fba3690, L_0x55dd3fba3690, L_0x55dd3fba3690; +LS_0x55dd3fba20e0_0_24 .concat [ 1 1 1 1], L_0x55dd3fba3690, L_0x55dd3fba3690, L_0x55dd3fba3690, L_0x55dd3fba3690; +LS_0x55dd3fba20e0_0_28 .concat [ 1 1 1 1], L_0x55dd3fba3690, L_0x55dd3fba3690, L_0x55dd3fba3690, L_0x55dd3fba3690; +LS_0x55dd3fba20e0_0_32 .concat [ 1 1 1 1], L_0x55dd3fba3690, L_0x55dd3fba3690, L_0x55dd3fba3690, L_0x55dd3fba3690; +LS_0x55dd3fba20e0_1_0 .concat [ 4 4 4 4], LS_0x55dd3fba20e0_0_0, LS_0x55dd3fba20e0_0_4, LS_0x55dd3fba20e0_0_8, LS_0x55dd3fba20e0_0_12; +LS_0x55dd3fba20e0_1_4 .concat [ 4 4 4 4], LS_0x55dd3fba20e0_0_16, LS_0x55dd3fba20e0_0_20, LS_0x55dd3fba20e0_0_24, LS_0x55dd3fba20e0_0_28; +LS_0x55dd3fba20e0_1_8 .concat [ 4 0 0 0], LS_0x55dd3fba20e0_0_32; +L_0x55dd3fba20e0 .concat [ 16 16 4 0], LS_0x55dd3fba20e0_1_0, LS_0x55dd3fba20e0_1_4, LS_0x55dd3fba20e0_1_8; +L_0x55dd3fbaef40 .concat [ 14 4 0 0], v0x55dd3f6ace00_0, L_0x7fc2ff3298d8; +S_0x55dd3f968b80 .scope module, "cmpc_pa0" "pa" 6 116, 3 31 0, S_0x55dd3faf4800; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +L_0x55dd3fba02f0 .functor AND 1, L_0x55dd3fb9f680, L_0x55dd3fba0200, C4<1>, C4<1>; +v0x55dd3fadbfb0_0 .net *"_s1", 0 0, L_0x55dd3fb9f680; 1 drivers +v0x55dd3fadc090_0 .net *"_s3", 0 0, L_0x55dd3fba0160; 1 drivers +v0x55dd3fadab80_0 .net *"_s5", 0 0, L_0x55dd3fba0200; 1 drivers +v0x55dd3fadac20_0 .net "clk", 0 0, o0x7fc2ff378458; alias, 0 drivers +v0x55dd3fad9710_0 .net "in", 0 0, L_0x55dd3fba0450; 1 drivers +v0x55dd3fad9800_0 .net "p", 0 0, L_0x55dd3fba02f0; alias, 1 drivers +v0x55dd3fac9080_0 .net "reset", 0 0, o0x7fc2ff3784e8; alias, 0 drivers +v0x55dd3fac9140_0 .var "x", 1 0; +E_0x55dd3fb0ea50 .event posedge, v0x55dd3fac9080_0, v0x55dd3fadac20_0; +L_0x55dd3fb9f680 .part v0x55dd3fac9140_0, 0, 1; +L_0x55dd3fba0160 .part v0x55dd3fac9140_0, 1, 1; +L_0x55dd3fba0200 .reduce/nor L_0x55dd3fba0160; +S_0x55dd3f954c40 .scope module, "cmpc_pa1" "pa" 6 117, 3 31 0, S_0x55dd3faf4800; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +L_0x55dd3fba0740 .functor AND 1, L_0x55dd3fba04c0, L_0x55dd3fba0650, C4<1>, C4<1>; +v0x55dd3fad7440_0 .net *"_s1", 0 0, L_0x55dd3fba04c0; 1 drivers +v0x55dd3fad7500_0 .net *"_s3", 0 0, L_0x55dd3fba0560; 1 drivers +v0x55dd3fad6560_0 .net *"_s5", 0 0, L_0x55dd3fba0650; 1 drivers +v0x55dd3fad6600_0 .net "clk", 0 0, o0x7fc2ff378458; alias, 0 drivers +v0x55dd3fad5680_0 .net "in", 0 0, L_0x55dd3fba08a0; 1 drivers +v0x55dd3fad5770_0 .net "p", 0 0, L_0x55dd3fba0740; alias, 1 drivers +v0x55dd3fad4710_0 .net "reset", 0 0, o0x7fc2ff3784e8; alias, 0 drivers +v0x55dd3fad47b0_0 .var "x", 1 0; +L_0x55dd3fba04c0 .part v0x55dd3fad47b0_0, 0, 1; +L_0x55dd3fba0560 .part v0x55dd3fad47b0_0, 1, 1; +L_0x55dd3fba0650 .reduce/nor L_0x55dd3fba0560; +S_0x55dd3f956740 .scope module, "cmpc_pa2" "pa" 6 118, 3 31 0, S_0x55dd3faf4800; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +L_0x55dd3fba0cc0 .functor AND 1, L_0x55dd3fba0a90, L_0x55dd3fba0bd0, C4<1>, C4<1>; +v0x55dd3fae3760_0 .net *"_s1", 0 0, L_0x55dd3fba0a90; 1 drivers +v0x55dd3fae3840_0 .net *"_s3", 0 0, L_0x55dd3fba0b30; 1 drivers +v0x55dd3fae1d90_0 .net *"_s5", 0 0, L_0x55dd3fba0bd0; 1 drivers +v0x55dd3fae1e60_0 .net "clk", 0 0, o0x7fc2ff378458; alias, 0 drivers +v0x55dd3fae0080_0 .net "in", 0 0, L_0x55dd3fba0e20; 1 drivers +v0x55dd3fade5d0_0 .net "p", 0 0, L_0x55dd3fba0cc0; alias, 1 drivers +v0x55dd3fade690_0 .net "reset", 0 0, o0x7fc2ff3784e8; alias, 0 drivers +v0x55dd3faf2540_0 .var "x", 1 0; +L_0x55dd3fba0a90 .part v0x55dd3faf2540_0, 0, 1; +L_0x55dd3fba0b30 .part v0x55dd3faf2540_0, 1, 1; +L_0x55dd3fba0bd0 .reduce/nor L_0x55dd3fba0b30; +S_0x55dd3f9581d0 .scope module, "cmpc_pa3" "pa" 6 119, 3 31 0, S_0x55dd3faf4800; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +L_0x55dd3fba1110 .functor AND 1, L_0x55dd3fba0e90, L_0x55dd3fba1020, C4<1>, C4<1>; +v0x55dd3faee120_0 .net *"_s1", 0 0, L_0x55dd3fba0e90; 1 drivers +v0x55dd3faec660_0 .net *"_s3", 0 0, L_0x55dd3fba0f30; 1 drivers +v0x55dd3faec720_0 .net *"_s5", 0 0, L_0x55dd3fba1020; 1 drivers +v0x55dd3faeac60_0 .net "clk", 0 0, o0x7fc2ff378458; alias, 0 drivers +v0x55dd3faead00_0 .net "in", 0 0, L_0x55dd3fba1270; 1 drivers +v0x55dd3fae8f30_0 .net "p", 0 0, L_0x55dd3fba1110; alias, 1 drivers +v0x55dd3fae8fd0_0 .net "reset", 0 0, o0x7fc2ff3784e8; alias, 0 drivers +v0x55dd3fae6b00_0 .var "x", 1 0; +L_0x55dd3fba0e90 .part v0x55dd3fae6b00_0, 0, 1; +L_0x55dd3fba0f30 .part v0x55dd3fae6b00_0, 1, 1; +L_0x55dd3fba1020 .reduce/nor L_0x55dd3fba0f30; +S_0x55dd3f959c00 .scope module, "dly0" "ldly1us" 6 139, 5 198 0, S_0x55dd3faf4800; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" + .port_info 4 /OUTPUT 1 "l" +v0x55dd3fae5180_0 .net *"_s0", 31 0, L_0x55dd3fba4ec0; 1 drivers +L_0x7fc2ff329188 .functor BUFT 1, C4<00000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x55dd3fa682c0_0 .net *"_s3", 25 0, L_0x7fc2ff329188; 1 drivers +L_0x7fc2ff3291d0 .functor BUFT 1, C4<00000000000000000000000000110010>, C4<0>, C4<0>, C4<0>; +v0x55dd3fa683a0_0 .net/2u *"_s4", 31 0, L_0x7fc2ff3291d0; 1 drivers +v0x55dd3fa66620_0 .net "clk", 0 0, o0x7fc2ff378458; alias, 0 drivers +v0x55dd3fa666c0_0 .net "in", 0 0, L_0x55dd3fba4db0; alias, 1 drivers +v0x55dd3fa63330_0 .var "l", 0 0; +v0x55dd3fa633f0_0 .net "p", 0 0, L_0x55dd3fba4fb0; alias, 1 drivers +v0x55dd3fa61780_0 .var "r", 5 0; +v0x55dd3fa61840_0 .net "reset", 0 0, o0x7fc2ff3784e8; alias, 0 drivers +L_0x55dd3fba4ec0 .concat [ 6 26 0 0], v0x55dd3fa61780_0, L_0x7fc2ff329188; +L_0x55dd3fba4fb0 .cmp/eq 32, L_0x55dd3fba4ec0, L_0x7fc2ff3291d0; +S_0x55dd3f95b6a0 .scope module, "dly1" "ldly1us" 6 141, 5 198 0, S_0x55dd3faf4800; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" + .port_info 4 /OUTPUT 1 "l" +v0x55dd3faa0060_0 .net *"_s0", 31 0, L_0x55dd3fba50f0; 1 drivers +L_0x7fc2ff329218 .functor BUFT 1, C4<00000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x55dd3faa0160_0 .net *"_s3", 25 0, L_0x7fc2ff329218; 1 drivers +L_0x7fc2ff329260 .functor BUFT 1, C4<00000000000000000000000000110010>, C4<0>, C4<0>, C4<0>; +v0x55dd3fa98bb0_0 .net/2u *"_s4", 31 0, L_0x7fc2ff329260; 1 drivers +v0x55dd3fa98c70_0 .net "clk", 0 0, o0x7fc2ff378458; alias, 0 drivers +v0x55dd3fa915e0_0 .net "in", 0 0, L_0x55dd3fba4fb0; alias, 1 drivers +v0x55dd3fa91680_0 .var "l", 0 0; +v0x55dd3fa895c0_0 .net "p", 0 0, L_0x55dd3fba5620; alias, 1 drivers +v0x55dd3fa89680_0 .var "r", 5 0; +v0x55dd3fa86b00_0 .net "reset", 0 0, o0x7fc2ff3784e8; alias, 0 drivers +L_0x55dd3fba50f0 .concat [ 6 26 0 0], v0x55dd3fa89680_0, L_0x7fc2ff329218; +L_0x55dd3fba5620 .cmp/eq 32, L_0x55dd3fba50f0, L_0x7fc2ff329260; +S_0x55dd3fa85f20 .scope module, "dly10" "dly550ns" 6 214, 5 136 0, S_0x55dd3faf4800; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +v0x55dd3fa85760_0 .net *"_s0", 31 0, L_0x55dd3fbae7f0; 1 drivers +L_0x7fc2ff329728 .functor BUFT 1, C4<000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x55dd3fa85820_0 .net *"_s3", 26 0, L_0x7fc2ff329728; 1 drivers +L_0x7fc2ff329770 .functor BUFT 1, C4<00000000000000000000000000011011>, C4<0>, C4<0>, C4<0>; +v0x55dd3fa7c6f0_0 .net/2u *"_s4", 31 0, L_0x7fc2ff329770; 1 drivers +v0x55dd3fa7c7e0_0 .net "clk", 0 0, o0x7fc2ff378458; alias, 0 drivers +v0x55dd3fa7aa50_0 .net "in", 0 0, L_0x55dd3fbac450; alias, 1 drivers +v0x55dd3fa7ab10_0 .net "p", 0 0, L_0x55dd3fbae8e0; alias, 1 drivers +v0x55dd3fa79950_0 .var "r", 4 0; +v0x55dd3fa79a10_0 .net "reset", 0 0, o0x7fc2ff3784e8; alias, 0 drivers +L_0x55dd3fbae7f0 .concat [ 5 27 0 0], v0x55dd3fa79950_0, L_0x7fc2ff329728; +L_0x55dd3fbae8e0 .cmp/eq 32, L_0x55dd3fbae7f0, L_0x7fc2ff329770; +S_0x55dd3fa78850 .scope module, "dly11" "dly750ns" 6 215, 5 151 0, S_0x55dd3faf4800; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +v0x55dd3fa77760_0 .net *"_s0", 31 0, L_0x55dd3fbaea20; 1 drivers +L_0x7fc2ff3297b8 .functor BUFT 1, C4<00000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x55dd3fa5dfc0_0 .net *"_s3", 25 0, L_0x7fc2ff3297b8; 1 drivers +L_0x7fc2ff329800 .functor BUFT 1, C4<00000000000000000000000000100101>, C4<0>, C4<0>, C4<0>; +v0x55dd3fa5e0a0_0 .net/2u *"_s4", 31 0, L_0x7fc2ff329800; 1 drivers +v0x55dd3fa6df40_0 .net "clk", 0 0, o0x7fc2ff378458; alias, 0 drivers +v0x55dd3fa6dfe0_0 .net "in", 0 0, L_0x55dd3fbac450; alias, 1 drivers +v0x55dd3fa69f60_0 .net "p", 0 0, L_0x55dd3fbaeb10; alias, 1 drivers +v0x55dd3fa6a000_0 .var "r", 5 0; +v0x55dd3fa7d890_0 .net "reset", 0 0, o0x7fc2ff3784e8; alias, 0 drivers +L_0x55dd3fbaea20 .concat [ 6 26 0 0], v0x55dd3fa6a000_0, L_0x7fc2ff3297b8; +L_0x55dd3fbaeb10 .cmp/eq 32, L_0x55dd3fbaea20, L_0x7fc2ff329800; +S_0x55dd3fa97580 .scope module, "dly12" "dly50ns" 6 216, 5 1 0, S_0x55dd3faf4800; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +v0x55dd3fa95cb0_0 .net *"_s0", 31 0, L_0x55dd3fbaec50; 1 drivers +L_0x7fc2ff329848 .functor BUFT 1, C4<000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x55dd3fa941e0_0 .net *"_s3", 29 0, L_0x7fc2ff329848; 1 drivers +L_0x7fc2ff329890 .functor BUFT 1, C4<00000000000000000000000000000010>, C4<0>, C4<0>, C4<0>; +v0x55dd3fa942c0_0 .net/2u *"_s4", 31 0, L_0x7fc2ff329890; 1 drivers +v0x55dd3fa92450_0 .net "clk", 0 0, o0x7fc2ff378458; alias, 0 drivers +v0x55dd3fa924f0_0 .net "in", 0 0, L_0x55dd3fba49d0; alias, 1 drivers +v0x55dd3fa8fc30_0 .net "p", 0 0, L_0x55dd3fbaed40; alias, 1 drivers +v0x55dd3fa8fcf0_0 .var "r", 1 0; +v0x55dd3fa8ded0_0 .net "reset", 0 0, o0x7fc2ff3784e8; alias, 0 drivers +L_0x55dd3fbaec50 .concat [ 2 30 0 0], v0x55dd3fa8fcf0_0, L_0x7fc2ff329848; +L_0x55dd3fbaed40 .cmp/eq 32, L_0x55dd3fbaec50, L_0x7fc2ff329890; +S_0x55dd3fa8c170 .scope module, "dly2" "dly250ns" 6 205, 5 76 0, S_0x55dd3faf4800; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +v0x55dd3fa8a480_0 .net *"_s0", 31 0, L_0x55dd3fbad4f0; 1 drivers +L_0x7fc2ff3292a8 .functor BUFT 1, C4<0000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x55dd3faa28d0_0 .net *"_s3", 27 0, L_0x7fc2ff3292a8; 1 drivers +L_0x7fc2ff3292f0 .functor BUFT 1, C4<00000000000000000000000000001100>, C4<0>, C4<0>, C4<0>; +v0x55dd3faa29b0_0 .net/2u *"_s4", 31 0, L_0x7fc2ff3292f0; 1 drivers +v0x55dd3faa0f30_0 .net "clk", 0 0, o0x7fc2ff378458; alias, 0 drivers +v0x55dd3faa0fd0_0 .net "in", 0 0, L_0x55dd3fba8d80; alias, 1 drivers +v0x55dd3fa9ead0_0 .net "p", 0 0, L_0x55dd3fbad5e0; alias, 1 drivers +v0x55dd3fa9eb90_0 .var "r", 3 0; +v0x55dd3fa9d130_0 .net "reset", 0 0, o0x7fc2ff3784e8; alias, 0 drivers +L_0x55dd3fbad4f0 .concat [ 4 28 0 0], v0x55dd3fa9eb90_0, L_0x7fc2ff3292a8; +L_0x55dd3fbad5e0 .cmp/eq 32, L_0x55dd3fbad4f0, L_0x7fc2ff3292f0; +S_0x55dd3fa9b400 .scope module, "dly3" "dly100ns" 6 206, 5 31 0, S_0x55dd3faf4800; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +v0x55dd3fa99a70_0 .net *"_s0", 31 0, L_0x55dd3fbad770; 1 drivers +L_0x7fc2ff329338 .functor BUFT 1, C4<00000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x55dd3fa88020_0 .net *"_s3", 28 0, L_0x7fc2ff329338; 1 drivers +L_0x7fc2ff329380 .functor BUFT 1, C4<00000000000000000000000000000101>, C4<0>, C4<0>, C4<0>; +v0x55dd3fa88100_0 .net/2u *"_s4", 31 0, L_0x7fc2ff329380; 1 drivers +v0x55dd3fa834c0_0 .net "clk", 0 0, o0x7fc2ff378458; alias, 0 drivers +v0x55dd3fa83560_0 .net "in", 0 0, L_0x55dd3fba7830; alias, 1 drivers +v0x55dd3fa74900_0 .net "p", 0 0, L_0x55dd3fbad860; alias, 1 drivers +v0x55dd3fa749c0_0 .var "r", 2 0; +v0x55dd3fa72bd0_0 .net "reset", 0 0, o0x7fc2ff3784e8; alias, 0 drivers +L_0x55dd3fbad770 .concat [ 3 29 0 0], v0x55dd3fa749c0_0, L_0x7fc2ff329338; +L_0x55dd3fbad860 .cmp/eq 32, L_0x55dd3fbad770, L_0x7fc2ff329380; +S_0x55dd3fa70ea0 .scope module, "dly4" "dly250ns" 6 207, 5 76 0, S_0x55dd3faf4800; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +v0x55dd3fa6f150_0 .net *"_s0", 31 0, L_0x55dd3fbad9e0; 1 drivers +L_0x7fc2ff3293c8 .functor BUFT 1, C4<0000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x55dd3fa2e780_0 .net *"_s3", 27 0, L_0x7fc2ff3293c8; 1 drivers +L_0x7fc2ff329410 .functor BUFT 1, C4<00000000000000000000000000001100>, C4<0>, C4<0>, C4<0>; +v0x55dd3fa2e860_0 .net/2u *"_s4", 31 0, L_0x7fc2ff329410; 1 drivers +v0x55dd3fa2df00_0 .net "clk", 0 0, o0x7fc2ff378458; alias, 0 drivers +v0x55dd3fa2dfa0_0 .net "in", 0 0, L_0x55dd3fbaa8f0; alias, 1 drivers +v0x55dd3fa28080_0 .net "p", 0 0, L_0x55dd3fbadad0; alias, 1 drivers +v0x55dd3fa28140_0 .var "r", 3 0; +v0x55dd3fa269e0_0 .net "reset", 0 0, o0x7fc2ff3784e8; alias, 0 drivers +L_0x55dd3fbad9e0 .concat [ 4 28 0 0], v0x55dd3fa28140_0, L_0x7fc2ff3293c8; +L_0x55dd3fbadad0 .cmp/eq 32, L_0x55dd3fbad9e0, L_0x7fc2ff329410; +S_0x55dd3fa25ad0 .scope module, "dly5" "dly450ns" 6 208, 5 121 0, S_0x55dd3faf4800; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +v0x55dd3f9f10e0_0 .net *"_s0", 31 0, L_0x55dd3fbadc10; 1 drivers +L_0x7fc2ff329458 .functor BUFT 1, C4<000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x55dd3f9f0550_0 .net *"_s3", 26 0, L_0x7fc2ff329458; 1 drivers +L_0x7fc2ff3294a0 .functor BUFT 1, C4<00000000000000000000000000010110>, C4<0>, C4<0>, C4<0>; +v0x55dd3f9f0630_0 .net/2u *"_s4", 31 0, L_0x7fc2ff3294a0; 1 drivers +v0x55dd3f9efa30_0 .net "clk", 0 0, o0x7fc2ff378458; alias, 0 drivers +v0x55dd3f9efad0_0 .net "in", 0 0, L_0x55dd3fbaa8f0; alias, 1 drivers +v0x55dd3f9eee90_0 .net "p", 0 0, L_0x55dd3fbadd00; alias, 1 drivers +v0x55dd3f9eef30_0 .var "r", 4 0; +v0x55dd3f9ee090_0 .net "reset", 0 0, o0x7fc2ff3784e8; alias, 0 drivers +L_0x55dd3fbadc10 .concat [ 5 27 0 0], v0x55dd3f9eef30_0, L_0x7fc2ff329458; +L_0x55dd3fbadd00 .cmp/eq 32, L_0x55dd3fbadc10, L_0x7fc2ff3294a0; +S_0x55dd3f9ed8f0 .scope module, "dly6" "dly550ns" 6 209, 5 136 0, S_0x55dd3faf4800; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +v0x55dd3f9ecc40_0 .net *"_s0", 31 0, L_0x55dd3fbade90; 1 drivers +L_0x7fc2ff3294e8 .functor BUFT 1, C4<000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x55dd3f9ecd20_0 .net *"_s3", 26 0, L_0x7fc2ff3294e8; 1 drivers +L_0x7fc2ff329530 .functor BUFT 1, C4<00000000000000000000000000011011>, C4<0>, C4<0>, C4<0>; +v0x55dd3f9ec4a0_0 .net/2u *"_s4", 31 0, L_0x7fc2ff329530; 1 drivers +v0x55dd3f9ec570_0 .net "clk", 0 0, o0x7fc2ff378458; alias, 0 drivers +v0x55dd3f9eb7f0_0 .net "in", 0 0, L_0x55dd3fbaa8f0; alias, 1 drivers +v0x55dd3f9eb050_0 .net "p", 0 0, L_0x55dd3fbadf80; alias, 1 drivers +v0x55dd3f9eb110_0 .var "r", 4 0; +v0x55dd3f9ea460_0 .net "reset", 0 0, o0x7fc2ff3784e8; alias, 0 drivers +L_0x55dd3fbade90 .concat [ 5 27 0 0], v0x55dd3f9eb110_0, L_0x7fc2ff3294e8; +L_0x55dd3fbadf80 .cmp/eq 32, L_0x55dd3fbade90, L_0x7fc2ff329530; +S_0x55dd3f9e9c90 .scope module, "dly7" "dly70ns" 6 211, 5 16 0, S_0x55dd3faf4800; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +v0x55dd3f9e9470_0 .net *"_s0", 31 0, L_0x55dd3fbae110; 1 drivers +L_0x7fc2ff329578 .functor BUFT 1, C4<000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x55dd3f9e9550_0 .net *"_s3", 29 0, L_0x7fc2ff329578; 1 drivers +L_0x7fc2ff3295c0 .functor BUFT 1, C4<00000000000000000000000000000011>, C4<0>, C4<0>, C4<0>; +v0x55dd3f9e7ba0_0 .net/2u *"_s4", 31 0, L_0x7fc2ff3295c0; 1 drivers +v0x55dd3f9e7c60_0 .net "clk", 0 0, o0x7fc2ff378458; alias, 0 drivers +v0x55dd3fa10ea0_0 .net "in", 0 0, L_0x55dd3fbab8e0; alias, 1 drivers +v0x55dd3fa0ec20_0 .net "p", 0 0, L_0x55dd3fbae200; alias, 1 drivers +v0x55dd3fa0ece0_0 .var "r", 1 0; +v0x55dd3fa054e0_0 .net "reset", 0 0, o0x7fc2ff3784e8; alias, 0 drivers +L_0x55dd3fbae110 .concat [ 2 30 0 0], v0x55dd3fa0ece0_0, L_0x7fc2ff329578; +L_0x55dd3fbae200 .cmp/eq 32, L_0x55dd3fbae110, L_0x7fc2ff3295c0; +S_0x55dd3f9fa880 .scope module, "dly8" "dly300ns" 6 212, 5 91 0, S_0x55dd3faf4800; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +v0x55dd3f9f9430_0 .net *"_s0", 31 0, L_0x55dd3fbae340; 1 drivers +L_0x7fc2ff329608 .functor BUFT 1, C4<0000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x55dd3f9f94f0_0 .net *"_s3", 27 0, L_0x7fc2ff329608; 1 drivers +L_0x7fc2ff329650 .functor BUFT 1, C4<00000000000000000000000000001111>, C4<0>, C4<0>, C4<0>; +v0x55dd3f9f7fe0_0 .net/2u *"_s4", 31 0, L_0x7fc2ff329650; 1 drivers +v0x55dd3f9f80d0_0 .net "clk", 0 0, o0x7fc2ff378458; alias, 0 drivers +v0x55dd3f9f6b90_0 .net "in", 0 0, L_0x55dd3fbab8e0; alias, 1 drivers +v0x55dd3f9f6c80_0 .net "p", 0 0, L_0x55dd3fbae430; alias, 1 drivers +v0x55dd3f9e64e0_0 .var "r", 3 0; +v0x55dd3f9e65c0_0 .net "reset", 0 0, o0x7fc2ff3784e8; alias, 0 drivers +L_0x55dd3fbae340 .concat [ 4 28 0 0], v0x55dd3f9e64e0_0, L_0x7fc2ff329608; +L_0x55dd3fbae430 .cmp/eq 32, L_0x55dd3fbae340, L_0x7fc2ff329650; +S_0x55dd3f9f57a0 .scope module, "dly9" "dly50ns" 6 213, 5 1 0, S_0x55dd3faf4800; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +v0x55dd3f9f4980_0 .net *"_s0", 31 0, L_0x55dd3fbae570; 1 drivers +L_0x7fc2ff329698 .functor BUFT 1, C4<000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x55dd3f9f39e0_0 .net *"_s3", 29 0, L_0x7fc2ff329698; 1 drivers +L_0x7fc2ff3296e0 .functor BUFT 1, C4<00000000000000000000000000000010>, C4<0>, C4<0>, C4<0>; +v0x55dd3f9f3aa0_0 .net/2u *"_s4", 31 0, L_0x7fc2ff3296e0; 1 drivers +v0x55dd3f9f2b00_0 .net "clk", 0 0, o0x7fc2ff378458; alias, 0 drivers +v0x55dd3f9f2ba0_0 .net "in", 0 0, L_0x55dd3fbac450; alias, 1 drivers +v0x55dd3f9f1be0_0 .net "p", 0 0, L_0x55dd3fbae660; alias, 1 drivers +v0x55dd3f9f1c80_0 .var "r", 1 0; +v0x55dd3fa0cf20_0 .net "reset", 0 0, o0x7fc2ff3784e8; alias, 0 drivers +L_0x55dd3fbae570 .concat [ 2 30 0 0], v0x55dd3f9f1c80_0, L_0x7fc2ff329698; +L_0x55dd3fbae660 .cmp/eq 32, L_0x55dd3fbae570, L_0x7fc2ff3296e0; +S_0x55dd3fa00be0 .scope module, "pa0" "pa" 6 142, 3 31 0, S_0x55dd3faf4800; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +L_0x55dd3fba5a10 .functor AND 1, L_0x55dd3fba5760, L_0x55dd3fba5920, C4<1>, C4<1>; +v0x55dd3f9ff2d0_0 .net *"_s1", 0 0, L_0x55dd3fba5760; 1 drivers +v0x55dd3f9fd4b0_0 .net *"_s3", 0 0, L_0x55dd3fba5800; 1 drivers +v0x55dd3f9fd590_0 .net *"_s5", 0 0, L_0x55dd3fba5920; 1 drivers +v0x55dd3f9fba50_0 .net "clk", 0 0, o0x7fc2ff378458; alias, 0 drivers +v0x55dd3f9fbaf0_0 .net "in", 0 0, L_0x55dd3fba5620; alias, 1 drivers +v0x55dd3fa0f9a0_0 .net "p", 0 0, L_0x55dd3fba5a10; alias, 1 drivers +v0x55dd3fa0fa40_0 .net "reset", 0 0, o0x7fc2ff3784e8; alias, 0 drivers +v0x55dd3fa0b4e0_0 .var "x", 1 0; +L_0x55dd3fba5760 .part v0x55dd3fa0b4e0_0, 0, 1; +L_0x55dd3fba5800 .part v0x55dd3fa0b4e0_0, 1, 1; +L_0x55dd3fba5920 .reduce/nor L_0x55dd3fba5800; +S_0x55dd3fa09ae0 .scope module, "pa1" "pa" 6 180, 3 31 0, S_0x55dd3faf4800; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +L_0x55dd3fba7830 .functor AND 1, L_0x55dd3fba75b0, L_0x55dd3fba7740, C4<1>, C4<1>; +v0x55dd3fa08150_0 .net *"_s1", 0 0, L_0x55dd3fba75b0; 1 drivers +v0x55dd3fa063b0_0 .net *"_s3", 0 0, L_0x55dd3fba7650; 1 drivers +v0x55dd3fa06490_0 .net *"_s5", 0 0, L_0x55dd3fba7740; 1 drivers +v0x55dd3fa03f80_0 .net "clk", 0 0, o0x7fc2ff378458; alias, 0 drivers +v0x55dd3fa04020_0 .net "in", 0 0, L_0x55dd3fba7e00; 1 drivers +v0x55dd3fa025b0_0 .net "p", 0 0, L_0x55dd3fba7830; alias, 1 drivers +v0x55dd3fa02650_0 .net "reset", 0 0, o0x7fc2ff3784e8; alias, 0 drivers +v0x55dd3f9df7e0_0 .var "x", 1 0; +L_0x55dd3fba75b0 .part v0x55dd3f9df7e0_0, 0, 1; +L_0x55dd3fba7650 .part v0x55dd3f9df7e0_0, 1, 1; +L_0x55dd3fba7740 .reduce/nor L_0x55dd3fba7650; +S_0x55dd3f9df2a0 .scope module, "pa10" "pa" 6 195, 3 31 0, S_0x55dd3faf4800; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +L_0x55dd3fbab8e0 .functor AND 1, L_0x55dd3fbab660, L_0x55dd3fbab7f0, C4<1>, C4<1>; +v0x55dd3f9d7ff0_0 .net *"_s1", 0 0, L_0x55dd3fbab660; 1 drivers +v0x55dd3f9da6d0_0 .net *"_s3", 0 0, L_0x55dd3fbab700; 1 drivers +v0x55dd3f9da7b0_0 .net *"_s5", 0 0, L_0x55dd3fbab7f0; 1 drivers +v0x55dd3f9d9750_0 .net "clk", 0 0, o0x7fc2ff378458; alias, 0 drivers +v0x55dd3f9d97f0_0 .net "in", 0 0, L_0x55dd3fbadad0; alias, 1 drivers +v0x55dd3f9759b0_0 .net "p", 0 0, L_0x55dd3fbab8e0; alias, 1 drivers +v0x55dd3f975aa0_0 .net "reset", 0 0, o0x7fc2ff3784e8; alias, 0 drivers +v0x55dd3f9741e0_0 .var "x", 1 0; +L_0x55dd3fbab660 .part v0x55dd3f9741e0_0, 0, 1; +L_0x55dd3fbab700 .part v0x55dd3f9741e0_0, 1, 1; +L_0x55dd3fbab7f0 .reduce/nor L_0x55dd3fbab700; +S_0x55dd3f9b4660 .scope module, "pa11" "pa" 6 196, 3 31 0, S_0x55dd3faf4800; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +L_0x55dd3fbabc20 .functor AND 1, L_0x55dd3fbab9a0, L_0x55dd3fbabb30, C4<1>, C4<1>; +v0x55dd3f9ad1b0_0 .net *"_s1", 0 0, L_0x55dd3fbab9a0; 1 drivers +v0x55dd3f9ad290_0 .net *"_s3", 0 0, L_0x55dd3fbaba40; 1 drivers +v0x55dd3f972aa0_0 .net *"_s5", 0 0, L_0x55dd3fbabb30; 1 drivers +v0x55dd3f972b70_0 .net "clk", 0 0, o0x7fc2ff378458; alias, 0 drivers +v0x55dd3f9a5be0_0 .net "in", 0 0, L_0x55dd3fbabd30; 1 drivers +v0x55dd3f99dbc0_0 .net "p", 0 0, L_0x55dd3fbabc20; alias, 1 drivers +v0x55dd3f99dc80_0 .net "reset", 0 0, o0x7fc2ff3784e8; alias, 0 drivers +v0x55dd3f99b100_0 .var "x", 1 0; +L_0x55dd3fbab9a0 .part v0x55dd3f99b100_0, 0, 1; +L_0x55dd3fbaba40 .part v0x55dd3f99b100_0, 1, 1; +L_0x55dd3fbabb30 .reduce/nor L_0x55dd3fbaba40; +S_0x55dd3f99a520 .scope module, "pa12" "pa" 6 197, 3 31 0, S_0x55dd3faf4800; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +L_0x55dd3fbac0c0 .functor AND 1, L_0x55dd3fbabe40, L_0x55dd3fbabfd0, C4<1>, C4<1>; +v0x55dd3f999dd0_0 .net *"_s1", 0 0, L_0x55dd3fbabe40; 1 drivers +v0x55dd3f990cf0_0 .net *"_s3", 0 0, L_0x55dd3fbabee0; 1 drivers +v0x55dd3f990dd0_0 .net *"_s5", 0 0, L_0x55dd3fbabfd0; 1 drivers +v0x55dd3f98f050_0 .net "clk", 0 0, o0x7fc2ff378458; alias, 0 drivers +v0x55dd3f98f0f0_0 .net "in", 0 0, L_0x55dd3fbabc20; alias, 1 drivers +v0x55dd3f98df50_0 .net "p", 0 0, L_0x55dd3fbac0c0; alias, 1 drivers +v0x55dd3f98dff0_0 .net "reset", 0 0, o0x7fc2ff3784e8; alias, 0 drivers +v0x55dd3f98ce50_0 .var "x", 1 0; +L_0x55dd3fbabe40 .part v0x55dd3f98ce50_0, 0, 1; +L_0x55dd3fbabee0 .part v0x55dd3f98ce50_0, 1, 1; +L_0x55dd3fbabfd0 .reduce/nor L_0x55dd3fbabee0; +S_0x55dd3f98bcf0 .scope module, "pa13" "pa" 6 199, 3 31 0, S_0x55dd3faf4800; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +L_0x55dd3fbac450 .functor AND 1, L_0x55dd3fbac1d0, L_0x55dd3fbac360, C4<1>, C4<1>; +v0x55dd3f9825b0_0 .net *"_s1", 0 0, L_0x55dd3fbac1d0; 1 drivers +v0x55dd3f971300_0 .net *"_s3", 0 0, L_0x55dd3fbac270; 1 drivers +v0x55dd3f9713e0_0 .net *"_s5", 0 0, L_0x55dd3fbac360; 1 drivers +v0x55dd3f97e560_0 .net "clk", 0 0, o0x7fc2ff378458; alias, 0 drivers +v0x55dd3f97e600_0 .net "in", 0 0, L_0x55dd3fbac9f0; 1 drivers +v0x55dd3f97c8c0_0 .net "p", 0 0, L_0x55dd3fbac450; alias, 1 drivers +v0x55dd3f97c960_0 .net "reset", 0 0, o0x7fc2ff3784e8; alias, 0 drivers +v0x55dd3f991e90_0 .var "x", 1 0; +L_0x55dd3fbac1d0 .part v0x55dd3f991e90_0, 0, 1; +L_0x55dd3fbac270 .part v0x55dd3f991e90_0, 1, 1; +L_0x55dd3fbac360 .reduce/nor L_0x55dd3fbac270; +S_0x55dd3f9abb80 .scope module, "pa14" "pa" 6 200, 3 31 0, S_0x55dd3faf4800; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +L_0x55dd3fbad050 .functor AND 1, L_0x55dd3fbacdd0, L_0x55dd3fbacf60, C4<1>, C4<1>; +v0x55dd3f9aa220_0 .net *"_s1", 0 0, L_0x55dd3fbacdd0; 1 drivers +v0x55dd3f9a87e0_0 .net *"_s3", 0 0, L_0x55dd3fbace70; 1 drivers +v0x55dd3f9a88c0_0 .net *"_s5", 0 0, L_0x55dd3fbacf60; 1 drivers +v0x55dd3f9a6a20_0 .net "clk", 0 0, o0x7fc2ff378458; alias, 0 drivers +v0x55dd3f9a6ac0_0 .net "in", 0 0, v0x55dd3f7873d0_0; 1 drivers +v0x55dd3f9a4230_0 .net "p", 0 0, L_0x55dd3fbad050; alias, 1 drivers +v0x55dd3f9a42f0_0 .net "reset", 0 0, o0x7fc2ff3784e8; alias, 0 drivers +v0x55dd3f9a24d0_0 .var "x", 1 0; +L_0x55dd3fbacdd0 .part v0x55dd3f9a24d0_0, 0, 1; +L_0x55dd3fbace70 .part v0x55dd3f9a24d0_0, 1, 1; +L_0x55dd3fbacf60 .reduce/nor L_0x55dd3fbace70; +S_0x55dd3f9a0770 .scope module, "pa15" "pa" 6 202, 3 31 0, S_0x55dd3faf4800; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +L_0x55dd3fbad3e0 .functor AND 1, L_0x55dd3fbad160, L_0x55dd3fbad2f0, C4<1>, C4<1>; +v0x55dd3f99ea80_0 .net *"_s1", 0 0, L_0x55dd3fbad160; 1 drivers +v0x55dd3f9b6ed0_0 .net *"_s3", 0 0, L_0x55dd3fbad200; 1 drivers +v0x55dd3f9b6fb0_0 .net *"_s5", 0 0, L_0x55dd3fbad2f0; 1 drivers +v0x55dd3f9b5530_0 .net "clk", 0 0, o0x7fc2ff378458; alias, 0 drivers +v0x55dd3f9b55d0_0 .net "in", 0 0, o0x7fc2ff37b038; alias, 0 drivers +v0x55dd3f9b30d0_0 .net "p", 0 0, L_0x55dd3fbad3e0; alias, 1 drivers +v0x55dd3f9b3190_0 .net "reset", 0 0, o0x7fc2ff3784e8; alias, 0 drivers +v0x55dd3f9b1730_0 .var "x", 1 0; +L_0x55dd3fbad160 .part v0x55dd3f9b1730_0, 0, 1; +L_0x55dd3fbad200 .part v0x55dd3f9b1730_0, 1, 1; +L_0x55dd3fbad2f0 .reduce/nor L_0x55dd3fbad200; +S_0x55dd3f9afa00 .scope module, "pa2" "pa" 6 183, 3 31 0, S_0x55dd3faf4800; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +L_0x55dd3fba8190 .functor AND 1, L_0x55dd3fba7f10, L_0x55dd3fba80a0, C4<1>, C4<1>; +v0x55dd3f9ae070_0 .net *"_s1", 0 0, L_0x55dd3fba7f10; 1 drivers +v0x55dd3f99c620_0 .net *"_s3", 0 0, L_0x55dd3fba7fb0; 1 drivers +v0x55dd3f99c700_0 .net *"_s5", 0 0, L_0x55dd3fba80a0; 1 drivers +v0x55dd3f997ac0_0 .net "clk", 0 0, o0x7fc2ff378458; alias, 0 drivers +v0x55dd3f997b60_0 .net "in", 0 0, L_0x55dd3fba82f0; 1 drivers +v0x55dd3f988f00_0 .net "p", 0 0, L_0x55dd3fba8190; alias, 1 drivers +v0x55dd3f988fc0_0 .net "reset", 0 0, o0x7fc2ff3784e8; alias, 0 drivers +v0x55dd3f9871d0_0 .var "x", 1 0; +L_0x55dd3fba7f10 .part v0x55dd3f9871d0_0, 0, 1; +L_0x55dd3fba7fb0 .part v0x55dd3f9871d0_0, 1, 1; +L_0x55dd3fba80a0 .reduce/nor L_0x55dd3fba7fb0; +S_0x55dd3f9854a0 .scope module, "pa3" "pa" 6 184, 3 31 0, S_0x55dd3faf4800; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +L_0x55dd3fba88e0 .functor AND 1, L_0x55dd3fba8660, L_0x55dd3fba87f0, C4<1>, C4<1>; +v0x55dd3f983750_0 .net *"_s1", 0 0, L_0x55dd3fba8660; 1 drivers +v0x55dd3f91e5e0_0 .net *"_s3", 0 0, L_0x55dd3fba8700; 1 drivers +v0x55dd3f91e6c0_0 .net *"_s5", 0 0, L_0x55dd3fba87f0; 1 drivers +v0x55dd3f91cec0_0 .net "clk", 0 0, o0x7fc2ff378458; alias, 0 drivers +v0x55dd3f91cf60_0 .net "in", 0 0, L_0x55dd3fba8a40; 1 drivers +v0x55dd3f9128a0_0 .net "p", 0 0, L_0x55dd3fba88e0; alias, 1 drivers +v0x55dd3f912960_0 .net "reset", 0 0, o0x7fc2ff3784e8; alias, 0 drivers +v0x55dd3f91b840_0 .var "x", 1 0; +L_0x55dd3fba8660 .part v0x55dd3f91b840_0, 0, 1; +L_0x55dd3fba8700 .part v0x55dd3f91b840_0, 1, 1; +L_0x55dd3fba87f0 .reduce/nor L_0x55dd3fba8700; +S_0x55dd3f91a220 .scope module, "pa4" "pa" 6 185, 3 31 0, S_0x55dd3faf4800; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +L_0x55dd3fba8d80 .functor AND 1, L_0x55dd3fba8b00, L_0x55dd3fba8c90, C4<1>, C4<1>; +v0x55dd3f918c10_0 .net *"_s1", 0 0, L_0x55dd3fba8b00; 1 drivers +v0x55dd3f916320_0 .net *"_s3", 0 0, L_0x55dd3fba8ba0; 1 drivers +v0x55dd3f916400_0 .net *"_s5", 0 0, L_0x55dd3fba8c90; 1 drivers +v0x55dd3f914f40_0 .net "clk", 0 0, o0x7fc2ff378458; alias, 0 drivers +v0x55dd3f914fe0_0 .net "in", 0 0, L_0x55dd3fba8e90; 1 drivers +v0x55dd3f913bf0_0 .net "p", 0 0, L_0x55dd3fba8d80; alias, 1 drivers +v0x55dd3f913cc0_0 .net "reset", 0 0, o0x7fc2ff3784e8; alias, 0 drivers +v0x55dd3f943420_0 .var "x", 1 0; +L_0x55dd3fba8b00 .part v0x55dd3f943420_0, 0, 1; +L_0x55dd3fba8ba0 .part v0x55dd3f943420_0, 1, 1; +L_0x55dd3fba8c90 .reduce/nor L_0x55dd3fba8ba0; +S_0x55dd3f93a810 .scope module, "pa5" "pa" 6 186, 3 31 0, S_0x55dd3faf4800; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +L_0x55dd3fba94d0 .functor AND 1, L_0x55dd3fba9250, L_0x55dd3fba93e0, C4<1>, C4<1>; +v0x55dd3f938890_0 .net *"_s1", 0 0, L_0x55dd3fba9250; 1 drivers +v0x55dd3f934660_0 .net *"_s3", 0 0, L_0x55dd3fba92f0; 1 drivers +v0x55dd3f934740_0 .net *"_s5", 0 0, L_0x55dd3fba93e0; 1 drivers +v0x55dd3f9295d0_0 .net "clk", 0 0, o0x7fc2ff378458; alias, 0 drivers +v0x55dd3f929670_0 .net "in", 0 0, L_0x55dd3fba9af0; 1 drivers +v0x55dd3f9235f0_0 .net "p", 0 0, L_0x55dd3fba94d0; alias, 1 drivers +v0x55dd3f9236b0_0 .net "reset", 0 0, o0x7fc2ff3784e8; alias, 0 drivers +v0x55dd3f922ce0_0 .var "x", 1 0; +L_0x55dd3fba9250 .part v0x55dd3f922ce0_0, 0, 1; +L_0x55dd3fba92f0 .part v0x55dd3f922ce0_0, 1, 1; +L_0x55dd3fba93e0 .reduce/nor L_0x55dd3fba92f0; +S_0x55dd3f921b50 .scope module, "pa6" "pa" 6 189, 3 31 0, S_0x55dd3faf4800; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +L_0x55dd3fbaa160 .functor AND 1, L_0x55dd3fba9ee0, L_0x55dd3fbaa070, C4<1>, C4<1>; +v0x55dd3f920a30_0 .net *"_s1", 0 0, L_0x55dd3fba9ee0; 1 drivers +v0x55dd3f91f800_0 .net *"_s3", 0 0, L_0x55dd3fba9f80; 1 drivers +v0x55dd3f91f8e0_0 .net *"_s5", 0 0, L_0x55dd3fbaa070; 1 drivers +v0x55dd3f92d820_0 .net "clk", 0 0, o0x7fc2ff378458; alias, 0 drivers +v0x55dd3f92d8c0_0 .net "in", 0 0, L_0x55dd3fbaa270; 1 drivers +v0x55dd3f92bdf0_0 .net "p", 0 0, L_0x55dd3fbaa160; alias, 1 drivers +v0x55dd3f92beb0_0 .net "reset", 0 0, o0x7fc2ff3784e8; alias, 0 drivers +v0x55dd3f92a420_0 .var "x", 1 0; +L_0x55dd3fba9ee0 .part v0x55dd3f92a420_0, 0, 1; +L_0x55dd3fba9f80 .part v0x55dd3f92a420_0, 1, 1; +L_0x55dd3fbaa070 .reduce/nor L_0x55dd3fba9f80; +S_0x55dd3f928030 .scope module, "pa7" "pa" 6 190, 3 31 0, S_0x55dd3faf4800; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +L_0x55dd3fbaa560 .functor AND 1, L_0x55dd3fbaa2e0, L_0x55dd3fbaa470, C4<1>, C4<1>; +v0x55dd3f9262e0_0 .net *"_s1", 0 0, L_0x55dd3fbaa2e0; 1 drivers +v0x55dd3f924810_0 .net *"_s3", 0 0, L_0x55dd3fbaa380; 1 drivers +v0x55dd3f9248f0_0 .net *"_s5", 0 0, L_0x55dd3fbaa470; 1 drivers +v0x55dd3f9404f0_0 .net "clk", 0 0, o0x7fc2ff378458; alias, 0 drivers +v0x55dd3f940590_0 .net "in", 0 0, L_0x55dd3fbaa160; alias, 1 drivers +v0x55dd3f93eaf0_0 .net "p", 0 0, L_0x55dd3fbaa560; alias, 1 drivers +v0x55dd3f93eb90_0 .net "reset", 0 0, o0x7fc2ff3784e8; alias, 0 drivers +v0x55dd3f93d0f0_0 .var "x", 1 0; +L_0x55dd3fbaa2e0 .part v0x55dd3f93d0f0_0, 0, 1; +L_0x55dd3fbaa380 .part v0x55dd3f93d0f0_0, 1, 1; +L_0x55dd3fbaa470 .reduce/nor L_0x55dd3fbaa380; +S_0x55dd3f93b6f0 .scope module, "pa8" "pa" 6 191, 3 31 0, S_0x55dd3faf4800; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +L_0x55dd3fbaa8f0 .functor AND 1, L_0x55dd3fbaa670, L_0x55dd3fbaa800, C4<1>, C4<1>; +v0x55dd3f9396a0_0 .net *"_s1", 0 0, L_0x55dd3fbaa670; 1 drivers +v0x55dd3f936e70_0 .net *"_s3", 0 0, L_0x55dd3fbaa710; 1 drivers +v0x55dd3f936f50_0 .net *"_s5", 0 0, L_0x55dd3fbaa800; 1 drivers +v0x55dd3f935470_0 .net "clk", 0 0, o0x7fc2ff378458; alias, 0 drivers +v0x55dd3f935510_0 .net "in", 0 0, L_0x55dd3fbaa560; alias, 1 drivers +v0x55dd3f932d10_0 .net "p", 0 0, L_0x55dd3fbaa8f0; alias, 1 drivers +v0x55dd3f932db0_0 .net "reset", 0 0, o0x7fc2ff3784e8; alias, 0 drivers +v0x55dd3f94aa90_0 .var "x", 1 0; +L_0x55dd3fbaa670 .part v0x55dd3f94aa90_0, 0, 1; +L_0x55dd3fbaa710 .part v0x55dd3f94aa90_0, 1, 1; +L_0x55dd3fbaa800 .reduce/nor L_0x55dd3fbaa710; +S_0x55dd3f9490c0 .scope module, "pa9" "pa" 6 192, 3 31 0, S_0x55dd3faf4800; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +L_0x55dd3fbaac80 .functor AND 1, L_0x55dd3fbaaa00, L_0x55dd3fbaab90, C4<1>, C4<1>; +v0x55dd3f6d68a0_0 .net *"_s1", 0 0, L_0x55dd3fbaaa00; 1 drivers +v0x55dd3f6d6980_0 .net *"_s3", 0 0, L_0x55dd3fbaaaa0; 1 drivers +v0x55dd3f9476c0_0 .net *"_s5", 0 0, L_0x55dd3fbaab90; 1 drivers +v0x55dd3f947790_0 .net "clk", 0 0, o0x7fc2ff378458; alias, 0 drivers +v0x55dd3f945cc0_0 .net "in", 0 0, L_0x55dd3fbab2a0; 1 drivers +v0x55dd3f945db0_0 .net "p", 0 0, L_0x55dd3fbaac80; alias, 1 drivers +v0x55dd3f9442c0_0 .net "reset", 0 0, o0x7fc2ff3784e8; alias, 0 drivers +v0x55dd3f944360_0 .var "x", 1 0; +L_0x55dd3fbaaa00 .part v0x55dd3f944360_0, 0, 1; +L_0x55dd3fbaaaa0 .part v0x55dd3f944360_0, 1, 1; +L_0x55dd3fbaab90 .reduce/nor L_0x55dd3fbaaaa0; +S_0x55dd3f941ef0 .scope module, "pg0" "pg" 6 137, 3 15 0, S_0x55dd3faf4800; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +L_0x55dd3fba4db0 .functor AND 1, L_0x55dd3fba4b30, L_0x55dd3fba4cc0, C4<1>, C4<1>; +v0x55dd3f931310_0 .net *"_s1", 0 0, L_0x55dd3fba4b30; 1 drivers +v0x55dd3f9313d0_0 .net *"_s3", 0 0, L_0x55dd3fba4bd0; 1 drivers +v0x55dd3f92f5b0_0 .net *"_s5", 0 0, L_0x55dd3fba4cc0; 1 drivers +v0x55dd3f92f680_0 .net "clk", 0 0, o0x7fc2ff378458; alias, 0 drivers +v0x55dd3fa75970_0 .net "in", 0 0, o0x7fc2ff37c058; alias, 0 drivers +v0x55dd3fa75a80_0 .net "p", 0 0, L_0x55dd3fba4db0; alias, 1 drivers +v0x55dd3f989f70_0 .net "reset", 0 0, o0x7fc2ff3784e8; alias, 0 drivers +v0x55dd3f98a010_0 .var "x", 1 0; +L_0x55dd3fba4b30 .part v0x55dd3f98a010_0, 0, 1; +L_0x55dd3fba4bd0 .part v0x55dd3f98a010_0, 1, 1; +L_0x55dd3fba4cc0 .reduce/nor L_0x55dd3fba4bd0; +S_0x55dd3faf65b0 .scope module, "dly100us" "dly100us" 5 267; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +v0x55dd3fb140f0_0 .net *"_s0", 31 0, L_0x55dd3fbaf4e0; 1 drivers +L_0x7fc2ff329920 .functor BUFT 1, C4<0000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb141f0_0 .net *"_s3", 18 0, L_0x7fc2ff329920; 1 drivers +L_0x7fc2ff329968 .functor BUFT 1, C4<00000000000000000001001110001000>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb142d0_0 .net/2u *"_s4", 31 0, L_0x7fc2ff329968; 1 drivers +o0x7fc2ff37ecc8 .functor BUFZ 1, C4; HiZ drive +v0x55dd3fb14390_0 .net "clk", 0 0, o0x7fc2ff37ecc8; 0 drivers +o0x7fc2ff37ecf8 .functor BUFZ 1, C4; HiZ drive +v0x55dd3fb14450_0 .net "in", 0 0, o0x7fc2ff37ecf8; 0 drivers +v0x55dd3fb14560_0 .net "p", 0 0, L_0x55dd3fbaf660; 1 drivers +v0x55dd3fb14620_0 .var "r", 12 0; +o0x7fc2ff37ed88 .functor BUFZ 1, C4; HiZ drive +v0x55dd3fb14700_0 .net "reset", 0 0, o0x7fc2ff37ed88; 0 drivers +E_0x55dd3f991ff0 .event posedge, v0x55dd3fb14700_0, v0x55dd3fb14390_0; +L_0x55dd3fbaf4e0 .concat [ 13 19 0 0], v0x55dd3fb14620_0, L_0x7fc2ff329920; +L_0x55dd3fbaf660 .cmp/eq 32, L_0x55dd3fbaf4e0, L_0x7fc2ff329968; +S_0x55dd3faf8050 .scope module, "dly150ns" "dly150ns" 5 46; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +v0x55dd3fb14880_0 .net *"_s0", 31 0, L_0x55dd3fbaf7d0; 1 drivers +L_0x7fc2ff3299b0 .functor BUFT 1, C4<00000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb14980_0 .net *"_s3", 28 0, L_0x7fc2ff3299b0; 1 drivers +L_0x7fc2ff3299f8 .functor BUFT 1, C4<00000000000000000000000000000111>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb14a60_0 .net/2u *"_s4", 31 0, L_0x7fc2ff3299f8; 1 drivers +o0x7fc2ff37ef08 .functor BUFZ 1, C4; HiZ drive +v0x55dd3fb14b20_0 .net "clk", 0 0, o0x7fc2ff37ef08; 0 drivers +o0x7fc2ff37ef38 .functor BUFZ 1, C4; HiZ drive +v0x55dd3fb14be0_0 .net "in", 0 0, o0x7fc2ff37ef38; 0 drivers +v0x55dd3fb14cf0_0 .net "p", 0 0, L_0x55dd3fbaf8f0; 1 drivers +v0x55dd3fb14db0_0 .var "r", 2 0; +o0x7fc2ff37efc8 .functor BUFZ 1, C4; HiZ drive +v0x55dd3fb14e90_0 .net "reset", 0 0, o0x7fc2ff37efc8; 0 drivers +E_0x55dd3f9a5d40 .event posedge, v0x55dd3fb14e90_0, v0x55dd3fb14b20_0; +L_0x55dd3fbaf7d0 .concat [ 3 29 0 0], v0x55dd3fb14db0_0, L_0x7fc2ff3299b0; +L_0x55dd3fbaf8f0 .cmp/eq 32, L_0x55dd3fbaf7d0, L_0x7fc2ff3299f8; +S_0x55dd3faf9af0 .scope module, "dlymemory" "dlymemory" 7 36; + .timescale -9 -9; + .port_info 0 /INPUT 1 "i_clk" + .port_info 1 /INPUT 1 "i_reset_n" + .port_info 2 /INPUT 18 "i_address" + .port_info 3 /INPUT 1 "i_write" + .port_info 4 /INPUT 1 "i_read" + .port_info 5 /INPUT 36 "i_writedata" + .port_info 6 /OUTPUT 36 "o_readdata" + .port_info 7 /OUTPUT 1 "o_waitrequest" +L_0x55dd3fbb0a70 .functor NOT 1, L_0x55dd3fbb0440, C4<0>, C4<0>, C4<0>; +v0x55dd3fb15f70_0 .net *"_s1", 3 0, L_0x55dd3fbafa60; 1 drivers +v0x55dd3fb16070_0 .net *"_s12", 35 0, L_0x55dd3fbaff00; 1 drivers +v0x55dd3fb16150_0 .net *"_s14", 15 0, L_0x55dd3fbaffa0; 1 drivers +L_0x7fc2ff329ad0 .functor BUFT 1, C4<00>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb16210_0 .net *"_s17", 1 0, L_0x7fc2ff329ad0; 1 drivers +L_0x7fc2ff329b18 .functor BUFT 1, C4<000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb162f0_0 .net/2u *"_s18", 35 0, L_0x7fc2ff329b18; 1 drivers +v0x55dd3fb16420_0 .net *"_s2", 31 0, L_0x55dd3fbafb00; 1 drivers +v0x55dd3fb16500_0 .net *"_s22", 31 0, L_0x55dd3fbb0300; 1 drivers +L_0x7fc2ff329b60 .functor BUFT 1, C4<0000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb165e0_0 .net *"_s25", 27 0, L_0x7fc2ff329b60; 1 drivers +L_0x7fc2ff329ba8 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb166c0_0 .net/2u *"_s26", 31 0, L_0x7fc2ff329ba8; 1 drivers +L_0x7fc2ff329bf0 .functor BUFT 1, C4<000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb167a0_0 .net/2u *"_s30", 35 0, L_0x7fc2ff329bf0; 1 drivers +L_0x7fc2ff329a40 .functor BUFT 1, C4<0000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb16880_0 .net *"_s5", 27 0, L_0x7fc2ff329a40; 1 drivers +L_0x7fc2ff329a88 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb16960_0 .net/2u *"_s6", 31 0, L_0x7fc2ff329a88; 1 drivers +v0x55dd3fb16a40_0 .net "addr", 13 0, L_0x55dd3fbafde0; 1 drivers +v0x55dd3fb16b20_0 .net "addrok", 0 0, L_0x55dd3fbafc70; 1 drivers +v0x55dd3fb16be0_0 .var "dly", 3 0; +o0x7fc2ff37f6e8 .functor BUFZ 18, C4; HiZ drive +v0x55dd3fb16cc0_0 .net "i_address", 17 0, o0x7fc2ff37f6e8; 0 drivers +o0x7fc2ff37f0e8 .functor BUFZ 1, C4; HiZ drive +v0x55dd3fb16da0_0 .net "i_clk", 0 0, o0x7fc2ff37f0e8; 0 drivers +o0x7fc2ff37f328 .functor BUFZ 1, C4; HiZ drive +v0x55dd3fb16e40_0 .net "i_read", 0 0, o0x7fc2ff37f328; 0 drivers +o0x7fc2ff37f178 .functor BUFZ 1, C4; HiZ drive +v0x55dd3fb16ee0_0 .net "i_reset_n", 0 0, o0x7fc2ff37f178; 0 drivers +o0x7fc2ff37f1a8 .functor BUFZ 1, C4; HiZ drive +v0x55dd3fb16fd0_0 .net "i_write", 0 0, o0x7fc2ff37f1a8; 0 drivers +o0x7fc2ff37f718 .functor BUFZ 36, C4; HiZ drive +v0x55dd3fb17070_0 .net "i_writedata", 35 0, o0x7fc2ff37f718; 0 drivers +v0x55dd3fb17110 .array "mem", 16383 0, 35 0; +v0x55dd3fb171d0_0 .net "memword", 35 0, L_0x55dd3fbb0170; 1 drivers +v0x55dd3fb172b0_0 .net "o_readdata", 35 0, L_0x55dd3fbb0920; 1 drivers +v0x55dd3fb17390_0 .net "o_waitrequest", 0 0, L_0x55dd3fbb0a70; 1 drivers +v0x55dd3fb17450_0 .net "read_edge", 0 0, L_0x55dd3fbb07c0; 1 drivers +v0x55dd3fb174f0_0 .net "ready", 0 0, L_0x55dd3fbb0440; 1 drivers +v0x55dd3fb17590_0 .net "write_edge", 0 0, L_0x55dd3fbb05f0; 1 drivers +L_0x55dd3fbafa60 .part o0x7fc2ff37f6e8, 14, 4; +L_0x55dd3fbafb00 .concat [ 4 28 0 0], L_0x55dd3fbafa60, L_0x7fc2ff329a40; +L_0x55dd3fbafc70 .cmp/eq 32, L_0x55dd3fbafb00, L_0x7fc2ff329a88; +L_0x55dd3fbafde0 .part o0x7fc2ff37f6e8, 0, 14; +L_0x55dd3fbaff00 .array/port v0x55dd3fb17110, L_0x55dd3fbaffa0; +L_0x55dd3fbaffa0 .concat [ 14 2 0 0], L_0x55dd3fbafde0, L_0x7fc2ff329ad0; +L_0x55dd3fbb0170 .functor MUXZ 36, L_0x7fc2ff329b18, L_0x55dd3fbaff00, L_0x55dd3fbafc70, C4<>; +L_0x55dd3fbb0300 .concat [ 4 28 0 0], v0x55dd3fb16be0_0, L_0x7fc2ff329b60; +L_0x55dd3fbb0440 .cmp/eq 32, L_0x55dd3fbb0300, L_0x7fc2ff329ba8; +L_0x55dd3fbb0920 .functor MUXZ 36, L_0x7fc2ff329bf0, L_0x55dd3fbb0170, o0x7fc2ff37f328, C4<>; +S_0x55dd3fb14fd0 .scope module, "e0" "edgedet" 7 61, 8 16 0, S_0x55dd3faf9af0; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "signal" + .port_info 3 /OUTPUT 1 "p" +L_0x55dd3fbb0580 .functor NOT 1, v0x55dd3fb15430_0, C4<0>, C4<0>, C4<0>; +L_0x55dd3fbb05f0 .functor AND 1, o0x7fc2ff37f1a8, L_0x55dd3fbb0580, C4<1>, C4<1>; +v0x55dd3fb15270_0 .net *"_s0", 0 0, L_0x55dd3fbb0580; 1 drivers +v0x55dd3fb15370_0 .net "clk", 0 0, o0x7fc2ff37f0e8; alias, 0 drivers +v0x55dd3fb15430_0 .var "last", 0 0; +v0x55dd3fb154d0_0 .net "p", 0 0, L_0x55dd3fbb05f0; alias, 1 drivers +v0x55dd3fb15590_0 .net "reset", 0 0, o0x7fc2ff37f178; alias, 0 drivers +v0x55dd3fb156a0_0 .net "signal", 0 0, o0x7fc2ff37f1a8; alias, 0 drivers +E_0x55dd3f99b260/0 .event negedge, v0x55dd3fb15590_0; +E_0x55dd3f99b260/1 .event posedge, v0x55dd3fb15370_0; +E_0x55dd3f99b260 .event/or E_0x55dd3f99b260/0, E_0x55dd3f99b260/1; +S_0x55dd3fb157e0 .scope module, "e1" "edgedet" 7 62, 8 16 0, S_0x55dd3faf9af0; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "signal" + .port_info 3 /OUTPUT 1 "p" +L_0x55dd3fbb0750 .functor NOT 1, v0x55dd3fb15be0_0, C4<0>, C4<0>, C4<0>; +L_0x55dd3fbb07c0 .functor AND 1, o0x7fc2ff37f328, L_0x55dd3fbb0750, C4<1>, C4<1>; +v0x55dd3fb15a40_0 .net *"_s0", 0 0, L_0x55dd3fbb0750; 1 drivers +v0x55dd3fb15b20_0 .net "clk", 0 0, o0x7fc2ff37f0e8; alias, 0 drivers +v0x55dd3fb15be0_0 .var "last", 0 0; +v0x55dd3fb15cb0_0 .net "p", 0 0, L_0x55dd3fbb07c0; alias, 1 drivers +v0x55dd3fb15d50_0 .net "reset", 0 0, o0x7fc2ff37f178; alias, 0 drivers +v0x55dd3fb15e40_0 .net "signal", 0 0, o0x7fc2ff37f328; alias, 0 drivers +S_0x55dd3fa563a0 .scope module, "fakeapr" "fakeapr" 9 1; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "key_start" + .port_info 3 /INPUT 1 "key_read_in" + .port_info 4 /INPUT 1 "key_mem_cont" + .port_info 5 /INPUT 1 "key_inst_cont" + .port_info 6 /INPUT 1 "key_mem_stop" + .port_info 7 /INPUT 1 "key_inst_stop" + .port_info 8 /INPUT 1 "key_exec" + .port_info 9 /INPUT 1 "key_io_reset" + .port_info 10 /INPUT 1 "key_dep" + .port_info 11 /INPUT 1 "key_dep_nxt" + .port_info 12 /INPUT 1 "key_ex" + .port_info 13 /INPUT 1 "key_ex_nxt" + .port_info 14 /INPUT 1 "sw_addr_stop" + .port_info 15 /INPUT 1 "sw_mem_disable" + .port_info 16 /INPUT 1 "sw_repeat" + .port_info 17 /INPUT 1 "sw_power" + .port_info 18 /INPUT 36 "datasw" + .port_info 19 /INPUT 18 "mas" + .port_info 20 /INPUT 1 "sw_rim_maint" + .port_info 21 /INPUT 1 "sw_repeat_bypass" + .port_info 22 /INPUT 1 "sw_art3_maint" + .port_info 23 /INPUT 1 "sw_sct_maint" + .port_info 24 /INPUT 1 "sw_split_cyc" + .port_info 25 /OUTPUT 1 "power" + .port_info 26 /OUTPUT 18 "ir" + .port_info 27 /OUTPUT 36 "mi" + .port_info 28 /OUTPUT 36 "ar" + .port_info 29 /OUTPUT 36 "mb" + .port_info 30 /OUTPUT 36 "mq" + .port_info 31 /OUTPUT 18 "pc" + .port_info 32 /OUTPUT 18 "ma" + .port_info 33 /OUTPUT 1 "run" + .port_info 34 /OUTPUT 1 "mc_stop" + .port_info 35 /OUTPUT 1 "pi_active" + .port_info 36 /OUTPUT 7 "pih" + .port_info 37 /OUTPUT 7 "pir" + .port_info 38 /OUTPUT 7 "pio" + .port_info 39 /OUTPUT 8 "pr" + .port_info 40 /OUTPUT 8 "rlr" + .port_info 41 /OUTPUT 8 "rla" + .port_info 42 /OUTPUT 8 "ff0" + .port_info 43 /OUTPUT 8 "ff1" + .port_info 44 /OUTPUT 8 "ff2" + .port_info 45 /OUTPUT 8 "ff3" + .port_info 46 /OUTPUT 8 "ff4" + .port_info 47 /OUTPUT 8 "ff5" + .port_info 48 /OUTPUT 8 "ff6" + .port_info 49 /OUTPUT 8 "ff7" + .port_info 50 /OUTPUT 8 "ff8" + .port_info 51 /OUTPUT 8 "ff9" + .port_info 52 /OUTPUT 8 "ff10" + .port_info 53 /OUTPUT 8 "ff11" + .port_info 54 /OUTPUT 8 "ff12" + .port_info 55 /OUTPUT 8 "ff13" +o0x7fc2ff3802e8 .functor BUFZ 1, C4; HiZ drive +L_0x55dd3fbb0b30 .functor BUFZ 1, o0x7fc2ff3802e8, C4<0>, C4<0>, C4<0>; +L_0x7fc2ff329cc8 .functor BUFT 1, C4<100100100100100100101101101101101101>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb17790_0 .net "ar", 0 35, L_0x7fc2ff329cc8; 1 drivers +o0x7fc2ff37f9b8 .functor BUFZ 1, C4; HiZ drive +v0x55dd3fb17890_0 .net "clk", 0 0, o0x7fc2ff37f9b8; 0 drivers +o0x7fc2ff37f9e8 .functor BUFZ 36, C4; HiZ drive +v0x55dd3fb17950_0 .net "datasw", 0 35, o0x7fc2ff37f9e8; 0 drivers +L_0x7fc2ff32a028 .functor BUFT 1, C4<10000001>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb17a40_0 .net "ff0", 0 7, L_0x7fc2ff32a028; 1 drivers +L_0x7fc2ff32a070 .functor BUFT 1, C4<10000010>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb17b20_0 .net "ff1", 0 7, L_0x7fc2ff32a070; 1 drivers +L_0x7fc2ff32a2f8 .functor BUFT 1, C4<10001011>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb17c00_0 .net "ff10", 0 7, L_0x7fc2ff32a2f8; 1 drivers +L_0x7fc2ff32a340 .functor BUFT 1, C4<10001100>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb17ce0_0 .net "ff11", 0 7, L_0x7fc2ff32a340; 1 drivers +L_0x7fc2ff32a388 .functor BUFT 1, C4<10001101>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb17dc0_0 .net "ff12", 0 7, L_0x7fc2ff32a388; 1 drivers +L_0x7fc2ff32a3d0 .functor BUFT 1, C4<10001110>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb17ea0_0 .net "ff13", 0 7, L_0x7fc2ff32a3d0; 1 drivers +L_0x7fc2ff32a0b8 .functor BUFT 1, C4<10000011>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb17f80_0 .net "ff2", 0 7, L_0x7fc2ff32a0b8; 1 drivers +L_0x7fc2ff32a100 .functor BUFT 1, C4<10000100>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb18060_0 .net "ff3", 0 7, L_0x7fc2ff32a100; 1 drivers +L_0x7fc2ff32a148 .functor BUFT 1, C4<10000101>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb18140_0 .net "ff4", 0 7, L_0x7fc2ff32a148; 1 drivers +L_0x7fc2ff32a190 .functor BUFT 1, C4<10000110>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb18220_0 .net "ff5", 0 7, L_0x7fc2ff32a190; 1 drivers +L_0x7fc2ff32a1d8 .functor BUFT 1, C4<10000111>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb18300_0 .net "ff6", 0 7, L_0x7fc2ff32a1d8; 1 drivers +L_0x7fc2ff32a220 .functor BUFT 1, C4<10001000>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb183e0_0 .net "ff7", 0 7, L_0x7fc2ff32a220; 1 drivers +L_0x7fc2ff32a268 .functor BUFT 1, C4<10001001>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb184c0_0 .net "ff8", 0 7, L_0x7fc2ff32a268; 1 drivers +L_0x7fc2ff32a2b0 .functor BUFT 1, C4<10001010>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb185a0_0 .net "ff9", 0 7, L_0x7fc2ff32a2b0; 1 drivers +L_0x7fc2ff329c38 .functor BUFT 1, C4<001001001001001001>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb18680_0 .net "ir", 0 17, L_0x7fc2ff329c38; 1 drivers +o0x7fc2ff37fce8 .functor BUFZ 1, C4; HiZ drive +v0x55dd3fb18760_0 .net "key_dep", 0 0, o0x7fc2ff37fce8; 0 drivers +o0x7fc2ff37fd18 .functor BUFZ 1, C4; HiZ drive +v0x55dd3fb18820_0 .net "key_dep_nxt", 0 0, o0x7fc2ff37fd18; 0 drivers +o0x7fc2ff37fd48 .functor BUFZ 1, C4; HiZ drive +v0x55dd3fb188e0_0 .net "key_ex", 0 0, o0x7fc2ff37fd48; 0 drivers +o0x7fc2ff37fd78 .functor BUFZ 1, C4; HiZ drive +v0x55dd3fb189a0_0 .net "key_ex_nxt", 0 0, o0x7fc2ff37fd78; 0 drivers +o0x7fc2ff37fda8 .functor BUFZ 1, C4; HiZ drive +v0x55dd3fb18a60_0 .net "key_exec", 0 0, o0x7fc2ff37fda8; 0 drivers +o0x7fc2ff37fdd8 .functor BUFZ 1, C4; HiZ drive +v0x55dd3fb18b20_0 .net "key_inst_cont", 0 0, o0x7fc2ff37fdd8; 0 drivers +o0x7fc2ff37fe08 .functor BUFZ 1, C4; HiZ drive +v0x55dd3fb18be0_0 .net "key_inst_stop", 0 0, o0x7fc2ff37fe08; 0 drivers +o0x7fc2ff37fe38 .functor BUFZ 1, C4; HiZ drive +v0x55dd3fb18ca0_0 .net "key_io_reset", 0 0, o0x7fc2ff37fe38; 0 drivers +o0x7fc2ff37fe68 .functor BUFZ 1, C4; HiZ drive +v0x55dd3fb18d60_0 .net "key_mem_cont", 0 0, o0x7fc2ff37fe68; 0 drivers +o0x7fc2ff37fe98 .functor BUFZ 1, C4; HiZ drive +v0x55dd3fb18e20_0 .net "key_mem_stop", 0 0, o0x7fc2ff37fe98; 0 drivers +o0x7fc2ff37fec8 .functor BUFZ 1, C4; HiZ drive +v0x55dd3fb18ee0_0 .net "key_read_in", 0 0, o0x7fc2ff37fec8; 0 drivers +o0x7fc2ff37fef8 .functor BUFZ 1, C4; HiZ drive +v0x55dd3fb18fa0_0 .net "key_start", 0 0, o0x7fc2ff37fef8; 0 drivers +L_0x7fc2ff329de8 .functor BUFT 1, C4<100000100000100000>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb19060_0 .net "ma", 18 35, L_0x7fc2ff329de8; 1 drivers +o0x7fc2ff37ff58 .functor BUFZ 18, C4; HiZ drive +v0x55dd3fb19140_0 .net "mas", 18 35, o0x7fc2ff37ff58; 0 drivers +L_0x7fc2ff329d10 .functor BUFT 1, C4<110110110110110110111111111111111111>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb19220_0 .net "mb", 0 35, L_0x7fc2ff329d10; 1 drivers +v0x55dd3fb19300_0 .net "mc_stop", 0 0, L_0x55dd3fbb0d90; 1 drivers +L_0x7fc2ff329c80 .functor BUFT 1, C4<010010010010010010011011011011011011>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb193c0_0 .net "mi", 0 35, L_0x7fc2ff329c80; 1 drivers +L_0x7fc2ff329d58 .functor BUFT 1, C4<001000001000001000010000010000010000>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb194a0_0 .net "mq", 0 35, L_0x7fc2ff329d58; 1 drivers +L_0x7fc2ff329da0 .functor BUFT 1, C4<011000011000011000>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb19580_0 .net "pc", 18 35, L_0x7fc2ff329da0; 1 drivers +L_0x7fc2ff329e30 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb19660_0 .net "pi_active", 0 0, L_0x7fc2ff329e30; 1 drivers +L_0x7fc2ff329e78 .functor BUFT 1, C4<1010011>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb19720_0 .net "pih", 1 7, L_0x7fc2ff329e78; 1 drivers +L_0x7fc2ff329f08 .functor BUFT 1, C4<1100101>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb19800_0 .net "pio", 1 7, L_0x7fc2ff329f08; 1 drivers +L_0x7fc2ff329ec0 .functor BUFT 1, C4<1011100>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb198e0_0 .net "pir", 1 7, L_0x7fc2ff329ec0; 1 drivers +v0x55dd3fb199c0_0 .net "power", 0 0, L_0x55dd3fbb0b30; 1 drivers +L_0x7fc2ff329f50 .functor BUFT 1, C4<11101010>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb19a80_0 .net "pr", 18 25, L_0x7fc2ff329f50; 1 drivers +o0x7fc2ff380198 .functor BUFZ 1, C4; HiZ drive +v0x55dd3fb19b60_0 .net "reset", 0 0, o0x7fc2ff380198; 0 drivers +L_0x7fc2ff329fe0 .functor BUFT 1, C4<10010010>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb19c20_0 .net "rla", 18 25, L_0x7fc2ff329fe0; 1 drivers +L_0x7fc2ff329f98 .functor BUFT 1, C4<11011011>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb19d00_0 .net "rlr", 18 25, L_0x7fc2ff329f98; 1 drivers +v0x55dd3fb19de0_0 .net "run", 0 0, L_0x55dd3fbb0c90; 1 drivers +o0x7fc2ff380258 .functor BUFZ 1, C4; HiZ drive +v0x55dd3fb19ea0_0 .net "sw_addr_stop", 0 0, o0x7fc2ff380258; 0 drivers +o0x7fc2ff380288 .functor BUFZ 1, C4; HiZ drive +v0x55dd3fb19f60_0 .net "sw_art3_maint", 0 0, o0x7fc2ff380288; 0 drivers +o0x7fc2ff3802b8 .functor BUFZ 1, C4; HiZ drive +v0x55dd3fb1a020_0 .net "sw_mem_disable", 0 0, o0x7fc2ff3802b8; 0 drivers +v0x55dd3fb1a0e0_0 .net "sw_power", 0 0, o0x7fc2ff3802e8; 0 drivers +o0x7fc2ff380318 .functor BUFZ 1, C4; HiZ drive +v0x55dd3fb1a1a0_0 .net "sw_repeat", 0 0, o0x7fc2ff380318; 0 drivers +o0x7fc2ff380348 .functor BUFZ 1, C4; HiZ drive +v0x55dd3fb1a260_0 .net "sw_repeat_bypass", 0 0, o0x7fc2ff380348; 0 drivers +o0x7fc2ff380378 .functor BUFZ 1, C4; HiZ drive +v0x55dd3fb1a320_0 .net "sw_rim_maint", 0 0, o0x7fc2ff380378; 0 drivers +o0x7fc2ff3803a8 .functor BUFZ 1, C4; HiZ drive +v0x55dd3fb1a3e0_0 .net "sw_sct_maint", 0 0, o0x7fc2ff3803a8; 0 drivers +o0x7fc2ff3803d8 .functor BUFZ 1, C4; HiZ drive +v0x55dd3fb1a4a0_0 .net "sw_split_cyc", 0 0, o0x7fc2ff3803d8; 0 drivers +L_0x55dd3fbb0c90 .part o0x7fc2ff37f9e8, 0, 1; +L_0x55dd3fbb0d90 .part o0x7fc2ff37f9e8, 1, 1; +S_0x55dd3fafb590 .scope module, "fast162" "fast162" 10 1; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "power" + .port_info 3 /INPUT 1 "sw_single_step" + .port_info 4 /INPUT 1 "sw_restart" + .port_info 5 /INPUT 1 "membus_wr_rs_p0" + .port_info 6 /INPUT 1 "membus_rq_cyc_p0" + .port_info 7 /INPUT 1 "membus_rd_rq_p0" + .port_info 8 /INPUT 1 "membus_wr_rq_p0" + .port_info 9 /INPUT 15 "membus_ma_p0" + .port_info 10 /INPUT 4 "membus_sel_p0" + .port_info 11 /INPUT 1 "membus_fmc_select_p0" + .port_info 12 /INPUT 36 "membus_mb_in_p0" + .port_info 13 /OUTPUT 1 "membus_addr_ack_p0" + .port_info 14 /OUTPUT 1 "membus_rd_rs_p0" + .port_info 15 /OUTPUT 36 "membus_mb_out_p0" + .port_info 16 /INPUT 1 "membus_wr_rs_p1" + .port_info 17 /INPUT 1 "membus_rq_cyc_p1" + .port_info 18 /INPUT 1 "membus_rd_rq_p1" + .port_info 19 /INPUT 1 "membus_wr_rq_p1" + .port_info 20 /INPUT 15 "membus_ma_p1" + .port_info 21 /INPUT 4 "membus_sel_p1" + .port_info 22 /INPUT 1 "membus_fmc_select_p1" + .port_info 23 /INPUT 36 "membus_mb_in_p1" + .port_info 24 /OUTPUT 1 "membus_addr_ack_p1" + .port_info 25 /OUTPUT 1 "membus_rd_rs_p1" + .port_info 26 /OUTPUT 36 "membus_mb_out_p1" + .port_info 27 /INPUT 1 "membus_wr_rs_p2" + .port_info 28 /INPUT 1 "membus_rq_cyc_p2" + .port_info 29 /INPUT 1 "membus_rd_rq_p2" + .port_info 30 /INPUT 1 "membus_wr_rq_p2" + .port_info 31 /INPUT 15 "membus_ma_p2" + .port_info 32 /INPUT 4 "membus_sel_p2" + .port_info 33 /INPUT 1 "membus_fmc_select_p2" + .port_info 34 /INPUT 36 "membus_mb_in_p2" + .port_info 35 /OUTPUT 1 "membus_addr_ack_p2" + .port_info 36 /OUTPUT 1 "membus_rd_rs_p2" + .port_info 37 /OUTPUT 36 "membus_mb_out_p2" + .port_info 38 /INPUT 1 "membus_wr_rs_p3" + .port_info 39 /INPUT 1 "membus_rq_cyc_p3" + .port_info 40 /INPUT 1 "membus_rd_rq_p3" + .port_info 41 /INPUT 1 "membus_wr_rq_p3" + .port_info 42 /INPUT 15 "membus_ma_p3" + .port_info 43 /INPUT 4 "membus_sel_p3" + .port_info 44 /INPUT 1 "membus_fmc_select_p3" + .port_info 45 /INPUT 36 "membus_mb_in_p3" + .port_info 46 /OUTPUT 1 "membus_addr_ack_p3" + .port_info 47 /OUTPUT 1 "membus_rd_rs_p3" + .port_info 48 /OUTPUT 36 "membus_mb_out_p3" +P_0x55dd3f7aeee0 .param/l "fmc_p0_sel" 0 10 62, C4<1>; +P_0x55dd3f7aef20 .param/l "fmc_p1_sel" 0 10 63, C4<0>; +P_0x55dd3f7aef60 .param/l "fmc_p2_sel" 0 10 64, C4<0>; +P_0x55dd3f7aefa0 .param/l "fmc_p3_sel" 0 10 65, C4<0>; +P_0x55dd3f7aefe0 .param/l "memsel_p0" 0 10 58, C4<0000>; +P_0x55dd3f7af020 .param/l "memsel_p1" 0 10 59, C4<0000>; +P_0x55dd3f7af060 .param/l "memsel_p2" 0 10 60, C4<0000>; +P_0x55dd3f7af0a0 .param/l "memsel_p3" 0 10 61, C4<0000>; +L_0x55dd3fbb1d70 .functor OR 1, L_0x55dd3fbb1c00, v0x55dd3fb2b320_0, C4<0>, C4<0>; +o0x7fc2ff3848a8 .functor BUFZ 1, C4; HiZ drive +L_0x55dd3fbb2110 .functor BUFZ 1, o0x7fc2ff3848a8, C4<0>, C4<0>, C4<0>; +o0x7fc2ff3844e8 .functor BUFZ 1, C4; HiZ drive +L_0x55dd3fbb21d0 .functor BUFZ 1, o0x7fc2ff3844e8, C4<0>, C4<0>, C4<0>; +o0x7fc2ff3847e8 .functor BUFZ 1, C4; HiZ drive +L_0x55dd3fbb2290 .functor BUFZ 1, o0x7fc2ff3847e8, C4<0>, C4<0>, C4<0>; +L_0x7fc2ff32a580 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>; +L_0x55dd3fbb2b20 .functor AND 1, L_0x55dd3fbbb0c0, L_0x7fc2ff32a580, C4<1>, C4<1>; +L_0x7fc2ff32a5c8 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>; +L_0x55dd3fbb2c60 .functor AND 1, L_0x55dd3fbbb320, L_0x7fc2ff32a5c8, C4<1>, C4<1>; +L_0x55dd3fbb2d70 .functor BUFZ 36, L_0x55dd3fbb3560, C4<000000000000000000000000000000000000>, C4<000000000000000000000000000000000000>, C4<000000000000000000000000000000000000>; +L_0x7fc2ff32a610 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x55dd3fbb2de0 .functor AND 1, L_0x55dd3fbbb0c0, L_0x7fc2ff32a610, C4<1>, C4<1>; +L_0x7fc2ff32a658 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x55dd3fbb2f20 .functor AND 1, L_0x55dd3fbbb320, L_0x7fc2ff32a658, C4<1>, C4<1>; +L_0x7fc2ff32a6e8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x55dd3fbb3040 .functor AND 1, L_0x55dd3fbbb0c0, L_0x7fc2ff32a6e8, C4<1>, C4<1>; +L_0x7fc2ff32a730 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x55dd3fbb31d0 .functor AND 1, L_0x55dd3fbbb320, L_0x7fc2ff32a730, C4<1>, C4<1>; +L_0x7fc2ff32a7c0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x55dd3fbb3330 .functor AND 1, L_0x55dd3fbbb0c0, L_0x7fc2ff32a7c0, C4<1>, C4<1>; +L_0x7fc2ff32a808 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x55dd3fbb3440 .functor AND 1, L_0x55dd3fbbb320, L_0x7fc2ff32a808, C4<1>, C4<1>; +L_0x55dd3fbb3740 .functor NOT 1, v0x55dd3fb2b870_0, C4<0>, C4<0>, C4<0>; +L_0x7fc2ff32a8e0 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>; +L_0x55dd3fbb33d0 .functor AND 1, L_0x7fc2ff32a8e0, L_0x55dd3fbb3740, C4<1>, C4<1>; +L_0x55dd3fbb38d0 .functor NOT 1, v0x55dd3fb2b870_0, C4<0>, C4<0>, C4<0>; +L_0x7fc2ff32a928 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x55dd3fbb3a20 .functor AND 1, L_0x7fc2ff32a928, L_0x55dd3fbb38d0, C4<1>, C4<1>; +L_0x55dd3fbb3b30 .functor NOT 1, v0x55dd3fb2b870_0, C4<0>, C4<0>, C4<0>; +L_0x7fc2ff32a970 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x55dd3fbb3c40 .functor AND 1, L_0x7fc2ff32a970, L_0x55dd3fbb3b30, C4<1>, C4<1>; +L_0x55dd3fbb3d80 .functor NOT 1, v0x55dd3fb2b870_0, C4<0>, C4<0>, C4<0>; +L_0x7fc2ff32a9b8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x55dd3fbb3ea0 .functor AND 1, L_0x7fc2ff32a9b8, L_0x55dd3fbb3d80, C4<1>, C4<1>; +L_0x7fc2ff32aa00 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>; +L_0x55dd3fbb3f90 .functor AND 1, L_0x7fc2ff32aa00, v0x55dd3fb2ab50_0, C4<1>, C4<1>; +L_0x55dd3fbb4160 .functor NOT 1, L_0x55dd3fbb21d0, C4<0>, C4<0>, C4<0>; +L_0x55dd3fbb41d0 .functor AND 1, L_0x55dd3fbb3f90, L_0x55dd3fbb4160, C4<1>, C4<1>; +L_0x7fc2ff32aa48 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x55dd3fbb4400 .functor AND 1, L_0x7fc2ff32aa48, v0x55dd3fb2ab50_0, C4<1>, C4<1>; +L_0x55dd3fbb44c0 .functor NOT 1, L_0x55dd3fbb21d0, C4<0>, C4<0>, C4<0>; +L_0x55dd3fbb46a0 .functor AND 1, L_0x55dd3fbb4400, L_0x55dd3fbb44c0, C4<1>, C4<1>; +L_0x7fc2ff32aa90 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x55dd3fbb47b0 .functor AND 1, L_0x7fc2ff32aa90, v0x55dd3fb2ab50_0, C4<1>, C4<1>; +L_0x55dd3fbb49f0 .functor NOT 1, L_0x55dd3fbb21d0, C4<0>, C4<0>, C4<0>; +L_0x55dd3fbb4a60 .functor AND 1, L_0x55dd3fbb47b0, L_0x55dd3fbb49f0, C4<1>, C4<1>; +L_0x7fc2ff32aad8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x55dd3fbb4c70 .functor AND 1, L_0x7fc2ff32aad8, v0x55dd3fb2ab50_0, C4<1>, C4<1>; +L_0x55dd3fbb4d30 .functor NOT 1, L_0x55dd3fbb21d0, C4<0>, C4<0>, C4<0>; +L_0x55dd3fbb4eb0 .functor AND 1, L_0x55dd3fbb4c70, L_0x55dd3fbb4d30, C4<1>, C4<1>; +L_0x55dd3fbb50d0 .functor AND 1, L_0x55dd3fbb33d0, L_0x55dd3fbb3ba0, C4<1>, C4<1>; +o0x7fc2ff3841e8 .functor BUFZ 1, C4; HiZ drive +L_0x55dd3fbb5300 .functor AND 1, L_0x55dd3fbb50d0, o0x7fc2ff3841e8, C4<1>, C4<1>; +o0x7fc2ff384668 .functor BUFZ 1, C4; HiZ drive +L_0x55dd3fbb53c0 .functor AND 1, L_0x55dd3fbb5300, o0x7fc2ff384668, C4<1>, C4<1>; +L_0x55dd3fbb55b0 .functor AND 1, L_0x55dd3fbb3a20, L_0x55dd3fbb51e0, C4<1>, C4<1>; +o0x7fc2ff384218 .functor BUFZ 1, C4; HiZ drive +L_0x55dd3fbb56c0 .functor AND 1, L_0x55dd3fbb55b0, o0x7fc2ff384218, C4<1>, C4<1>; +o0x7fc2ff384698 .functor BUFZ 1, C4; HiZ drive +L_0x55dd3fbb58c0 .functor AND 1, L_0x55dd3fbb56c0, o0x7fc2ff384698, C4<1>, C4<1>; +L_0x55dd3fbb5060 .functor AND 1, L_0x55dd3fbb3c40, L_0x55dd3fbb5980, C4<1>, C4<1>; +o0x7fc2ff384248 .functor BUFZ 1, C4; HiZ drive +L_0x55dd3fbb5d10 .functor AND 1, L_0x55dd3fbb5060, o0x7fc2ff384248, C4<1>, C4<1>; +o0x7fc2ff3846c8 .functor BUFZ 1, C4; HiZ drive +L_0x55dd3fbb5dd0 .functor AND 1, L_0x55dd3fbb5d10, o0x7fc2ff3846c8, C4<1>, C4<1>; +L_0x55dd3fbb6140 .functor AND 1, L_0x55dd3fbb3ea0, L_0x55dd3fbb6020, C4<1>, C4<1>; +o0x7fc2ff384278 .functor BUFZ 1, C4; HiZ drive +L_0x55dd3fbb6280 .functor AND 1, L_0x55dd3fbb6140, o0x7fc2ff384278, C4<1>, C4<1>; +o0x7fc2ff3846f8 .functor BUFZ 1, C4; HiZ drive +L_0x55dd3fbb5e90 .functor AND 1, L_0x55dd3fbb6280, o0x7fc2ff3846f8, C4<1>, C4<1>; +o0x7fc2ff384968 .functor BUFZ 1, C4; HiZ drive +L_0x55dd3fbb6c60 .functor AND 1, o0x7fc2ff384968, v0x55dd3fb2b870_0, C4<1>, C4<1>; +L_0x55dd3fbb7d30 .functor NOT 1, v0x55dd3fb2b870_0, C4<0>, C4<0>, C4<0>; +L_0x55dd3fbb7da0 .functor AND 1, L_0x55dd3fbba000, L_0x55dd3fbb7d30, C4<1>, C4<1>; +L_0x55dd3fbb8040 .functor OR 1, L_0x55dd3fbba750, L_0x55dd3fbb7da0, C4<0>, C4<0>; +L_0x55dd3fbb84e0 .functor AND 1, L_0x55dd3fbb70d0, L_0x55dd3fbb21d0, C4<1>, C4<1>; +L_0x55dd3fbb9600 .functor NOT 1, L_0x55dd3fbb21d0, C4<0>, C4<0>, C4<0>; +L_0x55dd3fbb9670 .functor AND 1, L_0x55dd3fbb70d0, L_0x55dd3fbb9600, C4<1>, C4<1>; +L_0x55dd3fbb98e0 .functor AND 1, L_0x55dd3fbb9670, L_0x55dd3fbb2290, C4<1>, C4<1>; +L_0x55dd3fbb99f0 .functor AND 1, L_0x55dd3fbbac20, L_0x55dd3fbb2290, C4<1>, C4<1>; +L_0x55dd3fbb9c70 .functor OR 1, L_0x55dd3fbb98e0, L_0x55dd3fbb99f0, C4<0>, C4<0>; +L_0x55dd3fbba110 .functor NOT 1, L_0x55dd3fbb2290, C4<0>, C4<0>, C4<0>; +L_0x55dd3fbba350 .functor AND 1, L_0x55dd3fbbac20, L_0x55dd3fbba110, C4<1>, C4<1>; +L_0x55dd3fbba3c0 .functor OR 1, L_0x55dd3fbba350, L_0x55dd3fbb77f0, C4<0>, C4<0>; +L_0x55dd3fbba890 .functor OR 1, L_0x55dd3fbb6b00, L_0x55dd3fbb6720, C4<0>, C4<0>; +v0x55dd3fb26550_0 .net *"_s0", 31 0, L_0x55dd3fbb1270; 1 drivers +v0x55dd3fb26650_0 .net *"_s10", 35 0, L_0x55dd3fbb1e30; 1 drivers +v0x55dd3fb26730_0 .net/2u *"_s100", 0 0, L_0x7fc2ff32a9b8; 1 drivers +v0x55dd3fb267f0_0 .net *"_s102", 0 0, L_0x55dd3fbb3d80; 1 drivers +v0x55dd3fb268d0_0 .net/2u *"_s106", 0 0, L_0x7fc2ff32aa00; 1 drivers +v0x55dd3fb26a00_0 .net *"_s108", 0 0, L_0x55dd3fbb3f90; 1 drivers +v0x55dd3fb26ae0_0 .net *"_s110", 0 0, L_0x55dd3fbb4160; 1 drivers +v0x55dd3fb26bc0_0 .net/2u *"_s114", 0 0, L_0x7fc2ff32aa48; 1 drivers +v0x55dd3fb26ca0_0 .net *"_s116", 0 0, L_0x55dd3fbb4400; 1 drivers +v0x55dd3fb26d80_0 .net *"_s118", 0 0, L_0x55dd3fbb44c0; 1 drivers +L_0x7fc2ff32a4a8 .functor BUFT 1, C4<000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb26e60_0 .net/2u *"_s12", 35 0, L_0x7fc2ff32a4a8; 1 drivers +v0x55dd3fb26f40_0 .net/2u *"_s122", 0 0, L_0x7fc2ff32aa90; 1 drivers +v0x55dd3fb27020_0 .net *"_s124", 0 0, L_0x55dd3fbb47b0; 1 drivers +v0x55dd3fb27100_0 .net *"_s126", 0 0, L_0x55dd3fbb49f0; 1 drivers +v0x55dd3fb271e0_0 .net/2u *"_s130", 0 0, L_0x7fc2ff32aad8; 1 drivers +v0x55dd3fb272c0_0 .net *"_s132", 0 0, L_0x55dd3fbb4c70; 1 drivers +v0x55dd3fb273a0_0 .net *"_s134", 0 0, L_0x55dd3fbb4d30; 1 drivers +L_0x7fc2ff32ab20 .functor BUFT 1, C4<0000>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb27480_0 .net/2u *"_s138", 3 0, L_0x7fc2ff32ab20; 1 drivers +v0x55dd3fb27560_0 .net *"_s140", 0 0, L_0x55dd3fbb3ba0; 1 drivers +v0x55dd3fb27620_0 .net *"_s142", 0 0, L_0x55dd3fbb50d0; 1 drivers +v0x55dd3fb27700_0 .net *"_s144", 0 0, L_0x55dd3fbb5300; 1 drivers +L_0x7fc2ff32ab68 .functor BUFT 1, C4<0000>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb277e0_0 .net/2u *"_s148", 3 0, L_0x7fc2ff32ab68; 1 drivers +v0x55dd3fb278c0_0 .net *"_s150", 0 0, L_0x55dd3fbb51e0; 1 drivers +v0x55dd3fb27980_0 .net *"_s152", 0 0, L_0x55dd3fbb55b0; 1 drivers +v0x55dd3fb27a60_0 .net *"_s154", 0 0, L_0x55dd3fbb56c0; 1 drivers +L_0x7fc2ff32abb0 .functor BUFT 1, C4<0000>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb27b40_0 .net/2u *"_s158", 3 0, L_0x7fc2ff32abb0; 1 drivers +v0x55dd3fb27c20_0 .net *"_s160", 0 0, L_0x55dd3fbb5980; 1 drivers +v0x55dd3fb27ce0_0 .net *"_s162", 0 0, L_0x55dd3fbb5060; 1 drivers +v0x55dd3fb27dc0_0 .net *"_s164", 0 0, L_0x55dd3fbb5d10; 1 drivers +L_0x7fc2ff32abf8 .functor BUFT 1, C4<0000>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb27ea0_0 .net/2u *"_s168", 3 0, L_0x7fc2ff32abf8; 1 drivers +v0x55dd3fb27f80_0 .net *"_s170", 0 0, L_0x55dd3fbb6020; 1 drivers +v0x55dd3fb28040_0 .net *"_s172", 0 0, L_0x55dd3fbb6140; 1 drivers +v0x55dd3fb28120_0 .net *"_s174", 0 0, L_0x55dd3fbb6280; 1 drivers +v0x55dd3fb28410_0 .net *"_s180", 0 0, L_0x55dd3fbb7d30; 1 drivers +v0x55dd3fb284f0_0 .net *"_s182", 0 0, L_0x55dd3fbb7da0; 1 drivers +v0x55dd3fb285d0_0 .net *"_s188", 0 0, L_0x55dd3fbb9600; 1 drivers +v0x55dd3fb286b0_0 .net *"_s190", 0 0, L_0x55dd3fbb9670; 1 drivers +v0x55dd3fb28790_0 .net *"_s192", 0 0, L_0x55dd3fbb98e0; 1 drivers +v0x55dd3fb28870_0 .net *"_s194", 0 0, L_0x55dd3fbb99f0; 1 drivers +v0x55dd3fb28950_0 .net *"_s198", 0 0, L_0x55dd3fbba110; 1 drivers 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L_0x7fc2ff32a460; 1 drivers +v0x55dd3fb292f0_0 .net/2u *"_s42", 0 0, L_0x7fc2ff32a5c8; 1 drivers +v0x55dd3fb293d0_0 .net/2u *"_s48", 0 0, L_0x7fc2ff32a610; 1 drivers +v0x55dd3fb294b0_0 .net/2u *"_s52", 0 0, L_0x7fc2ff32a658; 1 drivers +v0x55dd3fb29590_0 .net/2u *"_s58", 0 0, L_0x7fc2ff32a6e8; 1 drivers +v0x55dd3fb29670_0 .net *"_s6", 0 0, L_0x55dd3fbb1c00; 1 drivers +v0x55dd3fb29730_0 .net/2u *"_s62", 0 0, L_0x7fc2ff32a730; 1 drivers +v0x55dd3fb29810_0 .net/2u *"_s68", 0 0, L_0x7fc2ff32a7c0; 1 drivers +v0x55dd3fb298f0_0 .net/2u *"_s72", 0 0, L_0x7fc2ff32a808; 1 drivers +L_0x7fc2ff32a898 .functor BUFT 1, C4<000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb299d0_0 .net/2u *"_s78", 35 0, L_0x7fc2ff32a898; 1 drivers +v0x55dd3fb29ab0_0 .net *"_s8", 0 0, L_0x55dd3fbb1d70; 1 drivers +v0x55dd3fb29b90_0 .net/2u *"_s82", 0 0, L_0x7fc2ff32a8e0; 1 drivers +v0x55dd3fb29c70_0 .net *"_s84", 0 0, L_0x55dd3fbb3740; 1 drivers +v0x55dd3fb29d50_0 .net/2u *"_s88", 0 0, L_0x7fc2ff32a928; 1 drivers +v0x55dd3fb29e30_0 .net *"_s90", 0 0, L_0x55dd3fbb38d0; 1 drivers +v0x55dd3fb29f10_0 .net/2u *"_s94", 0 0, L_0x7fc2ff32a970; 1 drivers +v0x55dd3fb2a400_0 .net *"_s96", 0 0, L_0x55dd3fbb3b30; 1 drivers +o0x7fc2ff380f18 .functor BUFZ 1, C4; HiZ drive +v0x55dd3fb2a4e0_0 .net "clk", 0 0, o0x7fc2ff380f18; 0 drivers +v0x55dd3fb2a580 .array "ff", 15 0, 0 35; +v0x55dd3fb2a640_0 .net "fm_clr", 0 0, L_0x55dd3fbb8d90; 1 drivers +v0x55dd3fb2a6e0_0 .net "fm_out", 0 35, L_0x55dd3fbb1f20; 1 drivers +v0x55dd3fb2a7a0_0 .net "fma", 21 35, L_0x55dd3fbb2400; 1 drivers +v0x55dd3fb2a880_0 .net "fma_rd_rq", 0 0, L_0x55dd3fbb21d0; 1 drivers +v0x55dd3fb2a920_0 .net "fma_rd_rq_D", 0 0, L_0x55dd3fbba9f0; 1 drivers +v0x55dd3fb2a9c0_0 .net "fma_rd_rq_P", 0 0, L_0x55dd3fbb7460; 1 drivers +v0x55dd3fb2aab0_0 .net "fma_wr_rq", 0 0, L_0x55dd3fbb2290; 1 drivers +v0x55dd3fb2ab50_0 .var "fmc_act", 0 0; +v0x55dd3fb2abf0_0 .net "fmc_addr_ack", 0 0, L_0x55dd3fbbb0c0; 1 drivers +v0x55dd3fb2ac90_0 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L_0x55dd3fbb2f20; 1 drivers +v0x55dd3fb2e120_0 .net "membus_rd_rs_p2", 0 0, L_0x55dd3fbb31d0; 1 drivers +v0x55dd3fb2e1e0_0 .net "membus_rd_rs_p3", 0 0, L_0x55dd3fbb3440; 1 drivers +v0x55dd3fb2e2a0_0 .net "membus_rq_cyc_p0", 0 0, o0x7fc2ff384668; 0 drivers +v0x55dd3fb2e360_0 .net "membus_rq_cyc_p1", 0 0, o0x7fc2ff384698; 0 drivers +v0x55dd3fb2e420_0 .net "membus_rq_cyc_p2", 0 0, o0x7fc2ff3846c8; 0 drivers +v0x55dd3fb2e4e0_0 .net "membus_rq_cyc_p3", 0 0, o0x7fc2ff3846f8; 0 drivers +o0x7fc2ff384728 .functor BUFZ 4, C4; HiZ drive +v0x55dd3fb2e5a0_0 .net "membus_sel_p0", 18 21, o0x7fc2ff384728; 0 drivers +o0x7fc2ff384758 .functor BUFZ 4, C4; HiZ drive +v0x55dd3fb2e680_0 .net "membus_sel_p1", 18 21, o0x7fc2ff384758; 0 drivers +o0x7fc2ff384788 .functor BUFZ 4, C4; HiZ drive +v0x55dd3fb2e760_0 .net "membus_sel_p2", 18 21, o0x7fc2ff384788; 0 drivers +o0x7fc2ff3847b8 .functor BUFZ 4, C4; HiZ drive +v0x55dd3fb2e840_0 .net "membus_sel_p3", 18 21, o0x7fc2ff3847b8; 0 drivers +v0x55dd3fb2e920_0 .net "membus_wr_rq_p0", 0 0, o0x7fc2ff3847e8; 0 drivers +o0x7fc2ff384818 .functor BUFZ 1, C4; HiZ drive +v0x55dd3fb2e9e0_0 .net "membus_wr_rq_p1", 0 0, o0x7fc2ff384818; 0 drivers +o0x7fc2ff384848 .functor BUFZ 1, C4; HiZ drive +v0x55dd3fb2eaa0_0 .net "membus_wr_rq_p2", 0 0, o0x7fc2ff384848; 0 drivers +o0x7fc2ff384878 .functor BUFZ 1, C4; HiZ drive +v0x55dd3fb2eb60_0 .net "membus_wr_rq_p3", 0 0, o0x7fc2ff384878; 0 drivers +v0x55dd3fb2ec20_0 .net "membus_wr_rs_p0", 0 0, o0x7fc2ff3848a8; 0 drivers +o0x7fc2ff3848d8 .functor BUFZ 1, C4; HiZ drive +v0x55dd3fb2ece0_0 .net "membus_wr_rs_p1", 0 0, o0x7fc2ff3848d8; 0 drivers +o0x7fc2ff384908 .functor BUFZ 1, C4; HiZ drive +v0x55dd3fb2eda0_0 .net "membus_wr_rs_p2", 0 0, o0x7fc2ff384908; 0 drivers +o0x7fc2ff384938 .functor BUFZ 1, C4; HiZ drive +v0x55dd3fb2ee60_0 .net "membus_wr_rs_p3", 0 0, o0x7fc2ff384938; 0 drivers +o0x7fc2ff382898 .functor BUFZ 1, C4; HiZ drive +v0x55dd3fb2ef20_0 .net "power", 0 0, o0x7fc2ff382898; 0 drivers +o0x7fc2ff380fa8 .functor BUFZ 1, C4; HiZ drive +v0x55dd3fb2eff0_0 .net "reset", 0 0, o0x7fc2ff380fa8; 0 drivers +v0x55dd3fb2f090_0 .net "sw_restart", 0 0, o0x7fc2ff384968; 0 drivers +o0x7fc2ff384998 .functor BUFZ 1, C4; HiZ drive +v0x55dd3fb2f130_0 .net "sw_single_step", 0 0, o0x7fc2ff384998; 0 drivers +v0x55dd3fb2f1f0_0 .net "wr_rs", 0 0, L_0x55dd3fbb2110; 1 drivers +E_0x55dd3f99dd20 .event posedge, v0x55dd3fb1b370_0; +L_0x55dd3fbb1270 .concat [ 15 17 0 0], L_0x55dd3fbb2400, L_0x7fc2ff32a418; +L_0x55dd3fbb1c00 .cmp/ne 32, L_0x55dd3fbb1270, L_0x7fc2ff32a460; +L_0x55dd3fbb1e30 .array/port v0x55dd3fb2a580, L_0x55dd3fbb2400; +L_0x55dd3fbb1f20 .functor MUXZ 36, L_0x7fc2ff32a4a8, L_0x55dd3fbb1e30, L_0x55dd3fbb1d70, C4<>; +L_0x55dd3fbb2330 .part o0x7fc2ff3842a8, 0, 4; +L_0x55dd3fbb2400 .concat [ 4 11 0 0], L_0x55dd3fbb2330, L_0x7fc2ff32a4f0; +L_0x55dd3fbb2580 .functor MUXZ 36, L_0x7fc2ff32a538, o0x7fc2ff3843f8, L_0x55dd3fbb4eb0, C4<>; +L_0x55dd3fbb26a0 .functor MUXZ 36, L_0x55dd3fbb2580, o0x7fc2ff3843c8, L_0x55dd3fbb4a60, C4<>; +L_0x55dd3fbb2840 .functor MUXZ 36, L_0x55dd3fbb26a0, o0x7fc2ff384398, L_0x55dd3fbb46a0, C4<>; +L_0x55dd3fbb2990 .functor MUXZ 36, L_0x55dd3fbb2840, o0x7fc2ff384368, L_0x55dd3fbb41d0, C4<>; +L_0x55dd3fbb3560 .functor MUXZ 36, L_0x7fc2ff32a898, L_0x55dd3fbb1f20, L_0x55dd3fbbb580, C4<>; +L_0x55dd3fbb3ba0 .cmp/eq 4, L_0x7fc2ff32ab20, o0x7fc2ff384728; +L_0x55dd3fbb51e0 .cmp/eq 4, L_0x7fc2ff32ab68, o0x7fc2ff384758; +L_0x55dd3fbb5980 .cmp/eq 4, L_0x7fc2ff32abb0, o0x7fc2ff384788; +L_0x55dd3fbb6020 .cmp/eq 4, L_0x7fc2ff32abf8, o0x7fc2ff3847b8; +S_0x55dd3fb1ae70 .scope module, "cmc_pg5" "pg" 10 152, 3 15 0, S_0x55dd3fafb590; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +L_0x55dd3fbb77f0 .functor AND 1, L_0x55dd3fbb7570, L_0x55dd3fbb7700, C4<1>, C4<1>; +v0x55dd3fb1b0c0_0 .net *"_s1", 0 0, L_0x55dd3fbb7570; 1 drivers +v0x55dd3fb1b1c0_0 .net *"_s3", 0 0, L_0x55dd3fbb7610; 1 drivers +v0x55dd3fb1b2a0_0 .net *"_s5", 0 0, L_0x55dd3fbb7700; 1 drivers +v0x55dd3fb1b370_0 .net "clk", 0 0, o0x7fc2ff380f18; alias, 0 drivers +v0x55dd3fb1b430_0 .net "in", 0 0, L_0x55dd3fbb2110; alias, 1 drivers +v0x55dd3fb1b540_0 .net "p", 0 0, L_0x55dd3fbb77f0; alias, 1 drivers +v0x55dd3fb1b600_0 .net "reset", 0 0, o0x7fc2ff380fa8; alias, 0 drivers +v0x55dd3fb1b6c0_0 .var "x", 1 0; +E_0x55dd3f9ff370 .event posedge, v0x55dd3fb1b600_0, v0x55dd3fb1b370_0; +L_0x55dd3fbb7570 .part v0x55dd3fb1b6c0_0, 0, 1; +L_0x55dd3fbb7610 .part v0x55dd3fb1b6c0_0, 1, 1; +L_0x55dd3fbb7700 .reduce/nor L_0x55dd3fbb7610; +S_0x55dd3fb1b820 .scope module, "fmc_bd0" "bd" 10 192, 3 49 0, S_0x55dd3fafb590; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +v0x55dd3fb1ba80_0 .net *"_s0", 31 0, L_0x55dd3fbbafd0; 1 drivers +L_0x7fc2ff32ae80 .functor BUFT 1, C4<00000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb1bb60_0 .net *"_s3", 28 0, L_0x7fc2ff32ae80; 1 drivers +L_0x7fc2ff32aec8 .functor BUFT 1, C4<00000000000000000000000000000100>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb1bc40_0 .net/2u *"_s4", 31 0, L_0x7fc2ff32aec8; 1 drivers +v0x55dd3fb1bd30_0 .net "clk", 0 0, o0x7fc2ff380f18; alias, 0 drivers +v0x55dd3fb1be00_0 .net "in", 0 0, L_0x55dd3fbb70d0; alias, 1 drivers +v0x55dd3fb1bef0_0 .net "p", 0 0, L_0x55dd3fbbb0c0; alias, 1 drivers +v0x55dd3fb1bfb0_0 .var "r", 2 0; +v0x55dd3fb1c090_0 .net "reset", 0 0, o0x7fc2ff380fa8; alias, 0 drivers +L_0x55dd3fbbafd0 .concat [ 3 29 0 0], v0x55dd3fb1bfb0_0, L_0x7fc2ff32ae80; +L_0x55dd3fbbb0c0 .cmp/eq 32, L_0x55dd3fbbafd0, L_0x7fc2ff32aec8; +S_0x55dd3fb1c1c0 .scope module, "fmc_bd1" "bd" 10 193, 3 49 0, S_0x55dd3fafb590; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +v0x55dd3fb1c430_0 .net *"_s0", 31 0, L_0x55dd3fbbb200; 1 drivers +L_0x7fc2ff32af10 .functor BUFT 1, C4<00000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb1c510_0 .net *"_s3", 28 0, L_0x7fc2ff32af10; 1 drivers +L_0x7fc2ff32af58 .functor BUFT 1, C4<00000000000000000000000000000100>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb1c5f0_0 .net/2u *"_s4", 31 0, L_0x7fc2ff32af58; 1 drivers +v0x55dd3fb1c6e0_0 .net "clk", 0 0, o0x7fc2ff380f18; alias, 0 drivers +v0x55dd3fb1c7d0_0 .net "in", 0 0, L_0x55dd3fbb83d0; alias, 1 drivers +v0x55dd3fb1c8e0_0 .net "p", 0 0, L_0x55dd3fbbb320; alias, 1 drivers +v0x55dd3fb1c9a0_0 .var "r", 2 0; +v0x55dd3fb1ca80_0 .net "reset", 0 0, o0x7fc2ff380fa8; alias, 0 drivers +L_0x55dd3fbbb200 .concat [ 3 29 0 0], v0x55dd3fb1c9a0_0, L_0x7fc2ff32af10; +L_0x55dd3fbbb320 .cmp/eq 32, L_0x55dd3fbbb200, L_0x7fc2ff32af58; +S_0x55dd3fb1cbf0 .scope module, "fmc_bd2" "bd" 10 194, 3 49 0, S_0x55dd3fafb590; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +v0x55dd3fb1ce30_0 .net *"_s0", 31 0, L_0x55dd3fbbb460; 1 drivers +L_0x7fc2ff32afa0 .functor BUFT 1, C4<00000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb1cf30_0 .net *"_s3", 28 0, L_0x7fc2ff32afa0; 1 drivers +L_0x7fc2ff32afe8 .functor BUFT 1, C4<00000000000000000000000000000100>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb1d010_0 .net/2u *"_s4", 31 0, L_0x7fc2ff32afe8; 1 drivers +v0x55dd3fb1d0d0_0 .net "clk", 0 0, o0x7fc2ff380f18; alias, 0 drivers +v0x55dd3fb1d170_0 .net "in", 0 0, L_0x55dd3fbb83d0; alias, 1 drivers +v0x55dd3fb1d260_0 .net "p", 0 0, L_0x55dd3fbbb580; alias, 1 drivers +v0x55dd3fb1d300_0 .var "r", 2 0; +v0x55dd3fb1d3e0_0 .net "reset", 0 0, o0x7fc2ff380fa8; alias, 0 drivers +L_0x55dd3fbbb460 .concat [ 3 29 0 0], v0x55dd3fb1d300_0, L_0x7fc2ff32afa0; +L_0x55dd3fbbb580 .cmp/eq 32, L_0x55dd3fbbb460, L_0x7fc2ff32afe8; +S_0x55dd3fb1d500 .scope module, "fmc_dly0" "dly200ns" 10 179, 5 61 0, S_0x55dd3fafb590; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +v0x55dd3fb1d790_0 .net *"_s0", 31 0, L_0x55dd3fbba660; 1 drivers +L_0x7fc2ff32ac40 .functor BUFT 1, C4<0000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb1d890_0 .net *"_s3", 27 0, L_0x7fc2ff32ac40; 1 drivers +L_0x7fc2ff32ac88 .functor BUFT 1, C4<00000000000000000000000000001010>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb1d970_0 .net/2u *"_s4", 31 0, L_0x7fc2ff32ac88; 1 drivers +v0x55dd3fb1da30_0 .net "clk", 0 0, o0x7fc2ff380f18; alias, 0 drivers +v0x55dd3fb1dad0_0 .net "in", 0 0, L_0x55dd3fbba890; 1 drivers +v0x55dd3fb1db90_0 .net "p", 0 0, L_0x55dd3fbba750; alias, 1 drivers +v0x55dd3fb1dc50_0 .var "r", 3 0; +v0x55dd3fb1dd30_0 .net "reset", 0 0, o0x7fc2ff380fa8; alias, 0 drivers +L_0x55dd3fbba660 .concat [ 4 28 0 0], v0x55dd3fb1dc50_0, L_0x7fc2ff32ac40; +L_0x55dd3fbba750 .cmp/eq 32, L_0x55dd3fbba660, L_0x7fc2ff32ac88; +S_0x55dd3fb1dee0 .scope module, "fmc_dly1" "dly50ns" 10 182, 5 1 0, S_0x55dd3fafb590; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +v0x55dd3fb1e0d0_0 .net *"_s0", 31 0, L_0x55dd3fbba900; 1 drivers +L_0x7fc2ff32acd0 .functor BUFT 1, C4<000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb1e1d0_0 .net *"_s3", 29 0, L_0x7fc2ff32acd0; 1 drivers +L_0x7fc2ff32ad18 .functor BUFT 1, C4<00000000000000000000000000000010>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb1e2b0_0 .net/2u *"_s4", 31 0, L_0x7fc2ff32ad18; 1 drivers +v0x55dd3fb1e3a0_0 .net "clk", 0 0, o0x7fc2ff380f18; alias, 0 drivers +v0x55dd3fb1e440_0 .net "in", 0 0, L_0x55dd3fbb7460; alias, 1 drivers +v0x55dd3fb1e550_0 .net "p", 0 0, L_0x55dd3fbba9f0; alias, 1 drivers +v0x55dd3fb1e610_0 .var "r", 1 0; +v0x55dd3fb1e6f0_0 .net "reset", 0 0, o0x7fc2ff380fa8; alias, 0 drivers +L_0x55dd3fbba900 .concat [ 2 30 0 0], v0x55dd3fb1e610_0, L_0x7fc2ff32acd0; +L_0x55dd3fbba9f0 .cmp/eq 32, L_0x55dd3fbba900, L_0x7fc2ff32ad18; +S_0x55dd3fb1e810 .scope module, "fmc_dly3" "dly100ns" 10 185, 5 31 0, S_0x55dd3fafb590; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +v0x55dd3fb1ea50_0 .net *"_s0", 31 0, L_0x55dd3fbbab30; 1 drivers +L_0x7fc2ff32ad60 .functor BUFT 1, C4<00000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb1eb50_0 .net *"_s3", 28 0, L_0x7fc2ff32ad60; 1 drivers +L_0x7fc2ff32ada8 .functor BUFT 1, C4<00000000000000000000000000000101>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb1ec30_0 .net/2u *"_s4", 31 0, L_0x7fc2ff32ada8; 1 drivers +v0x55dd3fb1ed20_0 .net "clk", 0 0, o0x7fc2ff380f18; alias, 0 drivers +v0x55dd3fb1edc0_0 .net "in", 0 0, L_0x55dd3fbb83d0; alias, 1 drivers +v0x55dd3fb1ef00_0 .net "p", 0 0, L_0x55dd3fbbac20; alias, 1 drivers +v0x55dd3fb1efc0_0 .var "r", 2 0; +v0x55dd3fb1f0a0_0 .net "reset", 0 0, o0x7fc2ff380fa8; alias, 0 drivers +L_0x55dd3fbbab30 .concat [ 3 29 0 0], v0x55dd3fb1efc0_0, L_0x7fc2ff32ad60; +L_0x55dd3fbbac20 .cmp/eq 32, L_0x55dd3fbbab30, L_0x7fc2ff32ada8; +S_0x55dd3fb1f1c0 .scope module, "fmc_dly4" "dly50ns" 10 188, 5 1 0, S_0x55dd3fafb590; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +v0x55dd3fb1f400_0 .net *"_s0", 31 0, L_0x55dd3fbbada0; 1 drivers +L_0x7fc2ff32adf0 .functor BUFT 1, C4<000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb1f500_0 .net *"_s3", 29 0, L_0x7fc2ff32adf0; 1 drivers +L_0x7fc2ff32ae38 .functor BUFT 1, C4<00000000000000000000000000000010>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb1f5e0_0 .net/2u *"_s4", 31 0, L_0x7fc2ff32ae38; 1 drivers +v0x55dd3fb1f6a0_0 .net "clk", 0 0, o0x7fc2ff380f18; alias, 0 drivers +v0x55dd3fb1f740_0 .net "in", 0 0, L_0x55dd3fbb94b0; alias, 1 drivers +v0x55dd3fb1f850_0 .net "p", 0 0, L_0x55dd3fbbae90; alias, 1 drivers +v0x55dd3fb1f910_0 .var "r", 1 0; +v0x55dd3fb1f9f0_0 .net "reset", 0 0, o0x7fc2ff380fa8; alias, 0 drivers +L_0x55dd3fbbada0 .concat [ 2 30 0 0], v0x55dd3fb1f910_0, L_0x7fc2ff32adf0; +L_0x55dd3fbbae90 .cmp/eq 32, L_0x55dd3fbbada0, L_0x7fc2ff32ae38; +S_0x55dd3fb1fb10 .scope module, "fmc_pa0" "pa" 10 154, 3 31 0, S_0x55dd3fafb590; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +L_0x55dd3fbb7bd0 .functor AND 1, L_0x55dd3fbb7950, L_0x55dd3fbb7ae0, C4<1>, C4<1>; +v0x55dd3fb1fde0_0 .net *"_s1", 0 0, L_0x55dd3fbb7950; 1 drivers +v0x55dd3fb1fee0_0 .net *"_s3", 0 0, L_0x55dd3fbb79f0; 1 drivers +v0x55dd3fb1ffc0_0 .net *"_s5", 0 0, L_0x55dd3fbb7ae0; 1 drivers +v0x55dd3fb20090_0 .net "clk", 0 0, o0x7fc2ff380f18; alias, 0 drivers +v0x55dd3fb20130_0 .net "in", 0 0, L_0x55dd3fbb8040; 1 drivers +v0x55dd3fb201f0_0 .net "p", 0 0, L_0x55dd3fbb7bd0; alias, 1 drivers +v0x55dd3fb202b0_0 .net "reset", 0 0, o0x7fc2ff380fa8; alias, 0 drivers +v0x55dd3fb20350_0 .var "x", 1 0; +L_0x55dd3fbb7950 .part v0x55dd3fb20350_0, 0, 1; +L_0x55dd3fbb79f0 .part v0x55dd3fb20350_0, 1, 1; +L_0x55dd3fbb7ae0 .reduce/nor L_0x55dd3fbb79f0; +S_0x55dd3fb204b0 .scope module, "fmc_pa1" "pa" 10 158, 3 31 0, S_0x55dd3fafb590; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +L_0x55dd3fbb83d0 .functor AND 1, L_0x55dd3fbb8150, L_0x55dd3fbb82e0, C4<1>, C4<1>; +v0x55dd3fb206f0_0 .net *"_s1", 0 0, L_0x55dd3fbb8150; 1 drivers +v0x55dd3fb207f0_0 .net *"_s3", 0 0, L_0x55dd3fbb81f0; 1 drivers +v0x55dd3fb208d0_0 .net *"_s5", 0 0, L_0x55dd3fbb82e0; 1 drivers +v0x55dd3fb209a0_0 .net "clk", 0 0, o0x7fc2ff380f18; alias, 0 drivers +v0x55dd3fb20a40_0 .net "in", 0 0, L_0x55dd3fbb84e0; 1 drivers +v0x55dd3fb20b50_0 .net "p", 0 0, L_0x55dd3fbb83d0; alias, 1 drivers +v0x55dd3fb20bf0_0 .net "reset", 0 0, o0x7fc2ff380fa8; alias, 0 drivers +v0x55dd3fb20c90_0 .var "x", 1 0; +L_0x55dd3fbb8150 .part v0x55dd3fb20c90_0, 0, 1; +L_0x55dd3fbb81f0 .part v0x55dd3fb20c90_0, 1, 1; +L_0x55dd3fbb82e0 .reduce/nor L_0x55dd3fbb81f0; +S_0x55dd3fb20df0 .scope module, "fmc_pa2" "pa" 10 161, 3 31 0, S_0x55dd3fafb590; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +L_0x55dd3fbb89b0 .functor AND 1, L_0x55dd3fbb8780, L_0x55dd3fbb88c0, C4<1>, C4<1>; +v0x55dd3fb21030_0 .net *"_s1", 0 0, L_0x55dd3fbb8780; 1 drivers +v0x55dd3fb21130_0 .net *"_s3", 0 0, L_0x55dd3fbb8820; 1 drivers +v0x55dd3fb21210_0 .net *"_s5", 0 0, L_0x55dd3fbb88c0; 1 drivers +v0x55dd3fb212e0_0 .net "clk", 0 0, o0x7fc2ff380f18; alias, 0 drivers +v0x55dd3fb21380_0 .net "in", 0 0, L_0x55dd3fbba9f0; alias, 1 drivers +v0x55dd3fb21470_0 .net "p", 0 0, L_0x55dd3fbb89b0; alias, 1 drivers +v0x55dd3fb21510_0 .net "reset", 0 0, o0x7fc2ff380fa8; alias, 0 drivers +v0x55dd3fb215b0_0 .var "x", 1 0; +L_0x55dd3fbb8780 .part v0x55dd3fb215b0_0, 0, 1; +L_0x55dd3fbb8820 .part v0x55dd3fb215b0_0, 1, 1; +L_0x55dd3fbb88c0 .reduce/nor L_0x55dd3fbb8820; +S_0x55dd3fb21740 .scope module, "fmc_pa3" "pa" 10 164, 3 31 0, S_0x55dd3fafb590; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +L_0x55dd3fbb8d90 .functor AND 1, L_0x55dd3fbb8b10, L_0x55dd3fbb8ca0, C4<1>, C4<1>; +v0x55dd3fb21980_0 .net *"_s1", 0 0, L_0x55dd3fbb8b10; 1 drivers +v0x55dd3fb21a80_0 .net *"_s3", 0 0, L_0x55dd3fbb8bb0; 1 drivers +v0x55dd3fb21b60_0 .net *"_s5", 0 0, L_0x55dd3fbb8ca0; 1 drivers +v0x55dd3fb21c30_0 .net "clk", 0 0, o0x7fc2ff380f18; alias, 0 drivers +v0x55dd3fb21cd0_0 .net "in", 0 0, L_0x55dd3fbb94b0; alias, 1 drivers +v0x55dd3fb21dc0_0 .net "p", 0 0, L_0x55dd3fbb8d90; alias, 1 drivers +v0x55dd3fb21e60_0 .net "reset", 0 0, o0x7fc2ff380fa8; alias, 0 drivers +v0x55dd3fb21f00_0 .var "x", 1 0; +L_0x55dd3fbb8b10 .part v0x55dd3fb21f00_0, 0, 1; +L_0x55dd3fbb8bb0 .part v0x55dd3fb21f00_0, 1, 1; +L_0x55dd3fbb8ca0 .reduce/nor L_0x55dd3fbb8bb0; +S_0x55dd3fb22090 .scope module, "fmc_pa4" "pa" 10 167, 3 31 0, S_0x55dd3fafb590; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +L_0x55dd3fbb90d0 .functor AND 1, L_0x55dd3fbb8ef0, L_0x55dd3fbb9030, C4<1>, C4<1>; +v0x55dd3fb222d0_0 .net *"_s1", 0 0, L_0x55dd3fbb8ef0; 1 drivers +v0x55dd3fb223d0_0 .net *"_s3", 0 0, L_0x55dd3fbb8f90; 1 drivers +v0x55dd3fb224b0_0 .net *"_s5", 0 0, L_0x55dd3fbb9030; 1 drivers +v0x55dd3fb22580_0 .net "clk", 0 0, o0x7fc2ff380f18; alias, 0 drivers +v0x55dd3fb22620_0 .net "in", 0 0, L_0x55dd3fbbae90; alias, 1 drivers +v0x55dd3fb22710_0 .net "p", 0 0, L_0x55dd3fbb90d0; alias, 1 drivers +v0x55dd3fb227b0_0 .net "reset", 0 0, o0x7fc2ff380fa8; alias, 0 drivers +v0x55dd3fb22850_0 .var "x", 1 0; +L_0x55dd3fbb8ef0 .part v0x55dd3fb22850_0, 0, 1; +L_0x55dd3fbb8f90 .part v0x55dd3fb22850_0, 1, 1; +L_0x55dd3fbb9030 .reduce/nor L_0x55dd3fbb8f90; +S_0x55dd3fb229e0 .scope module, "fmc_pa6" "pa" 10 174, 3 31 0, S_0x55dd3fafb590; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +L_0x55dd3fbba000 .functor AND 1, L_0x55dd3fbb9d80, L_0x55dd3fbb9f10, C4<1>, C4<1>; +v0x55dd3fb22c20_0 .net *"_s1", 0 0, L_0x55dd3fbb9d80; 1 drivers +v0x55dd3fb22d20_0 .net *"_s3", 0 0, L_0x55dd3fbb9e20; 1 drivers +v0x55dd3fb22e00_0 .net *"_s5", 0 0, L_0x55dd3fbb9f10; 1 drivers +v0x55dd3fb22ed0_0 .net "clk", 0 0, o0x7fc2ff380f18; alias, 0 drivers +v0x55dd3fb22f70_0 .net "in", 0 0, L_0x55dd3fbba3c0; 1 drivers +v0x55dd3fb23080_0 .net "p", 0 0, L_0x55dd3fbba000; alias, 1 drivers +v0x55dd3fb23140_0 .net "reset", 0 0, o0x7fc2ff380fa8; alias, 0 drivers +v0x55dd3fb231e0_0 .var "x", 1 0; +L_0x55dd3fbb9d80 .part v0x55dd3fb231e0_0, 0, 1; +L_0x55dd3fbb9e20 .part v0x55dd3fb231e0_0, 1, 1; +L_0x55dd3fbb9f10 .reduce/nor L_0x55dd3fbb9e20; +S_0x55dd3fb23340 .scope module, "fmc_pg0" "pg" 10 147, 3 15 0, S_0x55dd3fafb590; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +L_0x55dd3fbb6720 .functor AND 1, L_0x55dd3fbb5f50, L_0x55dd3fbb6630, C4<1>, C4<1>; +v0x55dd3fb23580_0 .net *"_s1", 0 0, L_0x55dd3fbb5f50; 1 drivers +v0x55dd3fb23680_0 .net *"_s3", 0 0, L_0x55dd3fbb6510; 1 drivers +v0x55dd3fb23760_0 .net *"_s5", 0 0, L_0x55dd3fbb6630; 1 drivers +v0x55dd3fb23830_0 .net "clk", 0 0, o0x7fc2ff380f18; alias, 0 drivers +v0x55dd3fb238d0_0 .net "in", 0 0, o0x7fc2ff382898; alias, 0 drivers +v0x55dd3fb239e0_0 .net "p", 0 0, L_0x55dd3fbb6720; alias, 1 drivers +v0x55dd3fb23aa0_0 .net "reset", 0 0, o0x7fc2ff380fa8; alias, 0 drivers +v0x55dd3fb23b40_0 .var "x", 1 0; +L_0x55dd3fbb5f50 .part v0x55dd3fb23b40_0, 0, 1; +L_0x55dd3fbb6510 .part v0x55dd3fb23b40_0, 1, 1; +L_0x55dd3fbb6630 .reduce/nor L_0x55dd3fbb6510; +S_0x55dd3fb23ca0 .scope module, "fmc_pg1" "pg" 10 148, 3 15 0, S_0x55dd3fafb590; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +L_0x55dd3fbb6b00 .functor AND 1, L_0x55dd3fbb6880, L_0x55dd3fbb6a10, C4<1>, C4<1>; +v0x55dd3fb23ee0_0 .net *"_s1", 0 0, L_0x55dd3fbb6880; 1 drivers +v0x55dd3fb23fe0_0 .net *"_s3", 0 0, L_0x55dd3fbb6920; 1 drivers +v0x55dd3fb240c0_0 .net *"_s5", 0 0, L_0x55dd3fbb6a10; 1 drivers +v0x55dd3fb24190_0 .net "clk", 0 0, o0x7fc2ff380f18; alias, 0 drivers +v0x55dd3fb24230_0 .net "in", 0 0, L_0x55dd3fbb6c60; 1 drivers +v0x55dd3fb24340_0 .net "p", 0 0, L_0x55dd3fbb6b00; alias, 1 drivers +v0x55dd3fb24400_0 .net "reset", 0 0, o0x7fc2ff380fa8; alias, 0 drivers +v0x55dd3fb244a0_0 .var "x", 1 0; +L_0x55dd3fbb6880 .part v0x55dd3fb244a0_0, 0, 1; +L_0x55dd3fbb6920 .part v0x55dd3fb244a0_0, 1, 1; +L_0x55dd3fbb6a10 .reduce/nor L_0x55dd3fbb6920; +S_0x55dd3fb24600 .scope module, "fmc_pg2" "pg" 10 150, 3 15 0, S_0x55dd3fafb590; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +L_0x55dd3fbb70d0 .functor AND 1, L_0x55dd3fbb6e50, L_0x55dd3fbb6fe0, C4<1>, C4<1>; +v0x55dd3fb24950_0 .net *"_s1", 0 0, L_0x55dd3fbb6e50; 1 drivers +v0x55dd3fb24a50_0 .net *"_s3", 0 0, L_0x55dd3fbb6ef0; 1 drivers +v0x55dd3fb24b30_0 .net *"_s5", 0 0, L_0x55dd3fbb6fe0; 1 drivers +v0x55dd3fb24c00_0 .net "clk", 0 0, o0x7fc2ff380f18; alias, 0 drivers +v0x55dd3fb24ca0_0 .net "in", 0 0, v0x55dd3fb2ab50_0; 1 drivers +v0x55dd3fb24db0_0 .net "p", 0 0, L_0x55dd3fbb70d0; alias, 1 drivers +v0x55dd3fb24e50_0 .net "reset", 0 0, o0x7fc2ff380fa8; alias, 0 drivers +v0x55dd3fb25100_0 .var "x", 1 0; +L_0x55dd3fbb6e50 .part v0x55dd3fb25100_0, 0, 1; +L_0x55dd3fbb6ef0 .part v0x55dd3fb25100_0, 1, 1; +L_0x55dd3fbb6fe0 .reduce/nor L_0x55dd3fbb6ef0; +S_0x55dd3fb25270 .scope module, "fmc_pg3" "pg" 10 151, 3 15 0, S_0x55dd3fafb590; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +L_0x55dd3fbb7460 .functor AND 1, L_0x55dd3fbb71e0, L_0x55dd3fbb7370, C4<1>, C4<1>; +v0x55dd3fb254b0_0 .net *"_s1", 0 0, L_0x55dd3fbb71e0; 1 drivers +v0x55dd3fb255b0_0 .net *"_s3", 0 0, L_0x55dd3fbb7280; 1 drivers +v0x55dd3fb25690_0 .net *"_s5", 0 0, L_0x55dd3fbb7370; 1 drivers +v0x55dd3fb25760_0 .net "clk", 0 0, o0x7fc2ff380f18; alias, 0 drivers +v0x55dd3fb25800_0 .net "in", 0 0, L_0x55dd3fbb21d0; alias, 1 drivers +v0x55dd3fb25910_0 .net "p", 0 0, L_0x55dd3fbb7460; alias, 1 drivers +v0x55dd3fb259b0_0 .net "reset", 0 0, o0x7fc2ff380fa8; alias, 0 drivers +v0x55dd3fb25a50_0 .var "x", 1 0; +L_0x55dd3fbb71e0 .part v0x55dd3fb25a50_0, 0, 1; +L_0x55dd3fbb7280 .part v0x55dd3fb25a50_0, 1, 1; +L_0x55dd3fbb7370 .reduce/nor L_0x55dd3fbb7280; +S_0x55dd3fb25bc0 .scope module, "fmc_pg5" "pg" 10 170, 3 15 0, S_0x55dd3fafb590; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +L_0x55dd3fbb94b0 .functor AND 1, L_0x55dd3fbb9230, L_0x55dd3fbb93c0, C4<1>, C4<1>; +v0x55dd3fb25e00_0 .net *"_s1", 0 0, L_0x55dd3fbb9230; 1 drivers +v0x55dd3fb25f00_0 .net *"_s3", 0 0, L_0x55dd3fbb92d0; 1 drivers +v0x55dd3fb25fe0_0 .net *"_s5", 0 0, L_0x55dd3fbb93c0; 1 drivers +v0x55dd3fb260b0_0 .net "clk", 0 0, o0x7fc2ff380f18; alias, 0 drivers +v0x55dd3fb26150_0 .net "in", 0 0, L_0x55dd3fbb9c70; 1 drivers +v0x55dd3fb26260_0 .net "p", 0 0, L_0x55dd3fbb94b0; alias, 1 drivers +v0x55dd3fb26350_0 .net "reset", 0 0, o0x7fc2ff380fa8; alias, 0 drivers +v0x55dd3fb263f0_0 .var "x", 1 0; +L_0x55dd3fbb9230 .part v0x55dd3fb263f0_0, 0, 1; +L_0x55dd3fbb92d0 .part v0x55dd3fb263f0_0, 1, 1; +L_0x55dd3fbb93c0 .reduce/nor L_0x55dd3fbb92d0; +S_0x55dd3faa7730 .scope module, "ldly100us" "ldly100us" 5 283; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" + .port_info 4 /OUTPUT 1 "l" +v0x55dd3fb2fa90_0 .net *"_s0", 31 0, L_0x55dd3fbbb6c0; 1 drivers +L_0x7fc2ff32b030 .functor BUFT 1, C4<0000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb2fb90_0 .net *"_s3", 18 0, L_0x7fc2ff32b030; 1 drivers +L_0x7fc2ff32b078 .functor BUFT 1, C4<00000000000000000001001110001000>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb2fc70_0 .net/2u *"_s4", 31 0, L_0x7fc2ff32b078; 1 drivers +o0x7fc2ff385388 .functor BUFZ 1, C4; HiZ drive +v0x55dd3fb2fd60_0 .net "clk", 0 0, o0x7fc2ff385388; 0 drivers +o0x7fc2ff3853b8 .functor BUFZ 1, C4; HiZ drive +v0x55dd3fb2fe20_0 .net "in", 0 0, o0x7fc2ff3853b8; 0 drivers +v0x55dd3fb2ff30_0 .var "l", 0 0; +v0x55dd3fb2fff0_0 .net "p", 0 0, L_0x55dd3fbbb7e0; 1 drivers +v0x55dd3fb300b0_0 .var "r", 12 0; +o0x7fc2ff385478 .functor BUFZ 1, C4; HiZ drive +v0x55dd3fb30190_0 .net "reset", 0 0, o0x7fc2ff385478; 0 drivers +E_0x55dd3f9f4a20 .event posedge, v0x55dd3fb30190_0, v0x55dd3fb2fd60_0; +L_0x55dd3fbbb6c0 .concat [ 13 19 0 0], v0x55dd3fb300b0_0, L_0x7fc2ff32b030; +L_0x55dd3fbbb7e0 .cmp/eq 32, L_0x55dd3fbbb6c0, L_0x7fc2ff32b078; +S_0x55dd3faa91d0 .scope module, "ldly1_5us" "ldly1_5us" 5 221; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" + .port_info 4 /OUTPUT 1 "l" +v0x55dd3fb30330_0 .net *"_s0", 31 0, L_0x55dd3fbbb950; 1 drivers +L_0x7fc2ff32b0c0 .functor BUFT 1, C4<0000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb30430_0 .net *"_s3", 24 0, L_0x7fc2ff32b0c0; 1 drivers +L_0x7fc2ff32b108 .functor BUFT 1, C4<00000000000000000000000001001011>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb30510_0 .net/2u *"_s4", 31 0, L_0x7fc2ff32b108; 1 drivers +o0x7fc2ff385628 .functor BUFZ 1, C4; HiZ drive +v0x55dd3fb305d0_0 .net "clk", 0 0, o0x7fc2ff385628; 0 drivers +o0x7fc2ff385658 .functor BUFZ 1, C4; HiZ drive +v0x55dd3fb30690_0 .net "in", 0 0, o0x7fc2ff385658; 0 drivers +v0x55dd3fb30750_0 .var "l", 0 0; +v0x55dd3fb30810_0 .net "p", 0 0, L_0x55dd3fbbba70; 1 drivers +v0x55dd3fb308d0_0 .var "r", 6 0; +o0x7fc2ff385718 .functor BUFZ 1, C4; HiZ drive +v0x55dd3fb309b0_0 .net "reset", 0 0, o0x7fc2ff385718; 0 drivers +E_0x55dd3fa79ab0 .event posedge, v0x55dd3fb309b0_0, v0x55dd3fb305d0_0; +L_0x55dd3fbbb950 .concat [ 7 25 0 0], v0x55dd3fb308d0_0, L_0x7fc2ff32b0c0; +L_0x55dd3fbbba70 .cmp/eq 32, L_0x55dd3fbbb950, L_0x7fc2ff32b108; +S_0x55dd3faaaca0 .scope module, "ldly2us" "ldly2us" 5 244; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" + .port_info 4 /OUTPUT 1 "l" +v0x55dd3fb30b90_0 .net *"_s0", 31 0, L_0x55dd3fbbbbe0; 1 drivers +L_0x7fc2ff32b150 .functor BUFT 1, C4<0000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb30c90_0 .net *"_s3", 24 0, L_0x7fc2ff32b150; 1 drivers +L_0x7fc2ff32b198 .functor BUFT 1, C4<00000000000000000000000001100100>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb30d70_0 .net/2u *"_s4", 31 0, L_0x7fc2ff32b198; 1 drivers +o0x7fc2ff3858c8 .functor BUFZ 1, C4; HiZ drive +v0x55dd3fb30e30_0 .net "clk", 0 0, o0x7fc2ff3858c8; 0 drivers +o0x7fc2ff3858f8 .functor BUFZ 1, C4; HiZ drive +v0x55dd3fb30ef0_0 .net "in", 0 0, o0x7fc2ff3858f8; 0 drivers +v0x55dd3fb30fb0_0 .var "l", 0 0; +v0x55dd3fb31070_0 .net "p", 0 0, L_0x55dd3fbbbd00; 1 drivers +v0x55dd3fb31130_0 .var "r", 6 0; +o0x7fc2ff3859b8 .functor BUFZ 1, C4; HiZ drive +v0x55dd3fb31210_0 .net "reset", 0 0, o0x7fc2ff3859b8; 0 drivers +E_0x55dd3fb30b10 .event posedge, v0x55dd3fb31210_0, v0x55dd3fb30e30_0; +L_0x55dd3fbbbbe0 .concat [ 7 25 0 0], v0x55dd3fb31130_0, L_0x7fc2ff32b150; +L_0x55dd3fbbbd00 .cmp/eq 32, L_0x55dd3fbbbbe0, L_0x7fc2ff32b198; +S_0x55dd3faac770 .scope module, "memif" "memif" 11 1; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 2 "s_address" + .port_info 3 /INPUT 1 "s_write" + .port_info 4 /INPUT 1 "s_read" + .port_info 5 /INPUT 32 "s_writedata" + .port_info 6 /OUTPUT 32 "s_readdata" + .port_info 7 /OUTPUT 1 "s_waitrequest" + .port_info 8 /OUTPUT 18 "m_address" + .port_info 9 /OUTPUT 1 "m_write" + .port_info 10 /OUTPUT 1 "m_read" + .port_info 11 /OUTPUT 36 "m_writedata" + .port_info 12 /INPUT 36 "m_readdata" + .port_info 13 /INPUT 1 "m_waitrequest" +L_0x55dd3fbbbe70 .functor BUFZ 18, v0x55dd3fb326f0_0, C4<000000000000000000>, C4<000000000000000000>, C4<000000000000000000>; +L_0x55dd3fbbbee0 .functor BUFZ 36, v0x55dd3fb33580_0, C4<000000000000000000000000000000000000>, C4<000000000000000000000000000000000000>, C4<000000000000000000000000000000000000>; +L_0x55dd3fbbc3b0 .functor OR 1, L_0x55dd3fbbc080, L_0x55dd3fbbc250, C4<0>, C4<0>; +L_0x55dd3fbbc510 .functor AND 1, L_0x55dd3fbbc3b0, L_0x55dd3fbbc420, C4<1>, C4<1>; +L_0x55dd3fbbc650 .functor OR 1, L_0x55dd3fbbc510, v0x55dd3fb334c0_0, C4<0>, C4<0>; +v0x55dd3fb32470_0 .net *"_s4", 0 0, L_0x55dd3fbbc3b0; 1 drivers +L_0x7fc2ff32b1e0 .functor BUFT 1, C4<10>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb32570_0 .net/2u *"_s6", 1 0, L_0x7fc2ff32b1e0; 1 drivers +v0x55dd3fb32650_0 .net *"_s8", 0 0, L_0x55dd3fbbc420; 1 drivers +v0x55dd3fb326f0_0 .var "addr", 17 0; +o0x7fc2ff385b08 .functor BUFZ 1, C4; HiZ drive +v0x55dd3fb327d0_0 .net "clk", 0 0, o0x7fc2ff385b08; 0 drivers +v0x55dd3fb32910_0 .net "m_address", 17 0, L_0x55dd3fbbbe70; 1 drivers +v0x55dd3fb329f0_0 .var "m_read", 0 0; +o0x7fc2ff385f58 .functor BUFZ 36, C4; HiZ drive +v0x55dd3fb32ab0_0 .net "m_readdata", 35 0, o0x7fc2ff385f58; 0 drivers +o0x7fc2ff385f88 .functor BUFZ 1, C4; HiZ drive +v0x55dd3fb32b90_0 .net "m_waitrequest", 0 0, o0x7fc2ff385f88; 0 drivers +v0x55dd3fb32ce0_0 .var "m_write", 0 0; +v0x55dd3fb32da0_0 .net "m_writedata", 35 0, L_0x55dd3fbbbee0; 1 drivers +v0x55dd3fb32e80_0 .net "read_edge", 0 0, L_0x55dd3fbbc250; 1 drivers +v0x55dd3fb32f20_0 .net "req", 0 0, L_0x55dd3fbbc510; 1 drivers +o0x7fc2ff385b98 .functor BUFZ 1, C4; HiZ drive +v0x55dd3fb32fc0_0 .net "reset", 0 0, o0x7fc2ff385b98; 0 drivers +o0x7fc2ff386048 .functor BUFZ 2, C4; HiZ drive +v0x55dd3fb33060_0 .net "s_address", 1 0, o0x7fc2ff386048; 0 drivers +o0x7fc2ff385d48 .functor BUFZ 1, C4; HiZ drive +v0x55dd3fb33140_0 .net "s_read", 0 0, o0x7fc2ff385d48; 0 drivers +v0x55dd3fb331e0_0 .var "s_readdata", 31 0; +v0x55dd3fb332a0_0 .net "s_waitrequest", 0 0, L_0x55dd3fbbc650; 1 drivers +o0x7fc2ff385bc8 .functor BUFZ 1, C4; HiZ drive +v0x55dd3fb33360_0 .net "s_write", 0 0, o0x7fc2ff385bc8; 0 drivers +o0x7fc2ff3860d8 .functor BUFZ 32, C4; HiZ drive +v0x55dd3fb33400_0 .net "s_writedata", 31 0, o0x7fc2ff3860d8; 0 drivers +v0x55dd3fb334c0_0 .var "waiting", 0 0; +v0x55dd3fb33580_0 .var "word", 35 0; +v0x55dd3fb33660_0 .net "write_edge", 0 0, L_0x55dd3fbbc080; 1 drivers +E_0x55dd3fb31400 .event edge, v0x55dd3fb33060_0, v0x55dd3fb33580_0; +L_0x55dd3fbbc420 .cmp/eq 2, o0x7fc2ff386048, L_0x7fc2ff32b1e0; +S_0x55dd3fb31480 .scope module, "e0" "edgedet" 11 29, 8 16 0, S_0x55dd3faac770; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "signal" + .port_info 3 /OUTPUT 1 "p" +L_0x55dd3fbbbfb0 .functor NOT 1, v0x55dd3fb318d0_0, C4<0>, C4<0>, C4<0>; +L_0x55dd3fbbc080 .functor AND 1, o0x7fc2ff385bc8, L_0x55dd3fbbbfb0, C4<1>, C4<1>; +v0x55dd3fb31710_0 .net *"_s0", 0 0, L_0x55dd3fbbbfb0; 1 drivers +v0x55dd3fb31810_0 .net "clk", 0 0, o0x7fc2ff385b08; alias, 0 drivers +v0x55dd3fb318d0_0 .var "last", 0 0; +v0x55dd3fb319a0_0 .net "p", 0 0, L_0x55dd3fbbc080; alias, 1 drivers +v0x55dd3fb31a60_0 .net "reset", 0 0, o0x7fc2ff385b98; alias, 0 drivers +v0x55dd3fb31b70_0 .net "signal", 0 0, o0x7fc2ff385bc8; alias, 0 drivers +E_0x55dd3fb31690/0 .event negedge, v0x55dd3fb31a60_0; +E_0x55dd3fb31690/1 .event posedge, v0x55dd3fb31810_0; +E_0x55dd3fb31690 .event/or E_0x55dd3fb31690/0, E_0x55dd3fb31690/1; +S_0x55dd3fb31cb0 .scope module, "e1" "edgedet" 11 30, 8 16 0, S_0x55dd3faac770; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "signal" + .port_info 3 /OUTPUT 1 "p" +L_0x55dd3fbbc1e0 .functor NOT 1, v0x55dd3fb320e0_0, C4<0>, C4<0>, C4<0>; +L_0x55dd3fbbc250 .functor AND 1, o0x7fc2ff385d48, L_0x55dd3fbbc1e0, C4<1>, C4<1>; +v0x55dd3fb31f10_0 .net *"_s0", 0 0, L_0x55dd3fbbc1e0; 1 drivers +v0x55dd3fb31ff0_0 .net "clk", 0 0, o0x7fc2ff385b08; alias, 0 drivers +v0x55dd3fb320e0_0 .var "last", 0 0; +v0x55dd3fb321b0_0 .net "p", 0 0, L_0x55dd3fbbc250; alias, 1 drivers +v0x55dd3fb32250_0 .net "reset", 0 0, o0x7fc2ff385b98; alias, 0 drivers +v0x55dd3fb32340_0 .net "signal", 0 0, o0x7fc2ff385d48; alias, 0 drivers +S_0x55dd3faae210 .scope module, "memory" "memory" 7 1; + .timescale -9 -9; + .port_info 0 /INPUT 1 "i_clk" + .port_info 1 /INPUT 1 "i_reset_n" + .port_info 2 /INPUT 18 "i_address" + .port_info 3 /INPUT 1 "i_write" + .port_info 4 /INPUT 1 "i_read" + .port_info 5 /INPUT 36 "i_writedata" + .port_info 6 /OUTPUT 36 "o_readdata" + .port_info 7 /OUTPUT 1 "o_waitrequest" +v0x55dd3fb33950_0 .net *"_s1", 3 0, L_0x55dd3fbbc710; 1 drivers +v0x55dd3fb33a50_0 .net *"_s12", 35 0, L_0x55dd3fbbcbe0; 1 drivers +v0x55dd3fb33b30_0 .net *"_s14", 15 0, L_0x55dd3fbbcc80; 1 drivers +L_0x7fc2ff32b2b8 .functor BUFT 1, C4<00>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb33c20_0 .net *"_s17", 1 0, L_0x7fc2ff32b2b8; 1 drivers +L_0x7fc2ff32b300 .functor BUFT 1, C4<000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb33d00_0 .net/2u *"_s18", 35 0, L_0x7fc2ff32b300; 1 drivers +v0x55dd3fb33e30_0 .net *"_s2", 31 0, L_0x55dd3fbbc7e0; 1 drivers +L_0x7fc2ff32b348 .functor BUFT 1, C4<000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb33f10_0 .net/2u *"_s22", 35 0, L_0x7fc2ff32b348; 1 drivers +L_0x7fc2ff32b228 .functor BUFT 1, C4<0000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb33ff0_0 .net *"_s5", 27 0, L_0x7fc2ff32b228; 1 drivers +L_0x7fc2ff32b270 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb340d0_0 .net/2u *"_s6", 31 0, L_0x7fc2ff32b270; 1 drivers +v0x55dd3fb341b0_0 .net "addr", 13 0, L_0x55dd3fbbcac0; 1 drivers +v0x55dd3fb34290_0 .net "addrok", 0 0, L_0x55dd3fbbc950; 1 drivers +o0x7fc2ff386618 .functor BUFZ 18, C4; HiZ drive +v0x55dd3fb34350_0 .net "i_address", 17 0, o0x7fc2ff386618; 0 drivers +o0x7fc2ff386648 .functor BUFZ 1, C4; HiZ drive +v0x55dd3fb34430_0 .net "i_clk", 0 0, o0x7fc2ff386648; 0 drivers +o0x7fc2ff386678 .functor BUFZ 1, C4; HiZ drive +v0x55dd3fb344f0_0 .net "i_read", 0 0, o0x7fc2ff386678; 0 drivers +o0x7fc2ff3866a8 .functor BUFZ 1, C4; HiZ drive +v0x55dd3fb345b0_0 .net "i_reset_n", 0 0, o0x7fc2ff3866a8; 0 drivers +o0x7fc2ff3866d8 .functor BUFZ 1, C4; HiZ drive +v0x55dd3fb34670_0 .net "i_write", 0 0, o0x7fc2ff3866d8; 0 drivers +o0x7fc2ff386708 .functor BUFZ 36, C4; HiZ drive +v0x55dd3fb34730_0 .net "i_writedata", 35 0, o0x7fc2ff386708; 0 drivers +v0x55dd3fb34810 .array "mem", 16383 0, 35 0; +v0x55dd3fb348d0_0 .net "memword", 35 0, L_0x55dd3fbbce10; 1 drivers +v0x55dd3fb349b0_0 .net "o_readdata", 35 0, L_0x55dd3fbbcfa0; 1 drivers +L_0x7fc2ff32b390 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb34a90_0 .net "o_waitrequest", 0 0, L_0x7fc2ff32b390; 1 drivers +E_0x55dd3fb338d0/0 .event negedge, v0x55dd3fb345b0_0; +E_0x55dd3fb338d0/1 .event posedge, v0x55dd3fb34430_0; +E_0x55dd3fb338d0 .event/or E_0x55dd3fb338d0/0, E_0x55dd3fb338d0/1; +L_0x55dd3fbbc710 .part o0x7fc2ff386618, 14, 4; +L_0x55dd3fbbc7e0 .concat [ 4 28 0 0], L_0x55dd3fbbc710, L_0x7fc2ff32b228; +L_0x55dd3fbbc950 .cmp/eq 32, L_0x55dd3fbbc7e0, L_0x7fc2ff32b270; +L_0x55dd3fbbcac0 .part o0x7fc2ff386618, 0, 14; +L_0x55dd3fbbcbe0 .array/port v0x55dd3fb34810, L_0x55dd3fbbcc80; +L_0x55dd3fbbcc80 .concat [ 14 2 0 0], L_0x55dd3fbbcac0, L_0x7fc2ff32b2b8; +L_0x55dd3fbbce10 .functor MUXZ 36, L_0x7fc2ff32b300, L_0x55dd3fbbcbe0, L_0x55dd3fbbc950, C4<>; +L_0x55dd3fbbcfa0 .functor MUXZ 36, L_0x7fc2ff32b348, L_0x55dd3fbbce10, o0x7fc2ff386678, C4<>; +S_0x55dd3faafcb0 .scope module, "memory_16" "memory_16" 12 1; + .timescale -9 -9; + .port_info 0 /INPUT 1 "i_clk" + .port_info 1 /INPUT 1 "i_reset_n" + .port_info 2 /INPUT 18 "i_address" + .port_info 3 /INPUT 1 "i_write" + .port_info 4 /INPUT 1 "i_read" + .port_info 5 /INPUT 36 "i_writedata" + .port_info 6 /OUTPUT 36 "o_readdata" + .port_info 7 /OUTPUT 1 "o_waitrequest" +v0x55dd3fb35980_0 .net *"_s1", 13 0, L_0x55dd3fbbd130; 1 drivers +v0x55dd3fb35a80_0 .net *"_s2", 31 0, L_0x55dd3fbbd1d0; 1 drivers +L_0x7fc2ff32b3d8 .functor BUFT 1, C4<000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb35b60_0 .net *"_s5", 17 0, L_0x7fc2ff32b3d8; 1 drivers +L_0x7fc2ff32b420 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb35c20_0 .net/2u *"_s6", 31 0, L_0x7fc2ff32b420; 1 drivers +v0x55dd3fb35d00_0 .net "addr", 3 0, L_0x55dd3fbbd4b0; 1 drivers +v0x55dd3fb35dc0_0 .net "addrok", 0 0, L_0x55dd3fbbd340; 1 drivers +o0x7fc2ff386cd8 .functor BUFZ 18, C4; HiZ drive +v0x55dd3fb35e60_0 .net "i_address", 17 0, o0x7fc2ff386cd8; 0 drivers +o0x7fc2ff386a38 .functor BUFZ 1, C4; HiZ drive +v0x55dd3fb35f40_0 .net "i_clk", 0 0, o0x7fc2ff386a38; 0 drivers +o0x7fc2ff386d08 .functor BUFZ 1, C4; HiZ drive +v0x55dd3fb36010_0 .net "i_read", 0 0, o0x7fc2ff386d08; 0 drivers +o0x7fc2ff386d38 .functor BUFZ 1, C4; HiZ drive +v0x55dd3fb36140_0 .net "i_reset_n", 0 0, o0x7fc2ff386d38; 0 drivers +o0x7fc2ff386d68 .functor BUFZ 1, C4; HiZ drive +v0x55dd3fb36200_0 .net "i_write", 0 0, o0x7fc2ff386d68; 0 drivers +o0x7fc2ff386a68 .functor BUFZ 36, C4; HiZ drive +v0x55dd3fb362c0_0 .net "i_writedata", 35 0, o0x7fc2ff386a68; 0 drivers +v0x55dd3fb363b0_0 .net "o_readdata", 35 0, L_0x55dd3fbbd800; 1 drivers +v0x55dd3fb36480_0 .var "o_waitrequest", 0 0; +v0x55dd3fb36520_0 .var "we", 0 0; +L_0x55dd3fbbd130 .part o0x7fc2ff386cd8, 4, 14; +L_0x55dd3fbbd1d0 .concat [ 14 18 0 0], L_0x55dd3fbbd130, L_0x7fc2ff32b3d8; +L_0x55dd3fbbd340 .cmp/eq 32, L_0x55dd3fbbd1d0, L_0x7fc2ff32b420; +L_0x55dd3fbbd4b0 .part o0x7fc2ff386cd8, 0, 4; +S_0x55dd3fb34c50 .scope module, "ram" "onchip_ram" 12 18, 13 1 0, S_0x55dd3faafcb0; + .timescale -9 -9; + .port_info 0 /INPUT 36 "data" + .port_info 1 /INPUT 4 "addr" + .port_info 2 /INPUT 1 "we" + .port_info 3 /INPUT 1 "clk" + .port_info 4 /OUTPUT 36 "q" +P_0x55dd3fb32c30 .param/l "ADDR_WIDTH" 0 13 2, +C4<00000000000000000000000000000100>; +P_0x55dd3fb32c70 .param/l "DATA_WIDTH" 0 13 2, +C4<00000000000000000000000000100100>; +L_0x55dd3fbbd800 .functor BUFZ 36, L_0x55dd3fbbd620, C4<000000000000000000000000000000000000>, C4<000000000000000000000000000000000000>, C4<000000000000000000000000000000000000>; +v0x55dd3fb35000_0 .net *"_s0", 35 0, L_0x55dd3fbbd620; 1 drivers +v0x55dd3fb35100_0 .net *"_s2", 5 0, L_0x55dd3fbbd6c0; 1 drivers +L_0x7fc2ff32b468 .functor BUFT 1, C4<00>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb351e0_0 .net *"_s5", 1 0, L_0x7fc2ff32b468; 1 drivers +v0x55dd3fb352d0_0 .net "addr", 3 0, L_0x55dd3fbbd4b0; alias, 1 drivers +v0x55dd3fb353b0_0 .var "addr_reg", 3 0; +v0x55dd3fb354e0_0 .net "clk", 0 0, o0x7fc2ff386a38; alias, 0 drivers +v0x55dd3fb355a0_0 .net "data", 35 0, o0x7fc2ff386a68; alias, 0 drivers +v0x55dd3fb35680_0 .net "q", 35 0, L_0x55dd3fbbd800; alias, 1 drivers +v0x55dd3fb35760 .array "ram", 0 15, 35 0; +v0x55dd3fb35820_0 .net "we", 0 0, v0x55dd3fb36520_0; 1 drivers +E_0x55dd3fb34f80 .event posedge, v0x55dd3fb354e0_0; +L_0x55dd3fbbd620 .array/port v0x55dd3fb35760, L_0x55dd3fbbd6c0; +L_0x55dd3fbbd6c0 .concat [ 4 2 0 0], v0x55dd3fb353b0_0, L_0x7fc2ff32b468; +S_0x55dd3fac4a50 .scope module, "memory_16k" "memory_16k" 14 1; + .timescale -9 -9; + .port_info 0 /INPUT 1 "i_clk" + .port_info 1 /INPUT 1 "i_reset_n" + .port_info 2 /INPUT 18 "i_address" + .port_info 3 /INPUT 1 "i_write" + .port_info 4 /INPUT 1 "i_read" + .port_info 5 /INPUT 36 "i_writedata" + .port_info 6 /OUTPUT 36 "o_readdata" + .port_info 7 /OUTPUT 1 "o_waitrequest" +v0x55dd3fb374c0_0 .net *"_s1", 3 0, L_0x55dd3fbbd910; 1 drivers +v0x55dd3fb375c0_0 .net *"_s2", 31 0, L_0x55dd3fbbd9b0; 1 drivers +L_0x7fc2ff32b4b0 .functor BUFT 1, C4<0000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb376a0_0 .net *"_s5", 27 0, L_0x7fc2ff32b4b0; 1 drivers +L_0x7fc2ff32b4f8 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb37760_0 .net/2u *"_s6", 31 0, L_0x7fc2ff32b4f8; 1 drivers +v0x55dd3fb37840_0 .net "addr", 13 0, L_0x55dd3fbbdc30; 1 drivers +v0x55dd3fb37900_0 .net "addrok", 0 0, L_0x55dd3fbbdaf0; 1 drivers +o0x7fc2ff3872d8 .functor BUFZ 18, C4; HiZ drive +v0x55dd3fb379a0_0 .net "i_address", 17 0, o0x7fc2ff3872d8; 0 drivers +o0x7fc2ff387038 .functor BUFZ 1, C4; HiZ drive +v0x55dd3fb37a80_0 .net "i_clk", 0 0, o0x7fc2ff387038; 0 drivers +o0x7fc2ff387308 .functor BUFZ 1, C4; HiZ drive +v0x55dd3fb37b50_0 .net "i_read", 0 0, o0x7fc2ff387308; 0 drivers +o0x7fc2ff387338 .functor BUFZ 1, C4; HiZ drive +v0x55dd3fb37c80_0 .net "i_reset_n", 0 0, o0x7fc2ff387338; 0 drivers +o0x7fc2ff387368 .functor BUFZ 1, C4; HiZ drive +v0x55dd3fb37d40_0 .net "i_write", 0 0, o0x7fc2ff387368; 0 drivers +o0x7fc2ff387068 .functor BUFZ 36, C4; HiZ drive +v0x55dd3fb37e00_0 .net "i_writedata", 35 0, o0x7fc2ff387068; 0 drivers +v0x55dd3fb37ef0_0 .net "o_readdata", 35 0, L_0x55dd3fbbdf80; 1 drivers +v0x55dd3fb37fc0_0 .var "o_waitrequest", 0 0; +v0x55dd3fb38060_0 .var "we", 0 0; +L_0x55dd3fbbd910 .part o0x7fc2ff3872d8, 14, 4; +L_0x55dd3fbbd9b0 .concat [ 4 28 0 0], L_0x55dd3fbbd910, L_0x7fc2ff32b4b0; +L_0x55dd3fbbdaf0 .cmp/eq 32, L_0x55dd3fbbd9b0, L_0x7fc2ff32b4f8; +L_0x55dd3fbbdc30 .part o0x7fc2ff3872d8, 0, 14; +S_0x55dd3fb366d0 .scope module, "ram" "onchip_ram" 14 18, 13 1 0, S_0x55dd3fac4a50; + .timescale -9 -9; + .port_info 0 /INPUT 36 "data" + .port_info 1 /INPUT 14 "addr" + .port_info 2 /INPUT 1 "we" + .port_info 3 /INPUT 1 "clk" + .port_info 4 /OUTPUT 36 "q" +P_0x55dd3fb36870 .param/l "ADDR_WIDTH" 0 13 2, +C4<00000000000000000000000000001110>; +P_0x55dd3fb368b0 .param/l "DATA_WIDTH" 0 13 2, +C4<00000000000000000000000000100100>; +L_0x55dd3fbbdf80 .functor BUFZ 36, L_0x55dd3fbbdda0, C4<000000000000000000000000000000000000>, C4<000000000000000000000000000000000000>, C4<000000000000000000000000000000000000>; +v0x55dd3fb36b40_0 .net *"_s0", 35 0, L_0x55dd3fbbdda0; 1 drivers +v0x55dd3fb36c40_0 .net *"_s2", 15 0, L_0x55dd3fbbde40; 1 drivers +L_0x7fc2ff32b540 .functor BUFT 1, C4<00>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb36d20_0 .net *"_s5", 1 0, L_0x7fc2ff32b540; 1 drivers +v0x55dd3fb36e10_0 .net "addr", 13 0, L_0x55dd3fbbdc30; alias, 1 drivers +v0x55dd3fb36ef0_0 .var "addr_reg", 13 0; +v0x55dd3fb37020_0 .net "clk", 0 0, o0x7fc2ff387038; alias, 0 drivers +v0x55dd3fb370e0_0 .net "data", 35 0, o0x7fc2ff387068; alias, 0 drivers +v0x55dd3fb371c0_0 .net "q", 35 0, L_0x55dd3fbbdf80; alias, 1 drivers +v0x55dd3fb372a0 .array "ram", 0 16383, 35 0; +v0x55dd3fb37360_0 .net "we", 0 0, v0x55dd3fb38060_0; 1 drivers +E_0x55dd3fb36ac0 .event posedge, v0x55dd3fb37020_0; +L_0x55dd3fbbdda0 .array/port v0x55dd3fb372a0, L_0x55dd3fbbde40; +L_0x55dd3fbbde40 .concat [ 14 2 0 0], v0x55dd3fb36ef0_0, L_0x7fc2ff32b540; +S_0x55dd3faa5c90 .scope module, "panel_6" "panel_6" 15 44; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 5 "s_address" + .port_info 3 /INPUT 1 "s_write" + .port_info 4 /INPUT 1 "s_read" + .port_info 5 /INPUT 32 "s_writedata" + .port_info 6 /OUTPUT 32 "s_readdata" + .port_info 7 /OUTPUT 1 "s_waitrequest" + .port_info 8 /INPUT 1 "ext_sw_power" + .port_info 9 /OUTPUT 1 "ext_power" + .port_info 10 /OUTPUT 1 "ext_run" + .port_info 11 /OUTPUT 1 "ext_memstop" + .port_info 12 /OUTPUT 1 "key_start" + .port_info 13 /OUTPUT 1 "key_read_in" + .port_info 14 /OUTPUT 1 "key_mem_cont" + .port_info 15 /OUTPUT 1 "key_inst_cont" + .port_info 16 /OUTPUT 1 "key_mem_stop" + .port_info 17 /OUTPUT 1 "key_inst_stop" + .port_info 18 /OUTPUT 1 "key_exec" + .port_info 19 /OUTPUT 1 "key_io_reset" + .port_info 20 /OUTPUT 1 "key_dep" + .port_info 21 /OUTPUT 1 "key_dep_nxt" + .port_info 22 /OUTPUT 1 "key_ex" + .port_info 23 /OUTPUT 1 "key_ex_nxt" + .port_info 24 /OUTPUT 1 "sw_addr_stop" + .port_info 25 /OUTPUT 1 "sw_mem_disable" + .port_info 26 /OUTPUT 1 "sw_repeat" + .port_info 27 /OUTPUT 1 "sw_power" + .port_info 28 /OUTPUT 36 "datasw" + .port_info 29 /OUTPUT 18 "mas" + .port_info 30 /OUTPUT 1 "sw_rim_maint" + .port_info 31 /OUTPUT 1 "sw_repeat_bypass" + .port_info 32 /OUTPUT 1 "sw_art3_maint" + .port_info 33 /OUTPUT 1 "sw_sct_maint" + .port_info 34 /OUTPUT 1 "sw_split_cyc" + .port_info 35 /INPUT 1 "power" + .port_info 36 /INPUT 18 "ir" + .port_info 37 /INPUT 36 "mi" + .port_info 38 /INPUT 36 "ar" + .port_info 39 /INPUT 36 "mb" + .port_info 40 /INPUT 36 "mq" + .port_info 41 /INPUT 18 "pc" + .port_info 42 /INPUT 18 "ma" + .port_info 43 /INPUT 1 "run" + .port_info 44 /INPUT 1 "mc_stop" + .port_info 45 /INPUT 1 "pi_active" + .port_info 46 /INPUT 7 "pih" + .port_info 47 /INPUT 7 "pir" + .port_info 48 /INPUT 7 "pio" + .port_info 49 /INPUT 8 "pr" + .port_info 50 /INPUT 8 "rlr" + .port_info 51 /INPUT 8 "rla" + .port_info 52 /INPUT 8 "ff0" + .port_info 53 /INPUT 8 "ff1" + .port_info 54 /INPUT 8 "ff2" + .port_info 55 /INPUT 8 "ff3" + .port_info 56 /INPUT 8 "ff4" + .port_info 57 /INPUT 8 "ff5" + .port_info 58 /INPUT 8 "ff6" + .port_info 59 /INPUT 8 "ff7" + .port_info 60 /INPUT 8 "ff8" + .port_info 61 /INPUT 8 "ff9" + .port_info 62 /INPUT 8 "ff10" + .port_info 63 /INPUT 8 "ff11" + .port_info 64 /INPUT 8 "ff12" + .port_info 65 /INPUT 8 "ff13" +o0x7fc2ff387db8 .functor BUFZ 1, C4; HiZ drive +L_0x55dd3fbbe090 .functor BUFZ 1, o0x7fc2ff387db8, C4<0>, C4<0>, C4<0>; +o0x7fc2ff387ea8 .functor BUFZ 1, C4; HiZ drive +L_0x55dd3fbbe100 .functor BUFZ 1, o0x7fc2ff387ea8, C4<0>, C4<0>, C4<0>; +o0x7fc2ff387c38 .functor BUFZ 1, C4; HiZ drive +L_0x55dd3fbbe170 .functor BUFZ 1, o0x7fc2ff387c38, C4<0>, C4<0>, C4<0>; +o0x7fc2ff387548 .functor BUFZ 36, C4; HiZ drive +v0x55dd3fb38490_0 .net "ar", 0 35, o0x7fc2ff387548; 0 drivers +o0x7fc2ff387578 .functor BUFZ 1, C4; HiZ drive +v0x55dd3fb38590_0 .net "clk", 0 0, o0x7fc2ff387578; 0 drivers +v0x55dd3fb38650_0 .var "datasw", 0 35; +v0x55dd3fb38740_0 .net "ext_memstop", 0 0, L_0x55dd3fbbe170; 1 drivers +v0x55dd3fb38800_0 .net "ext_power", 0 0, L_0x55dd3fbbe090; 1 drivers +v0x55dd3fb388c0_0 .net "ext_run", 0 0, L_0x55dd3fbbe100; 1 drivers +o0x7fc2ff387668 .functor BUFZ 1, C4; HiZ drive +v0x55dd3fb38980_0 .net "ext_sw_power", 0 0, o0x7fc2ff387668; 0 drivers +o0x7fc2ff387698 .functor BUFZ 8, C4; HiZ drive +v0x55dd3fb38a40_0 .net "ff0", 0 7, o0x7fc2ff387698; 0 drivers +o0x7fc2ff3876c8 .functor BUFZ 8, C4; HiZ drive +v0x55dd3fb38b20_0 .net "ff1", 0 7, o0x7fc2ff3876c8; 0 drivers +o0x7fc2ff3876f8 .functor BUFZ 8, C4; HiZ drive +v0x55dd3fb38c90_0 .net "ff10", 0 7, o0x7fc2ff3876f8; 0 drivers +o0x7fc2ff387728 .functor BUFZ 8, C4; HiZ drive +v0x55dd3fb38d70_0 .net "ff11", 0 7, o0x7fc2ff387728; 0 drivers +o0x7fc2ff387758 .functor BUFZ 8, C4; HiZ drive +v0x55dd3fb38e50_0 .net "ff12", 0 7, o0x7fc2ff387758; 0 drivers +o0x7fc2ff387788 .functor BUFZ 8, C4; HiZ drive +v0x55dd3fb38f30_0 .net "ff13", 0 7, o0x7fc2ff387788; 0 drivers +o0x7fc2ff3877b8 .functor BUFZ 8, C4; HiZ drive +v0x55dd3fb39010_0 .net "ff2", 0 7, o0x7fc2ff3877b8; 0 drivers +o0x7fc2ff3877e8 .functor BUFZ 8, C4; HiZ drive +v0x55dd3fb390f0_0 .net "ff3", 0 7, o0x7fc2ff3877e8; 0 drivers +o0x7fc2ff387818 .functor BUFZ 8, C4; HiZ drive +v0x55dd3fb391d0_0 .net "ff4", 0 7, o0x7fc2ff387818; 0 drivers +o0x7fc2ff387848 .functor BUFZ 8, C4; HiZ drive +v0x55dd3fb392b0_0 .net "ff5", 0 7, o0x7fc2ff387848; 0 drivers +o0x7fc2ff387878 .functor BUFZ 8, C4; HiZ drive +v0x55dd3fb394a0_0 .net "ff6", 0 7, o0x7fc2ff387878; 0 drivers +o0x7fc2ff3878a8 .functor BUFZ 8, C4; HiZ drive +v0x55dd3fb39580_0 .net "ff7", 0 7, o0x7fc2ff3878a8; 0 drivers +o0x7fc2ff3878d8 .functor BUFZ 8, C4; HiZ drive +v0x55dd3fb39660_0 .net "ff8", 0 7, o0x7fc2ff3878d8; 0 drivers +o0x7fc2ff387908 .functor BUFZ 8, C4; HiZ drive +v0x55dd3fb39740_0 .net "ff9", 0 7, o0x7fc2ff387908; 0 drivers +o0x7fc2ff387938 .functor BUFZ 18, C4; HiZ drive +v0x55dd3fb39820_0 .net "ir", 0 17, o0x7fc2ff387938; 0 drivers +v0x55dd3fb39900_0 .var "key_dep", 0 0; +v0x55dd3fb399c0_0 .var "key_dep_nxt", 0 0; +v0x55dd3fb39a80_0 .var "key_ex", 0 0; +v0x55dd3fb39b40_0 .var "key_ex_nxt", 0 0; +v0x55dd3fb39c00_0 .var "key_exec", 0 0; +v0x55dd3fb39cc0_0 .var "key_inst_cont", 0 0; +v0x55dd3fb39d80_0 .var "key_inst_stop", 0 0; +v0x55dd3fb39e40_0 .var "key_io_reset", 0 0; +v0x55dd3fb39f00_0 .var "key_mem_cont", 0 0; +v0x55dd3fb39fc0_0 .var "key_mem_stop", 0 0; +v0x55dd3fb3a080_0 .var "key_read_in", 0 0; +v0x55dd3fb3a140_0 .var "key_start", 0 0; +o0x7fc2ff387ba8 .functor BUFZ 18, C4; HiZ drive +v0x55dd3fb3a200_0 .net "ma", 18 35, o0x7fc2ff387ba8; 0 drivers +v0x55dd3fb3a2e0_0 .var "mas", 18 35; +o0x7fc2ff387c08 .functor BUFZ 36, C4; HiZ drive +v0x55dd3fb3a3c0_0 .net "mb", 0 35, o0x7fc2ff387c08; 0 drivers +v0x55dd3fb3a4a0_0 .net "mc_stop", 0 0, o0x7fc2ff387c38; 0 drivers +o0x7fc2ff387c68 .functor BUFZ 36, C4; HiZ drive +v0x55dd3fb3a560_0 .net "mi", 0 35, o0x7fc2ff387c68; 0 drivers +o0x7fc2ff387c98 .functor BUFZ 36, C4; HiZ drive +v0x55dd3fb3a640_0 .net "mq", 0 35, o0x7fc2ff387c98; 0 drivers +o0x7fc2ff387cc8 .functor BUFZ 18, C4; HiZ drive +v0x55dd3fb3a720_0 .net "pc", 18 35, o0x7fc2ff387cc8; 0 drivers +o0x7fc2ff387cf8 .functor BUFZ 1, C4; HiZ drive +v0x55dd3fb3a800_0 .net "pi_active", 0 0, o0x7fc2ff387cf8; 0 drivers +o0x7fc2ff387d28 .functor BUFZ 7, C4; HiZ drive +v0x55dd3fb3a8c0_0 .net "pih", 1 7, o0x7fc2ff387d28; 0 drivers +o0x7fc2ff387d58 .functor BUFZ 7, C4; HiZ drive +v0x55dd3fb3a9a0_0 .net "pio", 1 7, o0x7fc2ff387d58; 0 drivers +o0x7fc2ff387d88 .functor BUFZ 7, C4; HiZ drive +v0x55dd3fb3aa80_0 .net "pir", 1 7, o0x7fc2ff387d88; 0 drivers +v0x55dd3fb3ab60_0 .net "power", 0 0, o0x7fc2ff387db8; 0 drivers +o0x7fc2ff387de8 .functor BUFZ 8, C4; HiZ drive +v0x55dd3fb3ac20_0 .net "pr", 18 25, o0x7fc2ff387de8; 0 drivers +o0x7fc2ff387e18 .functor BUFZ 1, C4; HiZ drive +v0x55dd3fb3ad00_0 .net "reset", 0 0, o0x7fc2ff387e18; 0 drivers +o0x7fc2ff387e48 .functor BUFZ 8, C4; HiZ drive +v0x55dd3fb3adc0_0 .net "rla", 18 25, o0x7fc2ff387e48; 0 drivers +o0x7fc2ff387e78 .functor BUFZ 8, C4; HiZ drive +v0x55dd3fb3aea0_0 .net "rlr", 18 25, o0x7fc2ff387e78; 0 drivers +v0x55dd3fb3af80_0 .net "run", 0 0, o0x7fc2ff387ea8; 0 drivers +o0x7fc2ff387ed8 .functor BUFZ 5, C4; HiZ drive +v0x55dd3fb3b040_0 .net "s_address", 4 0, o0x7fc2ff387ed8; 0 drivers +o0x7fc2ff387f08 .functor BUFZ 1, C4; HiZ drive +v0x55dd3fb3b120_0 .net "s_read", 0 0, o0x7fc2ff387f08; 0 drivers +v0x55dd3fb3b1e0_0 .var "s_readdata", 31 0; +L_0x7fc2ff32b588 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb3b2c0_0 .net "s_waitrequest", 0 0, L_0x7fc2ff32b588; 1 drivers +o0x7fc2ff387f98 .functor BUFZ 1, C4; HiZ drive +v0x55dd3fb3b380_0 .net "s_write", 0 0, o0x7fc2ff387f98; 0 drivers +o0x7fc2ff387fc8 .functor BUFZ 32, C4; HiZ drive +v0x55dd3fb3b440_0 .net "s_writedata", 31 0, o0x7fc2ff387fc8; 0 drivers +v0x55dd3fb3b520_0 .var "sw_addr_stop", 0 0; +v0x55dd3fb3b5e0_0 .var "sw_art3_maint", 0 0; +v0x55dd3fb3b6a0_0 .var "sw_mem_disable", 0 0; +v0x55dd3fb3b760_0 .var "sw_power", 0 0; +v0x55dd3fb3b820_0 .var "sw_repeat", 0 0; +v0x55dd3fb3b8e0_0 .var "sw_repeat_bypass", 0 0; +v0x55dd3fb3b9a0_0 .var "sw_rim_maint", 0 0; +v0x55dd3fb3ba60_0 .var "sw_sct_maint", 0 0; +v0x55dd3fb3bb20_0 .var "sw_split_cyc", 0 0; +E_0x55dd3fb38210/0 .event negedge, v0x55dd3fb3ad00_0; +E_0x55dd3fb38210/1 .event posedge, v0x55dd3fb38590_0; +E_0x55dd3fb38210 .event/or E_0x55dd3fb38210/0, E_0x55dd3fb38210/1; +E_0x55dd3fb38290/0 .event edge, v0x55dd3fb3b040_0, v0x55dd3fb3ab60_0, v0x55dd3fb3a4a0_0, v0x55dd3fb3af80_0; +E_0x55dd3fb38290/1 .event edge, v0x55dd3fb3b520_0, v0x55dd3fb39c00_0, v0x55dd3fb39e40_0, v0x55dd3fb39fc0_0; +E_0x55dd3fb38290/2 .event edge, v0x55dd3fb39d80_0, v0x55dd3fb39f00_0, v0x55dd3fb39cc0_0, v0x55dd3fb3a080_0; +E_0x55dd3fb38290/3 .event edge, v0x55dd3fb3a140_0, v0x55dd3fb3b6a0_0, v0x55dd3fb3b820_0, v0x55dd3fb39b40_0; +E_0x55dd3fb38290/4 .event edge, v0x55dd3fb39a80_0, v0x55dd3fb399c0_0, v0x55dd3fb39900_0, v0x55dd3fb3bb20_0; +E_0x55dd3fb38290/5 .event edge, v0x55dd3fb3ba60_0, v0x55dd3fb3b5e0_0, v0x55dd3fb3b8e0_0, v0x55dd3fb3b9a0_0; +E_0x55dd3fb38290/6 .event edge, v0x55dd3fb38650_0, v0x55dd3fb3a2e0_0, v0x55dd3fb39820_0, v0x55dd3fb3a560_0; +E_0x55dd3fb38290/7 .event edge, v0x55dd3fb3a720_0, v0x55dd3fb3a200_0, v0x55dd3fb3a8c0_0, v0x55dd3fb3aa80_0; +E_0x55dd3fb38290/8 .event edge, v0x55dd3fb3a9a0_0, v0x55dd3fb3a800_0, v0x55dd3fb3a3c0_0, v0x55dd3fb38490_0; +E_0x55dd3fb38290/9 .event edge, v0x55dd3fb3a640_0, v0x55dd3fb38a40_0, v0x55dd3fb38b20_0, v0x55dd3fb39010_0; +E_0x55dd3fb38290/10 .event edge, v0x55dd3fb390f0_0, v0x55dd3fb391d0_0, v0x55dd3fb392b0_0, v0x55dd3fb394a0_0; +E_0x55dd3fb38290/11 .event edge, v0x55dd3fb39580_0, v0x55dd3fb39660_0, v0x55dd3fb39740_0, v0x55dd3fb38c90_0; +E_0x55dd3fb38290/12 .event edge, v0x55dd3fb38d70_0, v0x55dd3fb38e50_0, v0x55dd3fb38f30_0, v0x55dd3fb3adc0_0; +E_0x55dd3fb38290/13 .event edge, v0x55dd3fb3aea0_0, v0x55dd3fb3ac20_0; +E_0x55dd3fb38290 .event/or E_0x55dd3fb38290/0, E_0x55dd3fb38290/1, E_0x55dd3fb38290/2, E_0x55dd3fb38290/3, E_0x55dd3fb38290/4, E_0x55dd3fb38290/5, E_0x55dd3fb38290/6, E_0x55dd3fb38290/7, E_0x55dd3fb38290/8, E_0x55dd3fb38290/9, E_0x55dd3fb38290/10, E_0x55dd3fb38290/11, E_0x55dd3fb38290/12, E_0x55dd3fb38290/13; +S_0x55dd3fa340e0 .scope module, "tb_membusif" "tb_membusif" 16 4; + .timescale -9 -9; +L_0x55dd3fbbe270 .functor OR 36, L_0x55dd3fbc76b0, L_0x55dd3fbd6d20, C4<000000000000000000000000000000000000>, C4<000000000000000000000000000000000000>; +L_0x55dd3fbbe3d0 .functor OR 1, L_0x55dd3fbc5780, L_0x55dd3fbd6b00, C4<0>, C4<0>; +L_0x55dd3fbbe4e0 .functor OR 1, L_0x55dd3fbc69b0, L_0x55dd3fbd6c10, C4<0>, C4<0>; +L_0x55dd3fbd4670 .functor NOT 1, v0x55dd3fb3ca00_0, C4<0>, C4<0>, C4<0>; +L_0x55dd3fbdf7e0 .functor NOT 1, v0x55dd3fb3ca00_0, C4<0>, C4<0>, C4<0>; +v0x55dd3fb75570_0 .var "a_address", 1 0; +v0x55dd3fb7a600_0 .var "a_read", 0 0; +v0x55dd3fb7a6f0_0 .net "a_readdata", 31 0, v0x55dd3fb79c40_0; 1 drivers +v0x55dd3fb7a790_0 .net "a_waitrequest", 0 0, L_0x55dd3fbbef70; 1 drivers +v0x55dd3fb7a830_0 .var "a_write", 0 0; +v0x55dd3fb7a970_0 .var "a_writedata", 31 0; +v0x55dd3fb7aa10_0 .net "b_addr_ack", 0 0, L_0x55dd3fbbe3d0; 1 drivers +v0x55dd3fb7aab0_0 .net "b_addr_ack_0", 0 0, L_0x55dd3fbc5780; 1 drivers +v0x55dd3fb7aba0_0 .net "b_addr_ack_1", 0 0, L_0x55dd3fbd6b00; 1 drivers +v0x55dd3fb7acd0_0 .net "b_fmc_select", 0 0, v0x55dd3fb78e70_0; 1 drivers +v0x55dd3fb7ad70_0 .net "b_ma", 21 35, L_0x55dd3fbbe640; 1 drivers +v0x55dd3fb7ae10_0 .net "b_mb_read", 0 35, L_0x55dd3fbbe270; 1 drivers +v0x55dd3fb7aeb0_0 .net "b_mb_read_0", 0 35, L_0x55dd3fbc76b0; 1 drivers +v0x55dd3fb7af80_0 .net "b_mb_read_1", 0 35, L_0x55dd3fbd6d20; 1 drivers +v0x55dd3fb7b050_0 .net "b_mb_write", 0 35, L_0x55dd3fbc0250; 1 drivers +v0x55dd3fb7b0f0_0 .net "b_rd_rq", 0 0, v0x55dd3fb79210_0; 1 drivers +v0x55dd3fb7b190_0 .net "b_rd_rs", 0 0, L_0x55dd3fbbe4e0; 1 drivers +v0x55dd3fb7b260_0 .net "b_rd_rs_0", 0 0, L_0x55dd3fbc69b0; 1 drivers +v0x55dd3fb7b330_0 .net "b_rd_rs_1", 0 0, L_0x55dd3fbd6c10; 1 drivers +v0x55dd3fb7b400_0 .net "b_rq_cyc", 0 0, v0x55dd3fb793c0_0; 1 drivers +v0x55dd3fb7b4a0_0 .net "b_sel", 18 21, L_0x55dd3fbbe770; 1 drivers +v0x55dd3fb7b540_0 .net "b_wr_rq", 0 0, v0x55dd3fb796d0_0; 1 drivers +v0x55dd3fb7b5e0_0 .net "b_wr_rs", 0 0, L_0x55dd3fbbf2a0; 1 drivers +v0x55dd3fb7b680_0 .net "clk", 0 0, v0x55dd3fb3c920_0; 1 drivers +v0x55dd3fb7b720_0 .net "cm_address", 17 0, L_0x55dd3fbd4100; 1 drivers +v0x55dd3fb7b7c0_0 .net "cm_read", 0 0, v0x55dd3fb5a5f0_0; 1 drivers +v0x55dd3fb7b860_0 .net "cm_readdata", 35 0, L_0x55dd3fbb1b20; 1 drivers +v0x55dd3fb7b900_0 .net "cm_waitrequest", 0 0, v0x55dd3fb5f880_0; 1 drivers +v0x55dd3fb7b9f0_0 .net "cm_write", 0 0, v0x55dd3fb5a7d0_0; 1 drivers +v0x55dd3fb7bae0_0 .net "cm_writedata", 35 0, L_0x55dd3fbd4240; 1 drivers +v0x55dd3fb7bb80_0 .var "data", 0 35; +v0x55dd3fb7bc20_0 .var "fm_address", 17 0; +v0x55dd3fb7bce0_0 .var "fm_read", 0 0; +v0x55dd3fb7bf90_0 .net "fm_readdata", 35 0, L_0x55dd3fbdf490; 1 drivers +L_0x7fc2ff32d700 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb7c030_0 .net "fm_waitrequest", 0 0, L_0x7fc2ff32d700; 1 drivers +v0x55dd3fb7c0d0_0 .var "fm_write", 0 0; +v0x55dd3fb7c1a0_0 .var "fm_writedata", 35 0; +v0x55dd3fb7c270_0 .net "reset", 0 0, v0x55dd3fb3ca00_0; 1 drivers +E_0x55dd3fb3c640 .event negedge, v0x55dd3fb75de0_0; +E_0x55dd3fb3c6c0 .event negedge, v0x55dd3fb76550_0; +S_0x55dd3fb3c720 .scope module, "clock" "clock" 16 7, 8 1 0, S_0x55dd3fa340e0; + .timescale -9 -9; + .port_info 0 /OUTPUT 1 "clk" + .port_info 1 /OUTPUT 1 "reset" +v0x55dd3fb3c920_0 .var "clk", 0 0; +v0x55dd3fb3ca00_0 .var "reset", 0 0; +S_0x55dd3fb3cb20 .scope module, "cmem" "core32k" 16 69, 17 1 0, S_0x55dd3fa340e0; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "power" + .port_info 3 /INPUT 1 "sw_single_step" + .port_info 4 /INPUT 1 "sw_restart" + .port_info 5 /INPUT 1 "membus_wr_rs_p0" + .port_info 6 /INPUT 1 "membus_rq_cyc_p0" + .port_info 7 /INPUT 1 "membus_rd_rq_p0" + .port_info 8 /INPUT 1 "membus_wr_rq_p0" + .port_info 9 /INPUT 15 "membus_ma_p0" + .port_info 10 /INPUT 4 "membus_sel_p0" + .port_info 11 /INPUT 1 "membus_fmc_select_p0" + .port_info 12 /INPUT 36 "membus_mb_in_p0" + .port_info 13 /OUTPUT 1 "membus_addr_ack_p0" + .port_info 14 /OUTPUT 1 "membus_rd_rs_p0" + .port_info 15 /OUTPUT 36 "membus_mb_out_p0" + .port_info 16 /INPUT 1 "membus_wr_rs_p1" + .port_info 17 /INPUT 1 "membus_rq_cyc_p1" + .port_info 18 /INPUT 1 "membus_rd_rq_p1" + .port_info 19 /INPUT 1 "membus_wr_rq_p1" + .port_info 20 /INPUT 15 "membus_ma_p1" + .port_info 21 /INPUT 4 "membus_sel_p1" + .port_info 22 /INPUT 1 "membus_fmc_select_p1" + .port_info 23 /INPUT 36 "membus_mb_in_p1" + .port_info 24 /OUTPUT 1 "membus_addr_ack_p1" + .port_info 25 /OUTPUT 1 "membus_rd_rs_p1" + .port_info 26 /OUTPUT 36 "membus_mb_out_p1" + .port_info 27 /INPUT 1 "membus_wr_rs_p2" + .port_info 28 /INPUT 1 "membus_rq_cyc_p2" + .port_info 29 /INPUT 1 "membus_rd_rq_p2" + .port_info 30 /INPUT 1 "membus_wr_rq_p2" + .port_info 31 /INPUT 15 "membus_ma_p2" + .port_info 32 /INPUT 4 "membus_sel_p2" + .port_info 33 /INPUT 1 "membus_fmc_select_p2" + .port_info 34 /INPUT 36 "membus_mb_in_p2" + .port_info 35 /OUTPUT 1 "membus_addr_ack_p2" + .port_info 36 /OUTPUT 1 "membus_rd_rs_p2" + .port_info 37 /OUTPUT 36 "membus_mb_out_p2" + .port_info 38 /INPUT 1 "membus_wr_rs_p3" + .port_info 39 /INPUT 1 "membus_rq_cyc_p3" + .port_info 40 /INPUT 1 "membus_rd_rq_p3" + .port_info 41 /INPUT 1 "membus_wr_rq_p3" + .port_info 42 /INPUT 15 "membus_ma_p3" + .port_info 43 /INPUT 4 "membus_sel_p3" + .port_info 44 /INPUT 1 "membus_fmc_select_p3" + .port_info 45 /INPUT 36 "membus_mb_in_p3" + .port_info 46 /OUTPUT 1 "membus_addr_ack_p3" + .port_info 47 /OUTPUT 1 "membus_rd_rs_p3" + .port_info 48 /OUTPUT 36 "membus_mb_out_p3" + .port_info 49 /OUTPUT 18 "m_address" + .port_info 50 /OUTPUT 1 "m_write" + .port_info 51 /OUTPUT 1 "m_read" + .port_info 52 /OUTPUT 36 "m_writedata" + .port_info 53 /INPUT 36 "m_readdata" + .port_info 54 /INPUT 1 "m_waitrequest" +P_0x55dd3fb39350 .param/l "memsel_p0" 0 17 65, C4<0000>; +P_0x55dd3fb39390 .param/l "memsel_p1" 0 17 66, C4<0000>; +P_0x55dd3fb393d0 .param/l "memsel_p2" 0 17 67, C4<0000>; +P_0x55dd3fb39410 .param/l "memsel_p3" 0 17 68, C4<0000>; +L_0x55dd3fbc0560 .functor NOT 1, v0x55dd3fb78e70_0, C4<0>, C4<0>, C4<0>; +L_0x55dd3fbc0660 .functor AND 1, L_0x55dd3fbc0420, L_0x55dd3fbc0560, C4<1>, C4<1>; +L_0x55dd3fbc0720 .functor AND 1, L_0x55dd3fbc0660, v0x55dd3fb793c0_0, C4<1>, C4<1>; +L_0x55dd3fbc0870 .functor AND 1, L_0x55dd3fbc0720, v0x55dd3fb57520_0, C4<1>, C4<1>; +L_0x7fc2ff32c4b8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x55dd3fbc0b50 .functor NOT 1, L_0x7fc2ff32c4b8, C4<0>, C4<0>, C4<0>; +L_0x55dd3fbc0bc0 .functor AND 1, L_0x55dd3fbc09b0, L_0x55dd3fbc0b50, C4<1>, C4<1>; +L_0x7fc2ff32c350 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x55dd3fbc0d00 .functor AND 1, L_0x55dd3fbc0bc0, L_0x7fc2ff32c350, C4<1>, C4<1>; +L_0x55dd3fbc0dc0 .functor AND 1, L_0x55dd3fbc0d00, v0x55dd3fb57520_0, C4<1>, C4<1>; +L_0x7fc2ff32c6f8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x55dd3fbc1130 .functor NOT 1, L_0x7fc2ff32c6f8, C4<0>, C4<0>, C4<0>; +L_0x55dd3fbc11a0 .functor AND 1, L_0x55dd3fbc0fc0, L_0x55dd3fbc1130, C4<1>, C4<1>; +L_0x7fc2ff32c590 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x55dd3fbc1310 .functor AND 1, L_0x55dd3fbc11a0, L_0x7fc2ff32c590, C4<1>, C4<1>; +L_0x55dd3fbc1380 .functor AND 1, L_0x55dd3fbc1310, v0x55dd3fb57520_0, C4<1>, C4<1>; +L_0x7fc2ff32c938 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x55dd3fbc1770 .functor NOT 1, L_0x7fc2ff32c938, C4<0>, C4<0>, C4<0>; +L_0x55dd3fbc17e0 .functor AND 1, L_0x55dd3fbc15b0, L_0x55dd3fbc1770, C4<1>, C4<1>; +L_0x7fc2ff32c7d0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x55dd3fbc1440 .functor AND 1, L_0x55dd3fbc17e0, L_0x7fc2ff32c7d0, C4<1>, C4<1>; +L_0x55dd3fbc19f0 .functor AND 1, L_0x55dd3fbc1440, v0x55dd3fb57520_0, C4<1>, C4<1>; +L_0x55dd3fbc1dc0 .functor AND 15, L_0x55dd3fbc1bd0, L_0x55dd3fbbe640, C4<111111111111111>, C4<111111111111111>; +L_0x7fc2ff32c428 .functor BUFT 1, C4<000000000000000>, C4<0>, C4<0>, C4<0>; +L_0x55dd3fbc1fe0 .functor AND 15, L_0x55dd3fbc1e30, L_0x7fc2ff32c428, C4<111111111111111>, C4<111111111111111>; +L_0x55dd3fbc20f0 .functor OR 15, L_0x55dd3fbc1dc0, L_0x55dd3fbc1fe0, C4<000000000000000>, C4<000000000000000>; +L_0x7fc2ff32c668 .functor BUFT 1, C4<000000000000000>, C4<0>, C4<0>, C4<0>; +L_0x55dd3fbc22d0 .functor AND 15, L_0x55dd3fbc21e0, L_0x7fc2ff32c668, C4<111111111111111>, C4<111111111111111>; +L_0x55dd3fbc23f0 .functor OR 15, L_0x55dd3fbc20f0, L_0x55dd3fbc22d0, C4<000000000000000>, C4<000000000000000>; +L_0x7fc2ff32c8a8 .functor BUFT 1, C4<000000000000000>, C4<0>, C4<0>, C4<0>; +L_0x55dd3fbc2680 .functor AND 15, L_0x55dd3fbc2050, L_0x7fc2ff32c8a8, C4<111111111111111>, C4<111111111111111>; +L_0x55dd3fbc2340 .functor OR 15, L_0x55dd3fbc23f0, L_0x55dd3fbc2680, C4<000000000000000>, C4<000000000000000>; +L_0x55dd3fbc2850 .functor AND 1, L_0x55dd3fbcad60, v0x55dd3fb79210_0, C4<1>, C4<1>; +L_0x7fc2ff32c398 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x55dd3fbc2990 .functor AND 1, L_0x55dd3fbcb000, L_0x7fc2ff32c398, C4<1>, C4<1>; +L_0x55dd3fbc2a30 .functor OR 1, L_0x55dd3fbc2850, L_0x55dd3fbc2990, C4<0>, C4<0>; +L_0x7fc2ff32c5d8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x55dd3fbc28c0 .functor AND 1, L_0x55dd3fbcb070, L_0x7fc2ff32c5d8, C4<1>, C4<1>; +L_0x55dd3fbc2c00 .functor OR 1, L_0x55dd3fbc2a30, L_0x55dd3fbc28c0, C4<0>, C4<0>; +L_0x7fc2ff32c818 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x55dd3fbc2e00 .functor AND 1, L_0x55dd3fbcb320, L_0x7fc2ff32c818, C4<1>, C4<1>; +L_0x55dd3fbc2e70 .functor OR 1, L_0x55dd3fbc2c00, L_0x55dd3fbc2e00, C4<0>, C4<0>; +L_0x55dd3fbc3080 .functor AND 1, L_0x55dd3fbcad60, v0x55dd3fb796d0_0, C4<1>, C4<1>; +L_0x7fc2ff32c3e0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x55dd3fbc30f0 .functor AND 1, L_0x55dd3fbcb000, L_0x7fc2ff32c3e0, C4<1>, C4<1>; +L_0x55dd3fbc32a0 .functor OR 1, L_0x55dd3fbc3080, L_0x55dd3fbc30f0, C4<0>, C4<0>; +L_0x7fc2ff32c620 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x55dd3fbc33e0 .functor AND 1, L_0x55dd3fbcb070, L_0x7fc2ff32c620, C4<1>, C4<1>; +L_0x55dd3fbc3570 .functor OR 1, L_0x55dd3fbc32a0, L_0x55dd3fbc33e0, C4<0>, C4<0>; +L_0x7fc2ff32c860 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x55dd3fbc36b0 .functor AND 1, L_0x55dd3fbcb320, L_0x7fc2ff32c860, C4<1>, C4<1>; +L_0x55dd3fbc3450 .functor OR 1, L_0x55dd3fbc3570, L_0x55dd3fbc36b0, C4<0>, C4<0>; +L_0x55dd3fbc3940 .functor AND 36, L_0x55dd3fbc38a0, L_0x55dd3fbc0250, C4<111111111111111111111111111111111111>, C4<111111111111111111111111111111111111>; +L_0x7fc2ff32c500 .functor BUFT 1, C4<000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +L_0x55dd3fbc2610 .functor AND 36, L_0x55dd3fbc3b40, L_0x7fc2ff32c500, C4<111111111111111111111111111111111111>, C4<111111111111111111111111111111111111>; +L_0x55dd3fbc4070 .functor OR 36, L_0x55dd3fbc3940, L_0x55dd3fbc2610, C4<000000000000000000000000000000000000>, C4<000000000000000000000000000000000000>; +L_0x7fc2ff32c740 .functor BUFT 1, C4<000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +L_0x55dd3fbc48b0 .functor AND 36, L_0x55dd3fbc42d0, L_0x7fc2ff32c740, C4<111111111111111111111111111111111111>, C4<111111111111111111111111111111111111>; +L_0x55dd3fbc4970 .functor OR 36, L_0x55dd3fbc4070, L_0x55dd3fbc48b0, C4<000000000000000000000000000000000000>, C4<000000000000000000000000000000000000>; +L_0x7fc2ff32c980 .functor BUFT 1, C4<000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +L_0x55dd3fbc5280 .functor AND 36, L_0x55dd3fbc4c10, L_0x7fc2ff32c980, C4<111111111111111111111111111111111111>, C4<111111111111111111111111111111111111>; +L_0x55dd3fbc5340 .functor OR 36, L_0x55dd3fbc4970, L_0x55dd3fbc5280, C4<000000000000000000000000000000000000>, C4<000000000000000000000000000000000000>; +L_0x55dd3fbc58d0 .functor AND 1, L_0x55dd3fbcf2c0, L_0x55dd3fbcad60, C4<1>, C4<1>; +L_0x55dd3fbc5d50 .functor AND 1, L_0x55dd3fbcf2c0, L_0x55dd3fbcb000, C4<1>, C4<1>; +L_0x55dd3fbc6360 .functor AND 1, L_0x55dd3fbcf2c0, L_0x55dd3fbcb070, C4<1>, C4<1>; +L_0x55dd3fbc67b0 .functor AND 1, L_0x55dd3fbcf2c0, L_0x55dd3fbcb320, C4<1>, C4<1>; +L_0x55dd3fbc69b0 .functor AND 1, L_0x55dd3fbd1220, L_0x55dd3fbcad60, C4<1>, C4<1>; +L_0x55dd3fbc6a70 .functor AND 1, L_0x55dd3fbd1220, L_0x55dd3fbcb000, C4<1>, C4<1>; +L_0x55dd3fbc6c80 .functor AND 1, L_0x55dd3fbd1220, L_0x55dd3fbcb070, C4<1>, C4<1>; +L_0x55dd3fbc6d80 .functor AND 1, L_0x55dd3fbd1220, L_0x55dd3fbcb320, C4<1>, C4<1>; +L_0x55dd3fbc6fa0 .functor AND 1, L_0x55dd3fbd0d80, L_0x55dd3fbcad60, C4<1>, C4<1>; +L_0x55dd3fbc76b0 .functor AND 36, v0x55dd3fb5d2b0_0, L_0x55dd3fbc7010, C4<111111111111111111111111111111111111>, C4<111111111111111111111111111111111111>; +L_0x55dd3fbc78e0 .functor AND 1, L_0x55dd3fbd0d80, L_0x55dd3fbcb000, C4<1>, C4<1>; +L_0x55dd3fbc8060 .functor AND 36, v0x55dd3fb5d2b0_0, L_0x55dd3fbc7950, C4<111111111111111111111111111111111111>, C4<111111111111111111111111111111111111>; +L_0x55dd3fbc82f0 .functor AND 1, L_0x55dd3fbd0d80, L_0x55dd3fbcb070, C4<1>, C4<1>; +L_0x55dd3fbc89c0 .functor AND 36, v0x55dd3fb5d2b0_0, L_0x55dd3fbc8360, C4<111111111111111111111111111111111111>, C4<111111111111111111111111111111111111>; +L_0x55dd3fbc8c10 .functor AND 1, L_0x55dd3fbd0d80, L_0x55dd3fbcb320, C4<1>, C4<1>; +L_0x55dd3fbc9360 .functor AND 36, v0x55dd3fb5d2b0_0, L_0x55dd3fbc8c80, C4<111111111111111111111111111111111111>, C4<111111111111111111111111111111111111>; +L_0x55dd3fbc95c0 .functor AND 1, L_0x55dd3fbbf2a0, L_0x55dd3fbcad60, C4<1>, C4<1>; +L_0x7fc2ff32c308 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x55dd3fbc9660 .functor AND 1, L_0x7fc2ff32c308, L_0x55dd3fbcb000, C4<1>, C4<1>; +L_0x55dd3fbc9930 .functor OR 1, L_0x55dd3fbc95c0, L_0x55dd3fbc9660, C4<0>, C4<0>; +L_0x7fc2ff32c548 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x55dd3fbc9a20 .functor AND 1, L_0x7fc2ff32c548, L_0x55dd3fbcb070, C4<1>, C4<1>; +L_0x55dd3fbc9ca0 .functor OR 1, L_0x55dd3fbc9930, L_0x55dd3fbc9a20, C4<0>, C4<0>; +L_0x7fc2ff32c788 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x55dd3fbc9de0 .functor AND 1, L_0x7fc2ff32c788, L_0x55dd3fbcb320, C4<1>, C4<1>; +L_0x55dd3fbca070 .functor OR 1, L_0x55dd3fbc9ca0, L_0x55dd3fbc9de0, C4<0>, C4<0>; +L_0x55dd3fbcad60 .functor BUFZ 1, v0x55dd3fb57a10_0, C4<0>, C4<0>, C4<0>; +L_0x55dd3fbcb000 .functor BUFZ 1, v0x55dd3fb57b90_0, C4<0>, C4<0>, C4<0>; +L_0x55dd3fbcb070 .functor BUFZ 1, v0x55dd3fb57d10_0, C4<0>, C4<0>, C4<0>; +L_0x55dd3fbcb320 .functor BUFZ 1, v0x55dd3fb57e90_0, C4<0>, C4<0>, C4<0>; +L_0x55dd3fbcb390 .functor OR 1, v0x55dd3fb57a10_0, v0x55dd3fb57b90_0, C4<0>, C4<0>; +L_0x55dd3fbcb720 .functor OR 1, L_0x55dd3fbcb390, v0x55dd3fb57d10_0, C4<0>, C4<0>; +L_0x55dd3fbcb830 .functor OR 1, L_0x55dd3fbcb720, v0x55dd3fb57e90_0, C4<0>, C4<0>; +L_0x55dd3fbcbba0 .functor NOT 1, L_0x55dd3fbcb830, C4<0>, C4<0>, C4<0>; +L_0x55dd3fbcbc60 .functor AND 1, L_0x55dd3fbd29c0, L_0x55dd3fbcbba0, C4<1>, C4<1>; +L_0x7fc2ff32b930 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x55dd3fbcbfe0 .functor NOT 1, L_0x7fc2ff32b930, C4<0>, C4<0>, C4<0>; +L_0x55dd3fbcc0a0 .functor AND 1, L_0x55dd3fbd29c0, L_0x55dd3fbcbfe0, C4<1>, C4<1>; +L_0x55dd3fbcc3e0 .functor AND 1, L_0x55dd3fbcc0a0, L_0x55dd3fbcb830, C4<1>, C4<1>; +L_0x55dd3fbcc4a0 .functor BUFZ 1, L_0x55dd3fbcf2c0, C4<0>, C4<0>, C4<0>; +L_0x55dd3fbccb30 .functor OR 1, L_0x55dd3fbc0870, L_0x55dd3fbc0dc0, C4<0>, C4<0>; +L_0x55dd3fbccc40 .functor OR 1, L_0x55dd3fbccb30, L_0x55dd3fbc1380, C4<0>, C4<0>; +L_0x55dd3fbccff0 .functor OR 1, L_0x55dd3fbccc40, L_0x55dd3fbc19f0, C4<0>, C4<0>; +L_0x55dd3fbcd4e0 .functor OR 1, L_0x55dd3fbd2540, L_0x55dd3fbcac00, C4<0>, C4<0>; +L_0x55dd3fbcdc30 .functor OR 1, L_0x55dd3fbcd380, L_0x55dd3fbd3a40, C4<0>, C4<0>; +L_0x55dd3fbce080 .functor OR 1, L_0x55dd3fbcd380, L_0x55dd3fbd3ca0, C4<0>, C4<0>; +L_0x55dd3fbce790 .functor NOT 1, v0x55dd3fb572c0_0, C4<0>, C4<0>, C4<0>; +L_0x55dd3fbce800 .functor AND 1, L_0x55dd3fbd15b0, L_0x55dd3fbce790, C4<1>, C4<1>; +L_0x55dd3fbceb90 .functor OR 1, L_0x55dd3fbcd380, L_0x55dd3fbce800, C4<0>, C4<0>; +L_0x55dd3fbcec50 .functor OR 1, L_0x55dd3fbceb90, L_0x55dd3fbd21b0, C4<0>, C4<0>; +L_0x55dd3fbcf3d0 .functor AND 1, v0x55dd3fb58890_0, v0x55dd3fb57750_0, C4<1>, C4<1>; +L_0x55dd3fbcff40 .functor AND 1, L_0x55dd3fbd3590, v0x55dd3fb57200_0, C4<1>, C4<1>; +L_0x55dd3fbd02f0 .functor AND 1, L_0x55dd3fbcff40, v0x55dd3fb572c0_0, C4<1>, C4<1>; +L_0x55dd3fbd0400 .functor OR 1, L_0x55dd3fbcf2c0, L_0x55dd3fbd02f0, C4<0>, C4<0>; +L_0x55dd3fbd0e90 .functor AND 1, L_0x55dd3fbd3360, v0x55dd3fb57200_0, C4<1>, C4<1>; +L_0x55dd3fbd16c0 .functor NOT 1, v0x55dd3fb572c0_0, C4<0>, C4<0>, C4<0>; +L_0x55dd3fbd1a40 .functor OR 1, v0x55dd3fb580d0_0, L_0x55dd3fbd16c0, C4<0>, C4<0>; +L_0x55dd3fbd1b50 .functor AND 1, v0x55dd3fb58270_0, L_0x55dd3fbd1a40, C4<1>, C4<1>; +L_0x55dd3fbd4240 .functor BUFZ 36, v0x55dd3fb57380_0, C4<000000000000000000000000000000000000>, C4<000000000000000000000000000000000000>, C4<000000000000000000000000000000000000>; +v0x55dd3fb52240_0 .net *"_s10", 0 0, L_0x55dd3fbc0660; 1 drivers +v0x55dd3fb52340_0 .net *"_s100", 0 0, L_0x55dd3fbc33e0; 1 drivers +v0x55dd3fb52420_0 .net *"_s102", 0 0, L_0x55dd3fbc3570; 1 drivers +v0x55dd3fb524e0_0 .net *"_s104", 0 0, L_0x55dd3fbc36b0; 1 drivers +v0x55dd3fb525c0_0 .net *"_s108", 35 0, L_0x55dd3fbc38a0; 1 drivers +v0x55dd3fb526f0_0 .net *"_s110", 35 0, L_0x55dd3fbc3940; 1 drivers +v0x55dd3fb527d0_0 .net *"_s112", 35 0, L_0x55dd3fbc3b40; 1 drivers +v0x55dd3fb528b0_0 .net *"_s114", 35 0, L_0x55dd3fbc2610; 1 drivers +v0x55dd3fb52990_0 .net *"_s116", 35 0, L_0x55dd3fbc4070; 1 drivers +v0x55dd3fb52a70_0 .net *"_s118", 35 0, L_0x55dd3fbc42d0; 1 drivers +v0x55dd3fb52b50_0 .net *"_s12", 0 0, L_0x55dd3fbc0720; 1 drivers +v0x55dd3fb52c30_0 .net *"_s120", 35 0, L_0x55dd3fbc48b0; 1 drivers +v0x55dd3fb52d10_0 .net *"_s122", 35 0, L_0x55dd3fbc4970; 1 drivers +v0x55dd3fb52df0_0 .net *"_s124", 35 0, L_0x55dd3fbc4c10; 1 drivers +v0x55dd3fb52ed0_0 .net *"_s126", 35 0, L_0x55dd3fbc5280; 1 drivers +v0x55dd3fb52fb0_0 .net *"_s146", 0 0, L_0x55dd3fbc6fa0; 1 drivers +v0x55dd3fb53090_0 .net *"_s148", 35 0, L_0x55dd3fbc7010; 1 drivers +v0x55dd3fb53170_0 .net *"_s152", 0 0, L_0x55dd3fbc78e0; 1 drivers +v0x55dd3fb53250_0 .net *"_s154", 35 0, L_0x55dd3fbc7950; 1 drivers +v0x55dd3fb53330_0 .net *"_s158", 0 0, L_0x55dd3fbc82f0; 1 drivers +v0x55dd3fb53410_0 .net *"_s160", 35 0, L_0x55dd3fbc8360; 1 drivers +v0x55dd3fb534f0_0 .net *"_s164", 0 0, L_0x55dd3fbc8c10; 1 drivers +v0x55dd3fb535d0_0 .net *"_s166", 35 0, L_0x55dd3fbc8c80; 1 drivers +v0x55dd3fb536b0_0 .net *"_s17", 2 0, L_0x55dd3fbc08e0; 1 drivers +v0x55dd3fb53790_0 .net *"_s170", 0 0, L_0x55dd3fbc95c0; 1 drivers +v0x55dd3fb53870_0 .net *"_s172", 0 0, L_0x55dd3fbc9660; 1 drivers +v0x55dd3fb53950_0 .net *"_s174", 0 0, L_0x55dd3fbc9930; 1 drivers +v0x55dd3fb53a30_0 .net *"_s176", 0 0, L_0x55dd3fbc9a20; 1 drivers +v0x55dd3fb53b10_0 .net *"_s178", 0 0, L_0x55dd3fbc9ca0; 1 drivers +L_0x7fc2ff32b9c0 .functor BUFT 1, C4<000>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb53bf0_0 .net/2u *"_s18", 2 0, L_0x7fc2ff32b9c0; 1 drivers +v0x55dd3fb53cd0_0 .net *"_s180", 0 0, L_0x55dd3fbc9de0; 1 drivers +v0x55dd3fb53db0_0 .net *"_s192", 0 0, L_0x55dd3fbcb390; 1 drivers +v0x55dd3fb53e90_0 .net *"_s194", 0 0, L_0x55dd3fbcb720; 1 drivers +v0x55dd3fb53f70_0 .net *"_s198", 0 0, L_0x55dd3fbcbba0; 1 drivers +v0x55dd3fb54050_0 .net *"_s20", 0 0, L_0x55dd3fbc09b0; 1 drivers +v0x55dd3fb54110_0 .net *"_s202", 0 0, L_0x55dd3fbcbfe0; 1 drivers +v0x55dd3fb541f0_0 .net *"_s204", 0 0, L_0x55dd3fbcc0a0; 1 drivers +v0x55dd3fb542d0_0 .net *"_s210", 0 0, L_0x55dd3fbccb30; 1 drivers +v0x55dd3fb543b0_0 .net *"_s212", 0 0, L_0x55dd3fbccc40; 1 drivers +v0x55dd3fb54490_0 .net *"_s22", 0 0, L_0x55dd3fbc0b50; 1 drivers +v0x55dd3fb54570_0 .net *"_s222", 0 0, L_0x55dd3fbce790; 1 drivers +v0x55dd3fb54650_0 .net *"_s224", 0 0, L_0x55dd3fbce800; 1 drivers +v0x55dd3fb54730_0 .net *"_s226", 0 0, L_0x55dd3fbceb90; 1 drivers +v0x55dd3fb54810_0 .net *"_s232", 0 0, L_0x55dd3fbcff40; 1 drivers +v0x55dd3fb548f0_0 .net *"_s234", 0 0, L_0x55dd3fbd02f0; 1 drivers +v0x55dd3fb549d0_0 .net *"_s24", 0 0, L_0x55dd3fbc0bc0; 1 drivers +v0x55dd3fb54ab0_0 .net *"_s240", 0 0, L_0x55dd3fbd16c0; 1 drivers +v0x55dd3fb54b90_0 .net *"_s242", 0 0, L_0x55dd3fbd1a40; 1 drivers +L_0x7fc2ff32c1e8 .functor BUFT 1, C4<000>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb54c70_0 .net/2u *"_s248", 2 0, L_0x7fc2ff32c1e8; 1 drivers +v0x55dd3fb54d50_0 .net *"_s26", 0 0, L_0x55dd3fbc0d00; 1 drivers +v0x55dd3fb54e30_0 .net *"_s3", 2 0, L_0x55dd3fbc0380; 1 drivers +v0x55dd3fb54f10_0 .net *"_s31", 2 0, L_0x55dd3fbc0f20; 1 drivers +L_0x7fc2ff32ba08 .functor BUFT 1, C4<000>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb54ff0_0 .net/2u *"_s32", 2 0, L_0x7fc2ff32ba08; 1 drivers +v0x55dd3fb550d0_0 .net *"_s34", 0 0, L_0x55dd3fbc0fc0; 1 drivers +v0x55dd3fb55190_0 .net *"_s36", 0 0, L_0x55dd3fbc1130; 1 drivers +v0x55dd3fb55270_0 .net *"_s38", 0 0, L_0x55dd3fbc11a0; 1 drivers +L_0x7fc2ff32b978 .functor BUFT 1, C4<000>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb55350_0 .net/2u *"_s4", 2 0, L_0x7fc2ff32b978; 1 drivers +v0x55dd3fb55430_0 .net *"_s40", 0 0, L_0x55dd3fbc1310; 1 drivers +v0x55dd3fb55510_0 .net *"_s45", 2 0, L_0x55dd3fbc14b0; 1 drivers +L_0x7fc2ff32ba50 .functor BUFT 1, C4<000>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb555f0_0 .net/2u *"_s46", 2 0, L_0x7fc2ff32ba50; 1 drivers +v0x55dd3fb556d0_0 .net *"_s48", 0 0, L_0x55dd3fbc15b0; 1 drivers +v0x55dd3fb55790_0 .net *"_s50", 0 0, L_0x55dd3fbc1770; 1 drivers +v0x55dd3fb55870_0 .net *"_s52", 0 0, L_0x55dd3fbc17e0; 1 drivers +v0x55dd3fb55950_0 .net *"_s54", 0 0, L_0x55dd3fbc1440; 1 drivers +v0x55dd3fb55a30_0 .net *"_s58", 14 0, L_0x55dd3fbc1bd0; 1 drivers +v0x55dd3fb55f20_0 .net *"_s6", 0 0, L_0x55dd3fbc0420; 1 drivers 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"cmc_p0_act", 0 0; +v0x55dd3fb57ad0_0 .net "cmc_p0_sel", 0 0, L_0x55dd3fbcad60; 1 drivers +v0x55dd3fb57b90_0 .var "cmc_p1_act", 0 0; +v0x55dd3fb57c50_0 .net "cmc_p1_sel", 0 0, L_0x55dd3fbcb000; 1 drivers +v0x55dd3fb57d10_0 .var "cmc_p2_act", 0 0; +v0x55dd3fb57dd0_0 .net "cmc_p2_sel", 0 0, L_0x55dd3fbcb070; 1 drivers +v0x55dd3fb57e90_0 .var "cmc_p3_act", 0 0; +v0x55dd3fb57f50_0 .net "cmc_p3_sel", 0 0, L_0x55dd3fbcb320; 1 drivers +v0x55dd3fb58010_0 .net "cmc_pn_act", 0 0, L_0x55dd3fbcb830; 1 drivers +v0x55dd3fb580d0_0 .var "cmc_proc_rs", 0 0; +v0x55dd3fb581a0_0 .net "cmc_proc_rs_pulse", 0 0, L_0x55dd3fbd21b0; 1 drivers +v0x55dd3fb58270_0 .var "cmc_pse_sync", 0 0; +v0x55dd3fb58310_0 .net "cmc_pse_sync_set", 0 0, L_0x55dd3fbd30e0; 1 drivers +v0x55dd3fb583e0_0 .net "cmc_pwr_clr", 0 0, v0x55dd3fb40b60_0; 1 drivers +v0x55dd3fb584b0_0 .net "cmc_pwr_start", 0 0, L_0x55dd3fbcac00; 1 drivers +v0x55dd3fb58580_0 .net "cmc_rd_rs", 0 0, L_0x55dd3fbd1220; 1 drivers +v0x55dd3fb58650_0 .var "cmc_read", 0 0; +v0x55dd3fb586f0_0 .net "cmc_read_off", 0 0, L_0x55dd3fbd2e60; 1 drivers +v0x55dd3fb587c0_0 .net "cmc_restart", 0 0, L_0x55dd3fbd2540; 1 drivers +v0x55dd3fb58890_0 .var "cmc_rq_sync", 0 0; +v0x55dd3fb58930_0 .net "cmc_rq_sync_set", 0 0, L_0x55dd3fbcc3e0; 1 drivers +v0x55dd3fb589d0_0 .net "cmc_sp", 0 0, L_0x7fc2ff32b930; 1 drivers +v0x55dd3fb58a70_0 .net "cmc_start", 0 0, L_0x55dd3fbcd380; 1 drivers +v0x55dd3fb58b40_0 .net "cmc_state_clr", 0 0, L_0x55dd3fbce630; 1 drivers +v0x55dd3fb58c10_0 .var "cmc_stop", 0 0; +v0x55dd3fb58cb0_0 .net "cmc_t0", 0 0, L_0x55dd3fbcca20; 1 drivers +v0x55dd3fb58d50_0 .net "cmc_t0_D", 0 0, L_0x55dd3fbd29c0; 1 drivers +v0x55dd3fb58df0_0 .net "cmc_t1a", 0 0, L_0x55dd3fbcfa50; 1 drivers +v0x55dd3fb58e90_0 .net "cmc_t1a_D1", 0 0, L_0x55dd3fbd2c30; 1 drivers +v0x55dd3fb58f30_0 .net "cmc_t1b", 0 0, L_0x55dd3fbcf2c0; 1 drivers +v0x55dd3fb59020_0 .net "cmc_t1b_D", 0 0, L_0x55dd3fbcf6c0; 1 drivers +v0x55dd3fb59920_0 .net "cmc_t2", 0 0, L_0x55dd3fbd0a40; 1 drivers +v0x55dd3fb599c0_0 .net "cmc_t2_D1", 0 0, L_0x55dd3fbd3360; 1 drivers +v0x55dd3fb59a60_0 .net "cmc_t2_D2", 0 0, L_0x55dd3fbd3590; 1 drivers +v0x55dd3fb59b00_0 .net "cmc_t3", 0 0, L_0x55dd3fbd15b0; 1 drivers +v0x55dd3fb59ba0_0 .net "cmc_t3_D1", 0 0, L_0x55dd3fbd3a40; 1 drivers +v0x55dd3fb59c40_0 .net "cmc_t3_D2", 0 0, L_0x55dd3fbd3ca0; 1 drivers +v0x55dd3fb59d10_0 .net "cmc_t4", 0 0, L_0x55dd3fbd37c0; 1 drivers +v0x55dd3fb59de0_0 .net "cmc_t5", 0 0, L_0x55dd3fbcdad0; 1 drivers +v0x55dd3fb59eb0_0 .net "cmc_t6", 0 0, L_0x55dd3fbd2740; 1 drivers +v0x55dd3fb59f80_0 .net "cmc_t6p", 0 0, L_0x55dd3fbcdf70; 1 drivers +v0x55dd3fb5a020_0 .var "cmc_write", 0 0; +v0x55dd3fb5a0c0_0 .net "cmpc_p0_rq", 0 0, L_0x55dd3fbc0870; 1 drivers +v0x55dd3fb5a160_0 .net "cmpc_p1_rq", 0 0, L_0x55dd3fbc0dc0; 1 drivers +v0x55dd3fb5a200_0 .net "cmpc_p2_rq", 0 0, L_0x55dd3fbc1380; 1 drivers +v0x55dd3fb5a2a0_0 .net "cmpc_p3_rq", 0 0, L_0x55dd3fbc19f0; 1 drivers +v0x55dd3fb5a340_0 .net "cmpc_rs_set", 0 0, L_0x55dd3fbca070; 1 drivers +v0x55dd3fb5a3e0_0 .net "cmpc_rs_set_D", 0 0, L_0x55dd3fbd3f00; 1 drivers +v0x55dd3fb5a4b0_0 .net "core_addr", 14 0, v0x55dd3fb57120_0; 1 drivers +v0x55dd3fb5a550_0 .net "m_address", 17 0, L_0x55dd3fbd4100; alias, 1 drivers +v0x55dd3fb5a5f0_0 .var "m_read", 0 0; +v0x55dd3fb5a690_0 .net "m_readdata", 35 0, L_0x55dd3fbb1b20; alias, 1 drivers +v0x55dd3fb5a730_0 .net "m_waitrequest", 0 0, v0x55dd3fb5f880_0; alias, 1 drivers +v0x55dd3fb5a7d0_0 .var "m_write", 0 0; +v0x55dd3fb5a870_0 .net "m_writedata", 35 0, L_0x55dd3fbd4240; alias, 1 drivers +v0x55dd3fb5a950_0 .net "ma_in", 21 35, L_0x55dd3fbc2340; 1 drivers +v0x55dd3fb5aa30_0 .net "mb_in", 0 35, L_0x55dd3fbc5340; 1 drivers +v0x55dd3fb5ab10_0 .net "membus_addr_ack_p0", 0 0, L_0x55dd3fbc5780; alias, 1 drivers +v0x55dd3fb5abe0_0 .net "membus_addr_ack_p1", 0 0, L_0x55dd3fbc5bf0; 1 drivers +v0x55dd3fb5acb0_0 .net "membus_addr_ack_p2", 0 0, L_0x55dd3fbc6200; 1 drivers +v0x55dd3fb5ad80_0 .net "membus_addr_ack_p3", 0 0, L_0x55dd3fbc6650; 1 drivers +v0x55dd3fb5ae50_0 .net "membus_fmc_select_p0", 0 0, v0x55dd3fb78e70_0; alias, 1 drivers +v0x55dd3fb5aef0_0 .net "membus_fmc_select_p1", 0 0, L_0x7fc2ff32c4b8; 1 drivers +v0x55dd3fb5af90_0 .net "membus_fmc_select_p2", 0 0, L_0x7fc2ff32c6f8; 1 drivers +v0x55dd3fb5b030_0 .net "membus_fmc_select_p3", 0 0, L_0x7fc2ff32c938; 1 drivers +v0x55dd3fb5b0d0_0 .net "membus_ma_p0", 21 35, L_0x55dd3fbbe640; alias, 1 drivers +v0x55dd3fb5b1b0_0 .net "membus_ma_p1", 21 35, L_0x7fc2ff32c428; 1 drivers +v0x55dd3fb5b290_0 .net "membus_ma_p2", 21 35, L_0x7fc2ff32c668; 1 drivers +v0x55dd3fb5b370_0 .net "membus_ma_p3", 21 35, L_0x7fc2ff32c8a8; 1 drivers +v0x55dd3fb5b450_0 .net "membus_mb_in_p0", 0 35, L_0x55dd3fbc0250; alias, 1 drivers +v0x55dd3fb5b530_0 .net "membus_mb_in_p1", 0 35, L_0x7fc2ff32c500; 1 drivers +v0x55dd3fb5b610_0 .net "membus_mb_in_p2", 0 35, L_0x7fc2ff32c740; 1 drivers +v0x55dd3fb5b6f0_0 .net "membus_mb_in_p3", 0 35, L_0x7fc2ff32c980; 1 drivers +v0x55dd3fb5b7d0_0 .net "membus_mb_out_p0", 0 35, L_0x55dd3fbc76b0; alias, 1 drivers +v0x55dd3fb5b8b0_0 .net "membus_mb_out_p1", 0 35, L_0x55dd3fbc8060; 1 drivers +v0x55dd3fb5b990_0 .net "membus_mb_out_p2", 0 35, L_0x55dd3fbc89c0; 1 drivers +v0x55dd3fb5ba70_0 .net "membus_mb_out_p3", 0 35, L_0x55dd3fbc9360; 1 drivers +v0x55dd3fb5bb50_0 .net "membus_rd_rq_p0", 0 0, v0x55dd3fb79210_0; alias, 1 drivers +v0x55dd3fb5bc10_0 .net "membus_rd_rq_p1", 0 0, L_0x7fc2ff32c398; 1 drivers +v0x55dd3fb5bcd0_0 .net "membus_rd_rq_p2", 0 0, L_0x7fc2ff32c5d8; 1 drivers +v0x55dd3fb5bd90_0 .net "membus_rd_rq_p3", 0 0, L_0x7fc2ff32c818; 1 drivers +v0x55dd3fb5be50_0 .net "membus_rd_rs_p0", 0 0, L_0x55dd3fbc69b0; alias, 1 drivers +v0x55dd3fb5bf10_0 .net "membus_rd_rs_p1", 0 0, L_0x55dd3fbc6a70; 1 drivers +v0x55dd3fb5bfd0_0 .net "membus_rd_rs_p2", 0 0, L_0x55dd3fbc6c80; 1 drivers +v0x55dd3fb5c090_0 .net "membus_rd_rs_p3", 0 0, L_0x55dd3fbc6d80; 1 drivers +v0x55dd3fb5c150_0 .net "membus_rq_cyc_p0", 0 0, v0x55dd3fb793c0_0; alias, 1 drivers +v0x55dd3fb5c210_0 .net "membus_rq_cyc_p1", 0 0, L_0x7fc2ff32c350; 1 drivers +v0x55dd3fb5c2d0_0 .net "membus_rq_cyc_p2", 0 0, L_0x7fc2ff32c590; 1 drivers +v0x55dd3fb5c390_0 .net "membus_rq_cyc_p3", 0 0, L_0x7fc2ff32c7d0; 1 drivers +v0x55dd3fb5c450_0 .net "membus_sel_p0", 18 21, L_0x55dd3fbbe770; alias, 1 drivers +L_0x7fc2ff32c470 .functor BUFT 1, C4<0000>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb5c530_0 .net "membus_sel_p1", 18 21, L_0x7fc2ff32c470; 1 drivers +L_0x7fc2ff32c6b0 .functor BUFT 1, C4<0000>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb5c610_0 .net "membus_sel_p2", 18 21, L_0x7fc2ff32c6b0; 1 drivers +L_0x7fc2ff32c8f0 .functor BUFT 1, C4<0000>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb5c6f0_0 .net "membus_sel_p3", 18 21, L_0x7fc2ff32c8f0; 1 drivers +v0x55dd3fb5c7d0_0 .net "membus_wr_rq_p0", 0 0, v0x55dd3fb796d0_0; alias, 1 drivers +v0x55dd3fb5c890_0 .net "membus_wr_rq_p1", 0 0, L_0x7fc2ff32c3e0; 1 drivers +v0x55dd3fb5c950_0 .net "membus_wr_rq_p2", 0 0, L_0x7fc2ff32c620; 1 drivers +v0x55dd3fb5ca10_0 .net "membus_wr_rq_p3", 0 0, L_0x7fc2ff32c860; 1 drivers +v0x55dd3fb5cad0_0 .net "membus_wr_rs_p0", 0 0, L_0x55dd3fbbf2a0; alias, 1 drivers +v0x55dd3fb5cb90_0 .net "membus_wr_rs_p1", 0 0, L_0x7fc2ff32c308; 1 drivers +v0x55dd3fb5cc50_0 .net "membus_wr_rs_p2", 0 0, L_0x7fc2ff32c548; 1 drivers +v0x55dd3fb5cd10_0 .net "membus_wr_rs_p3", 0 0, L_0x7fc2ff32c788; 1 drivers +L_0x7fc2ff32c230 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb5cdd0_0 .net "power", 0 0, L_0x7fc2ff32c230; 1 drivers +v0x55dd3fb5cea0_0 .net "pwr_t1", 0 0, L_0x55dd3fbca3b0; 1 drivers +v0x55dd3fb5cf90_0 .net "pwr_t2", 0 0, L_0x55dd3fbca5b0; 1 drivers +v0x55dd3fb5d080_0 .net "pwr_t3", 0 0, L_0x55dd3fbca810; 1 drivers +v0x55dd3fb5d170_0 .net "rd_rq_in", 0 0, L_0x55dd3fbc2e70; 1 drivers +v0x55dd3fb5d210_0 .net "reset", 0 0, L_0x55dd3fbd4670; 1 drivers +v0x55dd3fb5d2b0_0 .var "sa", 0 35; +v0x55dd3fb5d390_0 .net "strobe_sense", 0 0, L_0x55dd3fbd0d80; 1 drivers +L_0x7fc2ff32c2c0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb5d480_0 .net "sw_restart", 0 0, L_0x7fc2ff32c2c0; 1 drivers +L_0x7fc2ff32c278 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb5d520_0 .net "sw_single_step", 0 0, L_0x7fc2ff32c278; 1 drivers +v0x55dd3fb5d5c0_0 .net "wr_rq_in", 0 0, L_0x55dd3fbc3450; 1 drivers +L_0x55dd3fbc0380 .part L_0x55dd3fbbe770, 1, 3; +L_0x55dd3fbc0420 .cmp/eq 3, L_0x55dd3fbc0380, L_0x7fc2ff32b978; +L_0x55dd3fbc08e0 .part L_0x7fc2ff32c470, 1, 3; +L_0x55dd3fbc09b0 .cmp/eq 3, L_0x55dd3fbc08e0, L_0x7fc2ff32b9c0; +L_0x55dd3fbc0f20 .part L_0x7fc2ff32c6b0, 1, 3; +L_0x55dd3fbc0fc0 .cmp/eq 3, L_0x55dd3fbc0f20, L_0x7fc2ff32ba08; +L_0x55dd3fbc14b0 .part L_0x7fc2ff32c8f0, 1, 3; +L_0x55dd3fbc15b0 .cmp/eq 3, L_0x55dd3fbc14b0, L_0x7fc2ff32ba50; +LS_0x55dd3fbc1bd0_0_0 .concat [ 1 1 1 1], L_0x55dd3fbcad60, L_0x55dd3fbcad60, L_0x55dd3fbcad60, L_0x55dd3fbcad60; +LS_0x55dd3fbc1bd0_0_4 .concat [ 1 1 1 1], L_0x55dd3fbcad60, L_0x55dd3fbcad60, L_0x55dd3fbcad60, L_0x55dd3fbcad60; +LS_0x55dd3fbc1bd0_0_8 .concat [ 1 1 1 1], L_0x55dd3fbcad60, L_0x55dd3fbcad60, L_0x55dd3fbcad60, L_0x55dd3fbcad60; +LS_0x55dd3fbc1bd0_0_12 .concat [ 1 1 1 0], L_0x55dd3fbcad60, L_0x55dd3fbcad60, L_0x55dd3fbcad60; +L_0x55dd3fbc1bd0 .concat [ 4 4 4 3], LS_0x55dd3fbc1bd0_0_0, LS_0x55dd3fbc1bd0_0_4, LS_0x55dd3fbc1bd0_0_8, LS_0x55dd3fbc1bd0_0_12; +LS_0x55dd3fbc1e30_0_0 .concat [ 1 1 1 1], L_0x55dd3fbcb000, L_0x55dd3fbcb000, L_0x55dd3fbcb000, L_0x55dd3fbcb000; +LS_0x55dd3fbc1e30_0_4 .concat [ 1 1 1 1], L_0x55dd3fbcb000, L_0x55dd3fbcb000, L_0x55dd3fbcb000, L_0x55dd3fbcb000; +LS_0x55dd3fbc1e30_0_8 .concat [ 1 1 1 1], L_0x55dd3fbcb000, L_0x55dd3fbcb000, L_0x55dd3fbcb000, L_0x55dd3fbcb000; +LS_0x55dd3fbc1e30_0_12 .concat [ 1 1 1 0], L_0x55dd3fbcb000, L_0x55dd3fbcb000, L_0x55dd3fbcb000; +L_0x55dd3fbc1e30 .concat [ 4 4 4 3], LS_0x55dd3fbc1e30_0_0, LS_0x55dd3fbc1e30_0_4, LS_0x55dd3fbc1e30_0_8, LS_0x55dd3fbc1e30_0_12; +LS_0x55dd3fbc21e0_0_0 .concat [ 1 1 1 1], L_0x55dd3fbcb070, L_0x55dd3fbcb070, L_0x55dd3fbcb070, L_0x55dd3fbcb070; +LS_0x55dd3fbc21e0_0_4 .concat [ 1 1 1 1], L_0x55dd3fbcb070, L_0x55dd3fbcb070, L_0x55dd3fbcb070, L_0x55dd3fbcb070; +LS_0x55dd3fbc21e0_0_8 .concat [ 1 1 1 1], L_0x55dd3fbcb070, L_0x55dd3fbcb070, L_0x55dd3fbcb070, L_0x55dd3fbcb070; +LS_0x55dd3fbc21e0_0_12 .concat [ 1 1 1 0], L_0x55dd3fbcb070, L_0x55dd3fbcb070, L_0x55dd3fbcb070; +L_0x55dd3fbc21e0 .concat [ 4 4 4 3], LS_0x55dd3fbc21e0_0_0, LS_0x55dd3fbc21e0_0_4, LS_0x55dd3fbc21e0_0_8, LS_0x55dd3fbc21e0_0_12; +LS_0x55dd3fbc2050_0_0 .concat [ 1 1 1 1], L_0x55dd3fbcb320, L_0x55dd3fbcb320, L_0x55dd3fbcb320, L_0x55dd3fbcb320; +LS_0x55dd3fbc2050_0_4 .concat [ 1 1 1 1], L_0x55dd3fbcb320, L_0x55dd3fbcb320, L_0x55dd3fbcb320, L_0x55dd3fbcb320; +LS_0x55dd3fbc2050_0_8 .concat [ 1 1 1 1], L_0x55dd3fbcb320, L_0x55dd3fbcb320, L_0x55dd3fbcb320, L_0x55dd3fbcb320; +LS_0x55dd3fbc2050_0_12 .concat [ 1 1 1 0], L_0x55dd3fbcb320, L_0x55dd3fbcb320, L_0x55dd3fbcb320; +L_0x55dd3fbc2050 .concat [ 4 4 4 3], LS_0x55dd3fbc2050_0_0, LS_0x55dd3fbc2050_0_4, LS_0x55dd3fbc2050_0_8, LS_0x55dd3fbc2050_0_12; +LS_0x55dd3fbc38a0_0_0 .concat [ 1 1 1 1], L_0x55dd3fbcad60, L_0x55dd3fbcad60, L_0x55dd3fbcad60, L_0x55dd3fbcad60; +LS_0x55dd3fbc38a0_0_4 .concat [ 1 1 1 1], L_0x55dd3fbcad60, L_0x55dd3fbcad60, L_0x55dd3fbcad60, L_0x55dd3fbcad60; +LS_0x55dd3fbc38a0_0_8 .concat [ 1 1 1 1], L_0x55dd3fbcad60, L_0x55dd3fbcad60, L_0x55dd3fbcad60, L_0x55dd3fbcad60; +LS_0x55dd3fbc38a0_0_12 .concat [ 1 1 1 1], L_0x55dd3fbcad60, L_0x55dd3fbcad60, L_0x55dd3fbcad60, L_0x55dd3fbcad60; +LS_0x55dd3fbc38a0_0_16 .concat [ 1 1 1 1], L_0x55dd3fbcad60, L_0x55dd3fbcad60, L_0x55dd3fbcad60, L_0x55dd3fbcad60; +LS_0x55dd3fbc38a0_0_20 .concat [ 1 1 1 1], L_0x55dd3fbcad60, L_0x55dd3fbcad60, L_0x55dd3fbcad60, L_0x55dd3fbcad60; +LS_0x55dd3fbc38a0_0_24 .concat [ 1 1 1 1], L_0x55dd3fbcad60, L_0x55dd3fbcad60, L_0x55dd3fbcad60, L_0x55dd3fbcad60; +LS_0x55dd3fbc38a0_0_28 .concat [ 1 1 1 1], L_0x55dd3fbcad60, L_0x55dd3fbcad60, L_0x55dd3fbcad60, L_0x55dd3fbcad60; +LS_0x55dd3fbc38a0_0_32 .concat [ 1 1 1 1], L_0x55dd3fbcad60, L_0x55dd3fbcad60, L_0x55dd3fbcad60, L_0x55dd3fbcad60; +LS_0x55dd3fbc38a0_1_0 .concat [ 4 4 4 4], LS_0x55dd3fbc38a0_0_0, LS_0x55dd3fbc38a0_0_4, LS_0x55dd3fbc38a0_0_8, LS_0x55dd3fbc38a0_0_12; +LS_0x55dd3fbc38a0_1_4 .concat [ 4 4 4 4], LS_0x55dd3fbc38a0_0_16, LS_0x55dd3fbc38a0_0_20, LS_0x55dd3fbc38a0_0_24, LS_0x55dd3fbc38a0_0_28; +LS_0x55dd3fbc38a0_1_8 .concat [ 4 0 0 0], LS_0x55dd3fbc38a0_0_32; +L_0x55dd3fbc38a0 .concat [ 16 16 4 0], LS_0x55dd3fbc38a0_1_0, LS_0x55dd3fbc38a0_1_4, LS_0x55dd3fbc38a0_1_8; +LS_0x55dd3fbc3b40_0_0 .concat [ 1 1 1 1], L_0x55dd3fbcb000, L_0x55dd3fbcb000, L_0x55dd3fbcb000, L_0x55dd3fbcb000; +LS_0x55dd3fbc3b40_0_4 .concat [ 1 1 1 1], L_0x55dd3fbcb000, L_0x55dd3fbcb000, L_0x55dd3fbcb000, L_0x55dd3fbcb000; +LS_0x55dd3fbc3b40_0_8 .concat [ 1 1 1 1], L_0x55dd3fbcb000, L_0x55dd3fbcb000, L_0x55dd3fbcb000, L_0x55dd3fbcb000; +LS_0x55dd3fbc3b40_0_12 .concat [ 1 1 1 1], L_0x55dd3fbcb000, L_0x55dd3fbcb000, L_0x55dd3fbcb000, L_0x55dd3fbcb000; +LS_0x55dd3fbc3b40_0_16 .concat [ 1 1 1 1], L_0x55dd3fbcb000, L_0x55dd3fbcb000, L_0x55dd3fbcb000, L_0x55dd3fbcb000; +LS_0x55dd3fbc3b40_0_20 .concat [ 1 1 1 1], L_0x55dd3fbcb000, L_0x55dd3fbcb000, L_0x55dd3fbcb000, L_0x55dd3fbcb000; +LS_0x55dd3fbc3b40_0_24 .concat [ 1 1 1 1], L_0x55dd3fbcb000, L_0x55dd3fbcb000, L_0x55dd3fbcb000, L_0x55dd3fbcb000; +LS_0x55dd3fbc3b40_0_28 .concat [ 1 1 1 1], L_0x55dd3fbcb000, L_0x55dd3fbcb000, L_0x55dd3fbcb000, L_0x55dd3fbcb000; +LS_0x55dd3fbc3b40_0_32 .concat [ 1 1 1 1], L_0x55dd3fbcb000, L_0x55dd3fbcb000, L_0x55dd3fbcb000, L_0x55dd3fbcb000; +LS_0x55dd3fbc3b40_1_0 .concat [ 4 4 4 4], LS_0x55dd3fbc3b40_0_0, LS_0x55dd3fbc3b40_0_4, LS_0x55dd3fbc3b40_0_8, LS_0x55dd3fbc3b40_0_12; +LS_0x55dd3fbc3b40_1_4 .concat [ 4 4 4 4], LS_0x55dd3fbc3b40_0_16, LS_0x55dd3fbc3b40_0_20, LS_0x55dd3fbc3b40_0_24, LS_0x55dd3fbc3b40_0_28; +LS_0x55dd3fbc3b40_1_8 .concat [ 4 0 0 0], LS_0x55dd3fbc3b40_0_32; +L_0x55dd3fbc3b40 .concat [ 16 16 4 0], LS_0x55dd3fbc3b40_1_0, LS_0x55dd3fbc3b40_1_4, LS_0x55dd3fbc3b40_1_8; +LS_0x55dd3fbc42d0_0_0 .concat [ 1 1 1 1], L_0x55dd3fbcb070, L_0x55dd3fbcb070, L_0x55dd3fbcb070, L_0x55dd3fbcb070; +LS_0x55dd3fbc42d0_0_4 .concat [ 1 1 1 1], L_0x55dd3fbcb070, L_0x55dd3fbcb070, L_0x55dd3fbcb070, L_0x55dd3fbcb070; +LS_0x55dd3fbc42d0_0_8 .concat [ 1 1 1 1], L_0x55dd3fbcb070, L_0x55dd3fbcb070, L_0x55dd3fbcb070, L_0x55dd3fbcb070; +LS_0x55dd3fbc42d0_0_12 .concat [ 1 1 1 1], L_0x55dd3fbcb070, L_0x55dd3fbcb070, L_0x55dd3fbcb070, L_0x55dd3fbcb070; +LS_0x55dd3fbc42d0_0_16 .concat [ 1 1 1 1], L_0x55dd3fbcb070, L_0x55dd3fbcb070, L_0x55dd3fbcb070, L_0x55dd3fbcb070; +LS_0x55dd3fbc42d0_0_20 .concat [ 1 1 1 1], L_0x55dd3fbcb070, L_0x55dd3fbcb070, L_0x55dd3fbcb070, L_0x55dd3fbcb070; +LS_0x55dd3fbc42d0_0_24 .concat [ 1 1 1 1], L_0x55dd3fbcb070, L_0x55dd3fbcb070, L_0x55dd3fbcb070, L_0x55dd3fbcb070; +LS_0x55dd3fbc42d0_0_28 .concat [ 1 1 1 1], L_0x55dd3fbcb070, L_0x55dd3fbcb070, L_0x55dd3fbcb070, L_0x55dd3fbcb070; +LS_0x55dd3fbc42d0_0_32 .concat [ 1 1 1 1], L_0x55dd3fbcb070, L_0x55dd3fbcb070, L_0x55dd3fbcb070, L_0x55dd3fbcb070; +LS_0x55dd3fbc42d0_1_0 .concat [ 4 4 4 4], LS_0x55dd3fbc42d0_0_0, LS_0x55dd3fbc42d0_0_4, LS_0x55dd3fbc42d0_0_8, LS_0x55dd3fbc42d0_0_12; +LS_0x55dd3fbc42d0_1_4 .concat [ 4 4 4 4], LS_0x55dd3fbc42d0_0_16, LS_0x55dd3fbc42d0_0_20, LS_0x55dd3fbc42d0_0_24, LS_0x55dd3fbc42d0_0_28; +LS_0x55dd3fbc42d0_1_8 .concat [ 4 0 0 0], LS_0x55dd3fbc42d0_0_32; +L_0x55dd3fbc42d0 .concat [ 16 16 4 0], LS_0x55dd3fbc42d0_1_0, LS_0x55dd3fbc42d0_1_4, LS_0x55dd3fbc42d0_1_8; +LS_0x55dd3fbc4c10_0_0 .concat [ 1 1 1 1], L_0x55dd3fbcb320, L_0x55dd3fbcb320, L_0x55dd3fbcb320, L_0x55dd3fbcb320; +LS_0x55dd3fbc4c10_0_4 .concat [ 1 1 1 1], L_0x55dd3fbcb320, L_0x55dd3fbcb320, L_0x55dd3fbcb320, L_0x55dd3fbcb320; +LS_0x55dd3fbc4c10_0_8 .concat [ 1 1 1 1], L_0x55dd3fbcb320, L_0x55dd3fbcb320, L_0x55dd3fbcb320, L_0x55dd3fbcb320; +LS_0x55dd3fbc4c10_0_12 .concat [ 1 1 1 1], L_0x55dd3fbcb320, L_0x55dd3fbcb320, L_0x55dd3fbcb320, L_0x55dd3fbcb320; +LS_0x55dd3fbc4c10_0_16 .concat [ 1 1 1 1], L_0x55dd3fbcb320, L_0x55dd3fbcb320, L_0x55dd3fbcb320, L_0x55dd3fbcb320; +LS_0x55dd3fbc4c10_0_20 .concat [ 1 1 1 1], L_0x55dd3fbcb320, L_0x55dd3fbcb320, L_0x55dd3fbcb320, L_0x55dd3fbcb320; +LS_0x55dd3fbc4c10_0_24 .concat [ 1 1 1 1], L_0x55dd3fbcb320, L_0x55dd3fbcb320, L_0x55dd3fbcb320, L_0x55dd3fbcb320; +LS_0x55dd3fbc4c10_0_28 .concat [ 1 1 1 1], L_0x55dd3fbcb320, L_0x55dd3fbcb320, L_0x55dd3fbcb320, L_0x55dd3fbcb320; +LS_0x55dd3fbc4c10_0_32 .concat [ 1 1 1 1], L_0x55dd3fbcb320, L_0x55dd3fbcb320, L_0x55dd3fbcb320, L_0x55dd3fbcb320; +LS_0x55dd3fbc4c10_1_0 .concat [ 4 4 4 4], LS_0x55dd3fbc4c10_0_0, LS_0x55dd3fbc4c10_0_4, LS_0x55dd3fbc4c10_0_8, LS_0x55dd3fbc4c10_0_12; +LS_0x55dd3fbc4c10_1_4 .concat [ 4 4 4 4], LS_0x55dd3fbc4c10_0_16, LS_0x55dd3fbc4c10_0_20, LS_0x55dd3fbc4c10_0_24, LS_0x55dd3fbc4c10_0_28; +LS_0x55dd3fbc4c10_1_8 .concat [ 4 0 0 0], LS_0x55dd3fbc4c10_0_32; +L_0x55dd3fbc4c10 .concat [ 16 16 4 0], LS_0x55dd3fbc4c10_1_0, LS_0x55dd3fbc4c10_1_4, LS_0x55dd3fbc4c10_1_8; +LS_0x55dd3fbc7010_0_0 .concat [ 1 1 1 1], L_0x55dd3fbc6fa0, L_0x55dd3fbc6fa0, L_0x55dd3fbc6fa0, L_0x55dd3fbc6fa0; +LS_0x55dd3fbc7010_0_4 .concat [ 1 1 1 1], L_0x55dd3fbc6fa0, L_0x55dd3fbc6fa0, L_0x55dd3fbc6fa0, L_0x55dd3fbc6fa0; +LS_0x55dd3fbc7010_0_8 .concat [ 1 1 1 1], L_0x55dd3fbc6fa0, L_0x55dd3fbc6fa0, L_0x55dd3fbc6fa0, L_0x55dd3fbc6fa0; +LS_0x55dd3fbc7010_0_12 .concat [ 1 1 1 1], L_0x55dd3fbc6fa0, L_0x55dd3fbc6fa0, L_0x55dd3fbc6fa0, L_0x55dd3fbc6fa0; +LS_0x55dd3fbc7010_0_16 .concat [ 1 1 1 1], L_0x55dd3fbc6fa0, L_0x55dd3fbc6fa0, L_0x55dd3fbc6fa0, L_0x55dd3fbc6fa0; +LS_0x55dd3fbc7010_0_20 .concat [ 1 1 1 1], L_0x55dd3fbc6fa0, L_0x55dd3fbc6fa0, L_0x55dd3fbc6fa0, L_0x55dd3fbc6fa0; +LS_0x55dd3fbc7010_0_24 .concat [ 1 1 1 1], L_0x55dd3fbc6fa0, L_0x55dd3fbc6fa0, L_0x55dd3fbc6fa0, L_0x55dd3fbc6fa0; +LS_0x55dd3fbc7010_0_28 .concat [ 1 1 1 1], L_0x55dd3fbc6fa0, L_0x55dd3fbc6fa0, L_0x55dd3fbc6fa0, L_0x55dd3fbc6fa0; +LS_0x55dd3fbc7010_0_32 .concat [ 1 1 1 1], L_0x55dd3fbc6fa0, L_0x55dd3fbc6fa0, L_0x55dd3fbc6fa0, L_0x55dd3fbc6fa0; +LS_0x55dd3fbc7010_1_0 .concat [ 4 4 4 4], LS_0x55dd3fbc7010_0_0, LS_0x55dd3fbc7010_0_4, LS_0x55dd3fbc7010_0_8, LS_0x55dd3fbc7010_0_12; +LS_0x55dd3fbc7010_1_4 .concat [ 4 4 4 4], LS_0x55dd3fbc7010_0_16, LS_0x55dd3fbc7010_0_20, LS_0x55dd3fbc7010_0_24, LS_0x55dd3fbc7010_0_28; +LS_0x55dd3fbc7010_1_8 .concat [ 4 0 0 0], LS_0x55dd3fbc7010_0_32; +L_0x55dd3fbc7010 .concat [ 16 16 4 0], LS_0x55dd3fbc7010_1_0, LS_0x55dd3fbc7010_1_4, LS_0x55dd3fbc7010_1_8; +LS_0x55dd3fbc7950_0_0 .concat [ 1 1 1 1], L_0x55dd3fbc78e0, L_0x55dd3fbc78e0, L_0x55dd3fbc78e0, L_0x55dd3fbc78e0; +LS_0x55dd3fbc7950_0_4 .concat [ 1 1 1 1], L_0x55dd3fbc78e0, L_0x55dd3fbc78e0, L_0x55dd3fbc78e0, L_0x55dd3fbc78e0; +LS_0x55dd3fbc7950_0_8 .concat [ 1 1 1 1], L_0x55dd3fbc78e0, L_0x55dd3fbc78e0, L_0x55dd3fbc78e0, L_0x55dd3fbc78e0; +LS_0x55dd3fbc7950_0_12 .concat [ 1 1 1 1], L_0x55dd3fbc78e0, L_0x55dd3fbc78e0, L_0x55dd3fbc78e0, L_0x55dd3fbc78e0; +LS_0x55dd3fbc7950_0_16 .concat [ 1 1 1 1], L_0x55dd3fbc78e0, L_0x55dd3fbc78e0, L_0x55dd3fbc78e0, L_0x55dd3fbc78e0; +LS_0x55dd3fbc7950_0_20 .concat [ 1 1 1 1], L_0x55dd3fbc78e0, L_0x55dd3fbc78e0, L_0x55dd3fbc78e0, L_0x55dd3fbc78e0; +LS_0x55dd3fbc7950_0_24 .concat [ 1 1 1 1], L_0x55dd3fbc78e0, L_0x55dd3fbc78e0, L_0x55dd3fbc78e0, L_0x55dd3fbc78e0; +LS_0x55dd3fbc7950_0_28 .concat [ 1 1 1 1], L_0x55dd3fbc78e0, L_0x55dd3fbc78e0, L_0x55dd3fbc78e0, L_0x55dd3fbc78e0; +LS_0x55dd3fbc7950_0_32 .concat [ 1 1 1 1], L_0x55dd3fbc78e0, L_0x55dd3fbc78e0, L_0x55dd3fbc78e0, L_0x55dd3fbc78e0; +LS_0x55dd3fbc7950_1_0 .concat [ 4 4 4 4], LS_0x55dd3fbc7950_0_0, LS_0x55dd3fbc7950_0_4, LS_0x55dd3fbc7950_0_8, LS_0x55dd3fbc7950_0_12; +LS_0x55dd3fbc7950_1_4 .concat [ 4 4 4 4], LS_0x55dd3fbc7950_0_16, LS_0x55dd3fbc7950_0_20, LS_0x55dd3fbc7950_0_24, LS_0x55dd3fbc7950_0_28; +LS_0x55dd3fbc7950_1_8 .concat [ 4 0 0 0], LS_0x55dd3fbc7950_0_32; +L_0x55dd3fbc7950 .concat [ 16 16 4 0], LS_0x55dd3fbc7950_1_0, LS_0x55dd3fbc7950_1_4, LS_0x55dd3fbc7950_1_8; +LS_0x55dd3fbc8360_0_0 .concat [ 1 1 1 1], L_0x55dd3fbc82f0, L_0x55dd3fbc82f0, L_0x55dd3fbc82f0, L_0x55dd3fbc82f0; +LS_0x55dd3fbc8360_0_4 .concat [ 1 1 1 1], L_0x55dd3fbc82f0, L_0x55dd3fbc82f0, L_0x55dd3fbc82f0, L_0x55dd3fbc82f0; +LS_0x55dd3fbc8360_0_8 .concat [ 1 1 1 1], L_0x55dd3fbc82f0, L_0x55dd3fbc82f0, L_0x55dd3fbc82f0, L_0x55dd3fbc82f0; +LS_0x55dd3fbc8360_0_12 .concat [ 1 1 1 1], L_0x55dd3fbc82f0, L_0x55dd3fbc82f0, L_0x55dd3fbc82f0, L_0x55dd3fbc82f0; +LS_0x55dd3fbc8360_0_16 .concat [ 1 1 1 1], L_0x55dd3fbc82f0, L_0x55dd3fbc82f0, L_0x55dd3fbc82f0, L_0x55dd3fbc82f0; +LS_0x55dd3fbc8360_0_20 .concat [ 1 1 1 1], L_0x55dd3fbc82f0, L_0x55dd3fbc82f0, L_0x55dd3fbc82f0, L_0x55dd3fbc82f0; +LS_0x55dd3fbc8360_0_24 .concat [ 1 1 1 1], L_0x55dd3fbc82f0, L_0x55dd3fbc82f0, L_0x55dd3fbc82f0, L_0x55dd3fbc82f0; +LS_0x55dd3fbc8360_0_28 .concat [ 1 1 1 1], L_0x55dd3fbc82f0, L_0x55dd3fbc82f0, L_0x55dd3fbc82f0, L_0x55dd3fbc82f0; +LS_0x55dd3fbc8360_0_32 .concat [ 1 1 1 1], L_0x55dd3fbc82f0, L_0x55dd3fbc82f0, L_0x55dd3fbc82f0, L_0x55dd3fbc82f0; +LS_0x55dd3fbc8360_1_0 .concat [ 4 4 4 4], LS_0x55dd3fbc8360_0_0, LS_0x55dd3fbc8360_0_4, LS_0x55dd3fbc8360_0_8, LS_0x55dd3fbc8360_0_12; +LS_0x55dd3fbc8360_1_4 .concat [ 4 4 4 4], LS_0x55dd3fbc8360_0_16, LS_0x55dd3fbc8360_0_20, LS_0x55dd3fbc8360_0_24, LS_0x55dd3fbc8360_0_28; +LS_0x55dd3fbc8360_1_8 .concat [ 4 0 0 0], LS_0x55dd3fbc8360_0_32; +L_0x55dd3fbc8360 .concat [ 16 16 4 0], LS_0x55dd3fbc8360_1_0, LS_0x55dd3fbc8360_1_4, LS_0x55dd3fbc8360_1_8; +LS_0x55dd3fbc8c80_0_0 .concat [ 1 1 1 1], L_0x55dd3fbc8c10, L_0x55dd3fbc8c10, L_0x55dd3fbc8c10, L_0x55dd3fbc8c10; +LS_0x55dd3fbc8c80_0_4 .concat [ 1 1 1 1], L_0x55dd3fbc8c10, L_0x55dd3fbc8c10, L_0x55dd3fbc8c10, L_0x55dd3fbc8c10; +LS_0x55dd3fbc8c80_0_8 .concat [ 1 1 1 1], L_0x55dd3fbc8c10, L_0x55dd3fbc8c10, L_0x55dd3fbc8c10, L_0x55dd3fbc8c10; +LS_0x55dd3fbc8c80_0_12 .concat [ 1 1 1 1], L_0x55dd3fbc8c10, L_0x55dd3fbc8c10, L_0x55dd3fbc8c10, L_0x55dd3fbc8c10; +LS_0x55dd3fbc8c80_0_16 .concat [ 1 1 1 1], L_0x55dd3fbc8c10, L_0x55dd3fbc8c10, L_0x55dd3fbc8c10, L_0x55dd3fbc8c10; +LS_0x55dd3fbc8c80_0_20 .concat [ 1 1 1 1], L_0x55dd3fbc8c10, L_0x55dd3fbc8c10, L_0x55dd3fbc8c10, L_0x55dd3fbc8c10; +LS_0x55dd3fbc8c80_0_24 .concat [ 1 1 1 1], L_0x55dd3fbc8c10, L_0x55dd3fbc8c10, L_0x55dd3fbc8c10, L_0x55dd3fbc8c10; +LS_0x55dd3fbc8c80_0_28 .concat [ 1 1 1 1], L_0x55dd3fbc8c10, L_0x55dd3fbc8c10, L_0x55dd3fbc8c10, L_0x55dd3fbc8c10; +LS_0x55dd3fbc8c80_0_32 .concat [ 1 1 1 1], L_0x55dd3fbc8c10, L_0x55dd3fbc8c10, L_0x55dd3fbc8c10, L_0x55dd3fbc8c10; +LS_0x55dd3fbc8c80_1_0 .concat [ 4 4 4 4], LS_0x55dd3fbc8c80_0_0, LS_0x55dd3fbc8c80_0_4, LS_0x55dd3fbc8c80_0_8, LS_0x55dd3fbc8c80_0_12; +LS_0x55dd3fbc8c80_1_4 .concat [ 4 4 4 4], LS_0x55dd3fbc8c80_0_16, LS_0x55dd3fbc8c80_0_20, LS_0x55dd3fbc8c80_0_24, LS_0x55dd3fbc8c80_0_28; +LS_0x55dd3fbc8c80_1_8 .concat [ 4 0 0 0], LS_0x55dd3fbc8c80_0_32; +L_0x55dd3fbc8c80 .concat [ 16 16 4 0], LS_0x55dd3fbc8c80_1_0, LS_0x55dd3fbc8c80_1_4, LS_0x55dd3fbc8c80_1_8; +L_0x55dd3fbd4100 .concat [ 15 3 0 0], v0x55dd3fb57120_0, L_0x7fc2ff32c1e8; +S_0x55dd3fb3d3e0 .scope module, "cmpc_pa0" "pa" 17 116, 3 31 0, S_0x55dd3fb3cb20; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +L_0x55dd3fbc5780 .functor AND 1, L_0x55dd3fbc4ab0, L_0x55dd3fbc5690, C4<1>, C4<1>; +v0x55dd3fb3d6a0_0 .net *"_s1", 0 0, L_0x55dd3fbc4ab0; 1 drivers +v0x55dd3fb3d7a0_0 .net *"_s3", 0 0, L_0x55dd3fbc55f0; 1 drivers +v0x55dd3fb3d880_0 .net *"_s5", 0 0, L_0x55dd3fbc5690; 1 drivers +v0x55dd3fb3d950_0 .net "clk", 0 0, v0x55dd3fb3c920_0; alias, 1 drivers +v0x55dd3fb3da20_0 .net "in", 0 0, L_0x55dd3fbc58d0; 1 drivers +v0x55dd3fb3db10_0 .net "p", 0 0, L_0x55dd3fbc5780; alias, 1 drivers +v0x55dd3fb3dbd0_0 .net "reset", 0 0, L_0x55dd3fbd4670; alias, 1 drivers +v0x55dd3fb3dc90_0 .var "x", 1 0; +E_0x55dd3fb3d620 .event posedge, v0x55dd3fb3dbd0_0, v0x55dd3fb3c920_0; +L_0x55dd3fbc4ab0 .part v0x55dd3fb3dc90_0, 0, 1; +L_0x55dd3fbc55f0 .part v0x55dd3fb3dc90_0, 1, 1; +L_0x55dd3fbc5690 .reduce/nor L_0x55dd3fbc55f0; +S_0x55dd3fb3ddf0 .scope module, "cmpc_pa1" "pa" 17 117, 3 31 0, S_0x55dd3fb3cb20; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +L_0x55dd3fbc5bf0 .functor AND 1, L_0x55dd3fbc5940, L_0x55dd3fbc5b00, C4<1>, C4<1>; +v0x55dd3fb3e050_0 .net *"_s1", 0 0, L_0x55dd3fbc5940; 1 drivers +v0x55dd3fb3e130_0 .net *"_s3", 0 0, L_0x55dd3fbc59e0; 1 drivers +v0x55dd3fb3e210_0 .net *"_s5", 0 0, L_0x55dd3fbc5b00; 1 drivers +v0x55dd3fb3e2e0_0 .net "clk", 0 0, v0x55dd3fb3c920_0; alias, 1 drivers +v0x55dd3fb3e3d0_0 .net "in", 0 0, L_0x55dd3fbc5d50; 1 drivers +v0x55dd3fb3e4e0_0 .net "p", 0 0, L_0x55dd3fbc5bf0; alias, 1 drivers +v0x55dd3fb3e5a0_0 .net "reset", 0 0, L_0x55dd3fbd4670; alias, 1 drivers +v0x55dd3fb3e640_0 .var "x", 1 0; +L_0x55dd3fbc5940 .part v0x55dd3fb3e640_0, 0, 1; +L_0x55dd3fbc59e0 .part v0x55dd3fb3e640_0, 1, 1; +L_0x55dd3fbc5b00 .reduce/nor L_0x55dd3fbc59e0; +S_0x55dd3fb3e780 .scope module, "cmpc_pa2" "pa" 17 118, 3 31 0, S_0x55dd3fb3cb20; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +L_0x55dd3fbc6200 .functor AND 1, L_0x55dd3fbc5fd0, L_0x55dd3fbc6110, C4<1>, C4<1>; +v0x55dd3fb3e9f0_0 .net *"_s1", 0 0, L_0x55dd3fbc5fd0; 1 drivers +v0x55dd3fb3ead0_0 .net *"_s3", 0 0, L_0x55dd3fbc6070; 1 drivers +v0x55dd3fb3ebb0_0 .net *"_s5", 0 0, L_0x55dd3fbc6110; 1 drivers +v0x55dd3fb3ec80_0 .net "clk", 0 0, v0x55dd3fb3c920_0; alias, 1 drivers +v0x55dd3fb3ed20_0 .net "in", 0 0, L_0x55dd3fbc6360; 1 drivers +v0x55dd3fb3ee30_0 .net "p", 0 0, L_0x55dd3fbc6200; alias, 1 drivers +v0x55dd3fb3eef0_0 .net "reset", 0 0, L_0x55dd3fbd4670; alias, 1 drivers +v0x55dd3fb3efe0_0 .var "x", 1 0; +L_0x55dd3fbc5fd0 .part v0x55dd3fb3efe0_0, 0, 1; +L_0x55dd3fbc6070 .part v0x55dd3fb3efe0_0, 1, 1; +L_0x55dd3fbc6110 .reduce/nor L_0x55dd3fbc6070; +S_0x55dd3fb3f140 .scope module, "cmpc_pa3" "pa" 17 119, 3 31 0, S_0x55dd3fb3cb20; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +L_0x55dd3fbc6650 .functor AND 1, L_0x55dd3fbc63d0, L_0x55dd3fbc6560, C4<1>, C4<1>; +v0x55dd3fb3f380_0 .net *"_s1", 0 0, L_0x55dd3fbc63d0; 1 drivers +v0x55dd3fb3f480_0 .net *"_s3", 0 0, L_0x55dd3fbc6470; 1 drivers +v0x55dd3fb3f560_0 .net *"_s5", 0 0, L_0x55dd3fbc6560; 1 drivers +v0x55dd3fb3f600_0 .net "clk", 0 0, v0x55dd3fb3c920_0; alias, 1 drivers +v0x55dd3fb3f6a0_0 .net "in", 0 0, L_0x55dd3fbc67b0; 1 drivers +v0x55dd3fb3f760_0 .net "p", 0 0, L_0x55dd3fbc6650; alias, 1 drivers +v0x55dd3fb3f820_0 .net "reset", 0 0, L_0x55dd3fbd4670; alias, 1 drivers +v0x55dd3fb3f8c0_0 .var "x", 1 0; +L_0x55dd3fbc63d0 .part v0x55dd3fb3f8c0_0, 0, 1; +L_0x55dd3fbc6470 .part v0x55dd3fb3f8c0_0, 1, 1; +L_0x55dd3fbc6560 .reduce/nor L_0x55dd3fbc6470; +S_0x55dd3fb3fa20 .scope module, "dly0" "ldly1us" 17 139, 5 198 0, S_0x55dd3fb3cb20; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" + .port_info 4 /OUTPUT 1 "l" +v0x55dd3fb3fc40_0 .net *"_s0", 31 0, L_0x55dd3fbca4c0; 1 drivers +L_0x7fc2ff32ba98 .functor BUFT 1, C4<00000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb3fd40_0 .net *"_s3", 25 0, L_0x7fc2ff32ba98; 1 drivers +L_0x7fc2ff32bae0 .functor BUFT 1, C4<00000000000000000000000000110010>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb3fe20_0 .net/2u *"_s4", 31 0, L_0x7fc2ff32bae0; 1 drivers +v0x55dd3fb3fee0_0 .net "clk", 0 0, v0x55dd3fb3c920_0; alias, 1 drivers +v0x55dd3fb3ff80_0 .net "in", 0 0, L_0x55dd3fbca3b0; alias, 1 drivers +v0x55dd3fb40090_0 .var "l", 0 0; +v0x55dd3fb40150_0 .net "p", 0 0, L_0x55dd3fbca5b0; alias, 1 drivers +v0x55dd3fb40210_0 .var "r", 5 0; +v0x55dd3fb402f0_0 .net "reset", 0 0, L_0x55dd3fbd4670; alias, 1 drivers +L_0x55dd3fbca4c0 .concat [ 6 26 0 0], v0x55dd3fb40210_0, L_0x7fc2ff32ba98; +L_0x55dd3fbca5b0 .cmp/eq 32, L_0x55dd3fbca4c0, L_0x7fc2ff32bae0; +S_0x55dd3fb40550 .scope module, "dly1" "ldly1us" 17 141, 5 198 0, S_0x55dd3fb3cb20; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" + .port_info 4 /OUTPUT 1 "l" +v0x55dd3fb40750_0 .net *"_s0", 31 0, L_0x55dd3fbca6f0; 1 drivers +L_0x7fc2ff32bb28 .functor BUFT 1, C4<00000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb40850_0 .net *"_s3", 25 0, L_0x7fc2ff32bb28; 1 drivers +L_0x7fc2ff32bb70 .functor BUFT 1, C4<00000000000000000000000000110010>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb40930_0 .net/2u *"_s4", 31 0, L_0x7fc2ff32bb70; 1 drivers +v0x55dd3fb40a20_0 .net "clk", 0 0, v0x55dd3fb3c920_0; alias, 1 drivers +v0x55dd3fb40ac0_0 .net "in", 0 0, L_0x55dd3fbca5b0; alias, 1 drivers +v0x55dd3fb40b60_0 .var "l", 0 0; +v0x55dd3fb40c00_0 .net "p", 0 0, L_0x55dd3fbca810; alias, 1 drivers +v0x55dd3fb40cc0_0 .var "r", 5 0; +v0x55dd3fb40da0_0 .net "reset", 0 0, L_0x55dd3fbd4670; alias, 1 drivers +L_0x55dd3fbca6f0 .concat [ 6 26 0 0], v0x55dd3fb40cc0_0, L_0x7fc2ff32bb28; +L_0x55dd3fbca810 .cmp/eq 32, L_0x55dd3fbca6f0, L_0x7fc2ff32bb70; +S_0x55dd3fb40fa0 .scope module, "dly10" "dly550ns" 17 214, 5 136 0, S_0x55dd3fb3cb20; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +v0x55dd3fb41190_0 .net *"_s0", 31 0, L_0x55dd3fbd3950; 1 drivers +L_0x7fc2ff32c038 .functor BUFT 1, C4<000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb41290_0 .net *"_s3", 26 0, L_0x7fc2ff32c038; 1 drivers +L_0x7fc2ff32c080 .functor BUFT 1, C4<00000000000000000000000000011011>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb41370_0 .net/2u *"_s4", 31 0, L_0x7fc2ff32c080; 1 drivers +v0x55dd3fb41460_0 .net "clk", 0 0, v0x55dd3fb3c920_0; alias, 1 drivers +v0x55dd3fb41500_0 .net "in", 0 0, L_0x55dd3fbd15b0; alias, 1 drivers +v0x55dd3fb41610_0 .net "p", 0 0, L_0x55dd3fbd3a40; alias, 1 drivers +v0x55dd3fb416d0_0 .var "r", 4 0; +v0x55dd3fb417b0_0 .net "reset", 0 0, L_0x55dd3fbd4670; alias, 1 drivers +L_0x55dd3fbd3950 .concat [ 5 27 0 0], v0x55dd3fb416d0_0, L_0x7fc2ff32c038; +L_0x55dd3fbd3a40 .cmp/eq 32, L_0x55dd3fbd3950, L_0x7fc2ff32c080; +S_0x55dd3fb418d0 .scope module, "dly11" "dly750ns" 17 215, 5 151 0, S_0x55dd3fb3cb20; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +v0x55dd3fb41b10_0 .net *"_s0", 31 0, L_0x55dd3fbd3b80; 1 drivers +L_0x7fc2ff32c0c8 .functor BUFT 1, C4<00000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb41c10_0 .net *"_s3", 25 0, L_0x7fc2ff32c0c8; 1 drivers +L_0x7fc2ff32c110 .functor BUFT 1, C4<00000000000000000000000000100101>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb41cf0_0 .net/2u *"_s4", 31 0, L_0x7fc2ff32c110; 1 drivers +v0x55dd3fb41de0_0 .net "clk", 0 0, v0x55dd3fb3c920_0; alias, 1 drivers +v0x55dd3fb41f90_0 .net "in", 0 0, L_0x55dd3fbd15b0; alias, 1 drivers +v0x55dd3fb42080_0 .net "p", 0 0, L_0x55dd3fbd3ca0; alias, 1 drivers +v0x55dd3fb42120_0 .var "r", 5 0; +v0x55dd3fb42200_0 .net "reset", 0 0, L_0x55dd3fbd4670; alias, 1 drivers +L_0x55dd3fbd3b80 .concat [ 6 26 0 0], v0x55dd3fb42120_0, L_0x7fc2ff32c0c8; +L_0x55dd3fbd3ca0 .cmp/eq 32, L_0x55dd3fbd3b80, L_0x7fc2ff32c110; +S_0x55dd3fb42350 .scope module, "dly12" "dly50ns" 17 216, 5 1 0, S_0x55dd3fb3cb20; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +v0x55dd3fb42590_0 .net *"_s0", 31 0, L_0x55dd3fbd3de0; 1 drivers +L_0x7fc2ff32c158 .functor BUFT 1, C4<000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb42690_0 .net *"_s3", 29 0, L_0x7fc2ff32c158; 1 drivers +L_0x7fc2ff32c1a0 .functor BUFT 1, C4<00000000000000000000000000000010>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb42770_0 .net/2u *"_s4", 31 0, L_0x7fc2ff32c1a0; 1 drivers +v0x55dd3fb42860_0 .net "clk", 0 0, v0x55dd3fb3c920_0; alias, 1 drivers +v0x55dd3fb42900_0 .net "in", 0 0, L_0x55dd3fbca070; alias, 1 drivers +v0x55dd3fb429c0_0 .net "p", 0 0, L_0x55dd3fbd3f00; alias, 1 drivers +v0x55dd3fb42a80_0 .var "r", 1 0; +v0x55dd3fb42b60_0 .net "reset", 0 0, L_0x55dd3fbd4670; alias, 1 drivers +L_0x55dd3fbd3de0 .concat [ 2 30 0 0], v0x55dd3fb42a80_0, L_0x7fc2ff32c158; +L_0x55dd3fbd3f00 .cmp/eq 32, L_0x55dd3fbd3de0, L_0x7fc2ff32c1a0; +S_0x55dd3fb42d90 .scope module, "dly2" "dly250ns" 17 205, 5 76 0, S_0x55dd3fb3cb20; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +v0x55dd3fb42fd0_0 .net *"_s0", 31 0, L_0x55dd3fbd2650; 1 drivers +L_0x7fc2ff32bbb8 .functor BUFT 1, C4<0000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb430d0_0 .net *"_s3", 27 0, L_0x7fc2ff32bbb8; 1 drivers +L_0x7fc2ff32bc00 .functor BUFT 1, C4<00000000000000000000000000001100>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb431b0_0 .net/2u *"_s4", 31 0, L_0x7fc2ff32bc00; 1 drivers +v0x55dd3fb432a0_0 .net "clk", 0 0, v0x55dd3fb3c920_0; alias, 1 drivers +v0x55dd3fb43340_0 .net "in", 0 0, L_0x55dd3fbcdf70; alias, 1 drivers +v0x55dd3fb43450_0 .net "p", 0 0, L_0x55dd3fbd2740; alias, 1 drivers +v0x55dd3fb43510_0 .var "r", 3 0; +v0x55dd3fb435f0_0 .net "reset", 0 0, L_0x55dd3fbd4670; alias, 1 drivers +L_0x55dd3fbd2650 .concat [ 4 28 0 0], v0x55dd3fb43510_0, L_0x7fc2ff32bbb8; +L_0x55dd3fbd2740 .cmp/eq 32, L_0x55dd3fbd2650, L_0x7fc2ff32bc00; +S_0x55dd3fb43710 .scope module, "dly3" "dly100ns" 17 206, 5 31 0, S_0x55dd3fb3cb20; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +v0x55dd3fb43950_0 .net *"_s0", 31 0, L_0x55dd3fbd28d0; 1 drivers +L_0x7fc2ff32bc48 .functor BUFT 1, C4<00000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb43a50_0 .net *"_s3", 28 0, L_0x7fc2ff32bc48; 1 drivers +L_0x7fc2ff32bc90 .functor BUFT 1, C4<00000000000000000000000000000101>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb43b30_0 .net/2u *"_s4", 31 0, L_0x7fc2ff32bc90; 1 drivers +v0x55dd3fb43c20_0 .net "clk", 0 0, v0x55dd3fb3c920_0; alias, 1 drivers +v0x55dd3fb43cc0_0 .net "in", 0 0, L_0x55dd3fbcca20; alias, 1 drivers +v0x55dd3fb43dd0_0 .net "p", 0 0, L_0x55dd3fbd29c0; alias, 1 drivers +v0x55dd3fb43e90_0 .var "r", 2 0; +v0x55dd3fb43f70_0 .net "reset", 0 0, L_0x55dd3fbd4670; alias, 1 drivers +L_0x55dd3fbd28d0 .concat [ 3 29 0 0], v0x55dd3fb43e90_0, L_0x7fc2ff32bc48; +L_0x55dd3fbd29c0 .cmp/eq 32, L_0x55dd3fbd28d0, L_0x7fc2ff32bc90; +S_0x55dd3fb44090 .scope module, "dly4" "dly250ns" 17 207, 5 76 0, S_0x55dd3fb3cb20; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +v0x55dd3fb442d0_0 .net *"_s0", 31 0, L_0x55dd3fbd2b40; 1 drivers +L_0x7fc2ff32bcd8 .functor BUFT 1, C4<0000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb443d0_0 .net *"_s3", 27 0, L_0x7fc2ff32bcd8; 1 drivers +L_0x7fc2ff32bd20 .functor BUFT 1, C4<00000000000000000000000000001100>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb444b0_0 .net/2u *"_s4", 31 0, L_0x7fc2ff32bd20; 1 drivers +v0x55dd3fb445a0_0 .net "clk", 0 0, v0x55dd3fb3c920_0; alias, 1 drivers +v0x55dd3fb44640_0 .net "in", 0 0, L_0x55dd3fbcfa50; alias, 1 drivers +v0x55dd3fb44750_0 .net "p", 0 0, L_0x55dd3fbd2c30; alias, 1 drivers +v0x55dd3fb44810_0 .var "r", 3 0; +v0x55dd3fb448f0_0 .net "reset", 0 0, L_0x55dd3fbd4670; alias, 1 drivers +L_0x55dd3fbd2b40 .concat [ 4 28 0 0], v0x55dd3fb44810_0, L_0x7fc2ff32bcd8; +L_0x55dd3fbd2c30 .cmp/eq 32, L_0x55dd3fbd2b40, L_0x7fc2ff32bd20; +S_0x55dd3fb44a10 .scope module, "dly5" "dly450ns" 17 208, 5 121 0, S_0x55dd3fb3cb20; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +v0x55dd3fb44c50_0 .net *"_s0", 31 0, L_0x55dd3fbd2d70; 1 drivers +L_0x7fc2ff32bd68 .functor BUFT 1, C4<000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb44d50_0 .net *"_s3", 26 0, L_0x7fc2ff32bd68; 1 drivers +L_0x7fc2ff32bdb0 .functor BUFT 1, C4<00000000000000000000000000010110>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb44e30_0 .net/2u *"_s4", 31 0, L_0x7fc2ff32bdb0; 1 drivers +v0x55dd3fb44f20_0 .net "clk", 0 0, v0x55dd3fb3c920_0; alias, 1 drivers +v0x55dd3fb44fc0_0 .net "in", 0 0, L_0x55dd3fbcfa50; alias, 1 drivers +v0x55dd3fb450b0_0 .net "p", 0 0, L_0x55dd3fbd2e60; alias, 1 drivers +v0x55dd3fb45150_0 .var "r", 4 0; +v0x55dd3fb45230_0 .net "reset", 0 0, L_0x55dd3fbd4670; alias, 1 drivers +L_0x55dd3fbd2d70 .concat [ 5 27 0 0], v0x55dd3fb45150_0, L_0x7fc2ff32bd68; +L_0x55dd3fbd2e60 .cmp/eq 32, L_0x55dd3fbd2d70, L_0x7fc2ff32bdb0; +S_0x55dd3fb45380 .scope module, "dly6" "dly550ns" 17 209, 5 136 0, S_0x55dd3fb3cb20; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +v0x55dd3fb455c0_0 .net *"_s0", 31 0, L_0x55dd3fbd2ff0; 1 drivers +L_0x7fc2ff32bdf8 .functor BUFT 1, C4<000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb456c0_0 .net *"_s3", 26 0, L_0x7fc2ff32bdf8; 1 drivers +L_0x7fc2ff32be40 .functor BUFT 1, C4<00000000000000000000000000011011>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb457a0_0 .net/2u *"_s4", 31 0, L_0x7fc2ff32be40; 1 drivers +v0x55dd3fb45890_0 .net "clk", 0 0, v0x55dd3fb3c920_0; alias, 1 drivers +v0x55dd3fb45930_0 .net "in", 0 0, L_0x55dd3fbcfa50; alias, 1 drivers +v0x55dd3fb45a70_0 .net "p", 0 0, L_0x55dd3fbd30e0; alias, 1 drivers +v0x55dd3fb45b30_0 .var "r", 4 0; +v0x55dd3fb45c10_0 .net "reset", 0 0, L_0x55dd3fbd4670; alias, 1 drivers +L_0x55dd3fbd2ff0 .concat [ 5 27 0 0], v0x55dd3fb45b30_0, L_0x7fc2ff32bdf8; +L_0x55dd3fbd30e0 .cmp/eq 32, L_0x55dd3fbd2ff0, L_0x7fc2ff32be40; +S_0x55dd3fb45d30 .scope module, "dly7" "dly70ns" 17 211, 5 16 0, S_0x55dd3fb3cb20; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +v0x55dd3fb45f70_0 .net *"_s0", 31 0, L_0x55dd3fbd3270; 1 drivers +L_0x7fc2ff32be88 .functor BUFT 1, C4<000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb46070_0 .net *"_s3", 29 0, L_0x7fc2ff32be88; 1 drivers +L_0x7fc2ff32bed0 .functor BUFT 1, C4<00000000000000000000000000000011>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb46150_0 .net/2u *"_s4", 31 0, L_0x7fc2ff32bed0; 1 drivers +v0x55dd3fb46210_0 .net "clk", 0 0, v0x55dd3fb3c920_0; alias, 1 drivers +v0x55dd3fb462b0_0 .net "in", 0 0, L_0x55dd3fbd0a40; alias, 1 drivers +v0x55dd3fb463c0_0 .net "p", 0 0, L_0x55dd3fbd3360; alias, 1 drivers +v0x55dd3fb46480_0 .var "r", 1 0; +v0x55dd3fb46560_0 .net "reset", 0 0, L_0x55dd3fbd4670; alias, 1 drivers +L_0x55dd3fbd3270 .concat [ 2 30 0 0], v0x55dd3fb46480_0, L_0x7fc2ff32be88; +L_0x55dd3fbd3360 .cmp/eq 32, L_0x55dd3fbd3270, L_0x7fc2ff32bed0; +S_0x55dd3fb46680 .scope module, "dly8" "dly300ns" 17 212, 5 91 0, S_0x55dd3fb3cb20; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +v0x55dd3fb468c0_0 .net *"_s0", 31 0, L_0x55dd3fbd34a0; 1 drivers +L_0x7fc2ff32bf18 .functor BUFT 1, C4<0000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb469c0_0 .net *"_s3", 27 0, L_0x7fc2ff32bf18; 1 drivers +L_0x7fc2ff32bf60 .functor BUFT 1, C4<00000000000000000000000000001111>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb46aa0_0 .net/2u *"_s4", 31 0, L_0x7fc2ff32bf60; 1 drivers +v0x55dd3fb46b90_0 .net "clk", 0 0, v0x55dd3fb3c920_0; alias, 1 drivers +v0x55dd3fb46c30_0 .net "in", 0 0, L_0x55dd3fbd0a40; alias, 1 drivers +v0x55dd3fb46d20_0 .net "p", 0 0, L_0x55dd3fbd3590; alias, 1 drivers +v0x55dd3fb46dc0_0 .var "r", 3 0; +v0x55dd3fb46ea0_0 .net "reset", 0 0, L_0x55dd3fbd4670; alias, 1 drivers +L_0x55dd3fbd34a0 .concat [ 4 28 0 0], v0x55dd3fb46dc0_0, L_0x7fc2ff32bf18; +L_0x55dd3fbd3590 .cmp/eq 32, L_0x55dd3fbd34a0, L_0x7fc2ff32bf60; +S_0x55dd3fb46ff0 .scope module, "dly9" "dly50ns" 17 213, 5 1 0, S_0x55dd3fb3cb20; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +v0x55dd3fb47230_0 .net *"_s0", 31 0, L_0x55dd3fbd36d0; 1 drivers +L_0x7fc2ff32bfa8 .functor BUFT 1, C4<000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb47330_0 .net *"_s3", 29 0, L_0x7fc2ff32bfa8; 1 drivers +L_0x7fc2ff32bff0 .functor BUFT 1, C4<00000000000000000000000000000010>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb47410_0 .net/2u *"_s4", 31 0, L_0x7fc2ff32bff0; 1 drivers +v0x55dd3fb47500_0 .net "clk", 0 0, v0x55dd3fb3c920_0; alias, 1 drivers +v0x55dd3fb475a0_0 .net "in", 0 0, L_0x55dd3fbd15b0; alias, 1 drivers +v0x55dd3fb476e0_0 .net "p", 0 0, L_0x55dd3fbd37c0; alias, 1 drivers +v0x55dd3fb477a0_0 .var "r", 1 0; +v0x55dd3fb47880_0 .net "reset", 0 0, L_0x55dd3fbd4670; alias, 1 drivers +L_0x55dd3fbd36d0 .concat [ 2 30 0 0], v0x55dd3fb477a0_0, L_0x7fc2ff32bfa8; +L_0x55dd3fbd37c0 .cmp/eq 32, L_0x55dd3fbd36d0, L_0x7fc2ff32bff0; +S_0x55dd3fb47bb0 .scope module, "pa0" "pa" 17 142, 3 31 0, S_0x55dd3fb3cb20; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +L_0x55dd3fbcac00 .functor AND 1, L_0x55dd3fbca950, L_0x55dd3fbcab10, C4<1>, C4<1>; +v0x55dd3fb47df0_0 .net *"_s1", 0 0, L_0x55dd3fbca950; 1 drivers +v0x55dd3fb47ef0_0 .net *"_s3", 0 0, L_0x55dd3fbca9f0; 1 drivers +v0x55dd3fb47fd0_0 .net *"_s5", 0 0, L_0x55dd3fbcab10; 1 drivers +v0x55dd3fb48070_0 .net "clk", 0 0, v0x55dd3fb3c920_0; alias, 1 drivers +v0x55dd3fb48110_0 .net "in", 0 0, L_0x55dd3fbca810; alias, 1 drivers +v0x55dd3fb48200_0 .net "p", 0 0, L_0x55dd3fbcac00; alias, 1 drivers +v0x55dd3fb482a0_0 .net "reset", 0 0, L_0x55dd3fbd4670; alias, 1 drivers +v0x55dd3fb48340_0 .var "x", 1 0; +L_0x55dd3fbca950 .part v0x55dd3fb48340_0, 0, 1; +L_0x55dd3fbca9f0 .part v0x55dd3fb48340_0, 1, 1; +L_0x55dd3fbcab10 .reduce/nor L_0x55dd3fbca9f0; +S_0x55dd3fb484d0 .scope module, "pa1" "pa" 17 180, 3 31 0, S_0x55dd3fb3cb20; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +L_0x55dd3fbcca20 .functor AND 1, L_0x55dd3fbcc7a0, L_0x55dd3fbcc930, C4<1>, C4<1>; +v0x55dd3fb48710_0 .net *"_s1", 0 0, L_0x55dd3fbcc7a0; 1 drivers +v0x55dd3fb48810_0 .net *"_s3", 0 0, L_0x55dd3fbcc840; 1 drivers +v0x55dd3fb488f0_0 .net *"_s5", 0 0, L_0x55dd3fbcc930; 1 drivers +v0x55dd3fb489c0_0 .net "clk", 0 0, v0x55dd3fb3c920_0; alias, 1 drivers +v0x55dd3fb48a60_0 .net "in", 0 0, L_0x55dd3fbccff0; 1 drivers +v0x55dd3fb48b70_0 .net "p", 0 0, L_0x55dd3fbcca20; alias, 1 drivers +v0x55dd3fb48c10_0 .net "reset", 0 0, L_0x55dd3fbd4670; alias, 1 drivers +v0x55dd3fb48cb0_0 .var "x", 1 0; +L_0x55dd3fbcc7a0 .part v0x55dd3fb48cb0_0, 0, 1; +L_0x55dd3fbcc840 .part v0x55dd3fb48cb0_0, 1, 1; +L_0x55dd3fbcc930 .reduce/nor L_0x55dd3fbcc840; +S_0x55dd3fb48e20 .scope module, "pa10" "pa" 17 195, 3 31 0, S_0x55dd3fb3cb20; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +L_0x55dd3fbd0a40 .functor AND 1, L_0x55dd3fbd07c0, L_0x55dd3fbd0950, C4<1>, C4<1>; +v0x55dd3fb49060_0 .net *"_s1", 0 0, L_0x55dd3fbd07c0; 1 drivers +v0x55dd3fb49160_0 .net *"_s3", 0 0, L_0x55dd3fbd0860; 1 drivers +v0x55dd3fb49240_0 .net *"_s5", 0 0, L_0x55dd3fbd0950; 1 drivers +v0x55dd3fb49310_0 .net "clk", 0 0, v0x55dd3fb3c920_0; alias, 1 drivers +v0x55dd3fb493b0_0 .net "in", 0 0, L_0x55dd3fbd2c30; alias, 1 drivers +v0x55dd3fb494a0_0 .net "p", 0 0, L_0x55dd3fbd0a40; alias, 1 drivers +v0x55dd3fb49590_0 .net "reset", 0 0, L_0x55dd3fbd4670; alias, 1 drivers +v0x55dd3fb49630_0 .var "x", 1 0; +L_0x55dd3fbd07c0 .part v0x55dd3fb49630_0, 0, 1; +L_0x55dd3fbd0860 .part v0x55dd3fb49630_0, 1, 1; +L_0x55dd3fbd0950 .reduce/nor L_0x55dd3fbd0860; +S_0x55dd3fb49770 .scope module, "pa11" "pa" 17 196, 3 31 0, S_0x55dd3fb3cb20; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +L_0x55dd3fbd0d80 .functor AND 1, L_0x55dd3fbd0b00, L_0x55dd3fbd0c90, C4<1>, C4<1>; +v0x55dd3fb499b0_0 .net *"_s1", 0 0, L_0x55dd3fbd0b00; 1 drivers +v0x55dd3fb49ab0_0 .net *"_s3", 0 0, L_0x55dd3fbd0ba0; 1 drivers +v0x55dd3fb49b90_0 .net *"_s5", 0 0, L_0x55dd3fbd0c90; 1 drivers +v0x55dd3fb49c60_0 .net "clk", 0 0, v0x55dd3fb3c920_0; alias, 1 drivers +v0x55dd3fb49d00_0 .net "in", 0 0, L_0x55dd3fbd0e90; 1 drivers +v0x55dd3fb49e10_0 .net "p", 0 0, L_0x55dd3fbd0d80; alias, 1 drivers +v0x55dd3fb49ed0_0 .net "reset", 0 0, L_0x55dd3fbd4670; alias, 1 drivers +v0x55dd3fb49f70_0 .var "x", 1 0; +L_0x55dd3fbd0b00 .part v0x55dd3fb49f70_0, 0, 1; +L_0x55dd3fbd0ba0 .part v0x55dd3fb49f70_0, 1, 1; +L_0x55dd3fbd0c90 .reduce/nor L_0x55dd3fbd0ba0; +S_0x55dd3fb4a0d0 .scope module, "pa12" "pa" 17 197, 3 31 0, S_0x55dd3fb3cb20; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +L_0x55dd3fbd1220 .functor AND 1, L_0x55dd3fbd0fa0, L_0x55dd3fbd1130, C4<1>, C4<1>; +v0x55dd3fb4a310_0 .net *"_s1", 0 0, L_0x55dd3fbd0fa0; 1 drivers +v0x55dd3fb4a410_0 .net *"_s3", 0 0, L_0x55dd3fbd1040; 1 drivers +v0x55dd3fb4a4f0_0 .net *"_s5", 0 0, L_0x55dd3fbd1130; 1 drivers +v0x55dd3fb4a5c0_0 .net "clk", 0 0, v0x55dd3fb3c920_0; alias, 1 drivers +v0x55dd3fb4a660_0 .net "in", 0 0, L_0x55dd3fbd0d80; alias, 1 drivers +v0x55dd3fb4a750_0 .net "p", 0 0, L_0x55dd3fbd1220; alias, 1 drivers +v0x55dd3fb4a7f0_0 .net "reset", 0 0, L_0x55dd3fbd4670; alias, 1 drivers +v0x55dd3fb4a890_0 .var "x", 1 0; +L_0x55dd3fbd0fa0 .part v0x55dd3fb4a890_0, 0, 1; +L_0x55dd3fbd1040 .part v0x55dd3fb4a890_0, 1, 1; +L_0x55dd3fbd1130 .reduce/nor L_0x55dd3fbd1040; +S_0x55dd3fb4aa20 .scope module, "pa13" "pa" 17 199, 3 31 0, S_0x55dd3fb3cb20; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +L_0x55dd3fbd15b0 .functor AND 1, L_0x55dd3fbd1330, L_0x55dd3fbd14c0, C4<1>, C4<1>; +v0x55dd3fb4ac60_0 .net *"_s1", 0 0, L_0x55dd3fbd1330; 1 drivers +v0x55dd3fb4ad60_0 .net *"_s3", 0 0, L_0x55dd3fbd13d0; 1 drivers +v0x55dd3fb4ae40_0 .net *"_s5", 0 0, L_0x55dd3fbd14c0; 1 drivers +v0x55dd3fb4af10_0 .net "clk", 0 0, v0x55dd3fb3c920_0; alias, 1 drivers +v0x55dd3fb4afb0_0 .net "in", 0 0, L_0x55dd3fbd1b50; 1 drivers +v0x55dd3fb4b0c0_0 .net "p", 0 0, L_0x55dd3fbd15b0; alias, 1 drivers +v0x55dd3fb4b160_0 .net "reset", 0 0, L_0x55dd3fbd4670; alias, 1 drivers +v0x55dd3fb4b200_0 .var "x", 1 0; +L_0x55dd3fbd1330 .part v0x55dd3fb4b200_0, 0, 1; +L_0x55dd3fbd13d0 .part v0x55dd3fb4b200_0, 1, 1; +L_0x55dd3fbd14c0 .reduce/nor L_0x55dd3fbd13d0; +S_0x55dd3fb4b360 .scope module, "pa14" "pa" 17 200, 3 31 0, S_0x55dd3fb3cb20; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +L_0x55dd3fbd21b0 .functor AND 1, L_0x55dd3fbd1f30, L_0x55dd3fbd20c0, C4<1>, C4<1>; +v0x55dd3fb4b5a0_0 .net *"_s1", 0 0, L_0x55dd3fbd1f30; 1 drivers +v0x55dd3fb4b6a0_0 .net *"_s3", 0 0, L_0x55dd3fbd1fd0; 1 drivers +v0x55dd3fb4b780_0 .net *"_s5", 0 0, L_0x55dd3fbd20c0; 1 drivers +v0x55dd3fb4b850_0 .net "clk", 0 0, v0x55dd3fb3c920_0; alias, 1 drivers +v0x55dd3fb4b8f0_0 .net "in", 0 0, v0x55dd3fb580d0_0; 1 drivers +v0x55dd3fb4ba00_0 .net "p", 0 0, L_0x55dd3fbd21b0; alias, 1 drivers +v0x55dd3fb4bac0_0 .net "reset", 0 0, L_0x55dd3fbd4670; alias, 1 drivers +v0x55dd3fb4bb60_0 .var "x", 1 0; +L_0x55dd3fbd1f30 .part v0x55dd3fb4bb60_0, 0, 1; +L_0x55dd3fbd1fd0 .part v0x55dd3fb4bb60_0, 1, 1; +L_0x55dd3fbd20c0 .reduce/nor L_0x55dd3fbd1fd0; +S_0x55dd3fb4bcc0 .scope module, "pa15" "pa" 17 202, 3 31 0, S_0x55dd3fb3cb20; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +L_0x55dd3fbd2540 .functor AND 1, L_0x55dd3fbd22c0, L_0x55dd3fbd2450, C4<1>, C4<1>; +v0x55dd3fb4bf00_0 .net *"_s1", 0 0, L_0x55dd3fbd22c0; 1 drivers +v0x55dd3fb4c000_0 .net *"_s3", 0 0, L_0x55dd3fbd2360; 1 drivers +v0x55dd3fb4c0e0_0 .net *"_s5", 0 0, L_0x55dd3fbd2450; 1 drivers +v0x55dd3fb4c1b0_0 .net "clk", 0 0, v0x55dd3fb3c920_0; alias, 1 drivers +v0x55dd3fb4c250_0 .net "in", 0 0, L_0x7fc2ff32c2c0; alias, 1 drivers +v0x55dd3fb4c360_0 .net "p", 0 0, L_0x55dd3fbd2540; alias, 1 drivers +v0x55dd3fb4c420_0 .net "reset", 0 0, L_0x55dd3fbd4670; alias, 1 drivers +v0x55dd3fb4c4c0_0 .var "x", 1 0; +L_0x55dd3fbd22c0 .part v0x55dd3fb4c4c0_0, 0, 1; +L_0x55dd3fbd2360 .part v0x55dd3fb4c4c0_0, 1, 1; +L_0x55dd3fbd2450 .reduce/nor L_0x55dd3fbd2360; +S_0x55dd3fb4c620 .scope module, "pa2" "pa" 17 183, 3 31 0, S_0x55dd3fb3cb20; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +L_0x55dd3fbcd380 .functor AND 1, L_0x55dd3fbcd100, L_0x55dd3fbcd290, C4<1>, C4<1>; +v0x55dd3fb4c860_0 .net *"_s1", 0 0, L_0x55dd3fbcd100; 1 drivers +v0x55dd3fb4c960_0 .net *"_s3", 0 0, L_0x55dd3fbcd1a0; 1 drivers +v0x55dd3fb4ca40_0 .net *"_s5", 0 0, L_0x55dd3fbcd290; 1 drivers +v0x55dd3fb4cb10_0 .net "clk", 0 0, v0x55dd3fb3c920_0; alias, 1 drivers +v0x55dd3fb4cbb0_0 .net "in", 0 0, L_0x55dd3fbcd4e0; 1 drivers +v0x55dd3fb4ccc0_0 .net "p", 0 0, L_0x55dd3fbcd380; alias, 1 drivers +v0x55dd3fb4cd80_0 .net "reset", 0 0, L_0x55dd3fbd4670; alias, 1 drivers +v0x55dd3fb4ce20_0 .var "x", 1 0; +L_0x55dd3fbcd100 .part v0x55dd3fb4ce20_0, 0, 1; +L_0x55dd3fbcd1a0 .part v0x55dd3fb4ce20_0, 1, 1; +L_0x55dd3fbcd290 .reduce/nor L_0x55dd3fbcd1a0; +S_0x55dd3fb4cf80 .scope module, "pa3" "pa" 17 184, 3 31 0, S_0x55dd3fb3cb20; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +L_0x55dd3fbcdad0 .functor AND 1, L_0x55dd3fbcd850, L_0x55dd3fbcd9e0, C4<1>, C4<1>; +v0x55dd3fb4d1c0_0 .net *"_s1", 0 0, L_0x55dd3fbcd850; 1 drivers +v0x55dd3fb4d2c0_0 .net *"_s3", 0 0, L_0x55dd3fbcd8f0; 1 drivers +v0x55dd3fb4d3a0_0 .net *"_s5", 0 0, L_0x55dd3fbcd9e0; 1 drivers +v0x55dd3fb4d470_0 .net "clk", 0 0, v0x55dd3fb3c920_0; alias, 1 drivers +v0x55dd3fb4d510_0 .net "in", 0 0, L_0x55dd3fbcdc30; 1 drivers +v0x55dd3fb4d620_0 .net "p", 0 0, L_0x55dd3fbcdad0; alias, 1 drivers +v0x55dd3fb4d6e0_0 .net "reset", 0 0, L_0x55dd3fbd4670; alias, 1 drivers +v0x55dd3fb4d780_0 .var "x", 1 0; +L_0x55dd3fbcd850 .part v0x55dd3fb4d780_0, 0, 1; +L_0x55dd3fbcd8f0 .part v0x55dd3fb4d780_0, 1, 1; +L_0x55dd3fbcd9e0 .reduce/nor L_0x55dd3fbcd8f0; +S_0x55dd3fb4d8e0 .scope module, "pa4" "pa" 17 185, 3 31 0, S_0x55dd3fb3cb20; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +L_0x55dd3fbcdf70 .functor AND 1, L_0x55dd3fbcdcf0, L_0x55dd3fbcde80, C4<1>, C4<1>; +v0x55dd3fb4db20_0 .net *"_s1", 0 0, L_0x55dd3fbcdcf0; 1 drivers +v0x55dd3fb4dc20_0 .net *"_s3", 0 0, L_0x55dd3fbcdd90; 1 drivers +v0x55dd3fb4dd00_0 .net *"_s5", 0 0, L_0x55dd3fbcde80; 1 drivers +v0x55dd3fb4ddd0_0 .net "clk", 0 0, v0x55dd3fb3c920_0; alias, 1 drivers +v0x55dd3fb4de70_0 .net "in", 0 0, L_0x55dd3fbce080; 1 drivers +v0x55dd3fb4df80_0 .net "p", 0 0, L_0x55dd3fbcdf70; alias, 1 drivers +v0x55dd3fb4e020_0 .net "reset", 0 0, L_0x55dd3fbd4670; alias, 1 drivers +v0x55dd3fb4e0c0_0 .var "x", 1 0; +L_0x55dd3fbcdcf0 .part v0x55dd3fb4e0c0_0, 0, 1; +L_0x55dd3fbcdd90 .part v0x55dd3fb4e0c0_0, 1, 1; +L_0x55dd3fbcde80 .reduce/nor L_0x55dd3fbcdd90; +S_0x55dd3fb4e230 .scope module, "pa5" "pa" 17 186, 3 31 0, S_0x55dd3fb3cb20; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +L_0x55dd3fbce630 .functor AND 1, L_0x55dd3fbce3b0, L_0x55dd3fbce540, C4<1>, C4<1>; +v0x55dd3fb4e470_0 .net *"_s1", 0 0, L_0x55dd3fbce3b0; 1 drivers +v0x55dd3fb4e570_0 .net *"_s3", 0 0, L_0x55dd3fbce450; 1 drivers +v0x55dd3fb4e650_0 .net *"_s5", 0 0, L_0x55dd3fbce540; 1 drivers +v0x55dd3fb4e720_0 .net "clk", 0 0, v0x55dd3fb3c920_0; alias, 1 drivers +v0x55dd3fb4e7c0_0 .net "in", 0 0, L_0x55dd3fbcec50; 1 drivers +v0x55dd3fb4e8d0_0 .net "p", 0 0, L_0x55dd3fbce630; alias, 1 drivers +v0x55dd3fb4e990_0 .net "reset", 0 0, L_0x55dd3fbd4670; alias, 1 drivers +v0x55dd3fb4ea30_0 .var "x", 1 0; +L_0x55dd3fbce3b0 .part v0x55dd3fb4ea30_0, 0, 1; +L_0x55dd3fbce450 .part v0x55dd3fb4ea30_0, 1, 1; +L_0x55dd3fbce540 .reduce/nor L_0x55dd3fbce450; +S_0x55dd3fb4eb90 .scope module, "pa6" "pa" 17 189, 3 31 0, S_0x55dd3fb3cb20; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +L_0x55dd3fbcf2c0 .functor AND 1, L_0x55dd3fbcf040, L_0x55dd3fbcf1d0, C4<1>, C4<1>; +v0x55dd3fb4edd0_0 .net *"_s1", 0 0, L_0x55dd3fbcf040; 1 drivers +v0x55dd3fb4eed0_0 .net *"_s3", 0 0, L_0x55dd3fbcf0e0; 1 drivers +v0x55dd3fb4efb0_0 .net *"_s5", 0 0, L_0x55dd3fbcf1d0; 1 drivers +v0x55dd3fb4f080_0 .net "clk", 0 0, v0x55dd3fb3c920_0; alias, 1 drivers +v0x55dd3fb4f120_0 .net "in", 0 0, L_0x55dd3fbcf3d0; 1 drivers +v0x55dd3fb4f230_0 .net "p", 0 0, L_0x55dd3fbcf2c0; alias, 1 drivers +v0x55dd3fb4f2f0_0 .net "reset", 0 0, L_0x55dd3fbd4670; alias, 1 drivers +v0x55dd3fb4f390_0 .var "x", 1 0; +L_0x55dd3fbcf040 .part v0x55dd3fb4f390_0, 0, 1; +L_0x55dd3fbcf0e0 .part v0x55dd3fb4f390_0, 1, 1; +L_0x55dd3fbcf1d0 .reduce/nor L_0x55dd3fbcf0e0; +S_0x55dd3fb4f4f0 .scope module, "pa7" "pa" 17 190, 3 31 0, S_0x55dd3fb3cb20; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +L_0x55dd3fbcf6c0 .functor AND 1, L_0x55dd3fbcf440, L_0x55dd3fbcf5d0, C4<1>, C4<1>; +v0x55dd3fb4f730_0 .net *"_s1", 0 0, L_0x55dd3fbcf440; 1 drivers +v0x55dd3fb4f830_0 .net *"_s3", 0 0, L_0x55dd3fbcf4e0; 1 drivers +v0x55dd3fb4f910_0 .net *"_s5", 0 0, L_0x55dd3fbcf5d0; 1 drivers +v0x55dd3fb4f9e0_0 .net "clk", 0 0, v0x55dd3fb3c920_0; alias, 1 drivers +v0x55dd3fb4fa80_0 .net "in", 0 0, L_0x55dd3fbcf2c0; alias, 1 drivers +v0x55dd3fb4fb70_0 .net "p", 0 0, L_0x55dd3fbcf6c0; alias, 1 drivers +v0x55dd3fb4fc10_0 .net "reset", 0 0, L_0x55dd3fbd4670; alias, 1 drivers +v0x55dd3fb4fcb0_0 .var "x", 1 0; +L_0x55dd3fbcf440 .part v0x55dd3fb4fcb0_0, 0, 1; +L_0x55dd3fbcf4e0 .part v0x55dd3fb4fcb0_0, 1, 1; +L_0x55dd3fbcf5d0 .reduce/nor L_0x55dd3fbcf4e0; +S_0x55dd3fb4fe40 .scope module, "pa8" "pa" 17 191, 3 31 0, S_0x55dd3fb3cb20; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +L_0x55dd3fbcfa50 .functor AND 1, L_0x55dd3fbcf7d0, L_0x55dd3fbcf960, C4<1>, C4<1>; +v0x55dd3fb50080_0 .net *"_s1", 0 0, L_0x55dd3fbcf7d0; 1 drivers +v0x55dd3fb50180_0 .net *"_s3", 0 0, L_0x55dd3fbcf870; 1 drivers +v0x55dd3fb50260_0 .net *"_s5", 0 0, L_0x55dd3fbcf960; 1 drivers +v0x55dd3fb50330_0 .net "clk", 0 0, v0x55dd3fb3c920_0; alias, 1 drivers +v0x55dd3fb507e0_0 .net "in", 0 0, L_0x55dd3fbcf6c0; alias, 1 drivers +v0x55dd3fb508d0_0 .net "p", 0 0, L_0x55dd3fbcfa50; alias, 1 drivers +v0x55dd3fb50970_0 .net "reset", 0 0, L_0x55dd3fbd4670; alias, 1 drivers +v0x55dd3fb50a10_0 .var "x", 1 0; +L_0x55dd3fbcf7d0 .part v0x55dd3fb50a10_0, 0, 1; +L_0x55dd3fbcf870 .part v0x55dd3fb50a10_0, 1, 1; +L_0x55dd3fbcf960 .reduce/nor L_0x55dd3fbcf870; +S_0x55dd3fb50b80 .scope module, "pa9" "pa" 17 192, 3 31 0, S_0x55dd3fb3cb20; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +L_0x55dd3fbcfde0 .functor AND 1, L_0x55dd3fbcfb60, L_0x55dd3fbcfcf0, C4<1>, C4<1>; +v0x55dd3fb50dc0_0 .net *"_s1", 0 0, L_0x55dd3fbcfb60; 1 drivers +v0x55dd3fb50ec0_0 .net *"_s3", 0 0, L_0x55dd3fbcfc00; 1 drivers +v0x55dd3fb50fa0_0 .net *"_s5", 0 0, L_0x55dd3fbcfcf0; 1 drivers +v0x55dd3fb51070_0 .net "clk", 0 0, v0x55dd3fb3c920_0; alias, 1 drivers +v0x55dd3fb51110_0 .net "in", 0 0, L_0x55dd3fbd0400; 1 drivers +v0x55dd3fb51220_0 .net "p", 0 0, L_0x55dd3fbcfde0; alias, 1 drivers +v0x55dd3fb512e0_0 .net "reset", 0 0, L_0x55dd3fbd4670; alias, 1 drivers +v0x55dd3fb51790_0 .var "x", 1 0; +L_0x55dd3fbcfb60 .part v0x55dd3fb51790_0, 0, 1; +L_0x55dd3fbcfc00 .part v0x55dd3fb51790_0, 1, 1; +L_0x55dd3fbcfcf0 .reduce/nor L_0x55dd3fbcfc00; +S_0x55dd3fb518f0 .scope module, "pg0" "pg" 17 137, 3 15 0, S_0x55dd3fb3cb20; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +L_0x55dd3fbca3b0 .functor AND 1, L_0x55dd3fbc7fc0, L_0x55dd3fbca2c0, C4<1>, C4<1>; +v0x55dd3fb51b30_0 .net *"_s1", 0 0, L_0x55dd3fbc7fc0; 1 drivers +v0x55dd3fb51c30_0 .net *"_s3", 0 0, L_0x55dd3fbca1d0; 1 drivers +v0x55dd3fb51d10_0 .net *"_s5", 0 0, L_0x55dd3fbca2c0; 1 drivers +v0x55dd3fb51de0_0 .net "clk", 0 0, v0x55dd3fb3c920_0; alias, 1 drivers +v0x55dd3fb51e80_0 .net "in", 0 0, L_0x7fc2ff32c230; alias, 1 drivers +v0x55dd3fb51f90_0 .net "p", 0 0, L_0x55dd3fbca3b0; alias, 1 drivers +v0x55dd3fb52030_0 .net "reset", 0 0, L_0x55dd3fbd4670; alias, 1 drivers +v0x55dd3fb520d0_0 .var "x", 1 0; +L_0x55dd3fbc7fc0 .part v0x55dd3fb520d0_0, 0, 1; +L_0x55dd3fbca1d0 .part v0x55dd3fb520d0_0, 1, 1; +L_0x55dd3fbca2c0 .reduce/nor L_0x55dd3fbca1d0; +S_0x55dd3fb5dd60 .scope module, "cmem_x" "memory_32k" 16 124, 18 1 0, S_0x55dd3fa340e0; + .timescale -9 -9; + .port_info 0 /INPUT 1 "i_clk" + .port_info 1 /INPUT 1 "i_reset_n" + .port_info 2 /INPUT 18 "i_address" + .port_info 3 /INPUT 1 "i_write" + .port_info 4 /INPUT 1 "i_read" + .port_info 5 /INPUT 36 "i_writedata" + .port_info 6 /OUTPUT 36 "o_readdata" + .port_info 7 /OUTPUT 1 "o_waitrequest" +v0x55dd3fb5ed80_0 .net *"_s1", 2 0, L_0x55dd3fbb1580; 1 drivers +v0x55dd3fb5ee80_0 .net *"_s2", 31 0, L_0x55dd3fbb1620; 1 drivers +L_0x7fc2ff32c9c8 .functor BUFT 1, C4<00000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb5ef60_0 .net *"_s5", 28 0, L_0x7fc2ff32c9c8; 1 drivers +L_0x7fc2ff32ca10 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb5f020_0 .net/2u *"_s6", 31 0, L_0x7fc2ff32ca10; 1 drivers +v0x55dd3fb5f100_0 .net "addr", 14 0, L_0x55dd3fbb1850; 1 drivers +v0x55dd3fb5f1c0_0 .net "addrok", 0 0, L_0x55dd3fbb1710; 1 drivers +v0x55dd3fb5f260_0 .net "i_address", 17 0, L_0x55dd3fbd4100; alias, 1 drivers +v0x55dd3fb5f350_0 .net "i_clk", 0 0, v0x55dd3fb3c920_0; alias, 1 drivers +v0x55dd3fb5f3f0_0 .net "i_read", 0 0, v0x55dd3fb5a5f0_0; alias, 1 drivers +v0x55dd3fb5f550_0 .net "i_reset_n", 0 0, v0x55dd3fb3ca00_0; alias, 1 drivers +v0x55dd3fb5f620_0 .net "i_write", 0 0, v0x55dd3fb5a7d0_0; alias, 1 drivers +v0x55dd3fb5f6f0_0 .net "i_writedata", 35 0, L_0x55dd3fbd4240; alias, 1 drivers +v0x55dd3fb5f790_0 .net "o_readdata", 35 0, L_0x55dd3fbb1b20; alias, 1 drivers +v0x55dd3fb5f880_0 .var "o_waitrequest", 0 0; +v0x55dd3fb5f920_0 .var "we", 0 0; +L_0x55dd3fbb1580 .part L_0x55dd3fbd4100, 15, 3; +L_0x55dd3fbb1620 .concat [ 3 29 0 0], L_0x55dd3fbb1580, L_0x7fc2ff32c9c8; +L_0x55dd3fbb1710 .cmp/eq 32, L_0x55dd3fbb1620, L_0x7fc2ff32ca10; +L_0x55dd3fbb1850 .part L_0x55dd3fbd4100, 0, 15; +S_0x55dd3fb5df80 .scope module, "ram" "onchip_ram" 18 18, 13 1 0, S_0x55dd3fb5dd60; + .timescale -9 -9; + .port_info 0 /INPUT 36 "data" + .port_info 1 /INPUT 15 "addr" + .port_info 2 /INPUT 1 "we" + .port_info 3 /INPUT 1 "clk" + .port_info 4 /OUTPUT 36 "q" +P_0x55dd3fb5e150 .param/l "ADDR_WIDTH" 0 13 2, +C4<00000000000000000000000000001111>; +P_0x55dd3fb5e190 .param/l "DATA_WIDTH" 0 13 2, +C4<00000000000000000000000000100100>; +L_0x55dd3fbb1b20 .functor BUFZ 36, L_0x55dd3fbb1940, C4<000000000000000000000000000000000000>, C4<000000000000000000000000000000000000>, C4<000000000000000000000000000000000000>; +v0x55dd3fb5e440_0 .net *"_s0", 35 0, L_0x55dd3fbb1940; 1 drivers +v0x55dd3fb5e540_0 .net *"_s2", 16 0, L_0x55dd3fbb19e0; 1 drivers +L_0x7fc2ff32ca58 .functor BUFT 1, C4<00>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb5e620_0 .net *"_s5", 1 0, L_0x7fc2ff32ca58; 1 drivers +v0x55dd3fb5e710_0 .net "addr", 14 0, L_0x55dd3fbb1850; alias, 1 drivers +v0x55dd3fb5e7f0_0 .var "addr_reg", 14 0; +v0x55dd3fb5e920_0 .net "clk", 0 0, v0x55dd3fb3c920_0; alias, 1 drivers +v0x55dd3fb5e9c0_0 .net "data", 35 0, L_0x55dd3fbd4240; alias, 1 drivers +v0x55dd3fb5ea80_0 .net "q", 35 0, L_0x55dd3fbb1b20; alias, 1 drivers +v0x55dd3fb5eb50 .array "ram", 0 32767, 35 0; +v0x55dd3fb5ebf0_0 .net "we", 0 0, v0x55dd3fb5f920_0; 1 drivers +E_0x55dd3fb5e3c0 .event posedge, v0x55dd3fb3c920_0; +L_0x55dd3fbb1940 .array/port v0x55dd3fb5eb50, L_0x55dd3fbb19e0; +L_0x55dd3fbb19e0 .concat [ 15 2 0 0], v0x55dd3fb5e7f0_0, L_0x7fc2ff32ca58; +S_0x55dd3fb5fa90 .scope module, "fmem" "fast162_dp" 16 144, 19 1 0, S_0x55dd3fa340e0; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "power" + .port_info 3 /INPUT 1 "sw_single_step" + .port_info 4 /INPUT 1 "sw_restart" + .port_info 5 /INPUT 1 "membus_wr_rs_p0" + .port_info 6 /INPUT 1 "membus_rq_cyc_p0" + .port_info 7 /INPUT 1 "membus_rd_rq_p0" + .port_info 8 /INPUT 1 "membus_wr_rq_p0" + .port_info 9 /INPUT 15 "membus_ma_p0" + .port_info 10 /INPUT 4 "membus_sel_p0" + .port_info 11 /INPUT 1 "membus_fmc_select_p0" + .port_info 12 /INPUT 36 "membus_mb_in_p0" + .port_info 13 /OUTPUT 1 "membus_addr_ack_p0" + .port_info 14 /OUTPUT 1 "membus_rd_rs_p0" + .port_info 15 /OUTPUT 36 "membus_mb_out_p0" + .port_info 16 /INPUT 1 "membus_wr_rs_p1" + .port_info 17 /INPUT 1 "membus_rq_cyc_p1" + .port_info 18 /INPUT 1 "membus_rd_rq_p1" + .port_info 19 /INPUT 1 "membus_wr_rq_p1" + .port_info 20 /INPUT 15 "membus_ma_p1" + .port_info 21 /INPUT 4 "membus_sel_p1" + .port_info 22 /INPUT 1 "membus_fmc_select_p1" + .port_info 23 /INPUT 36 "membus_mb_in_p1" + .port_info 24 /OUTPUT 1 "membus_addr_ack_p1" + .port_info 25 /OUTPUT 1 "membus_rd_rs_p1" + .port_info 26 /OUTPUT 36 "membus_mb_out_p1" + .port_info 27 /INPUT 1 "membus_wr_rs_p2" + .port_info 28 /INPUT 1 "membus_rq_cyc_p2" + .port_info 29 /INPUT 1 "membus_rd_rq_p2" + .port_info 30 /INPUT 1 "membus_wr_rq_p2" + .port_info 31 /INPUT 15 "membus_ma_p2" + .port_info 32 /INPUT 4 "membus_sel_p2" + .port_info 33 /INPUT 1 "membus_fmc_select_p2" + .port_info 34 /INPUT 36 "membus_mb_in_p2" + .port_info 35 /OUTPUT 1 "membus_addr_ack_p2" + .port_info 36 /OUTPUT 1 "membus_rd_rs_p2" + .port_info 37 /OUTPUT 36 "membus_mb_out_p2" + .port_info 38 /INPUT 1 "membus_wr_rs_p3" + .port_info 39 /INPUT 1 "membus_rq_cyc_p3" + .port_info 40 /INPUT 1 "membus_rd_rq_p3" + .port_info 41 /INPUT 1 "membus_wr_rq_p3" + .port_info 42 /INPUT 15 "membus_ma_p3" + .port_info 43 /INPUT 4 "membus_sel_p3" + .port_info 44 /INPUT 1 "membus_fmc_select_p3" + .port_info 45 /INPUT 36 "membus_mb_in_p3" + .port_info 46 /OUTPUT 1 "membus_addr_ack_p3" + .port_info 47 /OUTPUT 1 "membus_rd_rs_p3" + .port_info 48 /OUTPUT 36 "membus_mb_out_p3" + .port_info 49 /INPUT 18 "s_address" + .port_info 50 /INPUT 1 "s_write" + .port_info 51 /INPUT 1 "s_read" + .port_info 52 /INPUT 36 "s_writedata" + .port_info 53 /OUTPUT 36 "s_readdata" + .port_info 54 /OUTPUT 1 "s_waitrequest" +P_0x55dd3fb47920 .param/l "fmc_p0_sel" 0 19 71, C4<1>; +P_0x55dd3fb47960 .param/l "fmc_p1_sel" 0 19 72, C4<0>; +P_0x55dd3fb479a0 .param/l "fmc_p2_sel" 0 19 73, C4<0>; +P_0x55dd3fb479e0 .param/l "fmc_p3_sel" 0 19 74, C4<0>; +P_0x55dd3fb47a20 .param/l "memsel_p0" 0 19 67, C4<0000>; +P_0x55dd3fb47a60 .param/l "memsel_p1" 0 19 68, C4<0000>; +P_0x55dd3fb47aa0 .param/l "memsel_p2" 0 19 69, C4<0000>; +P_0x55dd3fb47ae0 .param/l "memsel_p3" 0 19 70, C4<0000>; +L_0x55dd3fbd5fd0 .functor OR 1, L_0x55dd3fbd5e90, v0x55dd3fb70890_0, C4<0>, C4<0>; +L_0x55dd3fbd6310 .functor BUFZ 1, L_0x55dd3fbbf2a0, C4<0>, C4<0>, C4<0>; +L_0x55dd3fbd63d0 .functor BUFZ 1, v0x55dd3fb79210_0, C4<0>, C4<0>, C4<0>; +L_0x55dd3fbd6490 .functor BUFZ 1, v0x55dd3fb796d0_0, C4<0>, C4<0>, C4<0>; +L_0x7fc2ff32cc08 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>; +L_0x55dd3fbd6b00 .functor AND 1, L_0x55dd3fbdea40, L_0x7fc2ff32cc08, C4<1>, C4<1>; +L_0x7fc2ff32cc50 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>; +L_0x55dd3fbd6c10 .functor AND 1, L_0x55dd3fbdec70, L_0x7fc2ff32cc50, C4<1>, C4<1>; +L_0x55dd3fbd6d20 .functor BUFZ 36, L_0x55dd3fbd7360, C4<000000000000000000000000000000000000>, C4<000000000000000000000000000000000000>, C4<000000000000000000000000000000000000>; +L_0x7fc2ff32cc98 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x55dd3fbd6d90 .functor AND 1, L_0x55dd3fbdea40, L_0x7fc2ff32cc98, C4<1>, C4<1>; +L_0x7fc2ff32cce0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x55dd3fbd6ea0 .functor AND 1, L_0x55dd3fbdec70, L_0x7fc2ff32cce0, C4<1>, C4<1>; +L_0x7fc2ff32cd70 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x55dd3fbd6f60 .functor AND 1, L_0x55dd3fbdea40, L_0x7fc2ff32cd70, C4<1>, C4<1>; +L_0x7fc2ff32cdb8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x55dd3fbd70c0 .functor AND 1, L_0x55dd3fbdec70, L_0x7fc2ff32cdb8, C4<1>, C4<1>; +L_0x7fc2ff32ce48 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x55dd3fbd71c0 .functor AND 1, L_0x55dd3fbdea40, L_0x7fc2ff32ce48, C4<1>, C4<1>; +L_0x7fc2ff32ce90 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x55dd3fbd72a0 .functor AND 1, L_0x55dd3fbdec70, L_0x7fc2ff32ce90, C4<1>, C4<1>; +L_0x55dd3fbd7540 .functor NOT 1, v0x55dd3fb70de0_0, C4<0>, C4<0>, C4<0>; +L_0x7fc2ff32cf68 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>; +L_0x55dd3fbd7230 .functor AND 1, L_0x7fc2ff32cf68, L_0x55dd3fbd7540, C4<1>, C4<1>; +L_0x55dd3fbd76d0 .functor NOT 1, v0x55dd3fb70de0_0, C4<0>, C4<0>, C4<0>; +L_0x7fc2ff32cfb0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x55dd3fbd7820 .functor AND 1, L_0x7fc2ff32cfb0, L_0x55dd3fbd76d0, C4<1>, C4<1>; +L_0x55dd3fbd7930 .functor NOT 1, v0x55dd3fb70de0_0, C4<0>, C4<0>, C4<0>; +L_0x7fc2ff32cff8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x55dd3fbd7a40 .functor AND 1, L_0x7fc2ff32cff8, L_0x55dd3fbd7930, C4<1>, C4<1>; +L_0x55dd3fbd7b50 .functor NOT 1, v0x55dd3fb70de0_0, C4<0>, C4<0>, C4<0>; +L_0x7fc2ff32d040 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x55dd3fbd7c70 .functor AND 1, L_0x7fc2ff32d040, L_0x55dd3fbd7b50, C4<1>, C4<1>; +L_0x7fc2ff32d088 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>; +L_0x55dd3fbd7d30 .functor AND 1, L_0x7fc2ff32d088, v0x55dd3fb700c0_0, C4<1>, C4<1>; +L_0x55dd3fbd7bc0 .functor NOT 1, L_0x55dd3fbd63d0, C4<0>, C4<0>, C4<0>; +L_0x55dd3fbd7f00 .functor AND 1, L_0x55dd3fbd7d30, L_0x55dd3fbd7bc0, C4<1>, C4<1>; +L_0x7fc2ff32d0d0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x55dd3fbd8130 .functor AND 1, L_0x7fc2ff32d0d0, v0x55dd3fb700c0_0, C4<1>, C4<1>; +L_0x55dd3fbd81f0 .functor NOT 1, L_0x55dd3fbd63d0, C4<0>, C4<0>, C4<0>; +L_0x55dd3fbd8060 .functor AND 1, L_0x55dd3fbd8130, L_0x55dd3fbd81f0, C4<1>, C4<1>; +L_0x7fc2ff32d118 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x55dd3fbd8420 .functor AND 1, L_0x7fc2ff32d118, v0x55dd3fb700c0_0, C4<1>, C4<1>; +L_0x55dd3fbd82f0 .functor NOT 1, L_0x55dd3fbd63d0, C4<0>, C4<0>, C4<0>; +L_0x55dd3fbd8360 .functor AND 1, L_0x55dd3fbd8420, L_0x55dd3fbd82f0, C4<1>, C4<1>; +L_0x7fc2ff32d160 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x55dd3fbd8570 .functor AND 1, L_0x7fc2ff32d160, v0x55dd3fb700c0_0, C4<1>, C4<1>; +L_0x55dd3fbd8800 .functor NOT 1, L_0x55dd3fbd63d0, C4<0>, C4<0>, C4<0>; +L_0x55dd3fbd8980 .functor AND 1, L_0x55dd3fbd8570, L_0x55dd3fbd8800, C4<1>, C4<1>; +L_0x55dd3fbd8ba0 .functor AND 1, L_0x55dd3fbd7230, L_0x55dd3fbd79a0, C4<1>, C4<1>; +L_0x55dd3fbd8dd0 .functor AND 1, L_0x55dd3fbd8ba0, v0x55dd3fb78e70_0, C4<1>, C4<1>; +L_0x55dd3fbd8e90 .functor AND 1, L_0x55dd3fbd8dd0, v0x55dd3fb793c0_0, C4<1>, C4<1>; +L_0x55dd3fbd9080 .functor AND 1, L_0x55dd3fbd7820, L_0x55dd3fbd8cb0, C4<1>, C4<1>; +L_0x7fc2ff32d9d0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x55dd3fbd9190 .functor AND 1, L_0x55dd3fbd9080, L_0x7fc2ff32d9d0, C4<1>, C4<1>; +L_0x7fc2ff32d868 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x55dd3fbd9390 .functor AND 1, L_0x55dd3fbd9190, L_0x7fc2ff32d868, C4<1>, C4<1>; +L_0x55dd3fbd8b30 .functor AND 1, L_0x55dd3fbd7a40, L_0x55dd3fbd9450, C4<1>, C4<1>; +L_0x7fc2ff32dc10 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x55dd3fbd97b0 .functor AND 1, L_0x55dd3fbd8b30, L_0x7fc2ff32dc10, C4<1>, C4<1>; +L_0x7fc2ff32daa8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x55dd3fbd9870 .functor AND 1, L_0x55dd3fbd97b0, L_0x7fc2ff32daa8, C4<1>, C4<1>; +L_0x55dd3fbd9b80 .functor AND 1, L_0x55dd3fbd7c70, L_0x55dd3fbd9a90, C4<1>, C4<1>; +L_0x7fc2ff32de50 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x55dd3fbd9c90 .functor AND 1, L_0x55dd3fbd9b80, L_0x7fc2ff32de50, C4<1>, C4<1>; +L_0x7fc2ff32dce8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x55dd3fbd9930 .functor AND 1, L_0x55dd3fbd9c90, L_0x7fc2ff32dce8, C4<1>, C4<1>; +L_0x7fc2ff32d7d8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x55dd3fbda540 .functor AND 1, L_0x7fc2ff32d7d8, v0x55dd3fb70de0_0, C4<1>, C4<1>; +L_0x55dd3fbdb610 .functor NOT 1, v0x55dd3fb70de0_0, C4<0>, C4<0>, C4<0>; +L_0x55dd3fbdb680 .functor AND 1, L_0x55dd3fbdd980, L_0x55dd3fbdb610, C4<1>, C4<1>; +L_0x55dd3fbdb920 .functor OR 1, L_0x55dd3fbde0d0, L_0x55dd3fbdb680, C4<0>, C4<0>; +L_0x55dd3fbdbdc0 .functor AND 1, L_0x55dd3fbda9b0, L_0x55dd3fbd63d0, C4<1>, C4<1>; +L_0x55dd3fbdcf80 .functor NOT 1, L_0x55dd3fbd63d0, C4<0>, C4<0>, C4<0>; +L_0x55dd3fbdcff0 .functor AND 1, L_0x55dd3fbda9b0, L_0x55dd3fbdcf80, C4<1>, C4<1>; +L_0x55dd3fbdd260 .functor AND 1, L_0x55dd3fbdcff0, L_0x55dd3fbd6490, C4<1>, C4<1>; +L_0x55dd3fbdd370 .functor AND 1, L_0x55dd3fbde5a0, L_0x55dd3fbd6490, C4<1>, C4<1>; +L_0x55dd3fbdd5f0 .functor OR 1, L_0x55dd3fbdd260, L_0x55dd3fbdd370, C4<0>, C4<0>; +L_0x55dd3fbdda90 .functor NOT 1, L_0x55dd3fbd6490, C4<0>, C4<0>, C4<0>; +L_0x55dd3fbddcd0 .functor AND 1, L_0x55dd3fbde5a0, L_0x55dd3fbdda90, C4<1>, C4<1>; +L_0x55dd3fbddd40 .functor OR 1, L_0x55dd3fbddcd0, L_0x55dd3fbdb0d0, C4<0>, C4<0>; +L_0x55dd3fbde210 .functor OR 1, L_0x55dd3fbda3e0, L_0x55dd3fbda050, C4<0>, C4<0>; +L_0x55dd3fbdf490 .functor BUFZ 36, L_0x55dd3fbdefe0, C4<000000000000000000000000000000000000>, C4<000000000000000000000000000000000000>, C4<000000000000000000000000000000000000>; +v0x55dd3fb6bb50_0 .net *"_s0", 31 0, L_0x55dd3fbd5df0; 1 drivers +v0x55dd3fb6bc50_0 .net *"_s10", 35 0, L_0x55dd3fbd6090; 1 drivers +v0x55dd3fb6bd30_0 .net/2u *"_s100", 0 0, L_0x7fc2ff32d040; 1 drivers +v0x55dd3fb6bdf0_0 .net *"_s102", 0 0, L_0x55dd3fbd7b50; 1 drivers +v0x55dd3fb6bed0_0 .net/2u *"_s106", 0 0, L_0x7fc2ff32d088; 1 drivers +v0x55dd3fb6c000_0 .net *"_s108", 0 0, L_0x55dd3fbd7d30; 1 drivers +v0x55dd3fb6c0e0_0 .net *"_s110", 0 0, L_0x55dd3fbd7bc0; 1 drivers +v0x55dd3fb6c1c0_0 .net/2u *"_s114", 0 0, L_0x7fc2ff32d0d0; 1 drivers +v0x55dd3fb6c2a0_0 .net *"_s116", 0 0, L_0x55dd3fbd8130; 1 drivers +v0x55dd3fb6c380_0 .net *"_s118", 0 0, L_0x55dd3fbd81f0; 1 drivers +L_0x7fc2ff32cb30 .functor BUFT 1, C4<000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb6c460_0 .net/2u *"_s12", 35 0, L_0x7fc2ff32cb30; 1 drivers +v0x55dd3fb6c540_0 .net/2u *"_s122", 0 0, L_0x7fc2ff32d118; 1 drivers +v0x55dd3fb6c620_0 .net *"_s124", 0 0, L_0x55dd3fbd8420; 1 drivers +v0x55dd3fb6c700_0 .net *"_s126", 0 0, L_0x55dd3fbd82f0; 1 drivers +v0x55dd3fb6c7e0_0 .net/2u *"_s130", 0 0, L_0x7fc2ff32d160; 1 drivers +v0x55dd3fb6c8c0_0 .net *"_s132", 0 0, L_0x55dd3fbd8570; 1 drivers +v0x55dd3fb6c9a0_0 .net *"_s134", 0 0, L_0x55dd3fbd8800; 1 drivers +L_0x7fc2ff32d1a8 .functor BUFT 1, C4<0000>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb6ca80_0 .net/2u *"_s138", 3 0, L_0x7fc2ff32d1a8; 1 drivers +v0x55dd3fb6cb60_0 .net *"_s140", 0 0, L_0x55dd3fbd79a0; 1 drivers +v0x55dd3fb6cc20_0 .net *"_s142", 0 0, L_0x55dd3fbd8ba0; 1 drivers +v0x55dd3fb6cd00_0 .net *"_s144", 0 0, L_0x55dd3fbd8dd0; 1 drivers +L_0x7fc2ff32d1f0 .functor BUFT 1, C4<0000>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb6cde0_0 .net/2u *"_s148", 3 0, L_0x7fc2ff32d1f0; 1 drivers +v0x55dd3fb6cec0_0 .net *"_s150", 0 0, L_0x55dd3fbd8cb0; 1 drivers +v0x55dd3fb6cf80_0 .net *"_s152", 0 0, L_0x55dd3fbd9080; 1 drivers +v0x55dd3fb6d060_0 .net *"_s154", 0 0, L_0x55dd3fbd9190; 1 drivers +L_0x7fc2ff32d238 .functor BUFT 1, C4<0000>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb6d140_0 .net/2u *"_s158", 3 0, L_0x7fc2ff32d238; 1 drivers +v0x55dd3fb6d220_0 .net *"_s160", 0 0, L_0x55dd3fbd9450; 1 drivers +v0x55dd3fb6d2e0_0 .net *"_s162", 0 0, L_0x55dd3fbd8b30; 1 drivers +v0x55dd3fb6d3c0_0 .net *"_s164", 0 0, L_0x55dd3fbd97b0; 1 drivers +L_0x7fc2ff32d280 .functor BUFT 1, C4<0000>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb6d4a0_0 .net/2u *"_s168", 3 0, L_0x7fc2ff32d280; 1 drivers +v0x55dd3fb6d580_0 .net *"_s170", 0 0, L_0x55dd3fbd9a90; 1 drivers +v0x55dd3fb6d640_0 .net *"_s172", 0 0, L_0x55dd3fbd9b80; 1 drivers +v0x55dd3fb6d720_0 .net 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"membus_ma_p2", 21 35, L_0x7fc2ff32db80; 1 drivers +L_0x7fc2ff32ddc0 .functor BUFT 1, C4<000000000000000>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb72200_0 .net "membus_ma_p3", 21 35, L_0x7fc2ff32ddc0; 1 drivers +v0x55dd3fb722e0_0 .net "membus_mb_in_p0", 0 35, L_0x55dd3fbc0250; alias, 1 drivers +L_0x7fc2ff32da18 .functor BUFT 1, C4<000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb723d0_0 .net "membus_mb_in_p1", 0 35, L_0x7fc2ff32da18; 1 drivers +L_0x7fc2ff32dc58 .functor BUFT 1, C4<000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb72490_0 .net "membus_mb_in_p2", 0 35, L_0x7fc2ff32dc58; 1 drivers +L_0x7fc2ff32de98 .functor BUFT 1, C4<000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb72d80_0 .net "membus_mb_in_p3", 0 35, L_0x7fc2ff32de98; 1 drivers +v0x55dd3fb72e60_0 .net "membus_mb_out_p0", 0 35, L_0x55dd3fbd6d20; alias, 1 drivers +L_0x7fc2ff32cd28 .functor BUFT 1, C4<000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; 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+v0x55dd3fb73d50_0 .net "membus_sel_p3", 18 21, L_0x7fc2ff32de08; 1 drivers +v0x55dd3fb73e30_0 .net "membus_wr_rq_p0", 0 0, v0x55dd3fb796d0_0; alias, 1 drivers +L_0x7fc2ff32d8f8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb73f00_0 .net "membus_wr_rq_p1", 0 0, L_0x7fc2ff32d8f8; 1 drivers +L_0x7fc2ff32db38 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb73fa0_0 .net "membus_wr_rq_p2", 0 0, L_0x7fc2ff32db38; 1 drivers +L_0x7fc2ff32dd78 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb74060_0 .net "membus_wr_rq_p3", 0 0, L_0x7fc2ff32dd78; 1 drivers +v0x55dd3fb74120_0 .net "membus_wr_rs_p0", 0 0, L_0x55dd3fbbf2a0; alias, 1 drivers +L_0x7fc2ff32d820 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb741f0_0 .net "membus_wr_rs_p1", 0 0, L_0x7fc2ff32d820; 1 drivers +L_0x7fc2ff32da60 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb74290_0 .net "membus_wr_rs_p2", 0 0, L_0x7fc2ff32da60; 1 drivers +L_0x7fc2ff32dca0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb74350_0 .net "membus_wr_rs_p3", 0 0, L_0x7fc2ff32dca0; 1 drivers +L_0x7fc2ff32d748 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb74410_0 .net "power", 0 0, L_0x7fc2ff32d748; 1 drivers +v0x55dd3fb744e0_0 .net "reset", 0 0, L_0x55dd3fbdf7e0; 1 drivers +v0x55dd3fb74580_0 .net "s_address", 17 0, v0x55dd3fb7bc20_0; 1 drivers +v0x55dd3fb74640_0 .net "s_read", 0 0, v0x55dd3fb7bce0_0; 1 drivers +v0x55dd3fb74700_0 .net "s_readdata", 35 0, L_0x55dd3fbdf490; alias, 1 drivers +v0x55dd3fb747e0_0 .net "s_waitrequest", 0 0, L_0x7fc2ff32d700; alias, 1 drivers +v0x55dd3fb748a0_0 .net "s_write", 0 0, v0x55dd3fb7c0d0_0; 1 drivers +v0x55dd3fb74960_0 .net "s_writedata", 35 0, v0x55dd3fb7c1a0_0; 1 drivers +v0x55dd3fb74a40_0 .net "sw_restart", 0 0, L_0x7fc2ff32d7d8; 1 drivers +L_0x7fc2ff32d790 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb74b00_0 .net "sw_single_step", 0 0, L_0x7fc2ff32d790; 1 drivers +v0x55dd3fb74bc0_0 .net "wr_rs", 0 0, L_0x55dd3fbd6310; 1 drivers +L_0x55dd3fbd5df0 .concat [ 15 17 0 0], L_0x55dd3fbd65a0, L_0x7fc2ff32caa0; +L_0x55dd3fbd5e90 .cmp/ne 32, L_0x55dd3fbd5df0, L_0x7fc2ff32cae8; +L_0x55dd3fbd6090 .array/port v0x55dd3fb6faf0, L_0x55dd3fbd65a0; +L_0x55dd3fbd6180 .functor MUXZ 36, L_0x7fc2ff32cb30, L_0x55dd3fbd6090, L_0x55dd3fbd5fd0, C4<>; +L_0x55dd3fbd6500 .part L_0x55dd3fbbe640, 0, 4; +L_0x55dd3fbd65a0 .concat [ 4 11 0 0], L_0x55dd3fbd6500, L_0x7fc2ff32cb78; +L_0x55dd3fbd66e0 .functor MUXZ 36, L_0x7fc2ff32cbc0, L_0x7fc2ff32de98, L_0x55dd3fbd8980, C4<>; +L_0x55dd3fbd67d0 .functor MUXZ 36, L_0x55dd3fbd66e0, L_0x7fc2ff32dc58, L_0x55dd3fbd8360, C4<>; +L_0x55dd3fbd6910 .functor MUXZ 36, L_0x55dd3fbd67d0, L_0x7fc2ff32da18, L_0x55dd3fbd8060, C4<>; +L_0x55dd3fbd6a00 .functor MUXZ 36, L_0x55dd3fbd6910, L_0x55dd3fbc0250, L_0x55dd3fbd7f00, C4<>; +L_0x55dd3fbd7360 .functor MUXZ 36, L_0x7fc2ff32cf20, L_0x55dd3fbd6180, L_0x55dd3fbdeea0, C4<>; +L_0x55dd3fbd79a0 .cmp/eq 4, L_0x7fc2ff32d1a8, L_0x55dd3fbbe770; +L_0x55dd3fbd8cb0 .cmp/eq 4, L_0x7fc2ff32d1f0, L_0x7fc2ff32d988; +L_0x55dd3fbd9450 .cmp/eq 4, L_0x7fc2ff32d238, L_0x7fc2ff32dbc8; +L_0x55dd3fbd9a90 .cmp/eq 4, L_0x7fc2ff32d280, L_0x7fc2ff32de08; +L_0x55dd3fbdefe0 .array/port v0x55dd3fb6faf0, L_0x55dd3fbdf260; +L_0x55dd3fbdf140 .part v0x55dd3fb7bc20_0, 0, 4; +L_0x55dd3fbdf260 .concat [ 4 2 0 0], L_0x55dd3fbdf140, L_0x7fc2ff32d6b8; +S_0x55dd3fb604e0 .scope module, "cmc_pg5" "pg" 19 161, 3 15 0, S_0x55dd3fb5fa90; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +L_0x55dd3fbdb0d0 .functor AND 1, L_0x55dd3fbdae50, L_0x55dd3fbdafe0, C4<1>, C4<1>; +v0x55dd3fb607d0_0 .net *"_s1", 0 0, L_0x55dd3fbdae50; 1 drivers +v0x55dd3fb608d0_0 .net *"_s3", 0 0, L_0x55dd3fbdaef0; 1 drivers +v0x55dd3fb609b0_0 .net *"_s5", 0 0, L_0x55dd3fbdafe0; 1 drivers +v0x55dd3fb60a80_0 .net "clk", 0 0, v0x55dd3fb3c920_0; alias, 1 drivers +v0x55dd3fb60b20_0 .net "in", 0 0, L_0x55dd3fbd6310; alias, 1 drivers +v0x55dd3fb60c30_0 .net "p", 0 0, L_0x55dd3fbdb0d0; alias, 1 drivers +v0x55dd3fb60cf0_0 .net "reset", 0 0, L_0x55dd3fbdf7e0; alias, 1 drivers +v0x55dd3fb60db0_0 .var "x", 1 0; +E_0x55dd3fb60750 .event posedge, v0x55dd3fb60cf0_0, v0x55dd3fb3c920_0; +L_0x55dd3fbdae50 .part v0x55dd3fb60db0_0, 0, 1; +L_0x55dd3fbdaef0 .part v0x55dd3fb60db0_0, 1, 1; +L_0x55dd3fbdafe0 .reduce/nor L_0x55dd3fbdaef0; +S_0x55dd3fb60f10 .scope module, "fmc_bd0" "bd" 19 201, 3 49 0, S_0x55dd3fb5fa90; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +v0x55dd3fb61170_0 .net *"_s0", 31 0, L_0x55dd3fbde950; 1 drivers +L_0x7fc2ff32d508 .functor BUFT 1, C4<00000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb61250_0 .net *"_s3", 28 0, L_0x7fc2ff32d508; 1 drivers +L_0x7fc2ff32d550 .functor BUFT 1, C4<00000000000000000000000000000100>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb61330_0 .net/2u *"_s4", 31 0, L_0x7fc2ff32d550; 1 drivers +v0x55dd3fb61420_0 .net "clk", 0 0, v0x55dd3fb3c920_0; alias, 1 drivers +v0x55dd3fb614c0_0 .net "in", 0 0, L_0x55dd3fbda9b0; alias, 1 drivers +v0x55dd3fb615d0_0 .net "p", 0 0, L_0x55dd3fbdea40; alias, 1 drivers +v0x55dd3fb61690_0 .var "r", 2 0; +v0x55dd3fb61770_0 .net "reset", 0 0, L_0x55dd3fbdf7e0; alias, 1 drivers +L_0x55dd3fbde950 .concat [ 3 29 0 0], v0x55dd3fb61690_0, L_0x7fc2ff32d508; +L_0x55dd3fbdea40 .cmp/eq 32, L_0x55dd3fbde950, L_0x7fc2ff32d550; +S_0x55dd3fb618a0 .scope module, "fmc_bd1" "bd" 19 202, 3 49 0, S_0x55dd3fb5fa90; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +v0x55dd3fb61b10_0 .net *"_s0", 31 0, L_0x55dd3fbdeb80; 1 drivers +L_0x7fc2ff32d598 .functor BUFT 1, C4<00000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb61bf0_0 .net *"_s3", 28 0, L_0x7fc2ff32d598; 1 drivers +L_0x7fc2ff32d5e0 .functor BUFT 1, C4<00000000000000000000000000000100>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb61cd0_0 .net/2u *"_s4", 31 0, L_0x7fc2ff32d5e0; 1 drivers +v0x55dd3fb61dc0_0 .net "clk", 0 0, v0x55dd3fb3c920_0; alias, 1 drivers +v0x55dd3fb61e60_0 .net "in", 0 0, L_0x55dd3fbdbcb0; alias, 1 drivers +v0x55dd3fb61f70_0 .net "p", 0 0, L_0x55dd3fbdec70; alias, 1 drivers +v0x55dd3fb62030_0 .var "r", 2 0; +v0x55dd3fb62110_0 .net "reset", 0 0, L_0x55dd3fbdf7e0; alias, 1 drivers +L_0x55dd3fbdeb80 .concat [ 3 29 0 0], v0x55dd3fb62030_0, L_0x7fc2ff32d598; +L_0x55dd3fbdec70 .cmp/eq 32, L_0x55dd3fbdeb80, L_0x7fc2ff32d5e0; +S_0x55dd3fb62280 .scope module, "fmc_bd2" "bd" 19 203, 3 49 0, S_0x55dd3fb5fa90; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +v0x55dd3fb624c0_0 .net *"_s0", 31 0, L_0x55dd3fbdedb0; 1 drivers +L_0x7fc2ff32d628 .functor BUFT 1, C4<00000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb625c0_0 .net *"_s3", 28 0, L_0x7fc2ff32d628; 1 drivers +L_0x7fc2ff32d670 .functor BUFT 1, C4<00000000000000000000000000000100>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb626a0_0 .net/2u *"_s4", 31 0, L_0x7fc2ff32d670; 1 drivers +v0x55dd3fb62760_0 .net "clk", 0 0, v0x55dd3fb3c920_0; alias, 1 drivers +v0x55dd3fb62800_0 .net "in", 0 0, L_0x55dd3fbdbcb0; alias, 1 drivers +v0x55dd3fb628f0_0 .net "p", 0 0, L_0x55dd3fbdeea0; alias, 1 drivers +v0x55dd3fb62990_0 .var "r", 2 0; +v0x55dd3fb62a70_0 .net "reset", 0 0, L_0x55dd3fbdf7e0; alias, 1 drivers +L_0x55dd3fbdedb0 .concat [ 3 29 0 0], v0x55dd3fb62990_0, L_0x7fc2ff32d628; +L_0x55dd3fbdeea0 .cmp/eq 32, L_0x55dd3fbdedb0, L_0x7fc2ff32d670; +S_0x55dd3fb62bc0 .scope module, "fmc_dly0" "dly200ns" 19 188, 5 61 0, S_0x55dd3fb5fa90; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +v0x55dd3fb62e50_0 .net *"_s0", 31 0, L_0x55dd3fbddfe0; 1 drivers +L_0x7fc2ff32d2c8 .functor BUFT 1, C4<0000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb62f50_0 .net *"_s3", 27 0, L_0x7fc2ff32d2c8; 1 drivers +L_0x7fc2ff32d310 .functor BUFT 1, C4<00000000000000000000000000001010>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb63030_0 .net/2u *"_s4", 31 0, L_0x7fc2ff32d310; 1 drivers +v0x55dd3fb630f0_0 .net "clk", 0 0, v0x55dd3fb3c920_0; alias, 1 drivers +v0x55dd3fb63190_0 .net "in", 0 0, L_0x55dd3fbde210; 1 drivers +v0x55dd3fb632a0_0 .net "p", 0 0, L_0x55dd3fbde0d0; alias, 1 drivers +v0x55dd3fb63360_0 .var "r", 3 0; +v0x55dd3fb63440_0 .net "reset", 0 0, L_0x55dd3fbdf7e0; alias, 1 drivers +L_0x55dd3fbddfe0 .concat [ 4 28 0 0], v0x55dd3fb63360_0, L_0x7fc2ff32d2c8; +L_0x55dd3fbde0d0 .cmp/eq 32, L_0x55dd3fbddfe0, L_0x7fc2ff32d310; +S_0x55dd3fb635f0 .scope module, "fmc_dly1" "dly50ns" 19 191, 5 1 0, S_0x55dd3fb5fa90; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +v0x55dd3fb637e0_0 .net *"_s0", 31 0, L_0x55dd3fbde280; 1 drivers +L_0x7fc2ff32d358 .functor BUFT 1, C4<000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb638e0_0 .net *"_s3", 29 0, L_0x7fc2ff32d358; 1 drivers +L_0x7fc2ff32d3a0 .functor BUFT 1, C4<00000000000000000000000000000010>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb639c0_0 .net/2u *"_s4", 31 0, L_0x7fc2ff32d3a0; 1 drivers +v0x55dd3fb63ab0_0 .net "clk", 0 0, v0x55dd3fb3c920_0; alias, 1 drivers +v0x55dd3fb63b50_0 .net "in", 0 0, L_0x55dd3fbdad40; alias, 1 drivers +v0x55dd3fb63c60_0 .net "p", 0 0, L_0x55dd3fbde370; alias, 1 drivers +v0x55dd3fb63d20_0 .var "r", 1 0; +v0x55dd3fb63e00_0 .net "reset", 0 0, L_0x55dd3fbdf7e0; alias, 1 drivers +L_0x55dd3fbde280 .concat [ 2 30 0 0], v0x55dd3fb63d20_0, L_0x7fc2ff32d358; +L_0x55dd3fbde370 .cmp/eq 32, L_0x55dd3fbde280, L_0x7fc2ff32d3a0; +S_0x55dd3fb63f20 .scope module, "fmc_dly3" "dly100ns" 19 194, 5 31 0, S_0x55dd3fb5fa90; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +v0x55dd3fb64160_0 .net *"_s0", 31 0, L_0x55dd3fbde4b0; 1 drivers +L_0x7fc2ff32d3e8 .functor BUFT 1, C4<00000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb64260_0 .net *"_s3", 28 0, L_0x7fc2ff32d3e8; 1 drivers +L_0x7fc2ff32d430 .functor BUFT 1, C4<00000000000000000000000000000101>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb64340_0 .net/2u *"_s4", 31 0, L_0x7fc2ff32d430; 1 drivers +v0x55dd3fb64430_0 .net "clk", 0 0, v0x55dd3fb3c920_0; alias, 1 drivers +v0x55dd3fb644d0_0 .net "in", 0 0, L_0x55dd3fbdbcb0; alias, 1 drivers +v0x55dd3fb64610_0 .net "p", 0 0, L_0x55dd3fbde5a0; alias, 1 drivers +v0x55dd3fb646d0_0 .var "r", 2 0; +v0x55dd3fb647b0_0 .net "reset", 0 0, L_0x55dd3fbdf7e0; alias, 1 drivers +L_0x55dd3fbde4b0 .concat [ 3 29 0 0], v0x55dd3fb646d0_0, L_0x7fc2ff32d3e8; +L_0x55dd3fbde5a0 .cmp/eq 32, L_0x55dd3fbde4b0, L_0x7fc2ff32d430; +S_0x55dd3fb648d0 .scope module, "fmc_dly4" "dly50ns" 19 197, 5 1 0, S_0x55dd3fb5fa90; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +v0x55dd3fb64b10_0 .net *"_s0", 31 0, L_0x55dd3fbde720; 1 drivers +L_0x7fc2ff32d478 .functor BUFT 1, C4<000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb64c10_0 .net *"_s3", 29 0, L_0x7fc2ff32d478; 1 drivers +L_0x7fc2ff32d4c0 .functor BUFT 1, C4<00000000000000000000000000000010>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb64cf0_0 .net/2u *"_s4", 31 0, L_0x7fc2ff32d4c0; 1 drivers +v0x55dd3fb64db0_0 .net "clk", 0 0, v0x55dd3fb3c920_0; alias, 1 drivers +v0x55dd3fb64e50_0 .net "in", 0 0, L_0x55dd3fbdce30; alias, 1 drivers +v0x55dd3fb64f60_0 .net "p", 0 0, L_0x55dd3fbde810; alias, 1 drivers +v0x55dd3fb65020_0 .var "r", 1 0; +v0x55dd3fb65100_0 .net "reset", 0 0, L_0x55dd3fbdf7e0; alias, 1 drivers +L_0x55dd3fbde720 .concat [ 2 30 0 0], v0x55dd3fb65020_0, L_0x7fc2ff32d478; +L_0x55dd3fbde810 .cmp/eq 32, L_0x55dd3fbde720, L_0x7fc2ff32d4c0; +S_0x55dd3fb65220 .scope module, "fmc_pa0" "pa" 19 163, 3 31 0, S_0x55dd3fb5fa90; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +L_0x55dd3fbdb4b0 .functor AND 1, L_0x55dd3fbdb230, L_0x55dd3fbdb3c0, C4<1>, C4<1>; +v0x55dd3fb654f0_0 .net *"_s1", 0 0, L_0x55dd3fbdb230; 1 drivers +v0x55dd3fb655f0_0 .net *"_s3", 0 0, L_0x55dd3fbdb2d0; 1 drivers +v0x55dd3fb656d0_0 .net *"_s5", 0 0, L_0x55dd3fbdb3c0; 1 drivers +v0x55dd3fb657a0_0 .net "clk", 0 0, v0x55dd3fb3c920_0; alias, 1 drivers +v0x55dd3fb65840_0 .net "in", 0 0, L_0x55dd3fbdb920; 1 drivers +v0x55dd3fb65900_0 .net "p", 0 0, L_0x55dd3fbdb4b0; alias, 1 drivers +v0x55dd3fb659c0_0 .net "reset", 0 0, L_0x55dd3fbdf7e0; alias, 1 drivers +v0x55dd3fb65a60_0 .var "x", 1 0; +L_0x55dd3fbdb230 .part v0x55dd3fb65a60_0, 0, 1; +L_0x55dd3fbdb2d0 .part v0x55dd3fb65a60_0, 1, 1; +L_0x55dd3fbdb3c0 .reduce/nor L_0x55dd3fbdb2d0; +S_0x55dd3fb65bc0 .scope module, "fmc_pa1" "pa" 19 167, 3 31 0, S_0x55dd3fb5fa90; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +L_0x55dd3fbdbcb0 .functor AND 1, L_0x55dd3fbdba30, L_0x55dd3fbdbbc0, C4<1>, C4<1>; +v0x55dd3fb65e00_0 .net *"_s1", 0 0, L_0x55dd3fbdba30; 1 drivers +v0x55dd3fb65f00_0 .net *"_s3", 0 0, L_0x55dd3fbdbad0; 1 drivers +v0x55dd3fb65fe0_0 .net *"_s5", 0 0, L_0x55dd3fbdbbc0; 1 drivers +v0x55dd3fb660b0_0 .net "clk", 0 0, v0x55dd3fb3c920_0; alias, 1 drivers +v0x55dd3fb66150_0 .net "in", 0 0, L_0x55dd3fbdbdc0; 1 drivers +v0x55dd3fb66260_0 .net "p", 0 0, L_0x55dd3fbdbcb0; alias, 1 drivers +v0x55dd3fb66300_0 .net "reset", 0 0, L_0x55dd3fbdf7e0; alias, 1 drivers +v0x55dd3fb663a0_0 .var "x", 1 0; +L_0x55dd3fbdba30 .part v0x55dd3fb663a0_0, 0, 1; +L_0x55dd3fbdbad0 .part v0x55dd3fb663a0_0, 1, 1; +L_0x55dd3fbdbbc0 .reduce/nor L_0x55dd3fbdbad0; +S_0x55dd3fb66500 .scope module, "fmc_pa2" "pa" 19 170, 3 31 0, S_0x55dd3fb5fa90; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +L_0x55dd3fbdc290 .functor AND 1, L_0x55dd3fbdc060, L_0x55dd3fbdc1a0, C4<1>, C4<1>; +v0x55dd3fb66740_0 .net *"_s1", 0 0, L_0x55dd3fbdc060; 1 drivers +v0x55dd3fb66840_0 .net *"_s3", 0 0, L_0x55dd3fbdc100; 1 drivers +v0x55dd3fb66920_0 .net *"_s5", 0 0, L_0x55dd3fbdc1a0; 1 drivers +v0x55dd3fb669f0_0 .net "clk", 0 0, v0x55dd3fb3c920_0; alias, 1 drivers +v0x55dd3fb66a90_0 .net "in", 0 0, L_0x55dd3fbde370; alias, 1 drivers +v0x55dd3fb66b80_0 .net "p", 0 0, L_0x55dd3fbdc290; alias, 1 drivers +v0x55dd3fb66c20_0 .net "reset", 0 0, L_0x55dd3fbdf7e0; alias, 1 drivers +v0x55dd3fb66cc0_0 .var "x", 1 0; +L_0x55dd3fbdc060 .part v0x55dd3fb66cc0_0, 0, 1; +L_0x55dd3fbdc100 .part v0x55dd3fb66cc0_0, 1, 1; +L_0x55dd3fbdc1a0 .reduce/nor L_0x55dd3fbdc100; +S_0x55dd3fb66e50 .scope module, "fmc_pa3" "pa" 19 173, 3 31 0, S_0x55dd3fb5fa90; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +L_0x55dd3fbdc670 .functor AND 1, L_0x55dd3fbdc3f0, L_0x55dd3fbdc580, C4<1>, C4<1>; +v0x55dd3fb67090_0 .net *"_s1", 0 0, L_0x55dd3fbdc3f0; 1 drivers +v0x55dd3fb67190_0 .net *"_s3", 0 0, L_0x55dd3fbdc490; 1 drivers +v0x55dd3fb67270_0 .net *"_s5", 0 0, L_0x55dd3fbdc580; 1 drivers +v0x55dd3fb67340_0 .net "clk", 0 0, v0x55dd3fb3c920_0; alias, 1 drivers +v0x55dd3fb673e0_0 .net "in", 0 0, L_0x55dd3fbdce30; alias, 1 drivers +v0x55dd3fb674d0_0 .net "p", 0 0, L_0x55dd3fbdc670; alias, 1 drivers +v0x55dd3fb67570_0 .net "reset", 0 0, L_0x55dd3fbdf7e0; alias, 1 drivers +v0x55dd3fb67610_0 .var "x", 1 0; +L_0x55dd3fbdc3f0 .part v0x55dd3fb67610_0, 0, 1; +L_0x55dd3fbdc490 .part v0x55dd3fb67610_0, 1, 1; +L_0x55dd3fbdc580 .reduce/nor L_0x55dd3fbdc490; +S_0x55dd3fb677a0 .scope module, "fmc_pa4" "pa" 19 176, 3 31 0, S_0x55dd3fb5fa90; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +L_0x55dd3fbdca50 .functor AND 1, L_0x55dd3fbdc7d0, L_0x55dd3fbdc960, C4<1>, C4<1>; +v0x55dd3fb679e0_0 .net *"_s1", 0 0, L_0x55dd3fbdc7d0; 1 drivers +v0x55dd3fb67ae0_0 .net *"_s3", 0 0, L_0x55dd3fbdc870; 1 drivers +v0x55dd3fb67bc0_0 .net *"_s5", 0 0, L_0x55dd3fbdc960; 1 drivers +v0x55dd3fb67c90_0 .net "clk", 0 0, v0x55dd3fb3c920_0; alias, 1 drivers +v0x55dd3fb67d30_0 .net "in", 0 0, L_0x55dd3fbde810; alias, 1 drivers +v0x55dd3fb67e20_0 .net "p", 0 0, L_0x55dd3fbdca50; alias, 1 drivers +v0x55dd3fb67ec0_0 .net "reset", 0 0, L_0x55dd3fbdf7e0; alias, 1 drivers +v0x55dd3fb67f60_0 .var "x", 1 0; +L_0x55dd3fbdc7d0 .part v0x55dd3fb67f60_0, 0, 1; +L_0x55dd3fbdc870 .part v0x55dd3fb67f60_0, 1, 1; +L_0x55dd3fbdc960 .reduce/nor L_0x55dd3fbdc870; +S_0x55dd3fb680f0 .scope module, "fmc_pa6" "pa" 19 183, 3 31 0, S_0x55dd3fb5fa90; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +L_0x55dd3fbdd980 .functor AND 1, L_0x55dd3fbdd700, L_0x55dd3fbdd890, C4<1>, C4<1>; +v0x55dd3fb68330_0 .net *"_s1", 0 0, L_0x55dd3fbdd700; 1 drivers +v0x55dd3fb68430_0 .net *"_s3", 0 0, L_0x55dd3fbdd7a0; 1 drivers +v0x55dd3fb68510_0 .net *"_s5", 0 0, L_0x55dd3fbdd890; 1 drivers +v0x55dd3fb685e0_0 .net "clk", 0 0, v0x55dd3fb3c920_0; alias, 1 drivers +v0x55dd3fb68680_0 .net "in", 0 0, L_0x55dd3fbddd40; 1 drivers +v0x55dd3fb68790_0 .net "p", 0 0, L_0x55dd3fbdd980; alias, 1 drivers +v0x55dd3fb68850_0 .net "reset", 0 0, L_0x55dd3fbdf7e0; alias, 1 drivers +v0x55dd3fb688f0_0 .var "x", 1 0; +L_0x55dd3fbdd700 .part v0x55dd3fb688f0_0, 0, 1; +L_0x55dd3fbdd7a0 .part v0x55dd3fb688f0_0, 1, 1; +L_0x55dd3fbdd890 .reduce/nor L_0x55dd3fbdd7a0; +S_0x55dd3fb68a50 .scope module, "fmc_pg0" "pg" 19 156, 3 15 0, S_0x55dd3fb5fa90; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +L_0x55dd3fbda050 .functor AND 1, L_0x55dd3fbd99f0, L_0x55dd3fbd9fb0, C4<1>, C4<1>; +v0x55dd3fb68c90_0 .net *"_s1", 0 0, L_0x55dd3fbd99f0; 1 drivers +v0x55dd3fb68d90_0 .net *"_s3", 0 0, L_0x55dd3fbd9ec0; 1 drivers +v0x55dd3fb68e70_0 .net *"_s5", 0 0, L_0x55dd3fbd9fb0; 1 drivers +v0x55dd3fb68f40_0 .net "clk", 0 0, v0x55dd3fb3c920_0; alias, 1 drivers +v0x55dd3fb68fe0_0 .net "in", 0 0, L_0x7fc2ff32d748; alias, 1 drivers +v0x55dd3fb690f0_0 .net "p", 0 0, L_0x55dd3fbda050; alias, 1 drivers +v0x55dd3fb691b0_0 .net "reset", 0 0, L_0x55dd3fbdf7e0; alias, 1 drivers +v0x55dd3fb69250_0 .var "x", 1 0; +L_0x55dd3fbd99f0 .part v0x55dd3fb69250_0, 0, 1; +L_0x55dd3fbd9ec0 .part v0x55dd3fb69250_0, 1, 1; +L_0x55dd3fbd9fb0 .reduce/nor L_0x55dd3fbd9ec0; +S_0x55dd3fb693b0 .scope module, "fmc_pg1" "pg" 19 157, 3 15 0, S_0x55dd3fb5fa90; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +L_0x55dd3fbda3e0 .functor AND 1, L_0x55dd3fbda160, L_0x55dd3fbda2f0, C4<1>, C4<1>; +v0x55dd3fb695f0_0 .net *"_s1", 0 0, L_0x55dd3fbda160; 1 drivers +v0x55dd3fb696f0_0 .net *"_s3", 0 0, L_0x55dd3fbda200; 1 drivers +v0x55dd3fb697d0_0 .net *"_s5", 0 0, L_0x55dd3fbda2f0; 1 drivers +v0x55dd3fb698a0_0 .net "clk", 0 0, v0x55dd3fb3c920_0; alias, 1 drivers +v0x55dd3fb69940_0 .net "in", 0 0, L_0x55dd3fbda540; 1 drivers +v0x55dd3fb69a50_0 .net "p", 0 0, L_0x55dd3fbda3e0; alias, 1 drivers +v0x55dd3fb69b10_0 .net "reset", 0 0, L_0x55dd3fbdf7e0; alias, 1 drivers +v0x55dd3fb69bb0_0 .var "x", 1 0; +L_0x55dd3fbda160 .part v0x55dd3fb69bb0_0, 0, 1; +L_0x55dd3fbda200 .part v0x55dd3fb69bb0_0, 1, 1; +L_0x55dd3fbda2f0 .reduce/nor L_0x55dd3fbda200; +S_0x55dd3fb69d10 .scope module, "fmc_pg2" "pg" 19 159, 3 15 0, S_0x55dd3fb5fa90; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +L_0x55dd3fbda9b0 .functor AND 1, L_0x55dd3fbda730, L_0x55dd3fbda8c0, C4<1>, C4<1>; +v0x55dd3fb69f50_0 .net *"_s1", 0 0, L_0x55dd3fbda730; 1 drivers +v0x55dd3fb6a050_0 .net *"_s3", 0 0, L_0x55dd3fbda7d0; 1 drivers +v0x55dd3fb6a130_0 .net *"_s5", 0 0, L_0x55dd3fbda8c0; 1 drivers +v0x55dd3fb6a200_0 .net "clk", 0 0, v0x55dd3fb3c920_0; alias, 1 drivers +v0x55dd3fb6a2a0_0 .net "in", 0 0, v0x55dd3fb700c0_0; 1 drivers +v0x55dd3fb6a3b0_0 .net "p", 0 0, L_0x55dd3fbda9b0; alias, 1 drivers +v0x55dd3fb6a450_0 .net "reset", 0 0, L_0x55dd3fbdf7e0; alias, 1 drivers +v0x55dd3fb6a700_0 .var "x", 1 0; +L_0x55dd3fbda730 .part v0x55dd3fb6a700_0, 0, 1; +L_0x55dd3fbda7d0 .part v0x55dd3fb6a700_0, 1, 1; +L_0x55dd3fbda8c0 .reduce/nor L_0x55dd3fbda7d0; +S_0x55dd3fb6a870 .scope module, "fmc_pg3" "pg" 19 160, 3 15 0, S_0x55dd3fb5fa90; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +L_0x55dd3fbdad40 .functor AND 1, L_0x55dd3fbdaac0, L_0x55dd3fbdac50, C4<1>, C4<1>; +v0x55dd3fb6aab0_0 .net *"_s1", 0 0, L_0x55dd3fbdaac0; 1 drivers +v0x55dd3fb6abb0_0 .net *"_s3", 0 0, L_0x55dd3fbdab60; 1 drivers +v0x55dd3fb6ac90_0 .net *"_s5", 0 0, L_0x55dd3fbdac50; 1 drivers +v0x55dd3fb6ad60_0 .net "clk", 0 0, v0x55dd3fb3c920_0; alias, 1 drivers +v0x55dd3fb6ae00_0 .net "in", 0 0, L_0x55dd3fbd63d0; alias, 1 drivers +v0x55dd3fb6af10_0 .net "p", 0 0, L_0x55dd3fbdad40; alias, 1 drivers +v0x55dd3fb6afb0_0 .net "reset", 0 0, L_0x55dd3fbdf7e0; alias, 1 drivers +v0x55dd3fb6b050_0 .var "x", 1 0; +L_0x55dd3fbdaac0 .part v0x55dd3fb6b050_0, 0, 1; +L_0x55dd3fbdab60 .part v0x55dd3fb6b050_0, 1, 1; +L_0x55dd3fbdac50 .reduce/nor L_0x55dd3fbdab60; +S_0x55dd3fb6b1c0 .scope module, "fmc_pg5" "pg" 19 179, 3 15 0, S_0x55dd3fb5fa90; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +L_0x55dd3fbdce30 .functor AND 1, L_0x55dd3fbdcbb0, L_0x55dd3fbdcd40, C4<1>, C4<1>; +v0x55dd3fb6b400_0 .net *"_s1", 0 0, L_0x55dd3fbdcbb0; 1 drivers +v0x55dd3fb6b500_0 .net *"_s3", 0 0, L_0x55dd3fbdcc50; 1 drivers +v0x55dd3fb6b5e0_0 .net *"_s5", 0 0, L_0x55dd3fbdcd40; 1 drivers +v0x55dd3fb6b6b0_0 .net "clk", 0 0, v0x55dd3fb3c920_0; alias, 1 drivers +v0x55dd3fb6b750_0 .net "in", 0 0, L_0x55dd3fbdd5f0; 1 drivers +v0x55dd3fb6b860_0 .net "p", 0 0, L_0x55dd3fbdce30; alias, 1 drivers +v0x55dd3fb6b950_0 .net "reset", 0 0, L_0x55dd3fbdf7e0; alias, 1 drivers +v0x55dd3fb6b9f0_0 .var "x", 1 0; +L_0x55dd3fbdcbb0 .part v0x55dd3fb6b9f0_0, 0, 1; +L_0x55dd3fbdcc50 .part v0x55dd3fb6b9f0_0, 1, 1; +L_0x55dd3fbdcd40 .reduce/nor L_0x55dd3fbdcc50; +S_0x55dd3fb75350 .scope module, "membusif0" "membusif" 16 32, 20 1 0, S_0x55dd3fa340e0; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 2 "s_address" + .port_info 3 /INPUT 1 "s_write" + .port_info 4 /INPUT 1 "s_read" + .port_info 5 /INPUT 32 "s_writedata" + .port_info 6 /OUTPUT 32 "s_readdata" + .port_info 7 /OUTPUT 1 "s_waitrequest" + .port_info 8 /OUTPUT 1 "m_rq_cyc" + .port_info 9 /OUTPUT 1 "m_rd_rq" + .port_info 10 /OUTPUT 1 "m_wr_rq" + .port_info 11 /OUTPUT 15 "m_ma" + .port_info 12 /OUTPUT 4 "m_sel" + .port_info 13 /OUTPUT 1 "m_fmc_select" + .port_info 14 /OUTPUT 36 "m_mb_write" + .port_info 15 /OUTPUT 1 "m_wr_rs" + .port_info 16 /INPUT 36 "m_mb_read" + .port_info 17 /INPUT 1 "m_addr_ack" + .port_info 18 /INPUT 1 "m_rd_rs" +L_0x55dd3fbbeb50 .functor OR 1, L_0x55dd3fbbe910, L_0x55dd3fbbea40, C4<0>, C4<0>; +L_0x55dd3fbbed00 .functor AND 1, L_0x55dd3fbbeb50, L_0x55dd3fbbebc0, C4<1>, C4<1>; +L_0x55dd3fbbee10 .functor OR 1, L_0x55dd3fbbed00, v0x55dd3fb7a000_0, C4<0>, C4<0>; +L_0x55dd3fbbef70 .functor OR 1, L_0x55dd3fbbee10, L_0x55dd3fbbeed0, C4<0>, C4<0>; +L_0x55dd3fbbf100 .functor AND 1, L_0x55dd3fbbe3d0, v0x55dd3fb796d0_0, C4<1>, C4<1>; +L_0x55dd3fbbf3e0 .functor NOT 1, v0x55dd3fb3ca00_0, C4<0>, C4<0>, C4<0>; +L_0x55dd3fbc01e0 .functor NOT 1, v0x55dd3fb3ca00_0, C4<0>, C4<0>, C4<0>; +v0x55dd3fb786e0_0 .net *"_s12", 0 0, L_0x55dd3fbbee10; 1 drivers +v0x55dd3fb787e0_0 .net *"_s15", 0 0, L_0x55dd3fbbeed0; 1 drivers +L_0x7fc2ff32b8e8 .functor BUFT 1, C4<000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb788a0_0 .net/2u *"_s24", 35 0, L_0x7fc2ff32b8e8; 1 drivers +v0x55dd3fb78960_0 .net *"_s4", 0 0, L_0x55dd3fbbeb50; 1 drivers +L_0x7fc2ff32b5d0 .functor BUFT 1, C4<10>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb78a40_0 .net/2u *"_s6", 1 0, L_0x7fc2ff32b5d0; 1 drivers +v0x55dd3fb78b70_0 .net *"_s8", 0 0, L_0x55dd3fbbebc0; 1 drivers +v0x55dd3fb78c30_0 .var "addr", 0 17; +v0x55dd3fb78d10_0 .net "clk", 0 0, v0x55dd3fb3c920_0; alias, 1 drivers +v0x55dd3fb78db0_0 .net "m_addr_ack", 0 0, L_0x55dd3fbbe3d0; alias, 1 drivers +v0x55dd3fb78e70_0 .var "m_fmc_select", 0 0; +v0x55dd3fb78f10_0 .net "m_ma", 21 35, L_0x55dd3fbbe640; alias, 1 drivers +v0x55dd3fb79020_0 .net "m_mb_read", 0 35, L_0x55dd3fbbe270; alias, 1 drivers +v0x55dd3fb79100_0 .net "m_mb_write", 0 35, L_0x55dd3fbc0250; alias, 1 drivers +v0x55dd3fb79210_0 .var "m_rd_rq", 0 0; +v0x55dd3fb79300_0 .net "m_rd_rs", 0 0, L_0x55dd3fbbe4e0; alias, 1 drivers +v0x55dd3fb793c0_0 .var "m_rq_cyc", 0 0; +v0x55dd3fb794b0_0 .net "m_sel", 18 21, L_0x55dd3fbbe770; alias, 1 drivers +v0x55dd3fb796d0_0 .var "m_wr_rq", 0 0; +v0x55dd3fb797c0_0 .net "m_wr_rs", 0 0, L_0x55dd3fbbf2a0; alias, 1 drivers +v0x55dd3fb79860_0 .net "mb_write_pulse", 0 0, L_0x55dd3fbc0080; 1 drivers +v0x55dd3fb79900_0 .net "read_edge", 0 0, L_0x55dd3fbbea40; 1 drivers +v0x55dd3fb799a0_0 .net "req", 0 0, L_0x55dd3fbbed00; 1 drivers +v0x55dd3fb79a40_0 .net "reset", 0 0, v0x55dd3fb3ca00_0; alias, 1 drivers +v0x55dd3fb79ae0_0 .net "s_address", 1 0, v0x55dd3fb75570_0; 1 drivers +v0x55dd3fb79ba0_0 .net "s_read", 0 0, v0x55dd3fb7a600_0; 1 drivers +v0x55dd3fb79c40_0 .var "s_readdata", 31 0; +v0x55dd3fb79d00_0 .net "s_waitrequest", 0 0, L_0x55dd3fbbef70; alias, 1 drivers +v0x55dd3fb79dc0_0 .net "s_write", 0 0, v0x55dd3fb7a830_0; 1 drivers +v0x55dd3fb79e60_0 .net "s_writedata", 31 0, v0x55dd3fb7a970_0; 1 drivers +v0x55dd3fb79f20_0 .var "waitcyc", 7 0; +v0x55dd3fb7a000_0 .var "waiting", 0 0; +v0x55dd3fb7a0c0_0 .var "word", 0 35; +v0x55dd3fb7a1a0_0 .net "wr_rs", 0 0, L_0x55dd3fbbf100; 1 drivers +v0x55dd3fb7a240_0 .net "write_edge", 0 0, L_0x55dd3fbbe910; 1 drivers +E_0x55dd3fb75610 .event edge, v0x55dd3fb79ae0_0, v0x55dd3fb7a0c0_0; +L_0x55dd3fbbe640 .part v0x55dd3fb78c30_0, 0, 15; +L_0x55dd3fbbe770 .part v0x55dd3fb78c30_0, 14, 4; +L_0x55dd3fbbebc0 .cmp/eq 2, v0x55dd3fb75570_0, L_0x7fc2ff32b5d0; +L_0x55dd3fbbeed0 .reduce/or v0x55dd3fb79f20_0; +L_0x55dd3fbc0250 .functor MUXZ 36, L_0x7fc2ff32b8e8, v0x55dd3fb7a0c0_0, L_0x55dd3fbc0080, C4<>; +S_0x55dd3fb75690 .scope module, "e0" "edgedet" 20 33, 8 16 0, S_0x55dd3fb75350; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "signal" + .port_info 3 /OUTPUT 1 "p" +L_0x55dd3fbbe8a0 .functor NOT 1, v0x55dd3fb75b30_0, C4<0>, C4<0>, C4<0>; +L_0x55dd3fbbe910 .functor AND 1, v0x55dd3fb7a830_0, L_0x55dd3fbbe8a0, C4<1>, C4<1>; +v0x55dd3fb75970_0 .net *"_s0", 0 0, L_0x55dd3fbbe8a0; 1 drivers +v0x55dd3fb75a70_0 .net "clk", 0 0, v0x55dd3fb3c920_0; alias, 1 drivers +v0x55dd3fb75b30_0 .var "last", 0 0; +v0x55dd3fb75c00_0 .net "p", 0 0, L_0x55dd3fbbe910; alias, 1 drivers +v0x55dd3fb75ca0_0 .net "reset", 0 0, v0x55dd3fb3ca00_0; alias, 1 drivers +v0x55dd3fb75de0_0 .net "signal", 0 0, v0x55dd3fb7a830_0; alias, 1 drivers +E_0x55dd3fb758f0/0 .event negedge, v0x55dd3fb3ca00_0; +E_0x55dd3fb758f0/1 .event posedge, v0x55dd3fb3c920_0; +E_0x55dd3fb758f0 .event/or E_0x55dd3fb758f0/0, E_0x55dd3fb758f0/1; +S_0x55dd3fb75f20 .scope module, "e1" "edgedet" 20 34, 8 16 0, S_0x55dd3fb75350; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "signal" + .port_info 3 /OUTPUT 1 "p" +L_0x55dd3fbbe9d0 .functor NOT 1, v0x55dd3fb76320_0, C4<0>, C4<0>, C4<0>; +L_0x55dd3fbbea40 .functor AND 1, v0x55dd3fb7a600_0, L_0x55dd3fbbe9d0, C4<1>, C4<1>; +v0x55dd3fb76180_0 .net *"_s0", 0 0, L_0x55dd3fbbe9d0; 1 drivers +v0x55dd3fb76260_0 .net "clk", 0 0, v0x55dd3fb3c920_0; alias, 1 drivers +v0x55dd3fb76320_0 .var "last", 0 0; +v0x55dd3fb763c0_0 .net "p", 0 0, L_0x55dd3fbbea40; alias, 1 drivers +v0x55dd3fb76460_0 .net "reset", 0 0, v0x55dd3fb3ca00_0; alias, 1 drivers +v0x55dd3fb76550_0 .net "signal", 0 0, v0x55dd3fb7a600_0; alias, 1 drivers +S_0x55dd3fb76690 .scope module, "mb_bd1" "bd2" 20 43, 3 68 0, S_0x55dd3fb75350; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +L_0x55dd3fbbf930 .functor OR 1, L_0x55dd3fbbf540, L_0x55dd3fbbf7c0, C4<0>, C4<0>; +L_0x55dd3fbbfcb0 .functor OR 1, L_0x55dd3fbbf930, L_0x55dd3fbbfb30, C4<0>, C4<0>; +L_0x55dd3fbc0080 .functor OR 1, L_0x55dd3fbbfcb0, L_0x55dd3fbbfef0, C4<0>, C4<0>; +v0x55dd3fb76960_0 .net *"_s0", 31 0, L_0x55dd3fbbf450; 1 drivers +L_0x7fc2ff32b738 .functor BUFT 1, C4<00000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb76a60_0 .net *"_s11", 28 0, L_0x7fc2ff32b738; 1 drivers +L_0x7fc2ff32b780 .functor BUFT 1, C4<00000000000000000000000000000101>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb76b40_0 .net/2u *"_s12", 31 0, L_0x7fc2ff32b780; 1 drivers +v0x55dd3fb76c30_0 .net *"_s14", 0 0, L_0x55dd3fbbf7c0; 1 drivers +v0x55dd3fb76cf0_0 .net *"_s16", 0 0, L_0x55dd3fbbf930; 1 drivers +v0x55dd3fb76e00_0 .net *"_s18", 31 0, L_0x55dd3fbbfa40; 1 drivers +L_0x7fc2ff32b7c8 .functor BUFT 1, C4<00000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb76ee0_0 .net *"_s21", 28 0, L_0x7fc2ff32b7c8; 1 drivers +L_0x7fc2ff32b810 .functor BUFT 1, C4<00000000000000000000000000000110>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb76fc0_0 .net/2u *"_s22", 31 0, L_0x7fc2ff32b810; 1 drivers +v0x55dd3fb770a0_0 .net *"_s24", 0 0, L_0x55dd3fbbfb30; 1 drivers +v0x55dd3fb77160_0 .net *"_s26", 0 0, L_0x55dd3fbbfcb0; 1 drivers +v0x55dd3fb77220_0 .net *"_s28", 31 0, L_0x55dd3fbbfdc0; 1 drivers +L_0x7fc2ff32b6a8 .functor BUFT 1, C4<00000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb77300_0 .net *"_s3", 28 0, L_0x7fc2ff32b6a8; 1 drivers +L_0x7fc2ff32b858 .functor BUFT 1, C4<00000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb773e0_0 .net *"_s31", 28 0, L_0x7fc2ff32b858; 1 drivers +L_0x7fc2ff32b8a0 .functor BUFT 1, C4<00000000000000000000000000000111>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb774c0_0 .net/2u *"_s32", 31 0, L_0x7fc2ff32b8a0; 1 drivers +v0x55dd3fb775a0_0 .net *"_s34", 0 0, L_0x55dd3fbbfef0; 1 drivers +L_0x7fc2ff32b6f0 .functor BUFT 1, C4<00000000000000000000000000000100>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb77660_0 .net/2u *"_s4", 31 0, L_0x7fc2ff32b6f0; 1 drivers +v0x55dd3fb77740_0 .net *"_s6", 0 0, L_0x55dd3fbbf540; 1 drivers +v0x55dd3fb77800_0 .net *"_s8", 31 0, L_0x55dd3fbbf680; 1 drivers +v0x55dd3fb778e0_0 .net "clk", 0 0, v0x55dd3fb3c920_0; alias, 1 drivers +v0x55dd3fb77980_0 .net "in", 0 0, L_0x55dd3fbbf100; alias, 1 drivers +v0x55dd3fb77a40_0 .net "p", 0 0, L_0x55dd3fbc0080; alias, 1 drivers +v0x55dd3fb77b00_0 .var "r", 2 0; +v0x55dd3fb77be0_0 .net "reset", 0 0, L_0x55dd3fbc01e0; 1 drivers +E_0x55dd3fb76900 .event posedge, v0x55dd3fb77be0_0, v0x55dd3fb3c920_0; +L_0x55dd3fbbf450 .concat [ 3 29 0 0], v0x55dd3fb77b00_0, L_0x7fc2ff32b6a8; +L_0x55dd3fbbf540 .cmp/eq 32, L_0x55dd3fbbf450, L_0x7fc2ff32b6f0; +L_0x55dd3fbbf680 .concat [ 3 29 0 0], v0x55dd3fb77b00_0, L_0x7fc2ff32b738; +L_0x55dd3fbbf7c0 .cmp/eq 32, L_0x55dd3fbbf680, L_0x7fc2ff32b780; +L_0x55dd3fbbfa40 .concat [ 3 29 0 0], v0x55dd3fb77b00_0, L_0x7fc2ff32b7c8; +L_0x55dd3fbbfb30 .cmp/eq 32, L_0x55dd3fbbfa40, L_0x7fc2ff32b810; +L_0x55dd3fbbfdc0 .concat [ 3 29 0 0], v0x55dd3fb77b00_0, L_0x7fc2ff32b858; +L_0x55dd3fbbfef0 .cmp/eq 32, L_0x55dd3fbbfdc0, L_0x7fc2ff32b8a0; +S_0x55dd3fb77d20 .scope module, "mc_bd0" "bd" 20 42, 3 49 0, S_0x55dd3fb75350; + .timescale -9 -9; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 1 "reset" + .port_info 2 /INPUT 1 "in" + .port_info 3 /OUTPUT 1 "p" +v0x55dd3fb77f90_0 .net *"_s0", 31 0, L_0x55dd3fbbf200; 1 drivers +L_0x7fc2ff32b618 .functor BUFT 1, C4<00000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb78090_0 .net *"_s3", 28 0, L_0x7fc2ff32b618; 1 drivers +L_0x7fc2ff32b660 .functor BUFT 1, C4<00000000000000000000000000000100>, C4<0>, C4<0>, C4<0>; +v0x55dd3fb78170_0 .net/2u *"_s4", 31 0, L_0x7fc2ff32b660; 1 drivers +v0x55dd3fb78260_0 .net "clk", 0 0, v0x55dd3fb3c920_0; alias, 1 drivers +v0x55dd3fb78300_0 .net "in", 0 0, L_0x55dd3fbbf100; alias, 1 drivers +v0x55dd3fb783f0_0 .net "p", 0 0, L_0x55dd3fbbf2a0; alias, 1 drivers +v0x55dd3fb784e0_0 .var "r", 2 0; +v0x55dd3fb785a0_0 .net "reset", 0 0, L_0x55dd3fbbf3e0; 1 drivers +E_0x55dd3fb77f10 .event posedge, v0x55dd3fb785a0_0, v0x55dd3fb3c920_0; +L_0x55dd3fbbf200 .concat [ 3 29 0 0], v0x55dd3fb784e0_0, L_0x7fc2ff32b618; +L_0x55dd3fbbf2a0 .cmp/eq 32, L_0x55dd3fbbf200, L_0x7fc2ff32b660; + .scope S_0x55dd3fa50bf0; +T_0 ; + %wait E_0x55dd3f6b7f80; + %load/vec4 v0x55dd3f958ef0_0; + %inv; + %flag_set/vec4 8; + %jmp/0xz T_0.0, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3faa68b0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3faa69b0_0, 0; + %jmp T_0.1; +T_0.0 ; + %load/vec4 v0x55dd3faa68b0_0; + %load/vec4 v0x55dd3f950880_0; + %inv; + %and; + %load/vec4 v0x55dd3faa69b0_0; + %load/vec4 v0x55dd3f950980_0; + %inv; + %and; + %or; + %flag_set/vec4 8; + %jmp/0xz T_0.2, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3faa68b0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3faa69b0_0, 0; + %jmp T_0.3; +T_0.2 ; + %load/vec4 v0x55dd3f952420_0; + %inv; + %flag_set/vec4 8; + %jmp/0xz T_0.4, 8; + %load/vec4 v0x55dd3f950880_0; + %flag_set/vec4 8; + %jmp/0xz T_0.6, 8; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x55dd3faa68b0_0, 0; + %jmp T_0.7; +T_0.6 ; + %load/vec4 v0x55dd3f950980_0; + %flag_set/vec4 8; + %jmp/0xz T_0.8, 8; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x55dd3faa69b0_0, 0; +T_0.8 ; +T_0.7 ; +T_0.4 ; +T_0.3 ; +T_0.1 ; + %jmp T_0; + .thread T_0; + .scope S_0x55dd3fa50bf0; +T_1 ; + %wait E_0x55dd3f6b5ad0; + %load/vec4 v0x55dd3faa68b0_0; + %flag_set/vec4 8; + %jmp/0xz T_1.0, 8; + %load/vec4 v0x55dd3f957460_0; + %assign/vec4 v0x55dd3f94edb0_0, 0; + %load/vec4 v0x55dd3faad370_0; + %assign/vec4 v0x55dd3fa17bf0_0, 0; + %load/vec4 v0x55dd3fab08d0_0; + %assign/vec4 v0x55dd3f94eeb0_0, 0; + %load/vec4 v0x55dd3faad470_0; + %assign/vec4 v0x55dd3fabd980_0, 0; + %load/vec4 v0x55dd3f6cba40_0; + %assign/vec4 v0x55dd3fab09d0_0, 0; + %load/vec4 v0x55dd3fafc2b0_0; + %assign/vec4 v0x55dd3faaef30_0, 0; + %pushi/vec4 0, 0, 36; + %assign/vec4 v0x55dd3faa9df0_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x55dd3faa9ef0_0, 0; + %jmp T_1.1; +T_1.0 ; + %load/vec4 v0x55dd3faa69b0_0; + %flag_set/vec4 8; + %jmp/0xz T_1.2, 8; + %load/vec4 v0x55dd3faab8c0_0; + %assign/vec4 v0x55dd3f94edb0_0, 0; + %load/vec4 v0x55dd3faa8350_0; + %assign/vec4 v0x55dd3fa17bf0_0, 0; + %load/vec4 v0x55dd3faab9c0_0; + %assign/vec4 v0x55dd3f94eeb0_0, 0; + %load/vec4 v0x55dd3faa8450_0; + %assign/vec4 v0x55dd3fabd980_0, 0; + %load/vec4 v0x55dd3f6cba40_0; + %assign/vec4 v0x55dd3faa9df0_0, 0; + %load/vec4 v0x55dd3fafc2b0_0; + %assign/vec4 v0x55dd3faa9ef0_0, 0; + %pushi/vec4 0, 0, 36; + %assign/vec4 v0x55dd3fab09d0_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x55dd3faaef30_0, 0; + %jmp T_1.3; +T_1.2 ; + %pushi/vec4 0, 0, 18; + %assign/vec4 v0x55dd3f94edb0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fa17bf0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3f94eeb0_0, 0; + %pushi/vec4 0, 0, 36; + %assign/vec4 v0x55dd3fabd980_0, 0; + %pushi/vec4 0, 0, 36; + %assign/vec4 v0x55dd3fab09d0_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x55dd3faaef30_0, 0; + %pushi/vec4 0, 0, 36; + %assign/vec4 v0x55dd3faa9df0_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x55dd3faa9ef0_0, 0; +T_1.3 ; +T_1.1 ; + %jmp T_1; + .thread T_1, $push; + .scope S_0x55dd3fafd030; +T_2 ; + %pushi/vec4 0, 0, 30; + %store/vec4 v0x55dd3fa82500_0, 0, 30; + %end; + .thread T_2; + .scope S_0x55dd3fafd030; +T_3 ; + %wait E_0x55dd3f6b8090; + %load/vec4 v0x55dd3fa80360_0; + %flag_set/vec4 8; + %jmp/0xz T_3.0, 8; + %pushi/vec4 0, 0, 30; + %assign/vec4 v0x55dd3fa82500_0, 0; + %jmp T_3.1; +T_3.0 ; + %load/vec4 v0x55dd3fa82500_0; + %addi 1, 0, 30; + %assign/vec4 v0x55dd3fa82500_0, 0; +T_3.1 ; + %jmp T_3; + .thread T_3; + .scope S_0x55dd3f995830; +T_4 ; + %wait E_0x55dd3fb0e940; + %load/vec4 v0x55dd3f9dfaf0_0; + %flag_set/vec4 8; + %jmp/0xz T_4.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x55dd3f9dd170_0, 0; + %jmp T_4.1; +T_4.0 ; + %load/vec4 v0x55dd3f9dd170_0; + %parti/s 1, 0, 2; + %load/vec4 v0x55dd3f9dfe00_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x55dd3f9dd170_0, 0; +T_4.1 ; + %jmp T_4; + .thread T_4; + .scope S_0x55dd3f9c5d80; +T_5 ; + %wait E_0x55dd3fb0e940; + %load/vec4 v0x55dd3f9dbb80_0; + %flag_set/vec4 8; + %jmp/0xz T_5.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x55dd3f9d6e80_0, 0; + %jmp T_5.1; +T_5.0 ; + %load/vec4 v0x55dd3f9d6e80_0; + %parti/s 1, 0, 2; + %load/vec4 v0x55dd3f9de490_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x55dd3f9d6e80_0, 0; +T_5.1 ; + %jmp T_5; + .thread T_5; + .scope S_0x55dd3f9c7880; +T_6 ; + %wait E_0x55dd3fb0e940; + %load/vec4 v0x55dd3f96fd10_0; + %flag_set/vec4 8; + %jmp/0xz T_6.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x55dd3f91eab0_0, 0; + %jmp T_6.1; +T_6.0 ; + %load/vec4 v0x55dd3f91eab0_0; + %parti/s 1, 0, 2; + %load/vec4 v0x55dd3f98a4b0_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x55dd3f91eab0_0, 0; +T_6.1 ; + %jmp T_6; + .thread T_6; + .scope S_0x55dd3f9c92b0; +T_7 ; + %wait E_0x55dd3fb0e940; + %load/vec4 v0x55dd3f96a3c0_0; + %flag_set/vec4 8; + %jmp/0xz T_7.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x55dd3f922430_0, 0; + %jmp T_7.1; +T_7.0 ; + %load/vec4 v0x55dd3f922430_0; + %parti/s 1, 0, 2; + %load/vec4 v0x55dd3f9167d0_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x55dd3f922430_0, 0; +T_7.1 ; + %jmp T_7; + .thread T_7; + .scope S_0x55dd3f95d140; +T_8 ; + %wait E_0x55dd3fb0e940; + %load/vec4 v0x55dd3f91fd90_0; + %flag_set/vec4 8; + %jmp/0xz T_8.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x55dd3f91ef20_0, 0; + %jmp T_8.1; +T_8.0 ; + %load/vec4 v0x55dd3f91ef20_0; + %parti/s 1, 0, 2; + %load/vec4 v0x55dd3f9201b0_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x55dd3f91ef20_0, 0; +T_8.1 ; + %jmp T_8; + .thread T_8; + .scope S_0x55dd3f9670e0; +T_9 ; + %wait E_0x55dd3fb0e940; + %load/vec4 v0x55dd3f963cd0_0; + %flag_set/vec4 8; + %jmp/0xz T_9.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x55dd3f962110_0, 0; + %jmp T_9.1; +T_9.0 ; + %load/vec4 v0x55dd3f962110_0; + %parti/s 1, 0, 2; + %load/vec4 v0x55dd3f965640_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x55dd3f962110_0, 0; +T_9.1 ; + %jmp T_9; + .thread T_9; + .scope S_0x55dd3f9d6650; +T_10 ; + %wait E_0x55dd3fb0e940; + %load/vec4 v0x55dd3fa92ee0_0; + %flag_set/vec4 8; + %jmp/0xz T_10.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x55dd3fa92f80_0, 0; + %jmp T_10.1; +T_10.0 ; + %load/vec4 v0x55dd3fa92f80_0; + %parti/s 1, 0, 2; + %load/vec4 v0x55dd3fa8ea30_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x55dd3fa92f80_0, 0; +T_10.1 ; + %jmp T_10; + .thread T_10; + .scope S_0x55dd3fa18990; +T_11 ; + %wait E_0x55dd3fb0e940; + %load/vec4 v0x55dd3fae99f0_0; + %flag_set/vec4 8; + %jmp/0xz T_11.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x55dd3fae9a90_0, 0; + %jmp T_11.1; +T_11.0 ; + %load/vec4 v0x55dd3fae9a90_0; + %parti/s 1, 0, 2; + %load/vec4 v0x55dd3fa7e3f0_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x55dd3fae9a90_0, 0; +T_11.1 ; + %jmp T_11; + .thread T_11; + .scope S_0x55dd3f9bf2a0; +T_12 ; + %wait E_0x55dd3fb0e940; + %load/vec4 v0x55dd3f99f8d0_0; + %flag_set/vec4 8; + %jmp/0xz T_12.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x55dd3f989d20_0, 0; + %jmp T_12.1; +T_12.0 ; + %load/vec4 v0x55dd3f989d20_0; + %parti/s 1, 0, 2; + %load/vec4 v0x55dd3f9a1630_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x55dd3f989d20_0, 0; +T_12.1 ; + %jmp T_12; + .thread T_12; + .scope S_0x55dd3f9c0d70; +T_13 ; + %wait E_0x55dd3fb0e940; + %load/vec4 v0x55dd3f92e640_0; + %flag_set/vec4 8; + %jmp/0xz T_13.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x55dd3f92e6e0_0, 0; + %jmp T_13.1; +T_13.0 ; + %load/vec4 v0x55dd3f92e6e0_0; + %parti/s 1, 0, 2; + %load/vec4 v0x55dd3f94b950_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x55dd3f92e6e0_0, 0; +T_13.1 ; + %jmp T_13; + .thread T_13; + .scope S_0x55dd3f9c2810; +T_14 ; + %wait E_0x55dd3fb0e940; + %load/vec4 v0x55dd3f969cf0_0; + %flag_set/vec4 8; + %jmp/0xz T_14.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x55dd3f969d90_0, 0; + %jmp T_14.1; +T_14.0 ; + %load/vec4 v0x55dd3f969d90_0; + %parti/s 1, 0, 2; + %load/vec4 v0x55dd3f9ca450_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x55dd3f969d90_0, 0; +T_14.1 ; + %jmp T_14; + .thread T_14; + .scope S_0x55dd3f9c42b0; +T_15 ; + %wait E_0x55dd3fb0e940; + %load/vec4 v0x55dd3fa37710_0; + %flag_set/vec4 8; + %jmp/0xz T_15.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x55dd3fa2eb40_0, 0; + %jmp T_15.1; +T_15.0 ; + %load/vec4 v0x55dd3fa2eb40_0; + %parti/s 1, 0, 2; + %load/vec4 v0x55dd3fa75eb0_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x55dd3fa2eb40_0, 0; +T_15.1 ; + %jmp T_15; + .thread T_15; + .scope S_0x55dd3f9b87c0; +T_16 ; + %wait E_0x55dd3fb0e940; + %load/vec4 v0x55dd3f9e4180_0; + %flag_set/vec4 8; + %jmp/0xz T_16.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x55dd3f9e4220_0, 0; + %jmp T_16.1; +T_16.0 ; + %load/vec4 v0x55dd3f9e4220_0; + %parti/s 1, 0, 2; + %load/vec4 v0x55dd3f9e45e0_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x55dd3f9e4220_0, 0; +T_16.1 ; + %jmp T_16; + .thread T_16; + .scope S_0x55dd3f95ec40; +T_17 ; + %wait E_0x55dd3fb0e940; + %load/vec4 v0x55dd3f9e2ec0_0; + %flag_set/vec4 8; + %jmp/0xz T_17.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x55dd3f9e2f60_0, 0; + %jmp T_17.1; +T_17.0 ; + %load/vec4 v0x55dd3f9e2f60_0; + %parti/s 1, 0, 2; + %load/vec4 v0x55dd3f9e36e0_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x55dd3f9e2f60_0, 0; +T_17.1 ; + %jmp T_17; + .thread T_17; + .scope S_0x55dd3f960670; +T_18 ; + %wait E_0x55dd3fb0e940; + %load/vec4 v0x55dd3f9e1fc0_0; + %flag_set/vec4 8; + %jmp/0xz T_18.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x55dd3f9e2060_0, 0; + %jmp T_18.1; +T_18.0 ; + %load/vec4 v0x55dd3f9e2060_0; + %parti/s 1, 0, 2; + %load/vec4 v0x55dd3f9e27e0_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x55dd3f9e2060_0, 0; +T_18.1 ; + %jmp T_18; + .thread T_18; + .scope S_0x55dd3f993790; +T_19 ; + %wait E_0x55dd3fb0e940; + %load/vec4 v0x55dd3f9e1160_0; + %flag_set/vec4 8; + %jmp/0xz T_19.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x55dd3f9e0d00_0, 0; + %jmp T_19.1; +T_19.0 ; + %load/vec4 v0x55dd3f9e0d00_0; + %parti/s 1, 0, 2; + %load/vec4 v0x55dd3f9e1520_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x55dd3f9e0d00_0, 0; +T_19.1 ; + %jmp T_19; + .thread T_19; + .scope S_0x55dd3fa1a430; +T_20 ; + %wait E_0x55dd3fb0e940; + %load/vec4 v0x55dd3fadf130_0; + %flag_set/vec4 8; + %jmp/0xz T_20.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x55dd3fae0af0_0, 0; + %jmp T_20.1; +T_20.0 ; + %load/vec4 v0x55dd3fae0af0_0; + %parti/s 1, 0, 2; + %load/vec4 v0x55dd3faf3050_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x55dd3fae0af0_0, 0; +T_20.1 ; + %jmp T_20; + .thread T_20; + .scope S_0x55dd3fa1bed0; +T_21 ; + %wait E_0x55dd3fb0e940; + %load/vec4 v0x55dd3fb045c0_0; + %flag_set/vec4 8; + %jmp/0xz T_21.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x55dd3fb04660_0, 0; + %jmp T_21.1; +T_21.0 ; + %load/vec4 v0x55dd3fb04660_0; + %parti/s 1, 0, 2; + %load/vec4 v0x55dd3fb03b90_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x55dd3fb04660_0, 0; +T_21.1 ; + %jmp T_21; + .thread T_21; + .scope S_0x55dd3f9d2d50; +T_22 ; + %wait E_0x55dd3fb0e940; + %load/vec4 v0x55dd3face920_0; + %flag_set/vec4 8; + %jmp/0xz T_22.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x55dd3face9c0_0, 0; + %jmp T_22.1; +T_22.0 ; + %load/vec4 v0x55dd3face9c0_0; + %parti/s 1, 0, 2; + %load/vec4 v0x55dd3fad1260_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x55dd3face9c0_0, 0; +T_22.1 ; + %jmp T_22; + .thread T_22; + .scope S_0x55dd3f9ba290; +T_23 ; + %wait E_0x55dd3fb0e940; + %load/vec4 v0x55dd3fa8ecf0_0; + %flag_set/vec4 8; + %jmp/0xz T_23.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x55dd3fa8ed90_0, 0; + %jmp T_23.1; +T_23.0 ; + %load/vec4 v0x55dd3fa8ed90_0; + %parti/s 1, 0, 2; + %load/vec4 v0x55dd3fa9c2c0_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x55dd3fa8ed90_0, 0; +T_23.1 ; + %jmp T_23; + .thread T_23; + .scope S_0x55dd3f9bbd30; +T_24 ; + %wait E_0x55dd3fb0e940; + %load/vec4 v0x55dd3fa6ff60_0; + %flag_set/vec4 8; + %jmp/0xz T_24.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x55dd3fa70000_0, 0; + %jmp T_24.1; +T_24.0 ; + %load/vec4 v0x55dd3fa70000_0; + %parti/s 1, 0, 2; + %load/vec4 v0x55dd3fa73a90_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x55dd3fa70000_0, 0; +T_24.1 ; + %jmp T_24; + .thread T_24; + .scope S_0x55dd3f9bd7d0; +T_25 ; + %wait E_0x55dd3fb0e940; + %load/vec4 v0x55dd3fa07270_0; + %flag_set/vec4 8; + %jmp/0xz T_25.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x55dd3f9fe2d0_0, 0; + %jmp T_25.1; +T_25.0 ; + %load/vec4 v0x55dd3f9fe2d0_0; + %parti/s 1, 0, 2; + %load/vec4 v0x55dd3fa12c40_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x55dd3f9fe2d0_0, 0; +T_25.1 ; + %jmp T_25; + .thread T_25; + .scope S_0x55dd3fa7f190; +T_26 ; + %wait E_0x55dd3fb0e940; + %load/vec4 v0x55dd3f9daef0_0; + %flag_set/vec4 8; + %jmp/0xz T_26.0, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x55dd3fa196b0_0, 0; + %jmp T_26.1; +T_26.0 ; + %load/vec4 v0x55dd3fa196b0_0; + %cmpi/ne 0, 0, 3; + %jmp/0xz T_26.2, 4; + %load/vec4 v0x55dd3fa196b0_0; + %addi 1, 0, 3; + %assign/vec4 v0x55dd3fa196b0_0, 0; +T_26.2 ; + %load/vec4 v0x55dd3f957360_0; + %flag_set/vec4 8; + %jmp/0xz T_26.4, 8; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x55dd3fa196b0_0, 0; +T_26.4 ; +T_26.1 ; + %jmp T_26; + .thread T_26; + .scope S_0x55dd3fa81230; +T_27 ; + %wait E_0x55dd3fb0e940; + %load/vec4 v0x55dd3f9c4eb0_0; + %flag_set/vec4 8; + %jmp/0xz T_27.0, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x55dd3fa145b0_0, 0; + %jmp T_27.1; +T_27.0 ; + %load/vec4 v0x55dd3fa145b0_0; + %cmpi/ne 0, 0, 3; + %jmp/0xz T_27.2, 4; + %load/vec4 v0x55dd3fa145b0_0; + %addi 1, 0, 3; + %assign/vec4 v0x55dd3fa145b0_0, 0; +T_27.2 ; + %load/vec4 v0x55dd3fa1b050_0; + %flag_set/vec4 8; + %jmp/0xz T_27.4, 8; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x55dd3fa145b0_0, 0; +T_27.4 ; +T_27.1 ; + %jmp T_27; + .thread T_27; + .scope S_0x55dd3fab1780; +T_28 ; + %wait E_0x55dd3fb0e940; + %load/vec4 v0x55dd3f9bc950_0; + %flag_set/vec4 8; + %jmp/0xz T_28.0, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x55dd3f9be4f0_0, 0; + %jmp T_28.1; +T_28.0 ; + %load/vec4 v0x55dd3f9be4f0_0; + %cmpi/ne 0, 0, 3; + %jmp/0xz T_28.2, 4; + %load/vec4 v0x55dd3f9be4f0_0; + %addi 1, 0, 3; + %assign/vec4 v0x55dd3f9be4f0_0, 0; +T_28.2 ; + %load/vec4 v0x55dd3f9bffc0_0; + %flag_set/vec4 8; + %jmp/0xz T_28.4, 8; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x55dd3f9be4f0_0, 0; +T_28.4 ; +T_28.1 ; + %jmp T_28; + .thread T_28; + .scope S_0x55dd3fab3280; +T_29 ; + %wait E_0x55dd3fb0e940; + %load/vec4 v0x55dd3f9c69a0_0; + %flag_set/vec4 8; + %jmp/0xz T_29.0, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x55dd3f9c85a0_0, 0; + %jmp T_29.1; +T_29.0 ; + %load/vec4 v0x55dd3f9c85a0_0; + %cmpi/ne 0, 0, 3; + %jmp/0xz T_29.2, 4; + %load/vec4 v0x55dd3f9c85a0_0; + %addi 1, 0, 3; + %assign/vec4 v0x55dd3f9c85a0_0, 0; +T_29.2 ; + %load/vec4 v0x55dd3f9c9fb0_0; + %flag_set/vec4 8; + %jmp/0xz T_29.4, 8; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x55dd3f9c85a0_0, 0; +T_29.4 ; +T_29.1 ; + %jmp T_29; + .thread T_29; + .scope S_0x55dd3fab4cb0; +T_30 ; + %wait E_0x55dd3fb0e940; + %load/vec4 v0x55dd3f95f960_0; + %flag_set/vec4 8; + %jmp/0xz T_30.0, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x55dd3f958df0_0, 0; + %jmp T_30.1; +T_30.0 ; + %load/vec4 v0x55dd3f958df0_0; + %cmpi/ne 0, 0, 3; + %jmp/0xz T_30.2, 4; + %load/vec4 v0x55dd3f958df0_0; + %addi 1, 0, 3; + %assign/vec4 v0x55dd3f958df0_0, 0; +T_30.2 ; + %load/vec4 v0x55dd3f9697a0_0; + %flag_set/vec4 8; + %jmp/0xz T_30.4, 8; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x55dd3f958df0_0, 0; +T_30.4 ; +T_30.1 ; + %jmp T_30; + .thread T_30; + .scope S_0x55dd3fa1f840; +T_31 ; + %wait E_0x55dd3fb0e940; + %load/vec4 v0x55dd3f92c8b0_0; + %flag_set/vec4 8; + %jmp/0xz T_31.0, 8; + %pushi/vec4 0, 0, 4; + %assign/vec4 v0x55dd3f92aee0_0, 0; + %jmp T_31.1; +T_31.0 ; + %load/vec4 v0x55dd3f92aee0_0; + %cmpi/ne 0, 0, 4; + %jmp/0xz T_31.2, 4; + %load/vec4 v0x55dd3f92aee0_0; + %addi 1, 0, 4; + %assign/vec4 v0x55dd3f92aee0_0, 0; +T_31.2 ; + %load/vec4 v0x55dd3f926dd0_0; + %flag_set/vec4 8; + %jmp/0xz T_31.4, 8; + %pushi/vec4 1, 0, 4; + %assign/vec4 v0x55dd3f92aee0_0, 0; +T_31.4 ; +T_31.1 ; + %jmp T_31; + .thread T_31; + .scope S_0x55dd3fa21940; +T_32 ; + %wait E_0x55dd3fb0e940; + %load/vec4 v0x55dd3f9aeac0_0; + %flag_set/vec4 8; + %jmp/0xz T_32.0, 8; + %pushi/vec4 0, 0, 6; + %assign/vec4 v0x55dd3f99d0e0_0, 0; + %jmp T_32.1; +T_32.0 ; + %load/vec4 v0x55dd3f99d0e0_0; + %cmpi/ne 0, 0, 6; + %jmp/0xz T_32.2, 4; + %load/vec4 v0x55dd3f99d0e0_0; + %addi 1, 0, 6; + %assign/vec4 v0x55dd3f99d0e0_0, 0; +T_32.2 ; + %load/vec4 v0x55dd3f989a60_0; + %flag_set/vec4 8; + %jmp/0xz T_32.4, 8; + %pushi/vec4 1, 0, 6; + %assign/vec4 v0x55dd3f99d0e0_0, 0; +T_32.4 ; +T_32.1 ; + %jmp T_32; + .thread T_32; + .scope S_0x55dd3fa239e0; +T_33 ; + %wait E_0x55dd3fb0e940; + %load/vec4 v0x55dd3f99f4d0_0; + %flag_set/vec4 8; + %jmp/0xz T_33.0, 8; + %pushi/vec4 0, 0, 6; + %assign/vec4 v0x55dd3f9b7a30_0, 0; + %jmp T_33.1; +T_33.0 ; + %load/vec4 v0x55dd3f9b7a30_0; + %cmpi/ne 0, 0, 6; + %jmp/0xz T_33.2, 4; + %load/vec4 v0x55dd3f9b7a30_0; + %addi 1, 0, 6; + %assign/vec4 v0x55dd3f9b7a30_0, 0; +T_33.2 ; + %load/vec4 v0x55dd3f9b6090_0; + %flag_set/vec4 8; + %jmp/0xz T_33.4, 8; + %pushi/vec4 1, 0, 6; + %assign/vec4 v0x55dd3f9b7a30_0, 0; +T_33.4 ; +T_33.1 ; + %jmp T_33; + .thread T_33; + .scope S_0x55dd3fa2c5d0; +T_34 ; + %wait E_0x55dd3fb0e940; + %load/vec4 v0x55dd3f9aac70_0; + %flag_set/vec4 8; + %jmp/0xz T_34.0, 8; + %pushi/vec4 0, 0, 4; + %assign/vec4 v0x55dd3f9a9340_0, 0; + %jmp T_34.1; +T_34.0 ; + %load/vec4 v0x55dd3f9a9340_0; + %cmpi/ne 0, 0, 4; + %jmp/0xz T_34.2, 4; + %load/vec4 v0x55dd3f9a9340_0; + %addi 1, 0, 4; + %assign/vec4 v0x55dd3f9a9340_0, 0; +T_34.2 ; + %load/vec4 v0x55dd3f9a7580_0; + %flag_set/vec4 8; + %jmp/0xz T_34.4, 8; + %pushi/vec4 1, 0, 4; + %assign/vec4 v0x55dd3f9a9340_0, 0; +T_34.4 ; +T_34.1 ; + %jmp T_34; + .thread T_34; + .scope S_0x55dd3fa11c00; +T_35 ; + %wait E_0x55dd3fb0e940; + %load/vec4 v0x55dd3fa0a5a0_0; + %flag_set/vec4 8; + %jmp/0xz T_35.0, 8; + %pushi/vec4 0, 0, 4; + %assign/vec4 v0x55dd3fa08ba0_0, 0; + %jmp T_35.1; +T_35.0 ; + %load/vec4 v0x55dd3fa08ba0_0; + %cmpi/ne 0, 0, 4; + %jmp/0xz T_35.2, 4; + %load/vec4 v0x55dd3fa08ba0_0; + %addi 1, 0, 4; + %assign/vec4 v0x55dd3fa08ba0_0, 0; +T_35.2 ; + %load/vec4 v0x55dd3fa04ae0_0; + %flag_set/vec4 8; + %jmp/0xz T_35.4, 8; + %pushi/vec4 1, 0, 4; + %assign/vec4 v0x55dd3fa08ba0_0, 0; +T_35.4 ; +T_35.1 ; + %jmp T_35; + .thread T_35; + .scope S_0x55dd3f9d4800; +T_36 ; + %wait E_0x55dd3fb0e940; + %load/vec4 v0x55dd3fa016a0_0; + %flag_set/vec4 8; + %jmp/0xz T_36.0, 8; + %pushi/vec4 0, 0, 4; + %assign/vec4 v0x55dd3f9ffd70_0, 0; + %jmp T_36.1; +T_36.0 ; + %load/vec4 v0x55dd3f9ffd70_0; + %cmpi/ne 0, 0, 4; + %jmp/0xz T_36.2, 4; + %load/vec4 v0x55dd3f9ffd70_0; + %addi 1, 0, 4; + %assign/vec4 v0x55dd3f9ffd70_0, 0; +T_36.2 ; + %load/vec4 v0x55dd3f9fe010_0; + %flag_set/vec4 8; + %jmp/0xz T_36.4, 8; + %pushi/vec4 1, 0, 4; + %assign/vec4 v0x55dd3f9ffd70_0, 0; +T_36.4 ; +T_36.1 ; + %jmp T_36; + .thread T_36; + .scope S_0x55dd3f9d8e70; +T_37 ; + %wait E_0x55dd3fb0e940; + %load/vec4 v0x55dd3fa88ae0_0; + %flag_set/vec4 8; + %jmp/0xz T_37.0, 8; + %pushi/vec4 0, 0, 6; + %assign/vec4 v0x55dd3f7b1560_0, 0; + %jmp T_37.1; +T_37.0 ; + %load/vec4 v0x55dd3f7b1560_0; + %cmpi/ne 0, 0, 6; + %jmp/0xz T_37.2, 4; + %load/vec4 v0x55dd3f7b1560_0; + %addi 1, 0, 6; + %assign/vec4 v0x55dd3f7b1560_0, 0; +T_37.2 ; + %load/vec4 v0x55dd3fa83fb0_0; + %flag_set/vec4 8; + %jmp/0xz T_37.4, 8; + %pushi/vec4 1, 0, 6; + %assign/vec4 v0x55dd3f7b1560_0, 0; +T_37.4 ; +T_37.1 ; + %jmp T_37; + .thread T_37; + .scope S_0x55dd3f9db690; +T_38 ; + %wait E_0x55dd3fb0e940; + %load/vec4 v0x55dd3faa19f0_0; + %flag_set/vec4 8; + %jmp/0xz T_38.0, 8; + %pushi/vec4 0, 0, 5; + %assign/vec4 v0x55dd3fa9f630_0, 0; + %jmp T_38.1; +T_38.0 ; + %load/vec4 v0x55dd3fa9f630_0; + %cmpi/ne 0, 0, 5; + %jmp/0xz T_38.2, 4; + %load/vec4 v0x55dd3fa9f630_0; + %addi 1, 0, 5; + %assign/vec4 v0x55dd3fa9f630_0, 0; +T_38.2 ; + %load/vec4 v0x55dd3fa9dc90_0; + %flag_set/vec4 8; + %jmp/0xz T_38.4, 8; + %pushi/vec4 1, 0, 5; + %assign/vec4 v0x55dd3fa9f630_0, 0; +T_38.4 ; +T_38.1 ; + %jmp T_38; + .thread T_38; + .scope S_0x55dd3faa41c0; +T_39 ; + %wait E_0x55dd3fb0e940; + %load/vec4 v0x55dd3f967d00_0; + %flag_set/vec4 8; + %jmp/0xz T_39.0, 8; + %pushi/vec4 0, 0, 4; + %assign/vec4 v0x55dd3f961390_0, 0; + %jmp T_39.1; +T_39.0 ; + %load/vec4 v0x55dd3f961390_0; + %cmpi/ne 0, 0, 4; + %jmp/0xz T_39.2, 4; + %load/vec4 v0x55dd3f961390_0; + %addi 1, 0, 4; + %assign/vec4 v0x55dd3f961390_0, 0; +T_39.2 ; + %load/vec4 v0x55dd3f95a920_0; + %flag_set/vec4 8; + %jmp/0xz T_39.4, 8; + %pushi/vec4 1, 0, 4; + %assign/vec4 v0x55dd3f961390_0, 0; +T_39.4 ; +T_39.1 ; + %jmp T_39; + .thread T_39; + .scope S_0x55dd3fa306a0; +T_40 ; + %wait E_0x55dd3fb0e940; + %load/vec4 v0x55dd3f9d1f80_0; + %flag_set/vec4 8; + %jmp/0xz T_40.0, 8; + %pushi/vec4 0, 0, 6; + %assign/vec4 v0x55dd3f953ec0_0, 0; + %jmp T_40.1; +T_40.0 ; + %load/vec4 v0x55dd3f953ec0_0; + %cmpi/ne 0, 0, 6; + %jmp/0xz T_40.2, 4; + %load/vec4 v0x55dd3f953ec0_0; + %addi 1, 0, 6; + %assign/vec4 v0x55dd3f953ec0_0, 0; +T_40.2 ; + %load/vec4 v0x55dd3f962d30_0; + %flag_set/vec4 8; + %jmp/0xz T_40.4, 8; + %pushi/vec4 1, 0, 6; + %assign/vec4 v0x55dd3f953ec0_0, 0; +T_40.4 ; +T_40.1 ; + %jmp T_40; + .thread T_40; + .scope S_0x55dd3fa139b0; +T_41 ; + %wait E_0x55dd3fb0e940; + %load/vec4 v0x55dd3fb07270_0; + %flag_set/vec4 8; + %jmp/0xz T_41.0, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x55dd3fb06390_0, 0; + %jmp T_41.1; +T_41.0 ; + %load/vec4 v0x55dd3fb06390_0; + %cmpi/ne 0, 0, 3; + %jmp/0xz T_41.2, 4; + %load/vec4 v0x55dd3fb06390_0; + %addi 1, 0, 3; + %assign/vec4 v0x55dd3fb06390_0, 0; +T_41.2 ; + %load/vec4 v0x55dd3fb04a80_0; + %flag_set/vec4 8; + %jmp/0xz T_41.4, 8; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x55dd3fb06390_0, 0; +T_41.4 ; +T_41.1 ; + %jmp T_41; + .thread T_41; + .scope S_0x55dd3fa15450; +T_42 ; + %wait E_0x55dd3fb0e940; + %load/vec4 v0x55dd3f949b80_0; + %flag_set/vec4 8; + %jmp/0xz T_42.0, 8; + %pushi/vec4 0, 0, 4; + %assign/vec4 v0x55dd3f948180_0, 0; + %jmp T_42.1; +T_42.0 ; + %load/vec4 v0x55dd3f948180_0; + %cmpi/ne 0, 0, 4; + %jmp/0xz T_42.2, 4; + %load/vec4 v0x55dd3f948180_0; + %addi 1, 0, 4; + %assign/vec4 v0x55dd3f948180_0, 0; +T_42.2 ; + %load/vec4 v0x55dd3f942a50_0; + %flag_set/vec4 8; + %jmp/0xz T_42.4, 8; + %pushi/vec4 1, 0, 4; + %assign/vec4 v0x55dd3f948180_0, 0; +T_42.4 ; +T_42.1 ; + %jmp T_42; + .thread T_42; + .scope S_0x55dd3fa16ef0; +T_43 ; + %wait E_0x55dd3fb0e940; + %load/vec4 v0x55dd3f93dbb0_0; + %flag_set/vec4 8; + %jmp/0xz T_43.0, 8; + %pushi/vec4 0, 0, 4; + %assign/vec4 v0x55dd3f93c1b0_0, 0; + %jmp T_43.1; +T_43.0 ; + %load/vec4 v0x55dd3f93c1b0_0; + %cmpi/ne 0, 0, 4; + %jmp/0xz T_43.2, 4; + %load/vec4 v0x55dd3f93c1b0_0; + %addi 1, 0, 4; + %assign/vec4 v0x55dd3f93c1b0_0, 0; +T_43.2 ; + %load/vec4 v0x55dd3f9379d0_0; + %flag_set/vec4 8; + %jmp/0xz T_43.4, 8; + %pushi/vec4 1, 0, 4; + %assign/vec4 v0x55dd3f93c1b0_0, 0; +T_43.4 ; +T_43.1 ; + %jmp T_43; + .thread T_43; + .scope S_0x55dd3fafead0; +T_44 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x55dd3fb06110_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x55dd3fb05050_0, 0, 1; + %end; + .thread T_44; + .scope S_0x55dd3fafead0; +T_45 ; + %wait E_0x55dd3fb0e940; + %load/vec4 v0x55dd3faca7c0_0; + %flag_set/vec4 8; + %jmp/0xz T_45.0, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb06110_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb05b70_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb05050_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb08c60_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb08a10_0, 0; + %pushi/vec4 0, 0, 36; + %assign/vec4 v0x55dd3faf3a20_0, 0; + %jmp T_45.1; +T_45.0 ; + %load/vec4 v0x55dd3fb08a10_0; + %load/vec4 v0x55dd3fb08950_0; + %inv; + %and; + %flag_set/vec4 8; + %jmp/0xz T_45.2, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb08a10_0, 0; +T_45.2 ; + %load/vec4 v0x55dd3fb08c60_0; + %load/vec4 v0x55dd3fb08950_0; + %inv; + %and; + %flag_set/vec4 8; + %jmp/0xz T_45.4, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb08c60_0, 0; + %load/vec4 v0x55dd3fb08d20_0; + %assign/vec4 v0x55dd3faf3a20_0, 0; +T_45.4 ; + %load/vec4 v0x55dd3fac37a0_0; + %flag_set/vec4 8; + %jmp/0xz T_45.6, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb05360_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb05400_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fabe3b0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fabe470_0, 0; +T_45.6 ; + %load/vec4 v0x55dd3fb067b0_0; + %load/vec4 v0x55dd3fb082d0_0; + %or; + %assign/vec4 v0x55dd3fb067b0_0, 0; + %load/vec4 v0x55dd3fb05de0_0; + %flag_set/vec4 8; + %jmp/0xz T_45.8, 8; + %pushi/vec4 0, 0, 36; + %assign/vec4 v0x55dd3fb067b0_0, 0; +T_45.8 ; + %load/vec4 v0x55dd3fac3370_0; + %flag_set/vec4 8; + %jmp/0xz T_45.10, 8; + %load/vec4 v0x55dd3fb067b0_0; + %load/vec4 v0x55dd3faf3a20_0; + %or; + %assign/vec4 v0x55dd3fb067b0_0, 0; +T_45.10 ; + %load/vec4 v0x55dd3fabf6f0_0; + %flag_set/vec4 8; + %jmp/0xz T_45.12, 8; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x55dd3fb05050_0, 0; +T_45.12 ; + %load/vec4 v0x55dd3fac2a10_0; + %flag_set/vec4 8; + %jmp/0xz T_45.14, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb06110_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb05050_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb04800_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fac3840_0, 0; + %pushi/vec4 0, 0, 14; + %assign/vec4 v0x55dd3f84bef0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3f84bfd0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb066f0_0, 0; + %load/vec4 v0x55dd3fabfc90_0; + %flag_set/vec4 8; + %jmp/0xz T_45.16, 8; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x55dd3fb05360_0, 0; + %jmp T_45.17; +T_45.16 ; + %load/vec4 v0x55dd3fabf8e0_0; + %flag_set/vec4 8; + %jmp/0xz T_45.18, 8; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x55dd3fb05400_0, 0; + %jmp T_45.19; +T_45.18 ; + %load/vec4 v0x55dd3fabf980_0; + %flag_set/vec4 8; + %jmp/0xz T_45.20, 8; + %load/vec4 v0x55dd3fabf650_0; + %inv; + %load/vec4 v0x55dd3fb05b70_0; + %or; + %flag_set/vec4 8; + %jmp/0xz T_45.22, 8; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x55dd3fabe3b0_0, 0; +T_45.22 ; + %jmp T_45.21; +T_45.20 ; + %load/vec4 v0x55dd3fabf650_0; + %flag_set/vec4 8; + %jmp/0xz T_45.24, 8; + %load/vec4 v0x55dd3fabf980_0; + %inv; + %load/vec4 v0x55dd3fb05b70_0; + %inv; + %or; + %flag_set/vec4 8; + %jmp/0xz T_45.26, 8; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x55dd3fabe470_0, 0; +T_45.26 ; +T_45.24 ; +T_45.21 ; +T_45.19 ; +T_45.17 ; +T_45.14 ; + %load/vec4 v0x55dd3fac2700_0; + %flag_set/vec4 8; + %jmp/0xz T_45.28, 8; + %load/vec4 v0x55dd3f84bef0_0; + %load/vec4 v0x55dd3fb08700_0; + %parti/s 14, 0, 2; + %or; + %assign/vec4 v0x55dd3f84bef0_0, 0; + %load/vec4 v0x55dd3faca720_0; + %flag_set/vec4 8; + %jmp/0xz T_45.30, 8; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x55dd3f84bfd0_0, 0; +T_45.30 ; + %load/vec4 v0x55dd3faf1860_0; + %flag_set/vec4 8; + %jmp/0xz T_45.32, 8; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x55dd3fb066f0_0, 0; +T_45.32 ; +T_45.28 ; + %load/vec4 v0x55dd3fac1e70_0; + %flag_set/vec4 8; + %jmp/0xz T_45.34, 8; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x55dd3fb03e30_0, 0; + %load/vec4 v0x55dd3fabe3b0_0; + %flag_set/vec4 8; + %jmp/0xz T_45.36, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb05b70_0, 0; +T_45.36 ; + %load/vec4 v0x55dd3fabe470_0; + %flag_set/vec4 8; + %jmp/0xz T_45.38, 8; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x55dd3fb05b70_0, 0; +T_45.38 ; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x55dd3fb08c60_0, 0; +T_45.34 ; + %load/vec4 v0x55dd3fac1820_0; + %flag_set/vec4 8; + %jmp/0xz T_45.40, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb03e30_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x55dd3fb04800_0, 0; +T_45.40 ; + %load/vec4 v0x55dd3fac0ed0_0; + %flag_set/vec4 8; + %jmp/0xz T_45.42, 8; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x55dd3fb05e80_0, 0; + %load/vec4 v0x55dd3faf17a0_0; + %flag_set/vec4 8; + %jmp/0xz T_45.44, 8; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x55dd3fac3840_0, 0; +T_45.44 ; +T_45.42 ; + %load/vec4 v0x55dd3fac0bc0_0; + %flag_set/vec4 8; + %jmp/0xz T_45.46, 8; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x55dd3fabffa0_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x55dd3fb08a10_0, 0; +T_45.46 ; + %load/vec4 v0x55dd3fac24e0_0; + %flag_set/vec4 8; + %jmp/0xz T_45.48, 8; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x55dd3fb06110_0, 0; +T_45.48 ; + %load/vec4 v0x55dd3fac2180_0; + %flag_set/vec4 8; + %jmp/0xz T_45.50, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb03e30_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb05e80_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fabffa0_0, 0; +T_45.50 ; +T_45.1 ; + %jmp T_45; + .thread T_45; + .scope S_0x55dd3f968b80; +T_46 ; + %wait E_0x55dd3fb0ea50; + %load/vec4 v0x55dd3fac9080_0; + %flag_set/vec4 8; + %jmp/0xz T_46.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x55dd3fac9140_0, 0; + %jmp T_46.1; +T_46.0 ; + %load/vec4 v0x55dd3fac9140_0; + %parti/s 1, 0, 2; + %load/vec4 v0x55dd3fad9710_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x55dd3fac9140_0, 0; +T_46.1 ; + %jmp T_46; + .thread T_46; + .scope S_0x55dd3f954c40; +T_47 ; + %wait E_0x55dd3fb0ea50; + %load/vec4 v0x55dd3fad4710_0; + %flag_set/vec4 8; + %jmp/0xz T_47.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x55dd3fad47b0_0, 0; + %jmp T_47.1; +T_47.0 ; + %load/vec4 v0x55dd3fad47b0_0; + %parti/s 1, 0, 2; + %load/vec4 v0x55dd3fad5680_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x55dd3fad47b0_0, 0; +T_47.1 ; + %jmp T_47; + .thread T_47; + .scope S_0x55dd3f956740; +T_48 ; + %wait E_0x55dd3fb0ea50; + %load/vec4 v0x55dd3fade690_0; + %flag_set/vec4 8; + %jmp/0xz T_48.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x55dd3faf2540_0, 0; + %jmp T_48.1; +T_48.0 ; + %load/vec4 v0x55dd3faf2540_0; + %parti/s 1, 0, 2; + %load/vec4 v0x55dd3fae0080_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x55dd3faf2540_0, 0; +T_48.1 ; + %jmp T_48; + .thread T_48; + .scope S_0x55dd3f9581d0; +T_49 ; + %wait E_0x55dd3fb0ea50; + %load/vec4 v0x55dd3fae8fd0_0; + %flag_set/vec4 8; + %jmp/0xz T_49.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x55dd3fae6b00_0, 0; + %jmp T_49.1; +T_49.0 ; + %load/vec4 v0x55dd3fae6b00_0; + %parti/s 1, 0, 2; + %load/vec4 v0x55dd3faead00_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x55dd3fae6b00_0, 0; +T_49.1 ; + %jmp T_49; + .thread T_49; + .scope S_0x55dd3f941ef0; +T_50 ; + %wait E_0x55dd3fb0ea50; + %load/vec4 v0x55dd3f989f70_0; + %flag_set/vec4 8; + %jmp/0xz T_50.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x55dd3f98a010_0, 0; + %jmp T_50.1; +T_50.0 ; + %load/vec4 v0x55dd3f98a010_0; + %parti/s 1, 0, 2; + %load/vec4 v0x55dd3fa75970_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x55dd3f98a010_0, 0; +T_50.1 ; + %jmp T_50; + .thread T_50; + .scope S_0x55dd3f959c00; +T_51 ; + %wait E_0x55dd3fb0ea50; + %load/vec4 v0x55dd3fa61840_0; + %flag_set/vec4 8; + %jmp/0xz T_51.0, 8; + %pushi/vec4 0, 0, 6; + %assign/vec4 v0x55dd3fa61780_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fa63330_0, 0; + %jmp T_51.1; +T_51.0 ; + %load/vec4 v0x55dd3fa61780_0; + %cmpi/ne 0, 0, 6; + %jmp/0xz T_51.2, 4; + %load/vec4 v0x55dd3fa61780_0; + %addi 1, 0, 6; + %assign/vec4 v0x55dd3fa61780_0, 0; +T_51.2 ; + %load/vec4 v0x55dd3fa666c0_0; + %flag_set/vec4 8; + %jmp/0xz T_51.4, 8; + %pushi/vec4 1, 0, 6; + %assign/vec4 v0x55dd3fa61780_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x55dd3fa63330_0, 0; +T_51.4 ; + %load/vec4 v0x55dd3fa633f0_0; + %flag_set/vec4 8; + %jmp/0xz T_51.6, 8; + %pushi/vec4 0, 0, 6; + %assign/vec4 v0x55dd3fa61780_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fa63330_0, 0; +T_51.6 ; +T_51.1 ; + %jmp T_51; + .thread T_51; + .scope S_0x55dd3f95b6a0; +T_52 ; + %wait E_0x55dd3fb0ea50; + %load/vec4 v0x55dd3fa86b00_0; + %flag_set/vec4 8; + %jmp/0xz T_52.0, 8; + %pushi/vec4 0, 0, 6; + %assign/vec4 v0x55dd3fa89680_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fa91680_0, 0; + %jmp T_52.1; +T_52.0 ; + %load/vec4 v0x55dd3fa89680_0; + %cmpi/ne 0, 0, 6; + %jmp/0xz T_52.2, 4; + %load/vec4 v0x55dd3fa89680_0; + %addi 1, 0, 6; + %assign/vec4 v0x55dd3fa89680_0, 0; +T_52.2 ; + %load/vec4 v0x55dd3fa915e0_0; + %flag_set/vec4 8; + %jmp/0xz T_52.4, 8; + %pushi/vec4 1, 0, 6; + %assign/vec4 v0x55dd3fa89680_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x55dd3fa91680_0, 0; +T_52.4 ; + %load/vec4 v0x55dd3fa895c0_0; + %flag_set/vec4 8; + %jmp/0xz T_52.6, 8; + %pushi/vec4 0, 0, 6; + %assign/vec4 v0x55dd3fa89680_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fa91680_0, 0; +T_52.6 ; +T_52.1 ; + %jmp T_52; + .thread T_52; + .scope S_0x55dd3fa00be0; +T_53 ; + %wait E_0x55dd3fb0ea50; + %load/vec4 v0x55dd3fa0fa40_0; + %flag_set/vec4 8; + %jmp/0xz T_53.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x55dd3fa0b4e0_0, 0; + %jmp T_53.1; +T_53.0 ; + %load/vec4 v0x55dd3fa0b4e0_0; + %parti/s 1, 0, 2; + %load/vec4 v0x55dd3f9fbaf0_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x55dd3fa0b4e0_0, 0; +T_53.1 ; + %jmp T_53; + .thread T_53; + .scope S_0x55dd3fa09ae0; +T_54 ; + %wait E_0x55dd3fb0ea50; + %load/vec4 v0x55dd3fa02650_0; + %flag_set/vec4 8; + %jmp/0xz T_54.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x55dd3f9df7e0_0, 0; + %jmp T_54.1; +T_54.0 ; + %load/vec4 v0x55dd3f9df7e0_0; + %parti/s 1, 0, 2; + %load/vec4 v0x55dd3fa04020_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x55dd3f9df7e0_0, 0; +T_54.1 ; + %jmp T_54; + .thread T_54; + .scope S_0x55dd3f9afa00; +T_55 ; + %wait E_0x55dd3fb0ea50; + %load/vec4 v0x55dd3f988fc0_0; + %flag_set/vec4 8; + %jmp/0xz T_55.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x55dd3f9871d0_0, 0; + %jmp T_55.1; +T_55.0 ; + %load/vec4 v0x55dd3f9871d0_0; + %parti/s 1, 0, 2; + %load/vec4 v0x55dd3f997b60_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x55dd3f9871d0_0, 0; +T_55.1 ; + %jmp T_55; + .thread T_55; + .scope S_0x55dd3f9854a0; +T_56 ; + %wait E_0x55dd3fb0ea50; + %load/vec4 v0x55dd3f912960_0; + %flag_set/vec4 8; + %jmp/0xz T_56.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x55dd3f91b840_0, 0; + %jmp T_56.1; +T_56.0 ; + %load/vec4 v0x55dd3f91b840_0; + %parti/s 1, 0, 2; + %load/vec4 v0x55dd3f91cf60_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x55dd3f91b840_0, 0; +T_56.1 ; + %jmp T_56; + .thread T_56; + .scope S_0x55dd3f91a220; +T_57 ; + %wait E_0x55dd3fb0ea50; + %load/vec4 v0x55dd3f913cc0_0; + %flag_set/vec4 8; + %jmp/0xz T_57.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x55dd3f943420_0, 0; + %jmp T_57.1; +T_57.0 ; + %load/vec4 v0x55dd3f943420_0; + %parti/s 1, 0, 2; + %load/vec4 v0x55dd3f914fe0_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x55dd3f943420_0, 0; +T_57.1 ; + %jmp T_57; + .thread T_57; + .scope S_0x55dd3f93a810; +T_58 ; + %wait E_0x55dd3fb0ea50; + %load/vec4 v0x55dd3f9236b0_0; + %flag_set/vec4 8; + %jmp/0xz T_58.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x55dd3f922ce0_0, 0; + %jmp T_58.1; +T_58.0 ; + %load/vec4 v0x55dd3f922ce0_0; + %parti/s 1, 0, 2; + %load/vec4 v0x55dd3f929670_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x55dd3f922ce0_0, 0; +T_58.1 ; + %jmp T_58; + .thread T_58; + .scope S_0x55dd3f921b50; +T_59 ; + %wait E_0x55dd3fb0ea50; + %load/vec4 v0x55dd3f92beb0_0; + %flag_set/vec4 8; + %jmp/0xz T_59.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x55dd3f92a420_0, 0; + %jmp T_59.1; +T_59.0 ; + %load/vec4 v0x55dd3f92a420_0; + %parti/s 1, 0, 2; + %load/vec4 v0x55dd3f92d8c0_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x55dd3f92a420_0, 0; +T_59.1 ; + %jmp T_59; + .thread T_59; + .scope S_0x55dd3f928030; +T_60 ; + %wait E_0x55dd3fb0ea50; + %load/vec4 v0x55dd3f93eb90_0; + %flag_set/vec4 8; + %jmp/0xz T_60.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x55dd3f93d0f0_0, 0; + %jmp T_60.1; +T_60.0 ; + %load/vec4 v0x55dd3f93d0f0_0; + %parti/s 1, 0, 2; + %load/vec4 v0x55dd3f940590_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x55dd3f93d0f0_0, 0; +T_60.1 ; + %jmp T_60; + .thread T_60; + .scope S_0x55dd3f93b6f0; +T_61 ; + %wait E_0x55dd3fb0ea50; + %load/vec4 v0x55dd3f932db0_0; + %flag_set/vec4 8; + %jmp/0xz T_61.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x55dd3f94aa90_0, 0; + %jmp T_61.1; +T_61.0 ; + %load/vec4 v0x55dd3f94aa90_0; + %parti/s 1, 0, 2; + %load/vec4 v0x55dd3f935510_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x55dd3f94aa90_0, 0; +T_61.1 ; + %jmp T_61; + .thread T_61; + .scope S_0x55dd3f9490c0; +T_62 ; + %wait E_0x55dd3fb0ea50; + %load/vec4 v0x55dd3f9442c0_0; + %flag_set/vec4 8; + %jmp/0xz T_62.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x55dd3f944360_0, 0; + %jmp T_62.1; +T_62.0 ; + %load/vec4 v0x55dd3f944360_0; + %parti/s 1, 0, 2; + %load/vec4 v0x55dd3f945cc0_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x55dd3f944360_0, 0; +T_62.1 ; + %jmp T_62; + .thread T_62; + .scope S_0x55dd3f9df2a0; +T_63 ; + %wait E_0x55dd3fb0ea50; + %load/vec4 v0x55dd3f975aa0_0; + %flag_set/vec4 8; + %jmp/0xz T_63.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x55dd3f9741e0_0, 0; + %jmp T_63.1; +T_63.0 ; + %load/vec4 v0x55dd3f9741e0_0; + %parti/s 1, 0, 2; + %load/vec4 v0x55dd3f9d97f0_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x55dd3f9741e0_0, 0; +T_63.1 ; + %jmp T_63; + .thread T_63; + .scope S_0x55dd3f9b4660; +T_64 ; + %wait E_0x55dd3fb0ea50; + %load/vec4 v0x55dd3f99dc80_0; + %flag_set/vec4 8; + %jmp/0xz T_64.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x55dd3f99b100_0, 0; + %jmp T_64.1; +T_64.0 ; + %load/vec4 v0x55dd3f99b100_0; + %parti/s 1, 0, 2; + %load/vec4 v0x55dd3f9a5be0_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x55dd3f99b100_0, 0; +T_64.1 ; + %jmp T_64; + .thread T_64; + .scope S_0x55dd3f99a520; +T_65 ; + %wait E_0x55dd3fb0ea50; + %load/vec4 v0x55dd3f98dff0_0; + %flag_set/vec4 8; + %jmp/0xz T_65.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x55dd3f98ce50_0, 0; + %jmp T_65.1; +T_65.0 ; + %load/vec4 v0x55dd3f98ce50_0; + %parti/s 1, 0, 2; + %load/vec4 v0x55dd3f98f0f0_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x55dd3f98ce50_0, 0; +T_65.1 ; + %jmp T_65; + .thread T_65; + .scope S_0x55dd3f98bcf0; +T_66 ; + %wait E_0x55dd3fb0ea50; + %load/vec4 v0x55dd3f97c960_0; + %flag_set/vec4 8; + %jmp/0xz T_66.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x55dd3f991e90_0, 0; + %jmp T_66.1; +T_66.0 ; + %load/vec4 v0x55dd3f991e90_0; + %parti/s 1, 0, 2; + %load/vec4 v0x55dd3f97e600_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x55dd3f991e90_0, 0; +T_66.1 ; + %jmp T_66; + .thread T_66; + .scope S_0x55dd3f9abb80; +T_67 ; + %wait E_0x55dd3fb0ea50; + %load/vec4 v0x55dd3f9a42f0_0; + %flag_set/vec4 8; + %jmp/0xz T_67.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x55dd3f9a24d0_0, 0; + %jmp T_67.1; +T_67.0 ; + %load/vec4 v0x55dd3f9a24d0_0; + %parti/s 1, 0, 2; + %load/vec4 v0x55dd3f9a6ac0_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x55dd3f9a24d0_0, 0; +T_67.1 ; + %jmp T_67; + .thread T_67; + .scope S_0x55dd3f9a0770; +T_68 ; + %wait E_0x55dd3fb0ea50; + %load/vec4 v0x55dd3f9b3190_0; + %flag_set/vec4 8; + %jmp/0xz T_68.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x55dd3f9b1730_0, 0; + %jmp T_68.1; +T_68.0 ; + %load/vec4 v0x55dd3f9b1730_0; + %parti/s 1, 0, 2; + %load/vec4 v0x55dd3f9b55d0_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x55dd3f9b1730_0, 0; +T_68.1 ; + %jmp T_68; + .thread T_68; + .scope S_0x55dd3fa8c170; +T_69 ; + %wait E_0x55dd3fb0ea50; + %load/vec4 v0x55dd3fa9d130_0; + %flag_set/vec4 8; + %jmp/0xz T_69.0, 8; + %pushi/vec4 0, 0, 4; + %assign/vec4 v0x55dd3fa9eb90_0, 0; + %jmp T_69.1; +T_69.0 ; + %load/vec4 v0x55dd3fa9eb90_0; + %cmpi/ne 0, 0, 4; + %jmp/0xz T_69.2, 4; + %load/vec4 v0x55dd3fa9eb90_0; + %addi 1, 0, 4; + %assign/vec4 v0x55dd3fa9eb90_0, 0; +T_69.2 ; + %load/vec4 v0x55dd3faa0fd0_0; + %flag_set/vec4 8; + %jmp/0xz T_69.4, 8; + %pushi/vec4 1, 0, 4; + %assign/vec4 v0x55dd3fa9eb90_0, 0; +T_69.4 ; +T_69.1 ; + %jmp T_69; + .thread T_69; + .scope S_0x55dd3fa9b400; +T_70 ; + %wait E_0x55dd3fb0ea50; + %load/vec4 v0x55dd3fa72bd0_0; + %flag_set/vec4 8; + %jmp/0xz T_70.0, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x55dd3fa749c0_0, 0; + %jmp T_70.1; +T_70.0 ; + %load/vec4 v0x55dd3fa749c0_0; + %cmpi/ne 0, 0, 3; + %jmp/0xz T_70.2, 4; + %load/vec4 v0x55dd3fa749c0_0; + %addi 1, 0, 3; + %assign/vec4 v0x55dd3fa749c0_0, 0; +T_70.2 ; + %load/vec4 v0x55dd3fa83560_0; + %flag_set/vec4 8; + %jmp/0xz T_70.4, 8; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x55dd3fa749c0_0, 0; +T_70.4 ; +T_70.1 ; + %jmp T_70; + .thread T_70; + .scope S_0x55dd3fa70ea0; +T_71 ; + %wait E_0x55dd3fb0ea50; + %load/vec4 v0x55dd3fa269e0_0; + %flag_set/vec4 8; + %jmp/0xz T_71.0, 8; + %pushi/vec4 0, 0, 4; + %assign/vec4 v0x55dd3fa28140_0, 0; + %jmp T_71.1; +T_71.0 ; + %load/vec4 v0x55dd3fa28140_0; + %cmpi/ne 0, 0, 4; + %jmp/0xz T_71.2, 4; + %load/vec4 v0x55dd3fa28140_0; + %addi 1, 0, 4; + %assign/vec4 v0x55dd3fa28140_0, 0; +T_71.2 ; + %load/vec4 v0x55dd3fa2dfa0_0; + %flag_set/vec4 8; + %jmp/0xz T_71.4, 8; + %pushi/vec4 1, 0, 4; + %assign/vec4 v0x55dd3fa28140_0, 0; +T_71.4 ; +T_71.1 ; + %jmp T_71; + .thread T_71; + .scope S_0x55dd3fa25ad0; +T_72 ; + %wait E_0x55dd3fb0ea50; + %load/vec4 v0x55dd3f9ee090_0; + %flag_set/vec4 8; + %jmp/0xz T_72.0, 8; + %pushi/vec4 0, 0, 5; + %assign/vec4 v0x55dd3f9eef30_0, 0; + %jmp T_72.1; +T_72.0 ; + %load/vec4 v0x55dd3f9eef30_0; + %cmpi/ne 0, 0, 5; + %jmp/0xz T_72.2, 4; + %load/vec4 v0x55dd3f9eef30_0; + %addi 1, 0, 5; + %assign/vec4 v0x55dd3f9eef30_0, 0; +T_72.2 ; + %load/vec4 v0x55dd3f9efad0_0; + %flag_set/vec4 8; + %jmp/0xz T_72.4, 8; + %pushi/vec4 1, 0, 5; + %assign/vec4 v0x55dd3f9eef30_0, 0; +T_72.4 ; +T_72.1 ; + %jmp T_72; + .thread T_72; + .scope S_0x55dd3f9ed8f0; +T_73 ; + %wait E_0x55dd3fb0ea50; + %load/vec4 v0x55dd3f9ea460_0; + %flag_set/vec4 8; + %jmp/0xz T_73.0, 8; + %pushi/vec4 0, 0, 5; + %assign/vec4 v0x55dd3f9eb110_0, 0; + %jmp T_73.1; +T_73.0 ; + %load/vec4 v0x55dd3f9eb110_0; + %cmpi/ne 0, 0, 5; + %jmp/0xz T_73.2, 4; + %load/vec4 v0x55dd3f9eb110_0; + %addi 1, 0, 5; + %assign/vec4 v0x55dd3f9eb110_0, 0; +T_73.2 ; + %load/vec4 v0x55dd3f9eb7f0_0; + %flag_set/vec4 8; + %jmp/0xz T_73.4, 8; + %pushi/vec4 1, 0, 5; + %assign/vec4 v0x55dd3f9eb110_0, 0; +T_73.4 ; +T_73.1 ; + %jmp T_73; + .thread T_73; + .scope S_0x55dd3f9e9c90; +T_74 ; + %wait E_0x55dd3fb0ea50; + %load/vec4 v0x55dd3fa054e0_0; + %flag_set/vec4 8; + %jmp/0xz T_74.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x55dd3fa0ece0_0, 0; + %jmp T_74.1; +T_74.0 ; + %load/vec4 v0x55dd3fa0ece0_0; + %cmpi/ne 0, 0, 2; + %jmp/0xz T_74.2, 4; + %load/vec4 v0x55dd3fa0ece0_0; + %addi 1, 0, 2; + %assign/vec4 v0x55dd3fa0ece0_0, 0; +T_74.2 ; + %load/vec4 v0x55dd3fa10ea0_0; + %flag_set/vec4 8; + %jmp/0xz T_74.4, 8; + %pushi/vec4 1, 0, 2; + %assign/vec4 v0x55dd3fa0ece0_0, 0; +T_74.4 ; +T_74.1 ; + %jmp T_74; + .thread T_74; + .scope S_0x55dd3f9fa880; +T_75 ; + %wait E_0x55dd3fb0ea50; + %load/vec4 v0x55dd3f9e65c0_0; + %flag_set/vec4 8; + %jmp/0xz T_75.0, 8; + %pushi/vec4 0, 0, 4; + %assign/vec4 v0x55dd3f9e64e0_0, 0; + %jmp T_75.1; +T_75.0 ; + %load/vec4 v0x55dd3f9e64e0_0; + %cmpi/ne 0, 0, 4; + %jmp/0xz T_75.2, 4; + %load/vec4 v0x55dd3f9e64e0_0; + %addi 1, 0, 4; + %assign/vec4 v0x55dd3f9e64e0_0, 0; +T_75.2 ; + %load/vec4 v0x55dd3f9f6b90_0; + %flag_set/vec4 8; + %jmp/0xz T_75.4, 8; + %pushi/vec4 1, 0, 4; + %assign/vec4 v0x55dd3f9e64e0_0, 0; +T_75.4 ; +T_75.1 ; + %jmp T_75; + .thread T_75; + .scope S_0x55dd3f9f57a0; +T_76 ; + %wait E_0x55dd3fb0ea50; + %load/vec4 v0x55dd3fa0cf20_0; + %flag_set/vec4 8; + %jmp/0xz T_76.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x55dd3f9f1c80_0, 0; + %jmp T_76.1; +T_76.0 ; + %load/vec4 v0x55dd3f9f1c80_0; + %cmpi/ne 0, 0, 2; + %jmp/0xz T_76.2, 4; + %load/vec4 v0x55dd3f9f1c80_0; + %addi 1, 0, 2; + %assign/vec4 v0x55dd3f9f1c80_0, 0; +T_76.2 ; + %load/vec4 v0x55dd3f9f2ba0_0; + %flag_set/vec4 8; + %jmp/0xz T_76.4, 8; + %pushi/vec4 1, 0, 2; + %assign/vec4 v0x55dd3f9f1c80_0, 0; +T_76.4 ; +T_76.1 ; + %jmp T_76; + .thread T_76; + .scope S_0x55dd3fa85f20; +T_77 ; + %wait E_0x55dd3fb0ea50; + %load/vec4 v0x55dd3fa79a10_0; + %flag_set/vec4 8; + %jmp/0xz T_77.0, 8; + %pushi/vec4 0, 0, 5; + %assign/vec4 v0x55dd3fa79950_0, 0; + %jmp T_77.1; +T_77.0 ; + %load/vec4 v0x55dd3fa79950_0; + %cmpi/ne 0, 0, 5; + %jmp/0xz T_77.2, 4; + %load/vec4 v0x55dd3fa79950_0; + %addi 1, 0, 5; + %assign/vec4 v0x55dd3fa79950_0, 0; +T_77.2 ; + %load/vec4 v0x55dd3fa7aa50_0; + %flag_set/vec4 8; + %jmp/0xz T_77.4, 8; + %pushi/vec4 1, 0, 5; + %assign/vec4 v0x55dd3fa79950_0, 0; +T_77.4 ; +T_77.1 ; + %jmp T_77; + .thread T_77; + .scope S_0x55dd3fa78850; +T_78 ; + %wait E_0x55dd3fb0ea50; + %load/vec4 v0x55dd3fa7d890_0; + %flag_set/vec4 8; + %jmp/0xz T_78.0, 8; + %pushi/vec4 0, 0, 6; + %assign/vec4 v0x55dd3fa6a000_0, 0; + %jmp T_78.1; +T_78.0 ; + %load/vec4 v0x55dd3fa6a000_0; + %cmpi/ne 0, 0, 6; + %jmp/0xz T_78.2, 4; + %load/vec4 v0x55dd3fa6a000_0; + %addi 1, 0, 6; + %assign/vec4 v0x55dd3fa6a000_0, 0; +T_78.2 ; + %load/vec4 v0x55dd3fa6dfe0_0; + %flag_set/vec4 8; + %jmp/0xz T_78.4, 8; + %pushi/vec4 1, 0, 6; + %assign/vec4 v0x55dd3fa6a000_0, 0; +T_78.4 ; +T_78.1 ; + %jmp T_78; + .thread T_78; + .scope S_0x55dd3fa97580; +T_79 ; + %wait E_0x55dd3fb0ea50; + %load/vec4 v0x55dd3fa8ded0_0; + %flag_set/vec4 8; + %jmp/0xz T_79.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x55dd3fa8fcf0_0, 0; + %jmp T_79.1; +T_79.0 ; + %load/vec4 v0x55dd3fa8fcf0_0; + %cmpi/ne 0, 0, 2; + %jmp/0xz T_79.2, 4; + %load/vec4 v0x55dd3fa8fcf0_0; + %addi 1, 0, 2; + %assign/vec4 v0x55dd3fa8fcf0_0, 0; +T_79.2 ; + %load/vec4 v0x55dd3fa924f0_0; + %flag_set/vec4 8; + %jmp/0xz T_79.4, 8; + %pushi/vec4 1, 0, 2; + %assign/vec4 v0x55dd3fa8fcf0_0, 0; +T_79.4 ; +T_79.1 ; + %jmp T_79; + .thread T_79; + .scope S_0x55dd3faf4800; +T_80 ; + %wait E_0x55dd3fb0ea50; + %load/vec4 v0x55dd3fb13560_0; + %flag_set/vec4 8; + %jmp/0xz T_80.0, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3f7e4010_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3f7e41f0_0, 0; + %pushi/vec4 0, 0, 36; + %assign/vec4 v0x55dd3fb13600_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3f819e20_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3f7873d0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3f7dd8b0_0, 0; + %jmp T_80.1; +T_80.0 ; + %load/vec4 v0x55dd3f7e41f0_0; + %load/vec4 v0x55dd3f7e4150_0; + %inv; + %and; + %flag_set/vec4 8; + %jmp/0xz T_80.2, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3f7e41f0_0, 0; +T_80.2 ; + %load/vec4 v0x55dd3f7e4010_0; + %load/vec4 v0x55dd3f7e4150_0; + %inv; + %and; + %flag_set/vec4 8; + %jmp/0xz T_80.4, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3f7e4010_0, 0; + %load/vec4 v0x55dd3f7e40b0_0; + %assign/vec4 v0x55dd3fb13600_0, 0; +T_80.4 ; + %load/vec4 v0x55dd3f7d13c0_0; + %flag_set/vec4 8; + %jmp/0xz T_80.6, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3f766320_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3f7664a0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3f766620_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3f787190_0, 0; +T_80.6 ; + %load/vec4 v0x55dd3f6be1e0_0; + %load/vec4 v0x55dd3f6a7f80_0; + %or; + %load/vec4 v0x55dd3f6a8020_0; + %or; + %load/vec4 v0x55dd3f6a80c0_0; + %or; + %flag_set/vec4 8; + %jmp/0xz T_80.8, 8; + %load/vec4 v0x55dd3f6be1e0_0; + %flag_set/vec4 8; + %jmp/0xz T_80.10, 8; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x55dd3f766320_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3f7664a0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3f766620_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3f787190_0, 0; + %jmp T_80.11; +T_80.10 ; + %load/vec4 v0x55dd3f6a7f80_0; + %flag_set/vec4 8; + %jmp/0xz T_80.12, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3f766320_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x55dd3f7664a0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3f766620_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3f787190_0, 0; + %jmp T_80.13; +T_80.12 ; + %load/vec4 v0x55dd3f6a8020_0; + %load/vec4 v0x55dd3f6a80c0_0; + %and; + %flag_set/vec4 8; + %jmp/0xz T_80.14, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3f766320_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3f7664a0_0, 0; + %load/vec4 v0x55dd3f819e20_0; + %assign/vec4 v0x55dd3f766620_0, 0; + %load/vec4 v0x55dd3f819e20_0; + %inv; + %assign/vec4 v0x55dd3f787190_0, 0; + %load/vec4 v0x55dd3f819e20_0; + %inv; + %assign/vec4 v0x55dd3f819e20_0, 0; + %jmp T_80.15; +T_80.14 ; + %load/vec4 v0x55dd3f6a8020_0; + %flag_set/vec4 8; + %jmp/0xz T_80.16, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3f766320_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3f7664a0_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x55dd3f766620_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3f787190_0, 0; + %jmp T_80.17; +T_80.16 ; + %load/vec4 v0x55dd3f6a80c0_0; + %flag_set/vec4 8; + %jmp/0xz T_80.18, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3f766320_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3f7664a0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3f766620_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x55dd3f787190_0, 0; +T_80.18 ; +T_80.17 ; +T_80.15 ; +T_80.13 ; +T_80.11 ; +T_80.8 ; + %load/vec4 v0x55dd3f6c7f80_0; + %flag_set/vec4 8; + %jmp/0xz T_80.20, 8; + %load/vec4 v0x55dd3f766620_0; + %flag_set/vec4 8; + %jmp/0xz T_80.22, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3f819e20_0, 0; +T_80.22 ; + %load/vec4 v0x55dd3f787190_0; + %flag_set/vec4 8; + %jmp/0xz T_80.24, 8; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x55dd3f819e20_0, 0; +T_80.24 ; +T_80.20 ; + %load/vec4 v0x55dd3f7d1530_0; + %load/vec4 v0x55dd3f6a67d0_0; + %or; + %flag_set/vec4 8; + %jmp/0xz T_80.26, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3f6a6710_0, 0; +T_80.26 ; + %load/vec4 v0x55dd3f6bdf00_0; + %load/vec4 v0x55dd3f6a6650_0; + %or; + %flag_set/vec4 8; + %jmp/0xz T_80.28, 8; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x55dd3f6a6710_0, 0; +T_80.28 ; + %load/vec4 v0x55dd3f7d12f0_0; + %load/vec4 v0x55dd3f7dda20_0; + %or; + %flag_set/vec4 8; + %jmp/0xz T_80.30, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3f7d4aa0_0, 0; +T_80.30 ; + %load/vec4 v0x55dd3f7d11b0_0; + %load/vec4 v0x55dd3f7d1530_0; + %load/vec4 v0x55dd3f7d1250_0; + %and; + %or; + %flag_set/vec4 8; + %jmp/0xz T_80.32, 8; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x55dd3f7d4aa0_0, 0; +T_80.32 ; + %load/vec4 v0x55dd3f7dda20_0; + %flag_set/vec4 8; + %jmp/0xz T_80.34, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3f819c00_0, 0; +T_80.34 ; + %load/vec4 v0x55dd3f6bdfd0_0; + %load/vec4 v0x55dd3f7d1490_0; + %inv; + %and; + %flag_set/vec4 8; + %jmp/0xz T_80.36, 8; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x55dd3f819c00_0, 0; +T_80.36 ; + %load/vec4 v0x55dd3f7d7f60_0; + %flag_set/vec4 8; + %jmp/0xz T_80.38, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3f7dd8b0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3f7873d0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3f7d1490_0, 0; +T_80.38 ; + %load/vec4 v0x55dd3f7dd950_0; + %flag_set/vec4 8; + %jmp/0xz T_80.40, 8; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x55dd3f7dd8b0_0, 0; +T_80.40 ; + %load/vec4 v0x55dd3f6a8200_0; + %flag_set/vec4 8; + %jmp/0xz T_80.42, 8; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x55dd3f7873d0_0, 0; +T_80.42 ; + %load/vec4 v0x55dd3f7d12f0_0; + %flag_set/vec4 8; + %jmp/0xz T_80.44, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3f7d1490_0, 0; +T_80.44 ; + %load/vec4 v0x55dd3f6c7f80_0; + %load/vec4 v0x55dd3fb13870_0; + %and; + %flag_set/vec4 8; + %jmp/0xz T_80.46, 8; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x55dd3f7d1490_0, 0; +T_80.46 ; + %load/vec4 v0x55dd3f6c7f80_0; + %flag_set/vec4 8; + %jmp/0xz T_80.48, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3f7d4aa0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3f819c00_0, 0; +T_80.48 ; + %load/vec4 v0x55dd3f819d60_0; + %flag_set/vec4 8; + %jmp/0xz T_80.50, 8; + %load/vec4 v0x55dd3f7e8700_0; + %assign/vec4 v0x55dd3f6ace00_0, 0; + %load/vec4 v0x55dd3fb134c0_0; + %assign/vec4 v0x55dd3f6acee0_0, 0; + %load/vec4 v0x55dd3fb13910_0; + %assign/vec4 v0x55dd3f6a64b0_0, 0; +T_80.50 ; + %load/vec4 v0x55dd3f6a6570_0; + %load/vec4 v0x55dd3f7e87e0_0; + %or; + %assign/vec4 v0x55dd3f6a6570_0, 0; + %load/vec4 v0x55dd3f819b30_0; + %flag_set/vec4 8; + %jmp/0xz T_80.52, 8; + %pushi/vec4 0, 0, 36; + %assign/vec4 v0x55dd3f6a6570_0, 0; +T_80.52 ; + %load/vec4 v0x55dd3fb136e0_0; + %flag_set/vec4 8; + %jmp/0xz T_80.54, 8; + %load/vec4 v0x55dd3f6a6570_0; + %load/vec4 v0x55dd3fb13600_0; + %or; + %assign/vec4 v0x55dd3f6a6570_0, 0; +T_80.54 ; + %load/vec4 v0x55dd3f7dda20_0; + %load/vec4 v0x55dd3f6bdf00_0; + %or; + %flag_set/vec4 8; + %jmp/0xz T_80.56, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3f7d4860_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3f6be140_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3f819ca0_0, 0; +T_80.56 ; + %load/vec4 v0x55dd3f7d7e20_0; + %flag_set/vec4 8; + %jmp/0xz T_80.58, 8; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x55dd3f7d4860_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x55dd3f7e4010_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3f6be140_0, 0; +T_80.58 ; + %load/vec4 v0x55dd3f7d4900_0; + %flag_set/vec4 8; + %jmp/0xz T_80.60, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3f7d4860_0, 0; +T_80.60 ; + %load/vec4 v0x55dd3f6c8160_0; + %flag_set/vec4 8; + %jmp/0xz T_80.62, 8; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x55dd3f819ca0_0, 0; +T_80.62 ; + %load/vec4 v0x55dd3f6bde60_0; + %flag_set/vec4 8; + %jmp/0xz T_80.64, 8; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x55dd3f6be140_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x55dd3f7e41f0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3f7d4860_0, 0; +T_80.64 ; +T_80.1 ; + %jmp T_80; + .thread T_80; + .scope S_0x55dd3faf65b0; +T_81 ; + %wait E_0x55dd3f991ff0; + %load/vec4 v0x55dd3fb14700_0; + %flag_set/vec4 8; + %jmp/0xz T_81.0, 8; + %pushi/vec4 0, 0, 13; + %assign/vec4 v0x55dd3fb14620_0, 0; + %jmp T_81.1; +T_81.0 ; + %load/vec4 v0x55dd3fb14620_0; + %cmpi/ne 0, 0, 13; + %jmp/0xz T_81.2, 4; + %load/vec4 v0x55dd3fb14620_0; + %addi 1, 0, 13; + %assign/vec4 v0x55dd3fb14620_0, 0; +T_81.2 ; + %load/vec4 v0x55dd3fb14450_0; + %flag_set/vec4 8; + %jmp/0xz T_81.4, 8; + %pushi/vec4 1, 0, 13; + %assign/vec4 v0x55dd3fb14620_0, 0; +T_81.4 ; +T_81.1 ; + %jmp T_81; + .thread T_81; + .scope S_0x55dd3faf8050; +T_82 ; + %wait E_0x55dd3f9a5d40; + %load/vec4 v0x55dd3fb14e90_0; + %flag_set/vec4 8; + %jmp/0xz T_82.0, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x55dd3fb14db0_0, 0; + %jmp T_82.1; +T_82.0 ; + %load/vec4 v0x55dd3fb14db0_0; + %cmpi/ne 0, 0, 3; + %jmp/0xz T_82.2, 4; + %load/vec4 v0x55dd3fb14db0_0; + %addi 1, 0, 3; + %assign/vec4 v0x55dd3fb14db0_0, 0; +T_82.2 ; + %load/vec4 v0x55dd3fb14be0_0; + %flag_set/vec4 8; + %jmp/0xz T_82.4, 8; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x55dd3fb14db0_0, 0; +T_82.4 ; +T_82.1 ; + %jmp T_82; + .thread T_82; + .scope S_0x55dd3fb14fd0; +T_83 ; + %wait E_0x55dd3f99b260; + %load/vec4 v0x55dd3fb15590_0; + %inv; + %flag_set/vec4 8; + %jmp/0xz T_83.0, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb15430_0, 0; + %jmp T_83.1; +T_83.0 ; + %load/vec4 v0x55dd3fb156a0_0; + %assign/vec4 v0x55dd3fb15430_0, 0; +T_83.1 ; + %jmp T_83; + .thread T_83; + .scope S_0x55dd3fb157e0; +T_84 ; + %wait E_0x55dd3f99b260; + %load/vec4 v0x55dd3fb15d50_0; + %inv; + %flag_set/vec4 8; + %jmp/0xz T_84.0, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb15be0_0, 0; + %jmp T_84.1; +T_84.0 ; + %load/vec4 v0x55dd3fb15e40_0; + %assign/vec4 v0x55dd3fb15be0_0, 0; +T_84.1 ; + %jmp T_84; + .thread T_84; + .scope S_0x55dd3faf9af0; +T_85 ; + %wait E_0x55dd3f99b260; + %load/vec4 v0x55dd3fb16ee0_0; + %inv; + %flag_set/vec4 8; + %jmp/0xz T_85.0, 8; + %pushi/vec4 4, 0, 4; + %assign/vec4 v0x55dd3fb16be0_0, 0; + %jmp T_85.1; +T_85.0 ; + %load/vec4 v0x55dd3fb16fd0_0; + %load/vec4 v0x55dd3fb174f0_0; + %and; + %load/vec4 v0x55dd3fb16b20_0; + %and; + %flag_set/vec4 8; + %jmp/0xz T_85.2, 8; + %load/vec4 v0x55dd3fb17070_0; + %load/vec4 v0x55dd3fb16a40_0; + %pad/u 16; + %ix/vec4 3; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x55dd3fb17110, 0, 4; +T_85.2 ; + %load/vec4 v0x55dd3fb16fd0_0; + %load/vec4 v0x55dd3fb16e40_0; + %or; + %inv; + %flag_set/vec4 8; + %jmp/0xz T_85.4, 8; + %pushi/vec4 4, 0, 4; + %assign/vec4 v0x55dd3fb16be0_0, 0; + %jmp T_85.5; +T_85.4 ; + %load/vec4 v0x55dd3fb16be0_0; + %cmpi/ne 0, 0, 4; + %jmp/0xz T_85.6, 4; + %load/vec4 v0x55dd3fb16be0_0; + %subi 1, 0, 4; + %assign/vec4 v0x55dd3fb16be0_0, 0; +T_85.6 ; +T_85.5 ; +T_85.1 ; + %jmp T_85; + .thread T_85; + .scope S_0x55dd3fb23340; +T_86 ; + %wait E_0x55dd3f9ff370; + %load/vec4 v0x55dd3fb23aa0_0; + %flag_set/vec4 8; + %jmp/0xz T_86.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x55dd3fb23b40_0, 0; + %jmp T_86.1; +T_86.0 ; + %load/vec4 v0x55dd3fb23b40_0; + %parti/s 1, 0, 2; + %load/vec4 v0x55dd3fb238d0_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x55dd3fb23b40_0, 0; +T_86.1 ; + %jmp T_86; + .thread T_86; + .scope S_0x55dd3fb23ca0; +T_87 ; + %wait E_0x55dd3f9ff370; + %load/vec4 v0x55dd3fb24400_0; + %flag_set/vec4 8; + %jmp/0xz T_87.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x55dd3fb244a0_0, 0; + %jmp T_87.1; +T_87.0 ; + %load/vec4 v0x55dd3fb244a0_0; + %parti/s 1, 0, 2; + %load/vec4 v0x55dd3fb24230_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x55dd3fb244a0_0, 0; +T_87.1 ; + %jmp T_87; + .thread T_87; + .scope S_0x55dd3fb24600; +T_88 ; + %wait E_0x55dd3f9ff370; + %load/vec4 v0x55dd3fb24e50_0; + %flag_set/vec4 8; + %jmp/0xz T_88.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x55dd3fb25100_0, 0; + %jmp T_88.1; +T_88.0 ; + %load/vec4 v0x55dd3fb25100_0; + %parti/s 1, 0, 2; + %load/vec4 v0x55dd3fb24ca0_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x55dd3fb25100_0, 0; +T_88.1 ; + %jmp T_88; + .thread T_88; + .scope S_0x55dd3fb25270; +T_89 ; + %wait E_0x55dd3f9ff370; + %load/vec4 v0x55dd3fb259b0_0; + %flag_set/vec4 8; + %jmp/0xz T_89.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x55dd3fb25a50_0, 0; + %jmp T_89.1; +T_89.0 ; + %load/vec4 v0x55dd3fb25a50_0; + %parti/s 1, 0, 2; + %load/vec4 v0x55dd3fb25800_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x55dd3fb25a50_0, 0; +T_89.1 ; + %jmp T_89; + .thread T_89; + .scope S_0x55dd3fb1ae70; +T_90 ; + %wait E_0x55dd3f9ff370; + %load/vec4 v0x55dd3fb1b600_0; + %flag_set/vec4 8; + %jmp/0xz T_90.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x55dd3fb1b6c0_0, 0; + %jmp T_90.1; +T_90.0 ; + %load/vec4 v0x55dd3fb1b6c0_0; + %parti/s 1, 0, 2; + %load/vec4 v0x55dd3fb1b430_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x55dd3fb1b6c0_0, 0; +T_90.1 ; + %jmp T_90; + .thread T_90; + .scope S_0x55dd3fb1fb10; +T_91 ; + %wait E_0x55dd3f9ff370; + %load/vec4 v0x55dd3fb202b0_0; + %flag_set/vec4 8; + %jmp/0xz T_91.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x55dd3fb20350_0, 0; + %jmp T_91.1; +T_91.0 ; + %load/vec4 v0x55dd3fb20350_0; + %parti/s 1, 0, 2; + %load/vec4 v0x55dd3fb20130_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x55dd3fb20350_0, 0; +T_91.1 ; + %jmp T_91; + .thread T_91; + .scope S_0x55dd3fb204b0; +T_92 ; + %wait E_0x55dd3f9ff370; + %load/vec4 v0x55dd3fb20bf0_0; + %flag_set/vec4 8; + %jmp/0xz T_92.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x55dd3fb20c90_0, 0; + %jmp T_92.1; +T_92.0 ; + %load/vec4 v0x55dd3fb20c90_0; + %parti/s 1, 0, 2; + %load/vec4 v0x55dd3fb20a40_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x55dd3fb20c90_0, 0; +T_92.1 ; + %jmp T_92; + .thread T_92; + .scope S_0x55dd3fb20df0; +T_93 ; + %wait E_0x55dd3f9ff370; + %load/vec4 v0x55dd3fb21510_0; + %flag_set/vec4 8; + %jmp/0xz T_93.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x55dd3fb215b0_0, 0; + %jmp T_93.1; +T_93.0 ; + %load/vec4 v0x55dd3fb215b0_0; + %parti/s 1, 0, 2; + %load/vec4 v0x55dd3fb21380_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x55dd3fb215b0_0, 0; +T_93.1 ; + %jmp T_93; + .thread T_93; + .scope S_0x55dd3fb21740; +T_94 ; + %wait E_0x55dd3f9ff370; + %load/vec4 v0x55dd3fb21e60_0; + %flag_set/vec4 8; + %jmp/0xz T_94.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x55dd3fb21f00_0, 0; + %jmp T_94.1; +T_94.0 ; + %load/vec4 v0x55dd3fb21f00_0; + %parti/s 1, 0, 2; + %load/vec4 v0x55dd3fb21cd0_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x55dd3fb21f00_0, 0; +T_94.1 ; + %jmp T_94; + .thread T_94; + .scope S_0x55dd3fb22090; +T_95 ; + %wait E_0x55dd3f9ff370; + %load/vec4 v0x55dd3fb227b0_0; + %flag_set/vec4 8; + %jmp/0xz T_95.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x55dd3fb22850_0, 0; + %jmp T_95.1; +T_95.0 ; + %load/vec4 v0x55dd3fb22850_0; + %parti/s 1, 0, 2; + %load/vec4 v0x55dd3fb22620_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x55dd3fb22850_0, 0; +T_95.1 ; + %jmp T_95; + .thread T_95; + .scope S_0x55dd3fb25bc0; +T_96 ; + %wait E_0x55dd3f9ff370; + %load/vec4 v0x55dd3fb26350_0; + %flag_set/vec4 8; + %jmp/0xz T_96.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x55dd3fb263f0_0, 0; + %jmp T_96.1; +T_96.0 ; + %load/vec4 v0x55dd3fb263f0_0; + %parti/s 1, 0, 2; + %load/vec4 v0x55dd3fb26150_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x55dd3fb263f0_0, 0; +T_96.1 ; + %jmp T_96; + .thread T_96; + .scope S_0x55dd3fb229e0; +T_97 ; + %wait E_0x55dd3f9ff370; + %load/vec4 v0x55dd3fb23140_0; + %flag_set/vec4 8; + %jmp/0xz T_97.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x55dd3fb231e0_0, 0; + %jmp T_97.1; +T_97.0 ; + %load/vec4 v0x55dd3fb231e0_0; + %parti/s 1, 0, 2; + %load/vec4 v0x55dd3fb22f70_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x55dd3fb231e0_0, 0; +T_97.1 ; + %jmp T_97; + .thread T_97; + .scope S_0x55dd3fb1d500; +T_98 ; + %wait E_0x55dd3f9ff370; + %load/vec4 v0x55dd3fb1dd30_0; + %flag_set/vec4 8; + %jmp/0xz T_98.0, 8; + %pushi/vec4 0, 0, 4; + %assign/vec4 v0x55dd3fb1dc50_0, 0; + %jmp T_98.1; +T_98.0 ; + %load/vec4 v0x55dd3fb1dc50_0; + %cmpi/ne 0, 0, 4; + %jmp/0xz T_98.2, 4; + %load/vec4 v0x55dd3fb1dc50_0; + %addi 1, 0, 4; + %assign/vec4 v0x55dd3fb1dc50_0, 0; +T_98.2 ; + %load/vec4 v0x55dd3fb1dad0_0; + %flag_set/vec4 8; + %jmp/0xz T_98.4, 8; + %pushi/vec4 1, 0, 4; + %assign/vec4 v0x55dd3fb1dc50_0, 0; +T_98.4 ; +T_98.1 ; + %jmp T_98; + .thread T_98; + .scope S_0x55dd3fb1dee0; +T_99 ; + %wait E_0x55dd3f9ff370; + %load/vec4 v0x55dd3fb1e6f0_0; + %flag_set/vec4 8; + %jmp/0xz T_99.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x55dd3fb1e610_0, 0; + %jmp T_99.1; +T_99.0 ; + %load/vec4 v0x55dd3fb1e610_0; + %cmpi/ne 0, 0, 2; + %jmp/0xz T_99.2, 4; + %load/vec4 v0x55dd3fb1e610_0; + %addi 1, 0, 2; + %assign/vec4 v0x55dd3fb1e610_0, 0; +T_99.2 ; + %load/vec4 v0x55dd3fb1e440_0; + %flag_set/vec4 8; + %jmp/0xz T_99.4, 8; + %pushi/vec4 1, 0, 2; + %assign/vec4 v0x55dd3fb1e610_0, 0; +T_99.4 ; +T_99.1 ; + %jmp T_99; + .thread T_99; + .scope S_0x55dd3fb1e810; +T_100 ; + %wait E_0x55dd3f9ff370; + %load/vec4 v0x55dd3fb1f0a0_0; + %flag_set/vec4 8; + %jmp/0xz T_100.0, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x55dd3fb1efc0_0, 0; + %jmp T_100.1; +T_100.0 ; + %load/vec4 v0x55dd3fb1efc0_0; + %cmpi/ne 0, 0, 3; + %jmp/0xz T_100.2, 4; + %load/vec4 v0x55dd3fb1efc0_0; + %addi 1, 0, 3; + %assign/vec4 v0x55dd3fb1efc0_0, 0; +T_100.2 ; + %load/vec4 v0x55dd3fb1edc0_0; + %flag_set/vec4 8; + %jmp/0xz T_100.4, 8; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x55dd3fb1efc0_0, 0; +T_100.4 ; +T_100.1 ; + %jmp T_100; + .thread T_100; + .scope S_0x55dd3fb1f1c0; +T_101 ; + %wait E_0x55dd3f9ff370; + %load/vec4 v0x55dd3fb1f9f0_0; + %flag_set/vec4 8; + %jmp/0xz T_101.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x55dd3fb1f910_0, 0; + %jmp T_101.1; +T_101.0 ; + %load/vec4 v0x55dd3fb1f910_0; + %cmpi/ne 0, 0, 2; + %jmp/0xz T_101.2, 4; + %load/vec4 v0x55dd3fb1f910_0; + %addi 1, 0, 2; + %assign/vec4 v0x55dd3fb1f910_0, 0; +T_101.2 ; + %load/vec4 v0x55dd3fb1f740_0; + %flag_set/vec4 8; + %jmp/0xz T_101.4, 8; + %pushi/vec4 1, 0, 2; + %assign/vec4 v0x55dd3fb1f910_0, 0; +T_101.4 ; +T_101.1 ; + %jmp T_101; + .thread T_101; + .scope S_0x55dd3fb1b820; +T_102 ; + %wait E_0x55dd3f9ff370; + %load/vec4 v0x55dd3fb1c090_0; + %flag_set/vec4 8; + %jmp/0xz T_102.0, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x55dd3fb1bfb0_0, 0; + %jmp T_102.1; +T_102.0 ; + %load/vec4 v0x55dd3fb1bfb0_0; + %cmpi/ne 0, 0, 3; + %jmp/0xz T_102.2, 4; + %load/vec4 v0x55dd3fb1bfb0_0; + %addi 1, 0, 3; + %assign/vec4 v0x55dd3fb1bfb0_0, 0; +T_102.2 ; + %load/vec4 v0x55dd3fb1be00_0; + %flag_set/vec4 8; + %jmp/0xz T_102.4, 8; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x55dd3fb1bfb0_0, 0; +T_102.4 ; +T_102.1 ; + %jmp T_102; + .thread T_102; + .scope S_0x55dd3fb1c1c0; +T_103 ; + %wait E_0x55dd3f9ff370; + %load/vec4 v0x55dd3fb1ca80_0; + %flag_set/vec4 8; + %jmp/0xz T_103.0, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x55dd3fb1c9a0_0, 0; + %jmp T_103.1; +T_103.0 ; + %load/vec4 v0x55dd3fb1c9a0_0; + %cmpi/ne 0, 0, 3; + %jmp/0xz T_103.2, 4; + %load/vec4 v0x55dd3fb1c9a0_0; + %addi 1, 0, 3; + %assign/vec4 v0x55dd3fb1c9a0_0, 0; +T_103.2 ; + %load/vec4 v0x55dd3fb1c7d0_0; + %flag_set/vec4 8; + %jmp/0xz T_103.4, 8; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x55dd3fb1c9a0_0, 0; +T_103.4 ; +T_103.1 ; + %jmp T_103; + .thread T_103; + .scope S_0x55dd3fb1cbf0; +T_104 ; + %wait E_0x55dd3f9ff370; + %load/vec4 v0x55dd3fb1d3e0_0; + %flag_set/vec4 8; + %jmp/0xz T_104.0, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x55dd3fb1d300_0, 0; + %jmp T_104.1; +T_104.0 ; + %load/vec4 v0x55dd3fb1d300_0; + %cmpi/ne 0, 0, 3; + %jmp/0xz T_104.2, 4; + %load/vec4 v0x55dd3fb1d300_0; + %addi 1, 0, 3; + %assign/vec4 v0x55dd3fb1d300_0, 0; +T_104.2 ; + %load/vec4 v0x55dd3fb1d170_0; + %flag_set/vec4 8; + %jmp/0xz T_104.4, 8; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x55dd3fb1d300_0, 0; +T_104.4 ; +T_104.1 ; + %jmp T_104; + .thread T_104; + .scope S_0x55dd3fafb590; +T_105 ; + %wait E_0x55dd3f99dd20; + %load/vec4 v0x55dd3fb2b630_0; + %load/vec4 v0x55dd3fb2b250_0; + %or; + %flag_set/vec4 8; + %jmp/0xz T_105.0, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb2ab50_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x55dd3fb2b870_0, 0; +T_105.0 ; + %load/vec4 v0x55dd3fb2c030_0; + %load/vec4 v0x55dd3fb2c0d0_0; + %or; + %load/vec4 v0x55dd3fb2c170_0; + %or; + %load/vec4 v0x55dd3fb2c210_0; + %or; + %flag_set/vec4 8; + %jmp/0xz T_105.2, 8; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x55dd3fb2ab50_0, 0; +T_105.2 ; + %load/vec4 v0x55dd3fb2b9b0_0; + %flag_set/vec4 8; + %jmp/0xz T_105.4, 8; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x55dd3fb2b700_0, 0; +T_105.4 ; + %load/vec4 v0x55dd3fb2a880_0; + %inv; + %flag_set/vec4 8; + %jmp/0xz T_105.6, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb2b320_0, 0; +T_105.6 ; + %load/vec4 v0x55dd3fb2b3c0_0; + %flag_set/vec4 8; + %jmp/0xz T_105.8, 8; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x55dd3fb2b320_0, 0; +T_105.8 ; + %load/vec4 v0x55dd3fb2ba80_0; + %flag_set/vec4 8; + %jmp/0xz T_105.10, 8; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x55dd3fb2b910_0, 0; +T_105.10 ; + %load/vec4 v0x55dd3fb2a640_0; + %flag_set/vec4 8; + %jmp/0xz T_105.12, 8; + %pushi/vec4 0, 0, 36; + %ix/getv 3, v0x55dd3fb2a7a0_0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x55dd3fb2a580, 0, 4; +T_105.12 ; + %load/vec4 v0x55dd3fb2b910_0; + %flag_set/vec4 8; + %jmp/0xz T_105.14, 8; + %ix/getv 4, v0x55dd3fb2a7a0_0; + %load/vec4a v0x55dd3fb2a580, 4; + %load/vec4 v0x55dd3fb2c2b0_0; + %or; + %ix/getv 3, v0x55dd3fb2a7a0_0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x55dd3fb2a580, 0, 4; +T_105.14 ; + %load/vec4 v0x55dd3fb2bb50_0; + %flag_set/vec4 8; + %jmp/0xz T_105.16, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb2b700_0, 0; + %load/vec4 v0x55dd3fb2f130_0; + %assign/vec4 v0x55dd3fb2b870_0, 0; +T_105.16 ; + %load/vec4 v0x55dd3fb2bec0_0; + %flag_set/vec4 8; + %jmp/0xz T_105.18, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb2ab50_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb2b320_0, 0; +T_105.18 ; + %load/vec4 v0x55dd3fb2bf60_0; + %flag_set/vec4 8; + %jmp/0xz T_105.20, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb2b870_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb2b910_0, 0; +T_105.20 ; + %jmp T_105; + .thread T_105; + .scope S_0x55dd3faa7730; +T_106 ; + %wait E_0x55dd3f9f4a20; + %load/vec4 v0x55dd3fb30190_0; + %flag_set/vec4 8; + %jmp/0xz T_106.0, 8; + %pushi/vec4 0, 0, 13; + %assign/vec4 v0x55dd3fb300b0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb2ff30_0, 0; + %jmp T_106.1; +T_106.0 ; + %load/vec4 v0x55dd3fb300b0_0; + %cmpi/ne 0, 0, 13; + %jmp/0xz T_106.2, 4; + %load/vec4 v0x55dd3fb300b0_0; + %addi 1, 0, 13; + %assign/vec4 v0x55dd3fb300b0_0, 0; +T_106.2 ; + %load/vec4 v0x55dd3fb2fe20_0; + %flag_set/vec4 8; + %jmp/0xz T_106.4, 8; + %pushi/vec4 1, 0, 13; + %assign/vec4 v0x55dd3fb300b0_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x55dd3fb2ff30_0, 0; +T_106.4 ; + %load/vec4 v0x55dd3fb2fff0_0; + %flag_set/vec4 8; + %jmp/0xz T_106.6, 8; + %pushi/vec4 0, 0, 13; + %assign/vec4 v0x55dd3fb300b0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb2ff30_0, 0; +T_106.6 ; +T_106.1 ; + %jmp T_106; + .thread T_106; + .scope S_0x55dd3faa91d0; +T_107 ; + %wait E_0x55dd3fa79ab0; + %load/vec4 v0x55dd3fb309b0_0; + %flag_set/vec4 8; + %jmp/0xz T_107.0, 8; + %pushi/vec4 0, 0, 7; + %assign/vec4 v0x55dd3fb308d0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb30750_0, 0; + %jmp T_107.1; +T_107.0 ; + %load/vec4 v0x55dd3fb308d0_0; + %cmpi/ne 0, 0, 7; + %jmp/0xz T_107.2, 4; + %load/vec4 v0x55dd3fb308d0_0; + %addi 1, 0, 7; + %assign/vec4 v0x55dd3fb308d0_0, 0; +T_107.2 ; + %load/vec4 v0x55dd3fb30690_0; + %flag_set/vec4 8; + %jmp/0xz T_107.4, 8; + %pushi/vec4 1, 0, 7; + %assign/vec4 v0x55dd3fb308d0_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x55dd3fb30750_0, 0; +T_107.4 ; + %load/vec4 v0x55dd3fb30810_0; + %flag_set/vec4 8; + %jmp/0xz T_107.6, 8; + %pushi/vec4 0, 0, 7; + %assign/vec4 v0x55dd3fb308d0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb30750_0, 0; +T_107.6 ; +T_107.1 ; + %jmp T_107; + .thread T_107; + .scope S_0x55dd3faaaca0; +T_108 ; + %wait E_0x55dd3fb30b10; + %load/vec4 v0x55dd3fb31210_0; + %flag_set/vec4 8; + %jmp/0xz T_108.0, 8; + %pushi/vec4 0, 0, 7; + %assign/vec4 v0x55dd3fb31130_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb30fb0_0, 0; + %jmp T_108.1; +T_108.0 ; + %load/vec4 v0x55dd3fb31130_0; + %cmpi/ne 0, 0, 7; + %jmp/0xz T_108.2, 4; + %load/vec4 v0x55dd3fb31130_0; + %addi 1, 0, 7; + %assign/vec4 v0x55dd3fb31130_0, 0; +T_108.2 ; + %load/vec4 v0x55dd3fb30ef0_0; + %flag_set/vec4 8; + %jmp/0xz T_108.4, 8; + %pushi/vec4 1, 0, 7; + %assign/vec4 v0x55dd3fb31130_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x55dd3fb30fb0_0, 0; +T_108.4 ; + %load/vec4 v0x55dd3fb31070_0; + %flag_set/vec4 8; + %jmp/0xz T_108.6, 8; + %pushi/vec4 0, 0, 7; + %assign/vec4 v0x55dd3fb31130_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb30fb0_0, 0; +T_108.6 ; +T_108.1 ; + %jmp T_108; + .thread T_108; + .scope S_0x55dd3fb31480; +T_109 ; + %wait E_0x55dd3fb31690; + %load/vec4 v0x55dd3fb31a60_0; + %inv; + %flag_set/vec4 8; + %jmp/0xz T_109.0, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb318d0_0, 0; + %jmp T_109.1; +T_109.0 ; + %load/vec4 v0x55dd3fb31b70_0; + %assign/vec4 v0x55dd3fb318d0_0, 0; +T_109.1 ; + %jmp T_109; + .thread T_109; + .scope S_0x55dd3fb31cb0; +T_110 ; + %wait E_0x55dd3fb31690; + %load/vec4 v0x55dd3fb32250_0; + %inv; + %flag_set/vec4 8; + %jmp/0xz T_110.0, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb320e0_0, 0; + %jmp T_110.1; +T_110.0 ; + %load/vec4 v0x55dd3fb32340_0; + %assign/vec4 v0x55dd3fb320e0_0, 0; +T_110.1 ; + %jmp T_110; + .thread T_110; + .scope S_0x55dd3faac770; +T_111 ; + %wait E_0x55dd3fb31690; + %load/vec4 v0x55dd3fb32fc0_0; + %inv; + %flag_set/vec4 8; + %jmp/0xz T_111.0, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb32ce0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb329f0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb334c0_0, 0; + %pushi/vec4 0, 0, 18; + %assign/vec4 v0x55dd3fb326f0_0, 0; + %pushi/vec4 0, 0, 36; + %assign/vec4 v0x55dd3fb33580_0, 0; + %jmp T_111.1; +T_111.0 ; + %load/vec4 v0x55dd3fb33660_0; + %flag_set/vec4 8; + %jmp/0xz T_111.2, 8; + %load/vec4 v0x55dd3fb33060_0; + %dup/vec4; + %pushi/vec4 0, 0, 2; + %cmp/u; + %jmp/1 T_111.4, 6; + %dup/vec4; + %pushi/vec4 1, 0, 2; + %cmp/u; + %jmp/1 T_111.5, 6; + %dup/vec4; + %pushi/vec4 2, 0, 2; + %cmp/u; + %jmp/1 T_111.6, 6; + %jmp T_111.7; +T_111.4 ; + %load/vec4 v0x55dd3fb33400_0; + %parti/s 18, 0, 2; + %assign/vec4 v0x55dd3fb326f0_0, 0; + %jmp T_111.7; +T_111.5 ; + %load/vec4 v0x55dd3fb33400_0; + %parti/s 18, 0, 2; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x55dd3fb33580_0, 4, 5; + %jmp T_111.7; +T_111.6 ; + %load/vec4 v0x55dd3fb33400_0; + %parti/s 18, 0, 2; + %ix/load 4, 18, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x55dd3fb33580_0, 4, 5; + %jmp T_111.7; +T_111.7 ; + %pop/vec4 1; +T_111.2 ; + %load/vec4 v0x55dd3fb32f20_0; + %flag_set/vec4 8; + %jmp/0xz T_111.8, 8; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x55dd3fb334c0_0, 0; + %load/vec4 v0x55dd3fb33360_0; + %flag_set/vec4 8; + %jmp/0xz T_111.10, 8; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x55dd3fb32ce0_0, 0; + %jmp T_111.11; +T_111.10 ; + %load/vec4 v0x55dd3fb33140_0; + %flag_set/vec4 8; + %jmp/0xz T_111.12, 8; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x55dd3fb329f0_0, 0; +T_111.12 ; +T_111.11 ; +T_111.8 ; + %load/vec4 v0x55dd3fb32ce0_0; + %load/vec4 v0x55dd3fb32b90_0; + %inv; + %and; + %flag_set/vec4 8; + %jmp/0xz T_111.14, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb32ce0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb334c0_0, 0; +T_111.14 ; + %load/vec4 v0x55dd3fb329f0_0; + %load/vec4 v0x55dd3fb32b90_0; + %inv; + %and; + %flag_set/vec4 8; + %jmp/0xz T_111.16, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb329f0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb334c0_0, 0; + %load/vec4 v0x55dd3fb32ab0_0; + %assign/vec4 v0x55dd3fb33580_0, 0; +T_111.16 ; +T_111.1 ; + %jmp T_111; + .thread T_111; + .scope S_0x55dd3faac770; +T_112 ; + %wait E_0x55dd3fb31400; + %load/vec4 v0x55dd3fb33060_0; + %dup/vec4; + %pushi/vec4 1, 0, 2; + %cmp/u; + %jmp/1 T_112.0, 6; + %dup/vec4; + %pushi/vec4 2, 0, 2; + %cmp/u; + %jmp/1 T_112.1, 6; + %pushi/vec4 0, 0, 32; + %assign/vec4 v0x55dd3fb331e0_0, 0; + %jmp T_112.3; +T_112.0 ; + %pushi/vec4 0, 0, 14; + %load/vec4 v0x55dd3fb33580_0; + %parti/s 18, 0, 2; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x55dd3fb331e0_0, 0; + %jmp T_112.3; +T_112.1 ; + %pushi/vec4 0, 0, 14; + %load/vec4 v0x55dd3fb33580_0; + %parti/s 18, 18, 6; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x55dd3fb331e0_0, 0; + %jmp T_112.3; +T_112.3 ; + %pop/vec4 1; + %jmp T_112; + .thread T_112, $push; + .scope S_0x55dd3faae210; +T_113 ; + %wait E_0x55dd3fb338d0; + %load/vec4 v0x55dd3fb345b0_0; + %inv; + %flag_set/vec4 8; + %jmp/0xz T_113.0, 8; + %jmp T_113.1; +T_113.0 ; + %load/vec4 v0x55dd3fb34670_0; + %load/vec4 v0x55dd3fb34290_0; + %and; + %flag_set/vec4 8; + %jmp/0xz T_113.2, 8; + %load/vec4 v0x55dd3fb34730_0; + %load/vec4 v0x55dd3fb341b0_0; + %pad/u 16; + %ix/vec4 3; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x55dd3fb34810, 0, 4; +T_113.2 ; +T_113.1 ; + %jmp T_113; + .thread T_113; + .scope S_0x55dd3fb34c50; +T_114 ; + %wait E_0x55dd3fb34f80; + %load/vec4 v0x55dd3fb35820_0; + %flag_set/vec4 8; + %jmp/0xz T_114.0, 8; + %load/vec4 v0x55dd3fb355a0_0; + %load/vec4 v0x55dd3fb352d0_0; + %pad/u 6; + %ix/vec4 3; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x55dd3fb35760, 0, 4; +T_114.0 ; + %load/vec4 v0x55dd3fb352d0_0; + %assign/vec4 v0x55dd3fb353b0_0, 0; + %jmp T_114; + .thread T_114; + .scope S_0x55dd3faafcb0; +T_115 ; + %wait E_0x55dd3fb34f80; + %load/vec4 v0x55dd3fb36140_0; + %inv; + %flag_set/vec4 8; + %jmp/0xz T_115.0, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb36520_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb36480_0, 0; + %jmp T_115.1; +T_115.0 ; + %load/vec4 v0x55dd3fb36010_0; + %load/vec4 v0x55dd3fb36200_0; + %or; + %flag_set/vec4 8; + %jmp/0xz T_115.2, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb36480_0, 0; + %jmp T_115.3; +T_115.2 ; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x55dd3fb36480_0, 0; +T_115.3 ; + %load/vec4 v0x55dd3fb36520_0; + %flag_set/vec4 8; + %jmp/0xz T_115.4, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb36520_0, 0; + %jmp T_115.5; +T_115.4 ; + %load/vec4 v0x55dd3fb36200_0; + %load/vec4 v0x55dd3fb35dc0_0; + %and; + %assign/vec4 v0x55dd3fb36520_0, 0; +T_115.5 ; +T_115.1 ; + %jmp T_115; + .thread T_115; + .scope S_0x55dd3fb366d0; +T_116 ; + %wait E_0x55dd3fb36ac0; + %load/vec4 v0x55dd3fb37360_0; + %flag_set/vec4 8; + %jmp/0xz T_116.0, 8; + %load/vec4 v0x55dd3fb370e0_0; + %load/vec4 v0x55dd3fb36e10_0; + %pad/u 16; + %ix/vec4 3; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x55dd3fb372a0, 0, 4; +T_116.0 ; + %load/vec4 v0x55dd3fb36e10_0; + %assign/vec4 v0x55dd3fb36ef0_0, 0; + %jmp T_116; + .thread T_116; + .scope S_0x55dd3fac4a50; +T_117 ; + %wait E_0x55dd3fb36ac0; + %load/vec4 v0x55dd3fb37c80_0; + %inv; + %flag_set/vec4 8; + %jmp/0xz T_117.0, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb38060_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb37fc0_0, 0; + %jmp T_117.1; +T_117.0 ; + %load/vec4 v0x55dd3fb37b50_0; + %load/vec4 v0x55dd3fb37d40_0; + %or; + %flag_set/vec4 8; + %jmp/0xz T_117.2, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb37fc0_0, 0; + %jmp T_117.3; +T_117.2 ; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x55dd3fb37fc0_0, 0; +T_117.3 ; + %load/vec4 v0x55dd3fb38060_0; + %flag_set/vec4 8; + %jmp/0xz T_117.4, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb38060_0, 0; + %jmp T_117.5; +T_117.4 ; + %load/vec4 v0x55dd3fb37d40_0; + %load/vec4 v0x55dd3fb37900_0; + %and; + %assign/vec4 v0x55dd3fb38060_0, 0; +T_117.5 ; +T_117.1 ; + %jmp T_117; + .thread T_117; + .scope S_0x55dd3faa5c90; +T_118 ; + %wait E_0x55dd3fb38290; + %load/vec4 v0x55dd3fb3b040_0; + %dup/vec4; + %pushi/vec4 0, 0, 5; + %cmp/u; + %jmp/1 T_118.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 5; + %cmp/u; + %jmp/1 T_118.1, 6; + %dup/vec4; + %pushi/vec4 2, 0, 5; + %cmp/u; + %jmp/1 T_118.2, 6; + %dup/vec4; + %pushi/vec4 3, 0, 5; + %cmp/u; + %jmp/1 T_118.3, 6; + %dup/vec4; + %pushi/vec4 4, 0, 5; + %cmp/u; + %jmp/1 T_118.4, 6; + %dup/vec4; + %pushi/vec4 5, 0, 5; + %cmp/u; + %jmp/1 T_118.5, 6; + %dup/vec4; + %pushi/vec4 6, 0, 5; + %cmp/u; + %jmp/1 T_118.6, 6; + %dup/vec4; + %pushi/vec4 7, 0, 5; + %cmp/u; + %jmp/1 T_118.7, 6; + %dup/vec4; + %pushi/vec4 8, 0, 5; + %cmp/u; + %jmp/1 T_118.8, 6; + %dup/vec4; + %pushi/vec4 9, 0, 5; + %cmp/u; + %jmp/1 T_118.9, 6; + %dup/vec4; + %pushi/vec4 10, 0, 5; + %cmp/u; + %jmp/1 T_118.10, 6; + %dup/vec4; + %pushi/vec4 11, 0, 5; + %cmp/u; + %jmp/1 T_118.11, 6; + %dup/vec4; + %pushi/vec4 12, 0, 5; + %cmp/u; + %jmp/1 T_118.12, 6; + %dup/vec4; + %pushi/vec4 13, 0, 5; + %cmp/u; + %jmp/1 T_118.13, 6; + %dup/vec4; + %pushi/vec4 14, 0, 5; + %cmp/u; + %jmp/1 T_118.14, 6; + %dup/vec4; + %pushi/vec4 15, 0, 5; + %cmp/u; + %jmp/1 T_118.15, 6; + %dup/vec4; + %pushi/vec4 16, 0, 5; + %cmp/u; + %jmp/1 T_118.16, 6; + %dup/vec4; + %pushi/vec4 17, 0, 5; + %cmp/u; + %jmp/1 T_118.17, 6; + %dup/vec4; + %pushi/vec4 18, 0, 5; + %cmp/u; + %jmp/1 T_118.18, 6; + %dup/vec4; + %pushi/vec4 19, 0, 5; + %cmp/u; + %jmp/1 T_118.19, 6; + %dup/vec4; + %pushi/vec4 20, 0, 5; + %cmp/u; + %jmp/1 T_118.20, 6; + %dup/vec4; + %pushi/vec4 21, 0, 5; + %cmp/u; + %jmp/1 T_118.21, 6; + %dup/vec4; + %pushi/vec4 22, 0, 5; + %cmp/u; + %jmp/1 T_118.22, 6; + %dup/vec4; + %pushi/vec4 23, 0, 5; + %cmp/u; + %jmp/1 T_118.23, 6; + %dup/vec4; + %pushi/vec4 24, 0, 5; + %cmp/u; + %jmp/1 T_118.24, 6; + %dup/vec4; + %pushi/vec4 25, 0, 5; + %cmp/u; + %jmp/1 T_118.25, 6; + %dup/vec4; + %pushi/vec4 26, 0, 5; + %cmp/u; + %jmp/1 T_118.26, 6; + %dup/vec4; + %pushi/vec4 27, 0, 5; + %cmp/u; + %jmp/1 T_118.27, 6; + %dup/vec4; + %pushi/vec4 28, 0, 5; + %cmp/u; + %jmp/1 T_118.28, 6; + %dup/vec4; + %pushi/vec4 29, 0, 5; + %cmp/u; + %jmp/1 T_118.29, 6; + %dup/vec4; + %pushi/vec4 30, 0, 5; + %cmp/u; + %jmp/1 T_118.30, 6; + %dup/vec4; + %pushi/vec4 31, 0, 5; + %cmp/u; + %jmp/1 T_118.31, 6; + %pushi/vec4 0, 0, 32; + %assign/vec4 v0x55dd3fb3b1e0_0, 0; + %jmp T_118.33; +T_118.0 ; + %pushi/vec4 0, 0, 20; + %load/vec4 v0x55dd3fb3ab60_0; + %concat/vec4; draw_concat_vec4 + %load/vec4 v0x55dd3fb3a4a0_0; + %concat/vec4; draw_concat_vec4 + %load/vec4 v0x55dd3fb3af80_0; + %concat/vec4; draw_concat_vec4 + %load/vec4 v0x55dd3fb3b520_0; + %concat/vec4; draw_concat_vec4 + %load/vec4 v0x55dd3fb39c00_0; + %concat/vec4; draw_concat_vec4 + %load/vec4 v0x55dd3fb39e40_0; + %concat/vec4; draw_concat_vec4 + %load/vec4 v0x55dd3fb39fc0_0; + %concat/vec4; draw_concat_vec4 + %load/vec4 v0x55dd3fb39d80_0; + %concat/vec4; draw_concat_vec4 + %load/vec4 v0x55dd3fb39f00_0; + %concat/vec4; draw_concat_vec4 + %load/vec4 v0x55dd3fb39cc0_0; + %concat/vec4; draw_concat_vec4 + %load/vec4 v0x55dd3fb3a080_0; + %concat/vec4; draw_concat_vec4 + %load/vec4 v0x55dd3fb3a140_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x55dd3fb3b1e0_0, 0; + %jmp T_118.33; +T_118.1 ; + %pushi/vec4 0, 0, 32; + %assign/vec4 v0x55dd3fb3b1e0_0, 0; + %jmp T_118.33; +T_118.2 ; + %pushi/vec4 0, 0, 22; + %load/vec4 v0x55dd3fb3b6a0_0; + %concat/vec4; draw_concat_vec4 + %load/vec4 v0x55dd3fb3b820_0; + %concat/vec4; draw_concat_vec4 + %concati/vec4 0, 0, 1; + %concati/vec4 0, 0, 1; + %concati/vec4 0, 0, 1; + %concati/vec4 0, 0, 1; + %load/vec4 v0x55dd3fb39b40_0; + %concat/vec4; draw_concat_vec4 + %load/vec4 v0x55dd3fb39a80_0; + %concat/vec4; draw_concat_vec4 + %load/vec4 v0x55dd3fb399c0_0; + %concat/vec4; draw_concat_vec4 + %load/vec4 v0x55dd3fb39900_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x55dd3fb3b1e0_0, 0; + %jmp T_118.33; +T_118.3 ; + %pushi/vec4 0, 0, 32; + %assign/vec4 v0x55dd3fb3b1e0_0, 0; + %jmp T_118.33; +T_118.4 ; + %pushi/vec4 0, 0, 26; + %load/vec4 v0x55dd3fb3bb20_0; + %concat/vec4; draw_concat_vec4 + %load/vec4 v0x55dd3fb3ba60_0; + %concat/vec4; draw_concat_vec4 + %load/vec4 v0x55dd3fb3b5e0_0; + %concat/vec4; draw_concat_vec4 + %load/vec4 v0x55dd3fb3b8e0_0; + %concat/vec4; draw_concat_vec4 + %load/vec4 v0x55dd3fb3b9a0_0; + %concat/vec4; draw_concat_vec4 + %concati/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb3b1e0_0, 0; + %jmp T_118.33; +T_118.5 ; + %pushi/vec4 0, 0, 32; + %assign/vec4 v0x55dd3fb3b1e0_0, 0; + %jmp T_118.33; +T_118.6 ; + %pushi/vec4 0, 0, 14; + %load/vec4 v0x55dd3fb38650_0; + %parti/s 18, 18, 6; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x55dd3fb3b1e0_0, 0; + %jmp T_118.33; +T_118.7 ; + %pushi/vec4 0, 0, 14; + %load/vec4 v0x55dd3fb38650_0; + %parti/s 18, 0, 2; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x55dd3fb3b1e0_0, 0; + %jmp T_118.33; +T_118.8 ; + %pushi/vec4 0, 0, 14; + %load/vec4 v0x55dd3fb3a2e0_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x55dd3fb3b1e0_0, 0; + %jmp T_118.33; +T_118.9 ; + %pushi/vec4 0, 0, 32; + %assign/vec4 v0x55dd3fb3b1e0_0, 0; + %jmp T_118.33; +T_118.10 ; + %pushi/vec4 0, 0, 14; + %load/vec4 v0x55dd3fb39820_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x55dd3fb3b1e0_0, 0; + %jmp T_118.33; +T_118.11 ; + %pushi/vec4 0, 0, 14; + %load/vec4 v0x55dd3fb3a560_0; + %parti/s 18, 18, 6; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x55dd3fb3b1e0_0, 0; + %jmp T_118.33; +T_118.12 ; + %pushi/vec4 0, 0, 14; + %load/vec4 v0x55dd3fb3a560_0; + %parti/s 18, 0, 2; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x55dd3fb3b1e0_0, 0; + %jmp T_118.33; +T_118.13 ; + %pushi/vec4 0, 0, 14; + %load/vec4 v0x55dd3fb3a720_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x55dd3fb3b1e0_0, 0; + %jmp T_118.33; +T_118.14 ; + %pushi/vec4 0, 0, 14; + %load/vec4 v0x55dd3fb3a200_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x55dd3fb3b1e0_0, 0; + %jmp T_118.33; +T_118.15 ; + %pushi/vec4 0, 0, 10; + %load/vec4 v0x55dd3fb3a8c0_0; + %concat/vec4; draw_concat_vec4 + %load/vec4 v0x55dd3fb3aa80_0; + %concat/vec4; draw_concat_vec4 + %load/vec4 v0x55dd3fb3a9a0_0; + %concat/vec4; draw_concat_vec4 + %load/vec4 v0x55dd3fb3a800_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x55dd3fb3b1e0_0, 0; + %jmp T_118.33; +T_118.16 ; + %pushi/vec4 0, 0, 14; + %load/vec4 v0x55dd3fb3a3c0_0; + %parti/s 18, 18, 6; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x55dd3fb3b1e0_0, 0; + %jmp T_118.33; +T_118.17 ; + %pushi/vec4 0, 0, 14; + %load/vec4 v0x55dd3fb3a3c0_0; + %parti/s 18, 0, 2; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x55dd3fb3b1e0_0, 0; + %jmp T_118.33; +T_118.18 ; + %pushi/vec4 0, 0, 14; + %load/vec4 v0x55dd3fb38490_0; + %parti/s 18, 18, 6; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x55dd3fb3b1e0_0, 0; + %jmp T_118.33; +T_118.19 ; + %pushi/vec4 0, 0, 14; + %load/vec4 v0x55dd3fb38490_0; + %parti/s 18, 0, 2; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x55dd3fb3b1e0_0, 0; + %jmp T_118.33; +T_118.20 ; + %pushi/vec4 0, 0, 14; + %load/vec4 v0x55dd3fb3a640_0; + %parti/s 18, 18, 6; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x55dd3fb3b1e0_0, 0; + %jmp T_118.33; +T_118.21 ; + %pushi/vec4 0, 0, 14; + %load/vec4 v0x55dd3fb3a640_0; + %parti/s 18, 0, 2; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x55dd3fb3b1e0_0, 0; + %jmp T_118.33; +T_118.22 ; + %load/vec4 v0x55dd3fb38a40_0; + %load/vec4 v0x55dd3fb38b20_0; + %concat/vec4; draw_concat_vec4 + %load/vec4 v0x55dd3fb39010_0; + %concat/vec4; draw_concat_vec4 + %load/vec4 v0x55dd3fb390f0_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x55dd3fb3b1e0_0, 0; + %jmp T_118.33; +T_118.23 ; + %load/vec4 v0x55dd3fb391d0_0; + %load/vec4 v0x55dd3fb392b0_0; + %concat/vec4; draw_concat_vec4 + %load/vec4 v0x55dd3fb394a0_0; + %concat/vec4; draw_concat_vec4 + %load/vec4 v0x55dd3fb39580_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x55dd3fb3b1e0_0, 0; + %jmp T_118.33; +T_118.24 ; + %load/vec4 v0x55dd3fb39660_0; + %load/vec4 v0x55dd3fb39740_0; + %concat/vec4; draw_concat_vec4 + %load/vec4 v0x55dd3fb38c90_0; + %concat/vec4; draw_concat_vec4 + %load/vec4 v0x55dd3fb38d70_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x55dd3fb3b1e0_0, 0; + %jmp T_118.33; +T_118.25 ; + %load/vec4 v0x55dd3fb38e50_0; + %load/vec4 v0x55dd3fb38f30_0; + %concat/vec4; draw_concat_vec4 + %concati/vec4 0, 0, 16; + %assign/vec4 v0x55dd3fb3b1e0_0, 0; + %jmp T_118.33; +T_118.26 ; + %pushi/vec4 0, 0, 8; + %load/vec4 v0x55dd3fb3adc0_0; + %concat/vec4; draw_concat_vec4 + %load/vec4 v0x55dd3fb3aea0_0; + %concat/vec4; draw_concat_vec4 + %load/vec4 v0x55dd3fb3ac20_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x55dd3fb3b1e0_0, 0; + %jmp T_118.33; +T_118.27 ; + %pushi/vec4 0, 0, 32; + %assign/vec4 v0x55dd3fb3b1e0_0, 0; + %jmp T_118.33; +T_118.28 ; + %pushi/vec4 0, 0, 32; + %assign/vec4 v0x55dd3fb3b1e0_0, 0; + %jmp T_118.33; +T_118.29 ; + %pushi/vec4 0, 0, 32; + %assign/vec4 v0x55dd3fb3b1e0_0, 0; + %jmp T_118.33; +T_118.30 ; + %pushi/vec4 0, 0, 32; + %assign/vec4 v0x55dd3fb3b1e0_0, 0; + %jmp T_118.33; +T_118.31 ; + %pushi/vec4 0, 0, 32; + %assign/vec4 v0x55dd3fb3b1e0_0, 0; + %jmp T_118.33; +T_118.33 ; + %pop/vec4 1; + %jmp T_118; + .thread T_118, $push; + .scope S_0x55dd3faa5c90; +T_119 ; + %wait E_0x55dd3fb38210; + %load/vec4 v0x55dd3fb3ad00_0; + %inv; + %flag_set/vec4 8; + %jmp/0xz T_119.0, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb3a140_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb3a080_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb39f00_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb39cc0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb39fc0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb39d80_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb39c00_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb39e40_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb39900_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb399c0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb39a80_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb39b40_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb3b520_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb3b6a0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb3b820_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb3b760_0, 0; + %pushi/vec4 0, 0, 36; + %assign/vec4 v0x55dd3fb38650_0, 0; + %pushi/vec4 0, 0, 18; + %assign/vec4 v0x55dd3fb3a2e0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb3b9a0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb3b8e0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb3b5e0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb3ba60_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb3bb20_0, 0; + %jmp T_119.1; +T_119.0 ; + %load/vec4 v0x55dd3fb38980_0; + %assign/vec4 v0x55dd3fb3b760_0, 0; + %load/vec4 v0x55dd3fb3b380_0; + %flag_set/vec4 8; + %jmp/0xz T_119.2, 8; + %load/vec4 v0x55dd3fb3b040_0; + %dup/vec4; + %pushi/vec4 0, 0, 5; + %cmp/u; + %jmp/1 T_119.4, 6; + %dup/vec4; + %pushi/vec4 1, 0, 5; + %cmp/u; + %jmp/1 T_119.5, 6; + %dup/vec4; + %pushi/vec4 2, 0, 5; + %cmp/u; + %jmp/1 T_119.6, 6; + %dup/vec4; + %pushi/vec4 3, 0, 5; + %cmp/u; + %jmp/1 T_119.7, 6; + %dup/vec4; + %pushi/vec4 4, 0, 5; + %cmp/u; + %jmp/1 T_119.8, 6; + %dup/vec4; + %pushi/vec4 5, 0, 5; + %cmp/u; + %jmp/1 T_119.9, 6; + %dup/vec4; + %pushi/vec4 6, 0, 5; + %cmp/u; + %jmp/1 T_119.10, 6; + %dup/vec4; + %pushi/vec4 7, 0, 5; + %cmp/u; + %jmp/1 T_119.11, 6; + %dup/vec4; + %pushi/vec4 8, 0, 5; + %cmp/u; + %jmp/1 T_119.12, 6; + %jmp T_119.13; +T_119.4 ; + %load/vec4 v0x55dd3fb3b440_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_119.14, 8; + %pushi/vec4 1, 0, 2; + %split/vec4 1; + %assign/vec4 v0x55dd3fb3a140_0, 0; + %assign/vec4 v0x55dd3fb3a080_0, 0; +T_119.14 ; + %load/vec4 v0x55dd3fb3b440_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_119.16, 8; + %pushi/vec4 2, 0, 2; + %split/vec4 1; + %assign/vec4 v0x55dd3fb3a140_0, 0; + %assign/vec4 v0x55dd3fb3a080_0, 0; +T_119.16 ; + %load/vec4 v0x55dd3fb3b440_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_119.18, 8; + %pushi/vec4 1, 0, 2; + %split/vec4 1; + %assign/vec4 v0x55dd3fb39cc0_0, 0; + %assign/vec4 v0x55dd3fb39f00_0, 0; +T_119.18 ; + %load/vec4 v0x55dd3fb3b440_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_119.20, 8; + %pushi/vec4 2, 0, 2; + %split/vec4 1; + %assign/vec4 v0x55dd3fb39cc0_0, 0; + %assign/vec4 v0x55dd3fb39f00_0, 0; +T_119.20 ; + %load/vec4 v0x55dd3fb3b440_0; + %parti/s 1, 4, 4; + %flag_set/vec4 8; + %jmp/0xz T_119.22, 8; + %pushi/vec4 1, 0, 2; + %split/vec4 1; + %assign/vec4 v0x55dd3fb39d80_0, 0; + %assign/vec4 v0x55dd3fb39fc0_0, 0; +T_119.22 ; + %load/vec4 v0x55dd3fb3b440_0; + %parti/s 1, 5, 4; + %flag_set/vec4 8; + %jmp/0xz T_119.24, 8; + %pushi/vec4 2, 0, 2; + %split/vec4 1; + %assign/vec4 v0x55dd3fb39d80_0, 0; + %assign/vec4 v0x55dd3fb39fc0_0, 0; +T_119.24 ; + %load/vec4 v0x55dd3fb3b440_0; + %parti/s 1, 6, 4; + %flag_set/vec4 8; + %jmp/0xz T_119.26, 8; + %pushi/vec4 1, 0, 2; + %split/vec4 1; + %assign/vec4 v0x55dd3fb39e40_0, 0; + %assign/vec4 v0x55dd3fb39c00_0, 0; +T_119.26 ; + %load/vec4 v0x55dd3fb3b440_0; + %parti/s 1, 7, 4; + %flag_set/vec4 8; + %jmp/0xz T_119.28, 8; + %pushi/vec4 2, 0, 2; + %split/vec4 1; + %assign/vec4 v0x55dd3fb39e40_0, 0; + %assign/vec4 v0x55dd3fb39c00_0, 0; +T_119.28 ; + %load/vec4 v0x55dd3fb3b440_0; + %parti/s 1, 8, 5; + %flag_set/vec4 8; + %jmp/0xz T_119.30, 8; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x55dd3fb3b520_0, 0; +T_119.30 ; + %jmp T_119.13; +T_119.5 ; + %load/vec4 v0x55dd3fb3b440_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_119.32, 8; + %pushi/vec4 0, 0, 2; + %split/vec4 1; + %assign/vec4 v0x55dd3fb3a140_0, 0; + %assign/vec4 v0x55dd3fb3a080_0, 0; +T_119.32 ; + %load/vec4 v0x55dd3fb3b440_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_119.34, 8; + %pushi/vec4 0, 0, 2; + %split/vec4 1; + %assign/vec4 v0x55dd3fb3a140_0, 0; + %assign/vec4 v0x55dd3fb3a080_0, 0; +T_119.34 ; + %load/vec4 v0x55dd3fb3b440_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_119.36, 8; + %pushi/vec4 0, 0, 2; + %split/vec4 1; + %assign/vec4 v0x55dd3fb39cc0_0, 0; + %assign/vec4 v0x55dd3fb39f00_0, 0; +T_119.36 ; + %load/vec4 v0x55dd3fb3b440_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_119.38, 8; + %pushi/vec4 0, 0, 2; + %split/vec4 1; + %assign/vec4 v0x55dd3fb39cc0_0, 0; + %assign/vec4 v0x55dd3fb39f00_0, 0; +T_119.38 ; + %load/vec4 v0x55dd3fb3b440_0; + %parti/s 1, 4, 4; + %flag_set/vec4 8; + %jmp/0xz T_119.40, 8; + %pushi/vec4 0, 0, 2; + %split/vec4 1; + %assign/vec4 v0x55dd3fb39d80_0, 0; + %assign/vec4 v0x55dd3fb39fc0_0, 0; +T_119.40 ; + %load/vec4 v0x55dd3fb3b440_0; + %parti/s 1, 5, 4; + %flag_set/vec4 8; + %jmp/0xz T_119.42, 8; + %pushi/vec4 0, 0, 2; + %split/vec4 1; + %assign/vec4 v0x55dd3fb39d80_0, 0; + %assign/vec4 v0x55dd3fb39fc0_0, 0; +T_119.42 ; + %load/vec4 v0x55dd3fb3b440_0; + %parti/s 1, 6, 4; + %flag_set/vec4 8; + %jmp/0xz T_119.44, 8; + %pushi/vec4 0, 0, 2; + %split/vec4 1; + %assign/vec4 v0x55dd3fb39e40_0, 0; + %assign/vec4 v0x55dd3fb39c00_0, 0; +T_119.44 ; + %load/vec4 v0x55dd3fb3b440_0; + %parti/s 1, 7, 4; + %flag_set/vec4 8; + %jmp/0xz T_119.46, 8; + %pushi/vec4 0, 0, 2; + %split/vec4 1; + %assign/vec4 v0x55dd3fb39e40_0, 0; + %assign/vec4 v0x55dd3fb39c00_0, 0; +T_119.46 ; + %load/vec4 v0x55dd3fb3b440_0; + %parti/s 1, 8, 5; + %flag_set/vec4 8; + %jmp/0xz T_119.48, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb3b520_0, 0; +T_119.48 ; + %jmp T_119.13; +T_119.6 ; + %load/vec4 v0x55dd3fb3b440_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_119.50, 8; + %pushi/vec4 1, 0, 2; + %split/vec4 1; + %assign/vec4 v0x55dd3fb39900_0, 0; + %assign/vec4 v0x55dd3fb399c0_0, 0; +T_119.50 ; + %load/vec4 v0x55dd3fb3b440_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_119.52, 8; + %pushi/vec4 2, 0, 2; + %split/vec4 1; + %assign/vec4 v0x55dd3fb39900_0, 0; + %assign/vec4 v0x55dd3fb399c0_0, 0; +T_119.52 ; + %load/vec4 v0x55dd3fb3b440_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_119.54, 8; + %pushi/vec4 1, 0, 2; + %split/vec4 1; + %assign/vec4 v0x55dd3fb39a80_0, 0; + %assign/vec4 v0x55dd3fb39b40_0, 0; +T_119.54 ; + %load/vec4 v0x55dd3fb3b440_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_119.56, 8; + %pushi/vec4 2, 0, 2; + %split/vec4 1; + %assign/vec4 v0x55dd3fb39a80_0, 0; + %assign/vec4 v0x55dd3fb39b40_0, 0; +T_119.56 ; + %load/vec4 v0x55dd3fb3b440_0; + %parti/s 1, 8, 5; + %flag_set/vec4 8; + %jmp/0xz T_119.58, 8; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x55dd3fb3b820_0, 0; +T_119.58 ; + %load/vec4 v0x55dd3fb3b440_0; + %parti/s 1, 9, 5; + %flag_set/vec4 8; + %jmp/0xz T_119.60, 8; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x55dd3fb3b6a0_0, 0; +T_119.60 ; + %jmp T_119.13; +T_119.7 ; + %load/vec4 v0x55dd3fb3b440_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_119.62, 8; + %pushi/vec4 0, 0, 2; + %split/vec4 1; + %assign/vec4 v0x55dd3fb39900_0, 0; + %assign/vec4 v0x55dd3fb399c0_0, 0; +T_119.62 ; + %load/vec4 v0x55dd3fb3b440_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_119.64, 8; + %pushi/vec4 0, 0, 2; + %split/vec4 1; + %assign/vec4 v0x55dd3fb39900_0, 0; + %assign/vec4 v0x55dd3fb399c0_0, 0; +T_119.64 ; + %load/vec4 v0x55dd3fb3b440_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_119.66, 8; + %pushi/vec4 0, 0, 2; + %split/vec4 1; + %assign/vec4 v0x55dd3fb39a80_0, 0; + %assign/vec4 v0x55dd3fb39b40_0, 0; +T_119.66 ; + %load/vec4 v0x55dd3fb3b440_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_119.68, 8; + %pushi/vec4 0, 0, 2; + %split/vec4 1; + %assign/vec4 v0x55dd3fb39a80_0, 0; + %assign/vec4 v0x55dd3fb39b40_0, 0; +T_119.68 ; + %load/vec4 v0x55dd3fb3b440_0; + %parti/s 1, 8, 5; + %flag_set/vec4 8; + %jmp/0xz T_119.70, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb3b820_0, 0; +T_119.70 ; + %load/vec4 v0x55dd3fb3b440_0; + %parti/s 1, 9, 5; + %flag_set/vec4 8; + %jmp/0xz T_119.72, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb3b6a0_0, 0; +T_119.72 ; + %jmp T_119.13; +T_119.8 ; + %load/vec4 v0x55dd3fb3b440_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_119.74, 8; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x55dd3fb3b9a0_0, 0; +T_119.74 ; + %load/vec4 v0x55dd3fb3b440_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_119.76, 8; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x55dd3fb3b8e0_0, 0; +T_119.76 ; + %load/vec4 v0x55dd3fb3b440_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_119.78, 8; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x55dd3fb3b5e0_0, 0; +T_119.78 ; + %load/vec4 v0x55dd3fb3b440_0; + %parti/s 1, 4, 4; + %flag_set/vec4 8; + %jmp/0xz T_119.80, 8; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x55dd3fb3ba60_0, 0; +T_119.80 ; + %load/vec4 v0x55dd3fb3b440_0; + %parti/s 1, 5, 4; + %flag_set/vec4 8; + %jmp/0xz T_119.82, 8; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x55dd3fb3bb20_0, 0; +T_119.82 ; + %jmp T_119.13; +T_119.9 ; + %load/vec4 v0x55dd3fb3b440_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_119.84, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb3b9a0_0, 0; +T_119.84 ; + %load/vec4 v0x55dd3fb3b440_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_119.86, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb3b8e0_0, 0; +T_119.86 ; + %load/vec4 v0x55dd3fb3b440_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_119.88, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb3b5e0_0, 0; +T_119.88 ; + %load/vec4 v0x55dd3fb3b440_0; + %parti/s 1, 4, 4; + %flag_set/vec4 8; + %jmp/0xz T_119.90, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb3ba60_0, 0; +T_119.90 ; + %load/vec4 v0x55dd3fb3b440_0; + %parti/s 1, 5, 4; + %flag_set/vec4 8; + %jmp/0xz T_119.92, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb3bb20_0, 0; +T_119.92 ; + %jmp T_119.13; +T_119.10 ; + %load/vec4 v0x55dd3fb3b440_0; + %pad/u 18; + %ix/load 4, 18, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x55dd3fb38650_0, 4, 5; + %jmp T_119.13; +T_119.11 ; + %load/vec4 v0x55dd3fb3b440_0; + %pad/u 18; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x55dd3fb38650_0, 4, 5; + %jmp T_119.13; +T_119.12 ; + %load/vec4 v0x55dd3fb3b440_0; + %pad/u 18; + %assign/vec4 v0x55dd3fb3a2e0_0, 0; + %jmp T_119.13; +T_119.13 ; + %pop/vec4 1; +T_119.2 ; +T_119.1 ; + %jmp T_119; + .thread T_119; + .scope S_0x55dd3fb3c720; +T_120 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x55dd3fb3c920_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x55dd3fb3ca00_0, 0, 1; + %delay 50, 0; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x55dd3fb3ca00_0, 0, 1; + %end; + .thread T_120; + .scope S_0x55dd3fb3c720; +T_121 ; + %delay 10, 0; + %load/vec4 v0x55dd3fb3c920_0; + %inv; + %store/vec4 v0x55dd3fb3c920_0, 0, 1; + %jmp T_121; + .thread T_121; + .scope S_0x55dd3fb75690; +T_122 ; + %wait E_0x55dd3fb758f0; + %load/vec4 v0x55dd3fb75ca0_0; + %inv; + %flag_set/vec4 8; + %jmp/0xz T_122.0, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb75b30_0, 0; + %jmp T_122.1; +T_122.0 ; + %load/vec4 v0x55dd3fb75de0_0; + %assign/vec4 v0x55dd3fb75b30_0, 0; +T_122.1 ; + %jmp T_122; + .thread T_122; + .scope S_0x55dd3fb75f20; +T_123 ; + %wait E_0x55dd3fb758f0; + %load/vec4 v0x55dd3fb76460_0; + %inv; + %flag_set/vec4 8; + %jmp/0xz T_123.0, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb76320_0, 0; + %jmp T_123.1; +T_123.0 ; + %load/vec4 v0x55dd3fb76550_0; + %assign/vec4 v0x55dd3fb76320_0, 0; +T_123.1 ; + %jmp T_123; + .thread T_123; + .scope S_0x55dd3fb77d20; +T_124 ; + %wait E_0x55dd3fb77f10; + %load/vec4 v0x55dd3fb785a0_0; + %flag_set/vec4 8; + %jmp/0xz T_124.0, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x55dd3fb784e0_0, 0; + %jmp T_124.1; +T_124.0 ; + %load/vec4 v0x55dd3fb784e0_0; + %cmpi/ne 0, 0, 3; + %jmp/0xz T_124.2, 4; + %load/vec4 v0x55dd3fb784e0_0; + %addi 1, 0, 3; + %assign/vec4 v0x55dd3fb784e0_0, 0; +T_124.2 ; + %load/vec4 v0x55dd3fb78300_0; + %flag_set/vec4 8; + %jmp/0xz T_124.4, 8; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x55dd3fb784e0_0, 0; +T_124.4 ; +T_124.1 ; + %jmp T_124; + .thread T_124; + .scope S_0x55dd3fb76690; +T_125 ; + %wait E_0x55dd3fb76900; + %load/vec4 v0x55dd3fb77be0_0; + %flag_set/vec4 8; + %jmp/0xz T_125.0, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x55dd3fb77b00_0, 0; + %jmp T_125.1; +T_125.0 ; + %load/vec4 v0x55dd3fb77b00_0; + %cmpi/ne 0, 0, 3; + %jmp/0xz T_125.2, 4; + %load/vec4 v0x55dd3fb77b00_0; + %addi 1, 0, 3; + %assign/vec4 v0x55dd3fb77b00_0, 0; +T_125.2 ; + %load/vec4 v0x55dd3fb77980_0; + %flag_set/vec4 8; + %jmp/0xz T_125.4, 8; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x55dd3fb77b00_0, 0; +T_125.4 ; +T_125.1 ; + %jmp T_125; + .thread T_125; + .scope S_0x55dd3fb75350; +T_126 ; + %wait E_0x55dd3fb758f0; + %load/vec4 v0x55dd3fb79a40_0; + %inv; + %flag_set/vec4 8; + %jmp/0xz T_126.0, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb793c0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb79210_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb796d0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb7a000_0, 0; + %pushi/vec4 0, 0, 18; + %assign/vec4 v0x55dd3fb78c30_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb78e70_0, 0; + %pushi/vec4 0, 0, 36; + %assign/vec4 v0x55dd3fb7a0c0_0, 0; + %pushi/vec4 0, 0, 8; + %assign/vec4 v0x55dd3fb79f20_0, 0; + %jmp T_126.1; +T_126.0 ; + %load/vec4 v0x55dd3fb7a240_0; + %flag_set/vec4 8; + %jmp/0xz T_126.2, 8; + %load/vec4 v0x55dd3fb79ae0_0; + %dup/vec4; + %pushi/vec4 0, 0, 2; + %cmp/u; + %jmp/1 T_126.4, 6; + %dup/vec4; + %pushi/vec4 1, 0, 2; + %cmp/u; + %jmp/1 T_126.5, 6; + %dup/vec4; + %pushi/vec4 2, 0, 2; + %cmp/u; + %jmp/1 T_126.6, 6; + %jmp T_126.7; +T_126.4 ; + %load/vec4 v0x55dd3fb79e60_0; + %parti/s 18, 0, 2; + %assign/vec4 v0x55dd3fb78c30_0, 0; + %load/vec4 v0x55dd3fb79e60_0; + %parti/s 1, 18, 6; + %assign/vec4 v0x55dd3fb78e70_0, 0; + %jmp T_126.7; +T_126.5 ; + %load/vec4 v0x55dd3fb79e60_0; + %parti/s 18, 0, 2; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x55dd3fb7a0c0_0, 4, 5; + %jmp T_126.7; +T_126.6 ; + %load/vec4 v0x55dd3fb79e60_0; + %parti/s 18, 0, 2; + %ix/load 4, 18, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x55dd3fb7a0c0_0, 4, 5; + %jmp T_126.7; +T_126.7 ; + %pop/vec4 1; +T_126.2 ; + %load/vec4 v0x55dd3fb799a0_0; + %flag_set/vec4 8; + %jmp/0xz T_126.8, 8; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x55dd3fb7a000_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x55dd3fb793c0_0, 0; + %load/vec4 v0x55dd3fb79dc0_0; + %flag_set/vec4 8; + %jmp/0xz T_126.10, 8; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x55dd3fb796d0_0, 0; + %jmp T_126.11; +T_126.10 ; + %load/vec4 v0x55dd3fb79ba0_0; + %flag_set/vec4 8; + %jmp/0xz T_126.12, 8; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x55dd3fb79210_0, 0; + %pushi/vec4 0, 0, 36; + %assign/vec4 v0x55dd3fb7a0c0_0, 0; +T_126.12 ; +T_126.11 ; +T_126.8 ; + %load/vec4 v0x55dd3fb79f20_0; + %cmpi/ne 0, 0, 8; + %jmp/0xz T_126.14, 4; + %load/vec4 v0x55dd3fb79f20_0; + %pad/u 32; + %cmpi/e 12, 0, 32; + %jmp/0xz T_126.16, 4; + %pushi/vec4 0, 0, 8; + %assign/vec4 v0x55dd3fb79f20_0, 0; + %jmp T_126.17; +T_126.16 ; + %load/vec4 v0x55dd3fb79f20_0; + %addi 1, 0, 8; + %assign/vec4 v0x55dd3fb79f20_0, 0; +T_126.17 ; +T_126.14 ; + %load/vec4 v0x55dd3fb7a000_0; + %load/vec4 v0x55dd3fb79210_0; + %and; + %flag_set/vec4 8; + %jmp/0xz T_126.18, 8; + %load/vec4 v0x55dd3fb79020_0; + %assign/vec4 v0x55dd3fb7a0c0_0, 0; +T_126.18 ; + %load/vec4 v0x55dd3fb78db0_0; + %flag_set/vec4 8; + %jmp/0xz T_126.20, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb793c0_0, 0; + %pushi/vec4 1, 0, 8; + %assign/vec4 v0x55dd3fb79f20_0, 0; +T_126.20 ; + %load/vec4 v0x55dd3fb79300_0; + %flag_set/vec4 8; + %jmp/0xz T_126.22, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb79210_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb7a000_0, 0; +T_126.22 ; + %load/vec4 v0x55dd3fb797c0_0; + %flag_set/vec4 8; + %jmp/0xz T_126.24, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb796d0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb7a000_0, 0; +T_126.24 ; +T_126.1 ; + %jmp T_126; + .thread T_126; + .scope S_0x55dd3fb75350; +T_127 ; + %wait E_0x55dd3fb75610; + %load/vec4 v0x55dd3fb79ae0_0; + %dup/vec4; + %pushi/vec4 1, 0, 2; + %cmp/u; + %jmp/1 T_127.0, 6; + %dup/vec4; + %pushi/vec4 2, 0, 2; + %cmp/u; + %jmp/1 T_127.1, 6; + %pushi/vec4 0, 0, 32; + %assign/vec4 v0x55dd3fb79c40_0, 0; + %jmp T_127.3; +T_127.0 ; + %pushi/vec4 0, 0, 14; + %load/vec4 v0x55dd3fb7a0c0_0; + %parti/s 18, 0, 2; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x55dd3fb79c40_0, 0; + %jmp T_127.3; +T_127.1 ; + %pushi/vec4 0, 0, 14; + %load/vec4 v0x55dd3fb7a0c0_0; + %parti/s 18, 18, 6; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x55dd3fb79c40_0, 0; + %jmp T_127.3; +T_127.3 ; + %pop/vec4 1; + %jmp T_127; + .thread T_127, $push; + .scope S_0x55dd3fb3d3e0; +T_128 ; + %wait E_0x55dd3fb3d620; + %load/vec4 v0x55dd3fb3dbd0_0; + %flag_set/vec4 8; + %jmp/0xz T_128.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x55dd3fb3dc90_0, 0; + %jmp T_128.1; +T_128.0 ; + %load/vec4 v0x55dd3fb3dc90_0; + %parti/s 1, 0, 2; + %load/vec4 v0x55dd3fb3da20_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x55dd3fb3dc90_0, 0; +T_128.1 ; + %jmp T_128; + .thread T_128; + .scope S_0x55dd3fb3ddf0; +T_129 ; + %wait E_0x55dd3fb3d620; + %load/vec4 v0x55dd3fb3e5a0_0; + %flag_set/vec4 8; + %jmp/0xz T_129.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x55dd3fb3e640_0, 0; + %jmp T_129.1; +T_129.0 ; + %load/vec4 v0x55dd3fb3e640_0; + %parti/s 1, 0, 2; + %load/vec4 v0x55dd3fb3e3d0_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x55dd3fb3e640_0, 0; +T_129.1 ; + %jmp T_129; + .thread T_129; + .scope S_0x55dd3fb3e780; +T_130 ; + %wait E_0x55dd3fb3d620; + %load/vec4 v0x55dd3fb3eef0_0; + %flag_set/vec4 8; + %jmp/0xz T_130.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x55dd3fb3efe0_0, 0; + %jmp T_130.1; +T_130.0 ; + %load/vec4 v0x55dd3fb3efe0_0; + %parti/s 1, 0, 2; + %load/vec4 v0x55dd3fb3ed20_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x55dd3fb3efe0_0, 0; +T_130.1 ; + %jmp T_130; + .thread T_130; + .scope S_0x55dd3fb3f140; +T_131 ; + %wait E_0x55dd3fb3d620; + %load/vec4 v0x55dd3fb3f820_0; + %flag_set/vec4 8; + %jmp/0xz T_131.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x55dd3fb3f8c0_0, 0; + %jmp T_131.1; +T_131.0 ; + %load/vec4 v0x55dd3fb3f8c0_0; + %parti/s 1, 0, 2; + %load/vec4 v0x55dd3fb3f6a0_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x55dd3fb3f8c0_0, 0; +T_131.1 ; + %jmp T_131; + .thread T_131; + .scope S_0x55dd3fb518f0; +T_132 ; + %wait E_0x55dd3fb3d620; + %load/vec4 v0x55dd3fb52030_0; + %flag_set/vec4 8; + %jmp/0xz T_132.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x55dd3fb520d0_0, 0; + %jmp T_132.1; +T_132.0 ; + %load/vec4 v0x55dd3fb520d0_0; + %parti/s 1, 0, 2; + %load/vec4 v0x55dd3fb51e80_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x55dd3fb520d0_0, 0; +T_132.1 ; + %jmp T_132; + .thread T_132; + .scope S_0x55dd3fb3fa20; +T_133 ; + %wait E_0x55dd3fb3d620; + %load/vec4 v0x55dd3fb402f0_0; + %flag_set/vec4 8; + %jmp/0xz T_133.0, 8; + %pushi/vec4 0, 0, 6; + %assign/vec4 v0x55dd3fb40210_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb40090_0, 0; + %jmp T_133.1; +T_133.0 ; + %load/vec4 v0x55dd3fb40210_0; + %cmpi/ne 0, 0, 6; + %jmp/0xz T_133.2, 4; + %load/vec4 v0x55dd3fb40210_0; + %addi 1, 0, 6; + %assign/vec4 v0x55dd3fb40210_0, 0; +T_133.2 ; + %load/vec4 v0x55dd3fb3ff80_0; + %flag_set/vec4 8; + %jmp/0xz T_133.4, 8; + %pushi/vec4 1, 0, 6; + %assign/vec4 v0x55dd3fb40210_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x55dd3fb40090_0, 0; +T_133.4 ; + %load/vec4 v0x55dd3fb40150_0; + %flag_set/vec4 8; + %jmp/0xz T_133.6, 8; + %pushi/vec4 0, 0, 6; + %assign/vec4 v0x55dd3fb40210_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb40090_0, 0; +T_133.6 ; +T_133.1 ; + %jmp T_133; + .thread T_133; + .scope S_0x55dd3fb40550; +T_134 ; + %wait E_0x55dd3fb3d620; + %load/vec4 v0x55dd3fb40da0_0; + %flag_set/vec4 8; + %jmp/0xz T_134.0, 8; + %pushi/vec4 0, 0, 6; + %assign/vec4 v0x55dd3fb40cc0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb40b60_0, 0; + %jmp T_134.1; +T_134.0 ; + %load/vec4 v0x55dd3fb40cc0_0; + %cmpi/ne 0, 0, 6; + %jmp/0xz T_134.2, 4; + %load/vec4 v0x55dd3fb40cc0_0; + %addi 1, 0, 6; + %assign/vec4 v0x55dd3fb40cc0_0, 0; +T_134.2 ; + %load/vec4 v0x55dd3fb40ac0_0; + %flag_set/vec4 8; + %jmp/0xz T_134.4, 8; + %pushi/vec4 1, 0, 6; + %assign/vec4 v0x55dd3fb40cc0_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x55dd3fb40b60_0, 0; +T_134.4 ; + %load/vec4 v0x55dd3fb40c00_0; + %flag_set/vec4 8; + %jmp/0xz T_134.6, 8; + %pushi/vec4 0, 0, 6; + %assign/vec4 v0x55dd3fb40cc0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb40b60_0, 0; +T_134.6 ; +T_134.1 ; + %jmp T_134; + .thread T_134; + .scope S_0x55dd3fb47bb0; +T_135 ; + %wait E_0x55dd3fb3d620; + %load/vec4 v0x55dd3fb482a0_0; + %flag_set/vec4 8; + %jmp/0xz T_135.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x55dd3fb48340_0, 0; + %jmp T_135.1; +T_135.0 ; + %load/vec4 v0x55dd3fb48340_0; + %parti/s 1, 0, 2; + %load/vec4 v0x55dd3fb48110_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x55dd3fb48340_0, 0; +T_135.1 ; + %jmp T_135; + .thread T_135; + .scope S_0x55dd3fb484d0; +T_136 ; + %wait E_0x55dd3fb3d620; + %load/vec4 v0x55dd3fb48c10_0; + %flag_set/vec4 8; + %jmp/0xz T_136.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x55dd3fb48cb0_0, 0; + %jmp T_136.1; +T_136.0 ; + %load/vec4 v0x55dd3fb48cb0_0; + %parti/s 1, 0, 2; + %load/vec4 v0x55dd3fb48a60_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x55dd3fb48cb0_0, 0; +T_136.1 ; + %jmp T_136; + .thread T_136; + .scope S_0x55dd3fb4c620; +T_137 ; + %wait E_0x55dd3fb3d620; + %load/vec4 v0x55dd3fb4cd80_0; + %flag_set/vec4 8; + %jmp/0xz T_137.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x55dd3fb4ce20_0, 0; + %jmp T_137.1; +T_137.0 ; + %load/vec4 v0x55dd3fb4ce20_0; + %parti/s 1, 0, 2; + %load/vec4 v0x55dd3fb4cbb0_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x55dd3fb4ce20_0, 0; +T_137.1 ; + %jmp T_137; + .thread T_137; + .scope S_0x55dd3fb4cf80; +T_138 ; + %wait E_0x55dd3fb3d620; + %load/vec4 v0x55dd3fb4d6e0_0; + %flag_set/vec4 8; + %jmp/0xz T_138.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x55dd3fb4d780_0, 0; + %jmp T_138.1; +T_138.0 ; + %load/vec4 v0x55dd3fb4d780_0; + %parti/s 1, 0, 2; + %load/vec4 v0x55dd3fb4d510_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x55dd3fb4d780_0, 0; +T_138.1 ; + %jmp T_138; + .thread T_138; + .scope S_0x55dd3fb4d8e0; +T_139 ; + %wait E_0x55dd3fb3d620; + %load/vec4 v0x55dd3fb4e020_0; + %flag_set/vec4 8; + %jmp/0xz T_139.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x55dd3fb4e0c0_0, 0; + %jmp T_139.1; +T_139.0 ; + %load/vec4 v0x55dd3fb4e0c0_0; + %parti/s 1, 0, 2; + %load/vec4 v0x55dd3fb4de70_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x55dd3fb4e0c0_0, 0; +T_139.1 ; + %jmp T_139; + .thread T_139; + .scope S_0x55dd3fb4e230; +T_140 ; + %wait E_0x55dd3fb3d620; + %load/vec4 v0x55dd3fb4e990_0; + %flag_set/vec4 8; + %jmp/0xz T_140.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x55dd3fb4ea30_0, 0; + %jmp T_140.1; +T_140.0 ; + %load/vec4 v0x55dd3fb4ea30_0; + %parti/s 1, 0, 2; + %load/vec4 v0x55dd3fb4e7c0_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x55dd3fb4ea30_0, 0; +T_140.1 ; + %jmp T_140; + .thread T_140; + .scope S_0x55dd3fb4eb90; +T_141 ; + %wait E_0x55dd3fb3d620; + %load/vec4 v0x55dd3fb4f2f0_0; + %flag_set/vec4 8; + %jmp/0xz T_141.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x55dd3fb4f390_0, 0; + %jmp T_141.1; +T_141.0 ; + %load/vec4 v0x55dd3fb4f390_0; + %parti/s 1, 0, 2; + %load/vec4 v0x55dd3fb4f120_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x55dd3fb4f390_0, 0; +T_141.1 ; + %jmp T_141; + .thread T_141; + .scope S_0x55dd3fb4f4f0; +T_142 ; + %wait E_0x55dd3fb3d620; + %load/vec4 v0x55dd3fb4fc10_0; + %flag_set/vec4 8; + %jmp/0xz T_142.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x55dd3fb4fcb0_0, 0; + %jmp T_142.1; +T_142.0 ; + %load/vec4 v0x55dd3fb4fcb0_0; + %parti/s 1, 0, 2; + %load/vec4 v0x55dd3fb4fa80_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x55dd3fb4fcb0_0, 0; +T_142.1 ; + %jmp T_142; + .thread T_142; + .scope S_0x55dd3fb4fe40; +T_143 ; + %wait E_0x55dd3fb3d620; + %load/vec4 v0x55dd3fb50970_0; + %flag_set/vec4 8; + %jmp/0xz T_143.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x55dd3fb50a10_0, 0; + %jmp T_143.1; +T_143.0 ; + %load/vec4 v0x55dd3fb50a10_0; + %parti/s 1, 0, 2; + %load/vec4 v0x55dd3fb507e0_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x55dd3fb50a10_0, 0; +T_143.1 ; + %jmp T_143; + .thread T_143; + .scope S_0x55dd3fb50b80; +T_144 ; + %wait E_0x55dd3fb3d620; + %load/vec4 v0x55dd3fb512e0_0; + %flag_set/vec4 8; + %jmp/0xz T_144.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x55dd3fb51790_0, 0; + %jmp T_144.1; +T_144.0 ; + %load/vec4 v0x55dd3fb51790_0; + %parti/s 1, 0, 2; + %load/vec4 v0x55dd3fb51110_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x55dd3fb51790_0, 0; +T_144.1 ; + %jmp T_144; + .thread T_144; + .scope S_0x55dd3fb48e20; +T_145 ; + %wait E_0x55dd3fb3d620; + %load/vec4 v0x55dd3fb49590_0; + %flag_set/vec4 8; + %jmp/0xz T_145.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x55dd3fb49630_0, 0; + %jmp T_145.1; +T_145.0 ; + %load/vec4 v0x55dd3fb49630_0; + %parti/s 1, 0, 2; + %load/vec4 v0x55dd3fb493b0_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x55dd3fb49630_0, 0; +T_145.1 ; + %jmp T_145; + .thread T_145; + .scope S_0x55dd3fb49770; +T_146 ; + %wait E_0x55dd3fb3d620; + %load/vec4 v0x55dd3fb49ed0_0; + %flag_set/vec4 8; + %jmp/0xz T_146.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x55dd3fb49f70_0, 0; + %jmp T_146.1; +T_146.0 ; + %load/vec4 v0x55dd3fb49f70_0; + %parti/s 1, 0, 2; + %load/vec4 v0x55dd3fb49d00_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x55dd3fb49f70_0, 0; +T_146.1 ; + %jmp T_146; + .thread T_146; + .scope S_0x55dd3fb4a0d0; +T_147 ; + %wait E_0x55dd3fb3d620; + %load/vec4 v0x55dd3fb4a7f0_0; + %flag_set/vec4 8; + %jmp/0xz T_147.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x55dd3fb4a890_0, 0; + %jmp T_147.1; +T_147.0 ; + %load/vec4 v0x55dd3fb4a890_0; + %parti/s 1, 0, 2; + %load/vec4 v0x55dd3fb4a660_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x55dd3fb4a890_0, 0; +T_147.1 ; + %jmp T_147; + .thread T_147; + .scope S_0x55dd3fb4aa20; +T_148 ; + %wait E_0x55dd3fb3d620; + %load/vec4 v0x55dd3fb4b160_0; + %flag_set/vec4 8; + %jmp/0xz T_148.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x55dd3fb4b200_0, 0; + %jmp T_148.1; +T_148.0 ; + %load/vec4 v0x55dd3fb4b200_0; + %parti/s 1, 0, 2; + %load/vec4 v0x55dd3fb4afb0_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x55dd3fb4b200_0, 0; +T_148.1 ; + %jmp T_148; + .thread T_148; + .scope S_0x55dd3fb4b360; +T_149 ; + %wait E_0x55dd3fb3d620; + %load/vec4 v0x55dd3fb4bac0_0; + %flag_set/vec4 8; + %jmp/0xz T_149.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x55dd3fb4bb60_0, 0; + %jmp T_149.1; +T_149.0 ; + %load/vec4 v0x55dd3fb4bb60_0; + %parti/s 1, 0, 2; + %load/vec4 v0x55dd3fb4b8f0_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x55dd3fb4bb60_0, 0; +T_149.1 ; + %jmp T_149; + .thread T_149; + .scope S_0x55dd3fb4bcc0; +T_150 ; + %wait E_0x55dd3fb3d620; + %load/vec4 v0x55dd3fb4c420_0; + %flag_set/vec4 8; + %jmp/0xz T_150.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x55dd3fb4c4c0_0, 0; + %jmp T_150.1; +T_150.0 ; + %load/vec4 v0x55dd3fb4c4c0_0; + %parti/s 1, 0, 2; + %load/vec4 v0x55dd3fb4c250_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x55dd3fb4c4c0_0, 0; +T_150.1 ; + %jmp T_150; + .thread T_150; + .scope S_0x55dd3fb42d90; +T_151 ; + %wait E_0x55dd3fb3d620; + %load/vec4 v0x55dd3fb435f0_0; + %flag_set/vec4 8; + %jmp/0xz T_151.0, 8; + %pushi/vec4 0, 0, 4; + %assign/vec4 v0x55dd3fb43510_0, 0; + %jmp T_151.1; +T_151.0 ; + %load/vec4 v0x55dd3fb43510_0; + %cmpi/ne 0, 0, 4; + %jmp/0xz T_151.2, 4; + %load/vec4 v0x55dd3fb43510_0; + %addi 1, 0, 4; + %assign/vec4 v0x55dd3fb43510_0, 0; +T_151.2 ; + %load/vec4 v0x55dd3fb43340_0; + %flag_set/vec4 8; + %jmp/0xz T_151.4, 8; + %pushi/vec4 1, 0, 4; + %assign/vec4 v0x55dd3fb43510_0, 0; +T_151.4 ; +T_151.1 ; + %jmp T_151; + .thread T_151; + .scope S_0x55dd3fb43710; +T_152 ; + %wait E_0x55dd3fb3d620; + %load/vec4 v0x55dd3fb43f70_0; + %flag_set/vec4 8; + %jmp/0xz T_152.0, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x55dd3fb43e90_0, 0; + %jmp T_152.1; +T_152.0 ; + %load/vec4 v0x55dd3fb43e90_0; + %cmpi/ne 0, 0, 3; + %jmp/0xz T_152.2, 4; + %load/vec4 v0x55dd3fb43e90_0; + %addi 1, 0, 3; + %assign/vec4 v0x55dd3fb43e90_0, 0; +T_152.2 ; + %load/vec4 v0x55dd3fb43cc0_0; + %flag_set/vec4 8; + %jmp/0xz T_152.4, 8; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x55dd3fb43e90_0, 0; +T_152.4 ; +T_152.1 ; + %jmp T_152; + .thread T_152; + .scope S_0x55dd3fb44090; +T_153 ; + %wait E_0x55dd3fb3d620; + %load/vec4 v0x55dd3fb448f0_0; + %flag_set/vec4 8; + %jmp/0xz T_153.0, 8; + %pushi/vec4 0, 0, 4; + %assign/vec4 v0x55dd3fb44810_0, 0; + %jmp T_153.1; +T_153.0 ; + %load/vec4 v0x55dd3fb44810_0; + %cmpi/ne 0, 0, 4; + %jmp/0xz T_153.2, 4; + %load/vec4 v0x55dd3fb44810_0; + %addi 1, 0, 4; + %assign/vec4 v0x55dd3fb44810_0, 0; +T_153.2 ; + %load/vec4 v0x55dd3fb44640_0; + %flag_set/vec4 8; + %jmp/0xz T_153.4, 8; + %pushi/vec4 1, 0, 4; + %assign/vec4 v0x55dd3fb44810_0, 0; +T_153.4 ; +T_153.1 ; + %jmp T_153; + .thread T_153; + .scope S_0x55dd3fb44a10; +T_154 ; + %wait E_0x55dd3fb3d620; + %load/vec4 v0x55dd3fb45230_0; + %flag_set/vec4 8; + %jmp/0xz T_154.0, 8; + %pushi/vec4 0, 0, 5; + %assign/vec4 v0x55dd3fb45150_0, 0; + %jmp T_154.1; +T_154.0 ; + %load/vec4 v0x55dd3fb45150_0; + %cmpi/ne 0, 0, 5; + %jmp/0xz T_154.2, 4; + %load/vec4 v0x55dd3fb45150_0; + %addi 1, 0, 5; + %assign/vec4 v0x55dd3fb45150_0, 0; +T_154.2 ; + %load/vec4 v0x55dd3fb44fc0_0; + %flag_set/vec4 8; + %jmp/0xz T_154.4, 8; + %pushi/vec4 1, 0, 5; + %assign/vec4 v0x55dd3fb45150_0, 0; +T_154.4 ; +T_154.1 ; + %jmp T_154; + .thread T_154; + .scope S_0x55dd3fb45380; +T_155 ; + %wait E_0x55dd3fb3d620; + %load/vec4 v0x55dd3fb45c10_0; + %flag_set/vec4 8; + %jmp/0xz T_155.0, 8; + %pushi/vec4 0, 0, 5; + %assign/vec4 v0x55dd3fb45b30_0, 0; + %jmp T_155.1; +T_155.0 ; + %load/vec4 v0x55dd3fb45b30_0; + %cmpi/ne 0, 0, 5; + %jmp/0xz T_155.2, 4; + %load/vec4 v0x55dd3fb45b30_0; + %addi 1, 0, 5; + %assign/vec4 v0x55dd3fb45b30_0, 0; +T_155.2 ; + %load/vec4 v0x55dd3fb45930_0; + %flag_set/vec4 8; + %jmp/0xz T_155.4, 8; + %pushi/vec4 1, 0, 5; + %assign/vec4 v0x55dd3fb45b30_0, 0; +T_155.4 ; +T_155.1 ; + %jmp T_155; + .thread T_155; + .scope S_0x55dd3fb45d30; +T_156 ; + %wait E_0x55dd3fb3d620; + %load/vec4 v0x55dd3fb46560_0; + %flag_set/vec4 8; + %jmp/0xz T_156.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x55dd3fb46480_0, 0; + %jmp T_156.1; +T_156.0 ; + %load/vec4 v0x55dd3fb46480_0; + %cmpi/ne 0, 0, 2; + %jmp/0xz T_156.2, 4; + %load/vec4 v0x55dd3fb46480_0; + %addi 1, 0, 2; + %assign/vec4 v0x55dd3fb46480_0, 0; +T_156.2 ; + %load/vec4 v0x55dd3fb462b0_0; + %flag_set/vec4 8; + %jmp/0xz T_156.4, 8; + %pushi/vec4 1, 0, 2; + %assign/vec4 v0x55dd3fb46480_0, 0; +T_156.4 ; +T_156.1 ; + %jmp T_156; + .thread T_156; + .scope S_0x55dd3fb46680; +T_157 ; + %wait E_0x55dd3fb3d620; + %load/vec4 v0x55dd3fb46ea0_0; + %flag_set/vec4 8; + %jmp/0xz T_157.0, 8; + %pushi/vec4 0, 0, 4; + %assign/vec4 v0x55dd3fb46dc0_0, 0; + %jmp T_157.1; +T_157.0 ; + %load/vec4 v0x55dd3fb46dc0_0; + %cmpi/ne 0, 0, 4; + %jmp/0xz T_157.2, 4; + %load/vec4 v0x55dd3fb46dc0_0; + %addi 1, 0, 4; + %assign/vec4 v0x55dd3fb46dc0_0, 0; +T_157.2 ; + %load/vec4 v0x55dd3fb46c30_0; + %flag_set/vec4 8; + %jmp/0xz T_157.4, 8; + %pushi/vec4 1, 0, 4; + %assign/vec4 v0x55dd3fb46dc0_0, 0; +T_157.4 ; +T_157.1 ; + %jmp T_157; + .thread T_157; + .scope S_0x55dd3fb46ff0; +T_158 ; + %wait E_0x55dd3fb3d620; + %load/vec4 v0x55dd3fb47880_0; + %flag_set/vec4 8; + %jmp/0xz T_158.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x55dd3fb477a0_0, 0; + %jmp T_158.1; +T_158.0 ; + %load/vec4 v0x55dd3fb477a0_0; + %cmpi/ne 0, 0, 2; + %jmp/0xz T_158.2, 4; + %load/vec4 v0x55dd3fb477a0_0; + %addi 1, 0, 2; + %assign/vec4 v0x55dd3fb477a0_0, 0; +T_158.2 ; + %load/vec4 v0x55dd3fb475a0_0; + %flag_set/vec4 8; + %jmp/0xz T_158.4, 8; + %pushi/vec4 1, 0, 2; + %assign/vec4 v0x55dd3fb477a0_0, 0; +T_158.4 ; +T_158.1 ; + %jmp T_158; + .thread T_158; + .scope S_0x55dd3fb40fa0; +T_159 ; + %wait E_0x55dd3fb3d620; + %load/vec4 v0x55dd3fb417b0_0; + %flag_set/vec4 8; + %jmp/0xz T_159.0, 8; + %pushi/vec4 0, 0, 5; + %assign/vec4 v0x55dd3fb416d0_0, 0; + %jmp T_159.1; +T_159.0 ; + %load/vec4 v0x55dd3fb416d0_0; + %cmpi/ne 0, 0, 5; + %jmp/0xz T_159.2, 4; + %load/vec4 v0x55dd3fb416d0_0; + %addi 1, 0, 5; + %assign/vec4 v0x55dd3fb416d0_0, 0; +T_159.2 ; + %load/vec4 v0x55dd3fb41500_0; + %flag_set/vec4 8; + %jmp/0xz T_159.4, 8; + %pushi/vec4 1, 0, 5; + %assign/vec4 v0x55dd3fb416d0_0, 0; +T_159.4 ; +T_159.1 ; + %jmp T_159; + .thread T_159; + .scope S_0x55dd3fb418d0; +T_160 ; + %wait E_0x55dd3fb3d620; + %load/vec4 v0x55dd3fb42200_0; + %flag_set/vec4 8; + %jmp/0xz T_160.0, 8; + %pushi/vec4 0, 0, 6; + %assign/vec4 v0x55dd3fb42120_0, 0; + %jmp T_160.1; +T_160.0 ; + %load/vec4 v0x55dd3fb42120_0; + %cmpi/ne 0, 0, 6; + %jmp/0xz T_160.2, 4; + %load/vec4 v0x55dd3fb42120_0; + %addi 1, 0, 6; + %assign/vec4 v0x55dd3fb42120_0, 0; +T_160.2 ; + %load/vec4 v0x55dd3fb41f90_0; + %flag_set/vec4 8; + %jmp/0xz T_160.4, 8; + %pushi/vec4 1, 0, 6; + %assign/vec4 v0x55dd3fb42120_0, 0; +T_160.4 ; +T_160.1 ; + %jmp T_160; + .thread T_160; + .scope S_0x55dd3fb42350; +T_161 ; + %wait E_0x55dd3fb3d620; + %load/vec4 v0x55dd3fb42b60_0; + %flag_set/vec4 8; + %jmp/0xz T_161.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x55dd3fb42a80_0, 0; + %jmp T_161.1; +T_161.0 ; + %load/vec4 v0x55dd3fb42a80_0; + %cmpi/ne 0, 0, 2; + %jmp/0xz T_161.2, 4; + %load/vec4 v0x55dd3fb42a80_0; + %addi 1, 0, 2; + %assign/vec4 v0x55dd3fb42a80_0, 0; +T_161.2 ; + %load/vec4 v0x55dd3fb42900_0; + %flag_set/vec4 8; + %jmp/0xz T_161.4, 8; + %pushi/vec4 1, 0, 2; + %assign/vec4 v0x55dd3fb42a80_0, 0; +T_161.4 ; +T_161.1 ; + %jmp T_161; + .thread T_161; + .scope S_0x55dd3fb3cb20; +T_162 ; + %wait E_0x55dd3fb3d620; + %load/vec4 v0x55dd3fb5d210_0; + %flag_set/vec4 8; + %jmp/0xz T_162.0, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb5a5f0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb5a7d0_0, 0; + %pushi/vec4 0, 0, 36; + %assign/vec4 v0x55dd3fb5d2b0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb57950_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb580d0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb58270_0, 0; + %jmp T_162.1; +T_162.0 ; + %load/vec4 v0x55dd3fb5a7d0_0; + %load/vec4 v0x55dd3fb5a730_0; + %inv; + %and; + %flag_set/vec4 8; + %jmp/0xz T_162.2, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb5a7d0_0, 0; +T_162.2 ; + %load/vec4 v0x55dd3fb5a5f0_0; + %load/vec4 v0x55dd3fb5a730_0; + %inv; + %and; + %flag_set/vec4 8; + %jmp/0xz T_162.4, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb5a5f0_0, 0; + %load/vec4 v0x55dd3fb5a690_0; + %assign/vec4 v0x55dd3fb5d2b0_0, 0; +T_162.4 ; + %load/vec4 v0x55dd3fb58b40_0; + %flag_set/vec4 8; + %jmp/0xz T_162.6, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb57a10_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb57b90_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb57d10_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb57e90_0, 0; +T_162.6 ; + %load/vec4 v0x55dd3fb5a0c0_0; + %load/vec4 v0x55dd3fb5a160_0; + %or; + %load/vec4 v0x55dd3fb5a200_0; + %or; + %load/vec4 v0x55dd3fb5a2a0_0; + %or; + %flag_set/vec4 8; + %jmp/0xz T_162.8, 8; + %load/vec4 v0x55dd3fb5a0c0_0; + %flag_set/vec4 8; + %jmp/0xz T_162.10, 8; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x55dd3fb57a10_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb57b90_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb57d10_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb57e90_0, 0; + %jmp T_162.11; +T_162.10 ; + %load/vec4 v0x55dd3fb5a160_0; + %flag_set/vec4 8; + %jmp/0xz T_162.12, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb57a10_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x55dd3fb57b90_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb57d10_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb57e90_0, 0; + %jmp T_162.13; +T_162.12 ; + %load/vec4 v0x55dd3fb5a200_0; + %load/vec4 v0x55dd3fb5a2a0_0; + %and; + %flag_set/vec4 8; + %jmp/0xz T_162.14, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb57a10_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb57b90_0, 0; + %load/vec4 v0x55dd3fb57950_0; + %assign/vec4 v0x55dd3fb57d10_0, 0; + %load/vec4 v0x55dd3fb57950_0; + %inv; + %assign/vec4 v0x55dd3fb57e90_0, 0; + %load/vec4 v0x55dd3fb57950_0; + %inv; + %assign/vec4 v0x55dd3fb57950_0, 0; + %jmp T_162.15; +T_162.14 ; + %load/vec4 v0x55dd3fb5a200_0; + %flag_set/vec4 8; + %jmp/0xz T_162.16, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb57a10_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb57b90_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x55dd3fb57d10_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb57e90_0, 0; + %jmp T_162.17; +T_162.16 ; + %load/vec4 v0x55dd3fb5a2a0_0; + %flag_set/vec4 8; + %jmp/0xz T_162.18, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb57a10_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb57b90_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb57d10_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x55dd3fb57e90_0, 0; +T_162.18 ; +T_162.17 ; +T_162.15 ; +T_162.13 ; +T_162.11 ; +T_162.8 ; + %load/vec4 v0x55dd3fb59920_0; + %flag_set/vec4 8; + %jmp/0xz T_162.20, 8; + %load/vec4 v0x55dd3fb57d10_0; + %flag_set/vec4 8; + %jmp/0xz T_162.22, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb57950_0, 0; +T_162.22 ; + %load/vec4 v0x55dd3fb57e90_0; + %flag_set/vec4 8; + %jmp/0xz T_162.24, 8; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x55dd3fb57950_0, 0; +T_162.24 ; +T_162.20 ; + %load/vec4 v0x55dd3fb58cb0_0; + %load/vec4 v0x55dd3fb575e0_0; + %or; + %flag_set/vec4 8; + %jmp/0xz T_162.26, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb57520_0, 0; +T_162.26 ; + %load/vec4 v0x55dd3fb59de0_0; + %load/vec4 v0x55dd3fb57460_0; + %or; + %flag_set/vec4 8; + %jmp/0xz T_162.28, 8; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x55dd3fb57520_0, 0; +T_162.28 ; + %load/vec4 v0x55dd3fb58a70_0; + %load/vec4 v0x55dd3fb583e0_0; + %or; + %flag_set/vec4 8; + %jmp/0xz T_162.30, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb58890_0, 0; +T_162.30 ; + %load/vec4 v0x55dd3fb58930_0; + %load/vec4 v0x55dd3fb58cb0_0; + %load/vec4 v0x55dd3fb589d0_0; + %and; + %or; + %flag_set/vec4 8; + %jmp/0xz T_162.32, 8; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x55dd3fb58890_0, 0; +T_162.32 ; + %load/vec4 v0x55dd3fb583e0_0; + %flag_set/vec4 8; + %jmp/0xz T_162.34, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb57750_0, 0; +T_162.34 ; + %load/vec4 v0x55dd3fb59eb0_0; + %load/vec4 v0x55dd3fb58c10_0; + %inv; + %and; + %flag_set/vec4 8; + %jmp/0xz T_162.36, 8; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x55dd3fb57750_0, 0; +T_162.36 ; + %load/vec4 v0x55dd3fb58f30_0; + %flag_set/vec4 8; + %jmp/0xz T_162.38, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb58270_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb580d0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb58c10_0, 0; +T_162.38 ; + %load/vec4 v0x55dd3fb58310_0; + %flag_set/vec4 8; + %jmp/0xz T_162.40, 8; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x55dd3fb58270_0, 0; +T_162.40 ; + %load/vec4 v0x55dd3fb5a3e0_0; + %flag_set/vec4 8; + %jmp/0xz T_162.42, 8; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x55dd3fb580d0_0, 0; +T_162.42 ; + %load/vec4 v0x55dd3fb58a70_0; + %flag_set/vec4 8; + %jmp/0xz T_162.44, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb58c10_0, 0; +T_162.44 ; + %load/vec4 v0x55dd3fb59920_0; + %load/vec4 v0x55dd3fb5d520_0; + %and; + %flag_set/vec4 8; + %jmp/0xz T_162.46, 8; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x55dd3fb58c10_0, 0; +T_162.46 ; + %load/vec4 v0x55dd3fb59920_0; + %flag_set/vec4 8; + %jmp/0xz T_162.48, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb58890_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb57750_0, 0; +T_162.48 ; + %load/vec4 v0x55dd3fb57890_0; + %flag_set/vec4 8; + %jmp/0xz T_162.50, 8; + %load/vec4 v0x55dd3fb5a950_0; + %assign/vec4 v0x55dd3fb57120_0, 0; + %load/vec4 v0x55dd3fb5d170_0; + %assign/vec4 v0x55dd3fb57200_0, 0; + %load/vec4 v0x55dd3fb5d5c0_0; + %assign/vec4 v0x55dd3fb572c0_0, 0; +T_162.50 ; + %load/vec4 v0x55dd3fb57380_0; + %load/vec4 v0x55dd3fb5aa30_0; + %or; + %assign/vec4 v0x55dd3fb57380_0, 0; + %load/vec4 v0x55dd3fb57680_0; + %flag_set/vec4 8; + %jmp/0xz T_162.52, 8; + %pushi/vec4 0, 0, 36; + %assign/vec4 v0x55dd3fb57380_0, 0; +T_162.52 ; + %load/vec4 v0x55dd3fb5d390_0; + %flag_set/vec4 8; + %jmp/0xz T_162.54, 8; + %load/vec4 v0x55dd3fb57380_0; + %load/vec4 v0x55dd3fb5d2b0_0; + %or; + %assign/vec4 v0x55dd3fb57380_0, 0; +T_162.54 ; + %load/vec4 v0x55dd3fb583e0_0; + %load/vec4 v0x55dd3fb59de0_0; + %or; + %flag_set/vec4 8; + %jmp/0xz T_162.56, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb58650_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb5a020_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb577f0_0, 0; +T_162.56 ; + %load/vec4 v0x55dd3fb58df0_0; + %flag_set/vec4 8; + %jmp/0xz T_162.58, 8; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x55dd3fb58650_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x55dd3fb5a5f0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb5a020_0, 0; +T_162.58 ; + %load/vec4 v0x55dd3fb586f0_0; + %flag_set/vec4 8; + %jmp/0xz T_162.60, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb58650_0, 0; +T_162.60 ; + %load/vec4 v0x55dd3fb59b00_0; + %flag_set/vec4 8; + %jmp/0xz T_162.62, 8; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x55dd3fb577f0_0, 0; +T_162.62 ; + %load/vec4 v0x55dd3fb59d10_0; + %flag_set/vec4 8; + %jmp/0xz T_162.64, 8; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x55dd3fb5a020_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x55dd3fb5a7d0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb58650_0, 0; +T_162.64 ; +T_162.1 ; + %jmp T_162; + .thread T_162; + .scope S_0x55dd3fb5df80; +T_163 ; + %wait E_0x55dd3fb5e3c0; + %load/vec4 v0x55dd3fb5ebf0_0; + %flag_set/vec4 8; + %jmp/0xz T_163.0, 8; + %load/vec4 v0x55dd3fb5e9c0_0; + %load/vec4 v0x55dd3fb5e710_0; + %pad/u 17; + %ix/vec4 3; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x55dd3fb5eb50, 0, 4; +T_163.0 ; + %load/vec4 v0x55dd3fb5e710_0; + %assign/vec4 v0x55dd3fb5e7f0_0, 0; + %jmp T_163; + .thread T_163; + .scope S_0x55dd3fb5dd60; +T_164 ; + %wait E_0x55dd3fb5e3c0; + %load/vec4 v0x55dd3fb5f550_0; + %inv; + %flag_set/vec4 8; + %jmp/0xz T_164.0, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb5f920_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb5f880_0, 0; + %jmp T_164.1; +T_164.0 ; + %load/vec4 v0x55dd3fb5f3f0_0; + %load/vec4 v0x55dd3fb5f620_0; + %or; + %flag_set/vec4 8; + %jmp/0xz T_164.2, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb5f880_0, 0; + %jmp T_164.3; +T_164.2 ; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x55dd3fb5f880_0, 0; +T_164.3 ; + %load/vec4 v0x55dd3fb5f920_0; + %flag_set/vec4 8; + %jmp/0xz T_164.4, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb5f920_0, 0; + %jmp T_164.5; +T_164.4 ; + %load/vec4 v0x55dd3fb5f620_0; + %load/vec4 v0x55dd3fb5f1c0_0; + %and; + %assign/vec4 v0x55dd3fb5f920_0, 0; +T_164.5 ; +T_164.1 ; + %jmp T_164; + .thread T_164; + .scope S_0x55dd3fb68a50; +T_165 ; + %wait E_0x55dd3fb60750; + %load/vec4 v0x55dd3fb691b0_0; + %flag_set/vec4 8; + %jmp/0xz T_165.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x55dd3fb69250_0, 0; + %jmp T_165.1; +T_165.0 ; + %load/vec4 v0x55dd3fb69250_0; + %parti/s 1, 0, 2; + %load/vec4 v0x55dd3fb68fe0_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x55dd3fb69250_0, 0; +T_165.1 ; + %jmp T_165; + .thread T_165; + .scope S_0x55dd3fb693b0; +T_166 ; + %wait E_0x55dd3fb60750; + %load/vec4 v0x55dd3fb69b10_0; + %flag_set/vec4 8; + %jmp/0xz T_166.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x55dd3fb69bb0_0, 0; + %jmp T_166.1; +T_166.0 ; + %load/vec4 v0x55dd3fb69bb0_0; + %parti/s 1, 0, 2; + %load/vec4 v0x55dd3fb69940_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x55dd3fb69bb0_0, 0; +T_166.1 ; + %jmp T_166; + .thread T_166; + .scope S_0x55dd3fb69d10; +T_167 ; + %wait E_0x55dd3fb60750; + %load/vec4 v0x55dd3fb6a450_0; + %flag_set/vec4 8; + %jmp/0xz T_167.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x55dd3fb6a700_0, 0; + %jmp T_167.1; +T_167.0 ; + %load/vec4 v0x55dd3fb6a700_0; + %parti/s 1, 0, 2; + %load/vec4 v0x55dd3fb6a2a0_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x55dd3fb6a700_0, 0; +T_167.1 ; + %jmp T_167; + .thread T_167; + .scope S_0x55dd3fb6a870; +T_168 ; + %wait E_0x55dd3fb60750; + %load/vec4 v0x55dd3fb6afb0_0; + %flag_set/vec4 8; + %jmp/0xz T_168.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x55dd3fb6b050_0, 0; + %jmp T_168.1; +T_168.0 ; + %load/vec4 v0x55dd3fb6b050_0; + %parti/s 1, 0, 2; + %load/vec4 v0x55dd3fb6ae00_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x55dd3fb6b050_0, 0; +T_168.1 ; + %jmp T_168; + .thread T_168; + .scope S_0x55dd3fb604e0; +T_169 ; + %wait E_0x55dd3fb60750; + %load/vec4 v0x55dd3fb60cf0_0; + %flag_set/vec4 8; + %jmp/0xz T_169.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x55dd3fb60db0_0, 0; + %jmp T_169.1; +T_169.0 ; + %load/vec4 v0x55dd3fb60db0_0; + %parti/s 1, 0, 2; + %load/vec4 v0x55dd3fb60b20_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x55dd3fb60db0_0, 0; +T_169.1 ; + %jmp T_169; + .thread T_169; + .scope S_0x55dd3fb65220; +T_170 ; + %wait E_0x55dd3fb60750; + %load/vec4 v0x55dd3fb659c0_0; + %flag_set/vec4 8; + %jmp/0xz T_170.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x55dd3fb65a60_0, 0; + %jmp T_170.1; +T_170.0 ; + %load/vec4 v0x55dd3fb65a60_0; + %parti/s 1, 0, 2; + %load/vec4 v0x55dd3fb65840_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x55dd3fb65a60_0, 0; +T_170.1 ; + %jmp T_170; + .thread T_170; + .scope S_0x55dd3fb65bc0; +T_171 ; + %wait E_0x55dd3fb60750; + %load/vec4 v0x55dd3fb66300_0; + %flag_set/vec4 8; + %jmp/0xz T_171.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x55dd3fb663a0_0, 0; + %jmp T_171.1; +T_171.0 ; + %load/vec4 v0x55dd3fb663a0_0; + %parti/s 1, 0, 2; + %load/vec4 v0x55dd3fb66150_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x55dd3fb663a0_0, 0; +T_171.1 ; + %jmp T_171; + .thread T_171; + .scope S_0x55dd3fb66500; +T_172 ; + %wait E_0x55dd3fb60750; + %load/vec4 v0x55dd3fb66c20_0; + %flag_set/vec4 8; + %jmp/0xz T_172.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x55dd3fb66cc0_0, 0; + %jmp T_172.1; +T_172.0 ; + %load/vec4 v0x55dd3fb66cc0_0; + %parti/s 1, 0, 2; + %load/vec4 v0x55dd3fb66a90_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x55dd3fb66cc0_0, 0; +T_172.1 ; + %jmp T_172; + .thread T_172; + .scope S_0x55dd3fb66e50; +T_173 ; + %wait E_0x55dd3fb60750; + %load/vec4 v0x55dd3fb67570_0; + %flag_set/vec4 8; + %jmp/0xz T_173.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x55dd3fb67610_0, 0; + %jmp T_173.1; +T_173.0 ; + %load/vec4 v0x55dd3fb67610_0; + %parti/s 1, 0, 2; + %load/vec4 v0x55dd3fb673e0_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x55dd3fb67610_0, 0; +T_173.1 ; + %jmp T_173; + .thread T_173; + .scope S_0x55dd3fb677a0; +T_174 ; + %wait E_0x55dd3fb60750; + %load/vec4 v0x55dd3fb67ec0_0; + %flag_set/vec4 8; + %jmp/0xz T_174.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x55dd3fb67f60_0, 0; + %jmp T_174.1; +T_174.0 ; + %load/vec4 v0x55dd3fb67f60_0; + %parti/s 1, 0, 2; + %load/vec4 v0x55dd3fb67d30_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x55dd3fb67f60_0, 0; +T_174.1 ; + %jmp T_174; + .thread T_174; + .scope S_0x55dd3fb6b1c0; +T_175 ; + %wait E_0x55dd3fb60750; + %load/vec4 v0x55dd3fb6b950_0; + %flag_set/vec4 8; + %jmp/0xz T_175.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x55dd3fb6b9f0_0, 0; + %jmp T_175.1; +T_175.0 ; + %load/vec4 v0x55dd3fb6b9f0_0; + %parti/s 1, 0, 2; + %load/vec4 v0x55dd3fb6b750_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x55dd3fb6b9f0_0, 0; +T_175.1 ; + %jmp T_175; + .thread T_175; + .scope S_0x55dd3fb680f0; +T_176 ; + %wait E_0x55dd3fb60750; + %load/vec4 v0x55dd3fb68850_0; + %flag_set/vec4 8; + %jmp/0xz T_176.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x55dd3fb688f0_0, 0; + %jmp T_176.1; +T_176.0 ; + %load/vec4 v0x55dd3fb688f0_0; + %parti/s 1, 0, 2; + %load/vec4 v0x55dd3fb68680_0; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0x55dd3fb688f0_0, 0; +T_176.1 ; + %jmp T_176; + .thread T_176; + .scope S_0x55dd3fb62bc0; +T_177 ; + %wait E_0x55dd3fb60750; + %load/vec4 v0x55dd3fb63440_0; + %flag_set/vec4 8; + %jmp/0xz T_177.0, 8; + %pushi/vec4 0, 0, 4; + %assign/vec4 v0x55dd3fb63360_0, 0; + %jmp T_177.1; +T_177.0 ; + %load/vec4 v0x55dd3fb63360_0; + %cmpi/ne 0, 0, 4; + %jmp/0xz T_177.2, 4; + %load/vec4 v0x55dd3fb63360_0; + %addi 1, 0, 4; + %assign/vec4 v0x55dd3fb63360_0, 0; +T_177.2 ; + %load/vec4 v0x55dd3fb63190_0; + %flag_set/vec4 8; + %jmp/0xz T_177.4, 8; + %pushi/vec4 1, 0, 4; + %assign/vec4 v0x55dd3fb63360_0, 0; +T_177.4 ; +T_177.1 ; + %jmp T_177; + .thread T_177; + .scope S_0x55dd3fb635f0; +T_178 ; + %wait E_0x55dd3fb60750; + %load/vec4 v0x55dd3fb63e00_0; + %flag_set/vec4 8; + %jmp/0xz T_178.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x55dd3fb63d20_0, 0; + %jmp T_178.1; +T_178.0 ; + %load/vec4 v0x55dd3fb63d20_0; + %cmpi/ne 0, 0, 2; + %jmp/0xz T_178.2, 4; + %load/vec4 v0x55dd3fb63d20_0; + %addi 1, 0, 2; + %assign/vec4 v0x55dd3fb63d20_0, 0; +T_178.2 ; + %load/vec4 v0x55dd3fb63b50_0; + %flag_set/vec4 8; + %jmp/0xz T_178.4, 8; + %pushi/vec4 1, 0, 2; + %assign/vec4 v0x55dd3fb63d20_0, 0; +T_178.4 ; +T_178.1 ; + %jmp T_178; + .thread T_178; + .scope S_0x55dd3fb63f20; +T_179 ; + %wait E_0x55dd3fb60750; + %load/vec4 v0x55dd3fb647b0_0; + %flag_set/vec4 8; + %jmp/0xz T_179.0, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x55dd3fb646d0_0, 0; + %jmp T_179.1; +T_179.0 ; + %load/vec4 v0x55dd3fb646d0_0; + %cmpi/ne 0, 0, 3; + %jmp/0xz T_179.2, 4; + %load/vec4 v0x55dd3fb646d0_0; + %addi 1, 0, 3; + %assign/vec4 v0x55dd3fb646d0_0, 0; +T_179.2 ; + %load/vec4 v0x55dd3fb644d0_0; + %flag_set/vec4 8; + %jmp/0xz T_179.4, 8; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x55dd3fb646d0_0, 0; +T_179.4 ; +T_179.1 ; + %jmp T_179; + .thread T_179; + .scope S_0x55dd3fb648d0; +T_180 ; + %wait E_0x55dd3fb60750; + %load/vec4 v0x55dd3fb65100_0; + %flag_set/vec4 8; + %jmp/0xz T_180.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x55dd3fb65020_0, 0; + %jmp T_180.1; +T_180.0 ; + %load/vec4 v0x55dd3fb65020_0; + %cmpi/ne 0, 0, 2; + %jmp/0xz T_180.2, 4; + %load/vec4 v0x55dd3fb65020_0; + %addi 1, 0, 2; + %assign/vec4 v0x55dd3fb65020_0, 0; +T_180.2 ; + %load/vec4 v0x55dd3fb64e50_0; + %flag_set/vec4 8; + %jmp/0xz T_180.4, 8; + %pushi/vec4 1, 0, 2; + %assign/vec4 v0x55dd3fb65020_0, 0; +T_180.4 ; +T_180.1 ; + %jmp T_180; + .thread T_180; + .scope S_0x55dd3fb60f10; +T_181 ; + %wait E_0x55dd3fb60750; + %load/vec4 v0x55dd3fb61770_0; + %flag_set/vec4 8; + %jmp/0xz T_181.0, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x55dd3fb61690_0, 0; + %jmp T_181.1; +T_181.0 ; + %load/vec4 v0x55dd3fb61690_0; + %cmpi/ne 0, 0, 3; + %jmp/0xz T_181.2, 4; + %load/vec4 v0x55dd3fb61690_0; + %addi 1, 0, 3; + %assign/vec4 v0x55dd3fb61690_0, 0; +T_181.2 ; + %load/vec4 v0x55dd3fb614c0_0; + %flag_set/vec4 8; + %jmp/0xz T_181.4, 8; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x55dd3fb61690_0, 0; +T_181.4 ; +T_181.1 ; + %jmp T_181; + .thread T_181; + .scope S_0x55dd3fb618a0; +T_182 ; + %wait E_0x55dd3fb60750; + %load/vec4 v0x55dd3fb62110_0; + %flag_set/vec4 8; + %jmp/0xz T_182.0, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x55dd3fb62030_0, 0; + %jmp T_182.1; +T_182.0 ; + %load/vec4 v0x55dd3fb62030_0; + %cmpi/ne 0, 0, 3; + %jmp/0xz T_182.2, 4; + %load/vec4 v0x55dd3fb62030_0; + %addi 1, 0, 3; + %assign/vec4 v0x55dd3fb62030_0, 0; +T_182.2 ; + %load/vec4 v0x55dd3fb61e60_0; + %flag_set/vec4 8; + %jmp/0xz T_182.4, 8; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x55dd3fb62030_0, 0; +T_182.4 ; +T_182.1 ; + %jmp T_182; + .thread T_182; + .scope S_0x55dd3fb62280; +T_183 ; + %wait E_0x55dd3fb60750; + %load/vec4 v0x55dd3fb62a70_0; + %flag_set/vec4 8; + %jmp/0xz T_183.0, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x55dd3fb62990_0, 0; + %jmp T_183.1; +T_183.0 ; + %load/vec4 v0x55dd3fb62990_0; + %cmpi/ne 0, 0, 3; + %jmp/0xz T_183.2, 4; + %load/vec4 v0x55dd3fb62990_0; + %addi 1, 0, 3; + %assign/vec4 v0x55dd3fb62990_0, 0; +T_183.2 ; + %load/vec4 v0x55dd3fb62800_0; + %flag_set/vec4 8; + %jmp/0xz T_183.4, 8; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x55dd3fb62990_0, 0; +T_183.4 ; +T_183.1 ; + %jmp T_183; + .thread T_183; + .scope S_0x55dd3fb5fa90; +T_184 ; + %wait E_0x55dd3fb5e3c0; + %load/vec4 v0x55dd3fb70ba0_0; + %load/vec4 v0x55dd3fb707c0_0; + %or; + %flag_set/vec4 8; + %jmp/0xz T_184.0, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb700c0_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x55dd3fb70de0_0, 0; +T_184.0 ; + %load/vec4 v0x55dd3fb715a0_0; + %load/vec4 v0x55dd3fb71640_0; + %or; + %load/vec4 v0x55dd3fb716e0_0; + %or; + %load/vec4 v0x55dd3fb71780_0; + %or; + %flag_set/vec4 8; + %jmp/0xz T_184.2, 8; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x55dd3fb700c0_0, 0; +T_184.2 ; + %load/vec4 v0x55dd3fb70f20_0; + %flag_set/vec4 8; + %jmp/0xz T_184.4, 8; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x55dd3fb70c70_0, 0; +T_184.4 ; + %load/vec4 v0x55dd3fb6fdf0_0; + %inv; + %flag_set/vec4 8; + %jmp/0xz T_184.6, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb70890_0, 0; +T_184.6 ; + %load/vec4 v0x55dd3fb70930_0; + %flag_set/vec4 8; + %jmp/0xz T_184.8, 8; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x55dd3fb70890_0, 0; +T_184.8 ; + %load/vec4 v0x55dd3fb70ff0_0; + %flag_set/vec4 8; + %jmp/0xz T_184.10, 8; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x55dd3fb70e80_0, 0; +T_184.10 ; + %load/vec4 v0x55dd3fb6fbb0_0; + %flag_set/vec4 8; + %jmp/0xz T_184.12, 8; + %pushi/vec4 0, 0, 36; + %ix/getv 3, v0x55dd3fb6fd10_0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x55dd3fb6faf0, 0, 4; +T_184.12 ; + %load/vec4 v0x55dd3fb70e80_0; + %flag_set/vec4 8; + %jmp/0xz T_184.14, 8; + %ix/getv 4, v0x55dd3fb6fd10_0; + %load/vec4a v0x55dd3fb6faf0, 4; + %load/vec4 v0x55dd3fb71820_0; + %or; + %ix/getv 3, v0x55dd3fb6fd10_0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x55dd3fb6faf0, 0, 4; +T_184.14 ; + %load/vec4 v0x55dd3fb710c0_0; + %flag_set/vec4 8; + %jmp/0xz T_184.16, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb70c70_0, 0; + %load/vec4 v0x55dd3fb74b00_0; + %assign/vec4 v0x55dd3fb70de0_0, 0; +T_184.16 ; + %load/vec4 v0x55dd3fb71430_0; + %flag_set/vec4 8; + %jmp/0xz T_184.18, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb700c0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb70890_0, 0; +T_184.18 ; + %load/vec4 v0x55dd3fb714d0_0; + %flag_set/vec4 8; + %jmp/0xz T_184.20, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb70de0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb70e80_0, 0; +T_184.20 ; + %load/vec4 v0x55dd3fb748a0_0; + %flag_set/vec4 8; + %jmp/0xz T_184.22, 8; + %load/vec4 v0x55dd3fb74960_0; + %load/vec4 v0x55dd3fb74580_0; + %parti/s 4, 0, 2; + %pad/u 6; + %ix/vec4 3; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x55dd3fb6faf0, 0, 4; +T_184.22 ; + %jmp T_184; + .thread T_184; + .scope S_0x55dd3fa340e0; +T_185 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x55dd3fb7a830_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x55dd3fb7a600_0, 0, 1; + %pushi/vec4 0, 0, 32; + %store/vec4 v0x55dd3fb7a970_0, 0, 32; + %pushi/vec4 0, 0, 18; + %store/vec4 v0x55dd3fb7bc20_0, 0, 18; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x55dd3fb7c0d0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x55dd3fb7bce0_0, 0, 1; + %pushi/vec4 0, 0, 36; + %store/vec4 v0x55dd3fb7c1a0_0, 0, 36; + %end; + .thread T_185; + .scope S_0x55dd3fa340e0; +T_186 ; + %vpi_call 16 200 "$dumpfile", "dump.vcd" {0 0 0}; + %vpi_call 16 201 "$dumpvars" {0 0 0}; + %pushi/vec4 2181570690, 0, 34; + %concati/vec4 0, 0, 2; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x55dd3fb5eb50, 4, 0; + %pushi/vec4 123, 0, 36; + %ix/load 4, 4, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x55dd3fb5eb50, 4, 0; + %pushi/vec4 321, 0, 36; + %ix/load 4, 5, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x55dd3fb5eb50, 4, 0; + %pushi/vec4 2493223645, 0, 34; + %concati/vec4 2, 0, 2; + %ix/load 4, 83, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x55dd3fb5eb50, 4, 0; + %pushi/vec4 2454267026, 0, 34; + %concati/vec4 1, 0, 2; + %ix/load 4, 84, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x55dd3fb5eb50, 4, 0; + %pushi/vec4 2454267026, 0, 34; + %concati/vec4 1, 0, 2; + %ix/load 4, 16467, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x55dd3fb5eb50, 4, 0; + %pushi/vec4 4294964955, 0, 32; + %concati/vec4 6, 0, 4; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x55dd3fb6faf0, 4, 0; + %pushi/vec4 3067831442, 0, 32; + %concati/vec4 4, 0, 4; + %ix/load 4, 4, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x55dd3fb6faf0, 4, 0; + %pushi/vec4 3681395858, 0, 33; + %concati/vec4 2, 0, 3; + %ix/load 4, 5, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x55dd3fb6faf0, 4, 0; + %delay 5, 0; + %delay 200, 0; + %delay 5000, 0; + %wait E_0x55dd3fb5e3c0; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x55dd3fb75570_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x55dd3fb7a830_0, 0; + %pushi/vec4 16467, 0, 32; + %assign/vec4 v0x55dd3fb7a970_0, 0; + %wait E_0x55dd3fb3c640; + %wait E_0x55dd3fb5e3c0; + %pushi/vec4 2, 0, 2; + %assign/vec4 v0x55dd3fb75570_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x55dd3fb7a600_0, 0; + %wait E_0x55dd3fb3c6c0; + %wait E_0x55dd3fb5e3c0; + %pushi/vec4 1, 0, 2; + %assign/vec4 v0x55dd3fb75570_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x55dd3fb7a600_0, 0; + %wait E_0x55dd3fb3c6c0; + %delay 2000, 0; + %wait E_0x55dd3fb5e3c0; + %pushi/vec4 1, 0, 2; + %assign/vec4 v0x55dd3fb75570_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x55dd3fb7a830_0, 0; + %pushi/vec4 365, 0, 32; + %assign/vec4 v0x55dd3fb7a970_0, 0; + %wait E_0x55dd3fb3c640; + %wait E_0x55dd3fb5e3c0; + %pushi/vec4 2, 0, 2; + %assign/vec4 v0x55dd3fb75570_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x55dd3fb7a830_0, 0; + %pushi/vec4 33410, 0, 32; + %assign/vec4 v0x55dd3fb7a970_0, 0; + %wait E_0x55dd3fb3c640; + %end; + .thread T_186; + .scope S_0x55dd3fa340e0; +T_187 ; + %delay 40000, 0; + %vpi_call 16 307 "$finish" {0 0 0}; + %end; + .thread T_187; + .scope S_0x55dd3fa340e0; +T_188 ; + %wait E_0x55dd3fb5e3c0; + %load/vec4 v0x55dd3fb7a790_0; + %inv; + %load/vec4 v0x55dd3fb7a830_0; + %and; + %flag_set/vec4 8; + %jmp/0xz T_188.0, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb7a830_0, 0; +T_188.0 ; + %load/vec4 v0x55dd3fb7a790_0; + %inv; + %load/vec4 v0x55dd3fb7a600_0; + %and; + %flag_set/vec4 8; + %jmp/0xz T_188.2, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb7a600_0, 0; + %load/vec4 v0x55dd3fb7a6f0_0; + %pad/u 36; + %assign/vec4 v0x55dd3fb7bb80_0, 0; +T_188.2 ; + %load/vec4 v0x55dd3fb7c030_0; + %inv; + %load/vec4 v0x55dd3fb7c0d0_0; + %and; + %flag_set/vec4 8; + %jmp/0xz T_188.4, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb7c0d0_0, 0; +T_188.4 ; + %load/vec4 v0x55dd3fb7c030_0; + %inv; + %load/vec4 v0x55dd3fb7bce0_0; + %and; + %flag_set/vec4 8; + %jmp/0xz T_188.6, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55dd3fb7bce0_0, 0; + %load/vec4 v0x55dd3fb7bf90_0; + %assign/vec4 v0x55dd3fb7bb80_0, 0; +T_188.6 ; + %jmp T_188; + .thread T_188; +# The file index is used to find the file name in the following table. +:file_names 21; + "N/A"; + ""; + "arbiter.v"; + "modules_50.v"; + "core161c.v"; + "dly_50.v"; + "core164.v"; + "memory.v"; + "clk.v"; + "fakeapr.v"; + "fast162.v"; + "memif.v"; + "memory_16.v"; + "onchip_ram.v"; + "memory_16k.v"; + "panel_6.v"; + "tb_membusif_x.v"; + "core32k.v"; + "memory_32k.v"; + "fast162_dp.v"; + "membusif.v"; diff --git a/verilog/tb/tb_membusif_x.v b/verilog/tb/tb_membusif_x.v new file mode 100644 index 0000000..3a9076d --- /dev/null +++ b/verilog/tb/tb_membusif_x.v @@ -0,0 +1,327 @@ +`default_nettype none +`timescale 1ns/1ns + +module tb_membusif(); + + wire clk, reset; + clock clock(clk, reset); + + // avalon + reg a_write = 0; + reg a_read = 0; + reg [31:0] a_writedata = 0; + reg [1:0] a_address; + wire [31:0] a_readdata; + wire a_waitrequest; + + // membus + wire b_rq_cyc; + wire b_rd_rq; + wire b_wr_rq; + wire [21:35] b_ma; + wire [18:21] b_sel; + wire b_fmc_select; + wire [0:35] b_mb_write; + wire b_wr_rs; + + wire [0:35] b_mb_read = b_mb_read_0 | b_mb_read_1; + wire b_addr_ack = b_addr_ack_0 | b_addr_ack_1; + wire b_rd_rs = b_rd_rs_0 | b_rd_rs_1; + + + membusif membusif0( + .clk(clk), + .reset(reset), + + .s_address(a_address), + .s_write(a_write), + .s_read(a_read), + .s_writedata(a_writedata), + .s_readdata(a_readdata), + .s_waitrequest(a_waitrequest), + + .m_rq_cyc(b_rq_cyc), + .m_rd_rq(b_rd_rq), + .m_wr_rq(b_wr_rq), + .m_ma(b_ma), + .m_sel(b_sel), + .m_fmc_select(b_fmc_select), + .m_mb_write(b_mb_write), + .m_wr_rs(b_wr_rs), + .m_mb_read(b_mb_read), + .m_addr_ack(b_addr_ack), + .m_rd_rs(b_rd_rs)); + + + // Memory + wire [17:0] cm_address; + wire cm_write; + wire cm_read; + wire [35:0] cm_writedata; + wire [35:0] cm_readdata; + wire cm_waitrequest; + + wire [0:35] b_mb_read_0; + wire b_addr_ack_0; + wire b_rd_rs_0; +// core161c_x cmem( +// core164 cmem( + core32k cmem( + .clk(clk), + .reset(~reset), + .power(1'b1), + .sw_single_step(1'b0), + .sw_restart(1'b0), + + .membus_rq_cyc_p0(b_rq_cyc), + .membus_rd_rq_p0(b_rd_rq), + .membus_wr_rq_p0(b_wr_rq), + .membus_ma_p0(b_ma), + .membus_sel_p0(b_sel), + .membus_fmc_select_p0(b_fmc_select), + .membus_mb_in_p0(b_mb_write), + .membus_wr_rs_p0(b_wr_rs), + .membus_mb_out_p0(b_mb_read_0), + .membus_addr_ack_p0(b_addr_ack_0), + .membus_rd_rs_p0(b_rd_rs_0), + + .membus_wr_rs_p1(1'b0), + .membus_rq_cyc_p1(1'b0), + .membus_rd_rq_p1(1'b0), + .membus_wr_rq_p1(1'b0), + .membus_ma_p1(15'b0), + .membus_sel_p1(4'b0), + .membus_fmc_select_p1(1'b0), + .membus_mb_in_p1(36'b0), + + .membus_wr_rs_p2(1'b0), + .membus_rq_cyc_p2(1'b0), + .membus_rd_rq_p2(1'b0), + .membus_wr_rq_p2(1'b0), + .membus_ma_p2(15'b0), + .membus_sel_p2(4'b0), + .membus_fmc_select_p2(1'b0), + .membus_mb_in_p2(36'b0), + + .membus_wr_rs_p3(1'b0), + .membus_rq_cyc_p3(1'b0), + .membus_rd_rq_p3(1'b0), + .membus_wr_rq_p3(1'b0), + .membus_ma_p3(15'b0), + .membus_sel_p3(4'b0), + .membus_fmc_select_p3(1'b0), + .membus_mb_in_p3(36'b0), + + .m_address(cm_address), + .m_write(cm_write), + .m_read(cm_read), + .m_writedata(cm_writedata), + .m_readdata(cm_readdata), + .m_waitrequest(cm_waitrequest) + ); + +// memory_16k cmem_x( + memory_32k cmem_x( + .i_clk(clk), + .i_reset_n(reset), + .i_address(cm_address), + .i_write(cm_write), + .i_read(cm_read), + .i_writedata(cm_writedata), + .o_readdata(cm_readdata), + .o_waitrequest(cm_waitrequest)); + + reg [17:0] fm_address = 0; + reg fm_write = 0; + reg fm_read = 0; + reg [35:0] fm_writedata = 0; + wire [35:0] fm_readdata; + wire fm_waitrequest; + + wire [0:35] b_mb_read_1; + wire b_addr_ack_1; + wire b_rd_rs_1; + fast162_dp fmem( + .clk(clk), + .reset(~reset), + .power(1'b1), + .sw_single_step(1'b0), + .sw_restart(1'b0), + + .membus_rq_cyc_p0(b_rq_cyc), + .membus_rd_rq_p0(b_rd_rq), + .membus_wr_rq_p0(b_wr_rq), + .membus_ma_p0(b_ma), + .membus_sel_p0(b_sel), + .membus_fmc_select_p0(b_fmc_select), + .membus_mb_in_p0(b_mb_write), + .membus_wr_rs_p0(b_wr_rs), + .membus_mb_out_p0(b_mb_read_1), + .membus_addr_ack_p0(b_addr_ack_1), + .membus_rd_rs_p0(b_rd_rs_1), + + .membus_wr_rs_p1(1'b0), + .membus_rq_cyc_p1(1'b0), + .membus_rd_rq_p1(1'b0), + .membus_wr_rq_p1(1'b0), + .membus_ma_p1(15'b0), + .membus_sel_p1(4'b0), + .membus_fmc_select_p1(1'b0), + .membus_mb_in_p1(36'b0), + + .membus_wr_rs_p2(1'b0), + .membus_rq_cyc_p2(1'b0), + .membus_rd_rq_p2(1'b0), + .membus_wr_rq_p2(1'b0), + .membus_ma_p2(15'b0), + .membus_sel_p2(4'b0), + .membus_fmc_select_p2(1'b0), + .membus_mb_in_p2(36'b0), + + .membus_wr_rs_p3(1'b0), + .membus_rq_cyc_p3(1'b0), + .membus_rd_rq_p3(1'b0), + .membus_wr_rq_p3(1'b0), + .membus_ma_p3(15'b0), + .membus_sel_p3(4'b0), + .membus_fmc_select_p3(1'b0), + .membus_mb_in_p3(36'b0), + + + .s_address(fm_address), + .s_write(fm_write), + .s_read(fm_read), + .s_writedata(fm_writedata), + .s_readdata(fm_readdata), + .s_waitrequest(fm_waitrequest) + ); + + initial begin + $dumpfile("dump.vcd"); + $dumpvars(); + + cmem_x.ram.ram[3] = 36'o101010101010; + cmem_x.ram.ram[4] = 123; + cmem_x.ram.ram[5] = 321; + cmem_x.ram.ram['o123] = 36'o112233445566; + cmem_x.ram.ram['o124] = 36'o111111111111; + cmem_x.ram.ram['o40123] = 36'o111111111111; + fmem.ff[3] = 36'o777777666666; + fmem.ff[4] = 36'o555555444444; + fmem.ff[5] = 36'o333333222222; + + #5; + + #200; + #5000; + +/* + @(posedge clk); + fm_address <= 3; + fm_write <= 1; + fm_writedata <= 36'o1000123; + @(negedge fm_write); + + @(posedge clk); + fm_address <= 5; + fm_write <= 1; + fm_writedata <= 36'o101202303404; + @(negedge fm_write); + + @(posedge clk); + fm_address <= 3; + fm_read <= 1; + @(negedge fm_read); +*/ + + // write address + @(posedge clk); + a_address <= 0; + a_write <= 1; + a_writedata <= 32'o0040123; + @(negedge a_write); + + @(posedge clk); + a_address <= 2; + a_read <= 1; + @(negedge a_read); + + @(posedge clk); + a_address <= 1; + a_read <= 1; + @(negedge a_read); + + #2000; + + @(posedge clk); + a_address <= 1; + a_write <= 1; + a_writedata <= 32'o0000555; + @(negedge a_write); + + @(posedge clk); + a_address <= 2; + a_write <= 1; + a_writedata <= 32'o101202; + @(negedge a_write); + + + +/* // write address + @(posedge clk); + a_address <= 0; + a_write <= 1; + a_writedata <= 32'o0000124; + @(negedge a_write); + + @(posedge clk); + a_address <= 2; + a_read <= 1; + @(negedge a_read); + + @(posedge clk); + a_address <= 1; + a_read <= 1; + @(negedge a_read); +*/ + +/* + // write low word + @(posedge clk); + a_address <= 1; + a_write <= 1; + a_writedata <= 32'o111222; + @(negedge a_write); + + // write high word + @(posedge clk); + a_address <= 2; + a_write <= 1; + a_writedata <= 32'o333444; + @(negedge a_write); +*/ + end + + initial begin + #40000; + $finish; + end + + reg [0:35] data; + always @(posedge clk) begin + if(~a_waitrequest & a_write) + a_write <= 0; + if(~a_waitrequest & a_read) begin + a_read <= 0; + data <= a_readdata; + end + + if(~fm_waitrequest & fm_write) + fm_write <= 0; + if(~fm_waitrequest & fm_read) begin + fm_read <= 0; + data <= fm_readdata; + end + end + +endmodule diff --git a/verilog/tb/tb_memif.v b/verilog/tb/tb_memif.v new file mode 100644 index 0000000..402e34e --- /dev/null +++ b/verilog/tb/tb_memif.v @@ -0,0 +1,111 @@ +`default_nettype none +`timescale 1ns/1ns + +module tb_memif(); + + wire clk, reset; + clock clock(clk, reset); + + reg a_write = 0; + reg a_read = 0; + reg [31:0] a_writedata = 0; + reg [1:0] a_address; + wire [31:0] a_readdata; + wire a_waitrequest; + + wire [17:0] b_address; + wire b_write; + wire b_read; + wire [35:0] b_writedata; + wire [35:0] b_readdata; + wire b_waitrequest; + + memif memif0( + .clk(clk), + .reset(reset), + + .s_address(a_address), + .s_write(a_write), + .s_read(a_read), + .s_writedata(a_writedata), + .s_readdata(a_readdata), + .s_waitrequest(a_waitrequest), + + .m_address(b_address), + .m_write(b_write), + .m_read(b_read), + .m_writedata(b_writedata), + .m_readdata(b_readdata), + .m_waitrequest(b_waitrequest)); + + dlymemory memory( + .i_clk(clk), + .i_reset_n(reset), + + .i_address(b_address), + .i_write(b_write), + .i_read(b_read), + .i_writedata(b_writedata), + .o_readdata(b_readdata), + .o_waitrequest(b_waitrequest)); + + initial begin + $dumpfile("dump.vcd"); + $dumpvars(); + + memory.mem[4] = 123; + memory.mem[5] = 321; + memory.mem['o123] = 36'o112233445566; + + #5; + + #200; + + // write address + @(posedge clk); + a_address <= 0; + a_write <= 1; + a_writedata <= 32'o123; + @(negedge a_write); + + + @(posedge clk); + a_address <= 2; + a_read <= 1; + @(negedge a_read); + + @(posedge clk); + a_address <= 1; + a_read <= 1; + @(negedge a_read); + +/* + // write low word + @(posedge clk); + a_address <= 1; + a_write <= 1; + a_writedata <= 32'o111222; + @(negedge a_write); + + // write high word + @(posedge clk); + a_address <= 2; + a_write <= 1; + a_writedata <= 32'o333444; + @(negedge a_write); +*/ + end + + initial begin + #40000; + $finish; + end + + always @(posedge clk) begin + if(~a_waitrequest & a_write) + a_write <= 0; + if(~a_waitrequest & a_read) + a_read <= 0; + end + +endmodule diff --git a/verilog/tb/tb_panel.v b/verilog/tb/tb_panel.v new file mode 100644 index 0000000..54a71d9 --- /dev/null +++ b/verilog/tb/tb_panel.v @@ -0,0 +1,284 @@ +`default_nettype none +`timescale 1ns/1ns + +module tb_panel(); + + wire clk, reset; + clock clock(clk, reset); + + reg a_write = 0; + reg a_read = 0; + reg [31:0] a_writedata = 0; + reg [4:0] a_address; + wire [31:0] a_readdata; + wire a_waitrequest; + + + wire key_start; + wire key_read_in; + wire key_mem_cont; + wire key_inst_cont; + wire key_mem_stop; + wire key_inst_stop; + wire key_exec; + wire key_io_reset; + wire key_dep; + wire key_dep_nxt; + wire key_ex; + wire key_ex_nxt; + + // switches + wire sw_addr_stop; + wire sw_mem_disable; + wire sw_repeat; + wire sw_power; + wire [0:35] datasw; + wire [18:35] mas; + + // maintenance switches + wire sw_rim_maint; + wire sw_repeat_bypass; + wire sw_art3_maint; + wire sw_sct_maint; + wire sw_split_cyc; + + // lights + wire power; + wire [0:17] ir; + wire [0:35] mi; + wire [0:35] ar; + wire [0:35] mb; + wire [0:35] mq; + wire [18:35] pc; + wire [18:35] ma; + wire run; + wire mc_stop; + wire pi_active; + wire [1:7] pih; + wire [1:7] pir; + wire [1:7] pio; + wire [18:25] pr; + wire [18:25] rlr; + wire [18:25] rla; + wire [0:7] ff0; + wire [0:7] ff1; + wire [0:7] ff2; + wire [0:7] ff3; + wire [0:7] ff4; + wire [0:7] ff5; + wire [0:7] ff6; + wire [0:7] ff7; + wire [0:7] ff8; + wire [0:7] ff9; + wire [0:7] ff10; + wire [0:7] ff11; + wire [0:7] ff12; + wire [0:7] ff13; + + panel_6 panel( + .clk(clk), + .reset(reset), + + .s_address(a_address), + .s_write(a_write), + .s_read(a_read), + .s_writedata(a_writedata), + .s_readdata(a_readdata), + .s_waitrequest(a_waitrequest), + + .key_start(key_start), + .key_read_in(key_read_in), + .key_mem_cont(key_mem_cont), + .key_inst_cont(key_inst_cont), + .key_mem_stop(key_mem_stop), + .key_inst_stop(key_inst_stop), + .key_exec(key_exec), + .key_io_reset(key_io_reset), + .key_dep(key_dep), + .key_dep_nxt(key_dep_nxt), + .key_ex(key_ex), + .key_ex_nxt(key_ex_nxt), + .sw_addr_stop(sw_addr_stop), + .sw_mem_disable(sw_mem_disable), + .sw_repeat(sw_repeat), + .sw_power(sw_power), + .datasw(datasw), + .mas(mas), + .sw_rim_maint(sw_rim_maint), + .sw_repeat_bypass(sw_repeat_bypass), + .sw_art3_maint(sw_art3_maint), + .sw_sct_maint(sw_sct_maint), + .sw_split_cyc(sw_split_cyc), + .power(power), + .ir(ir), + .mi(mi), + .ar(ar), + .mb(mb), + .mq(mq), + .pc(pc), + .ma(ma), + .run(run), + .mc_stop(mc_stop), + .pi_active(pi_active), + .pih(pih), + .pir(pir), + .pio(pio), + .pr(pr), + .rlr(rlr), + .rla(rla), + .ff0(ff0), + .ff1(ff1), + .ff2(ff2), + .ff3(ff3), + .ff4(ff4), + .ff5(ff5), + .ff6(ff6), + .ff7(ff7), + .ff8(ff8), + .ff9(ff9), + .ff10(ff10), + .ff11(ff11), + .ff12(ff12), + .ff13(ff13) + ); + + fakeapr apr( + .clk(clk), + .reset(reset), + + .key_start(key_start), + .key_read_in(key_read_in), + .key_mem_cont(key_mem_cont), + .key_inst_cont(key_inst_cont), + .key_mem_stop(key_mem_stop), + .key_inst_stop(key_inst_stop), + .key_exec(key_exec), + .key_io_reset(key_io_reset), + .key_dep(key_dep), + .key_dep_nxt(key_dep_nxt), + .key_ex(key_ex), + .key_ex_nxt(key_ex_nxt), + .sw_addr_stop(sw_addr_stop), + .sw_mem_disable(sw_mem_disable), + .sw_repeat(sw_repeat), + .sw_power(sw_power), + .datasw(datasw), + .mas(mas), + .sw_rim_maint(sw_rim_maint), + .sw_repeat_bypass(sw_repeat_bypass), + .sw_art3_maint(sw_art3_maint), + .sw_sct_maint(sw_sct_maint), + .sw_split_cyc(sw_split_cyc), + .power(power), + .ir(ir), + .mi(mi), + .ar(ar), + .mb(mb), + .mq(mq), + .pc(pc), + .ma(ma), + .run(run), + .mc_stop(mc_stop), + .pi_active(pi_active), + .pih(pih), + .pir(pir), + .pio(pio), + .pr(pr), + .rlr(rlr), + .rla(rla), + .ff0(ff0), + .ff1(ff1), + .ff2(ff2), + .ff3(ff3), + .ff4(ff4), + .ff5(ff5), + .ff6(ff6), + .ff7(ff7), + .ff8(ff8), + .ff9(ff9), + .ff10(ff10), + .ff11(ff11), + .ff12(ff12), + .ff13(ff13) + ); + + initial begin + $dumpfile("dump.vcd"); + $dumpvars(); + + memory.mem[4] = 123; + memory.mem[5] = 321; + memory.mem['o123] = 36'o112233445566; + + #5; + + #200; + + @(posedge clk); + a_address <= 6; + a_write <= 1; + a_writedata = 32'o123456; + @(negedge a_write); + + @(posedge clk); + a_address <= 7; + a_write <= 1; + a_writedata = 32'o654321; + @(negedge a_write); + + @(posedge clk); + a_address <= 'o10; + a_write <= 1; + a_writedata = 32'o112233; + @(negedge a_write); + + @(posedge clk); + a_address <= 'o01; + a_write <= 1; + a_writedata = 32'o7777777; + @(negedge a_write); + + + @(posedge clk); + a_address <= 4; + a_read <= 1; + @(negedge a_read); + + @(posedge clk); + a_address <= 5; + a_read <= 1; + @(negedge a_read); + +/* + // write low word + @(posedge clk); + a_address <= 1; + a_write <= 1; + a_writedata <= 32'o111222; + @(negedge a_write); + + // write high word + @(posedge clk); + a_address <= 2; + a_write <= 1; + a_writedata <= 32'o333444; + @(negedge a_write); +*/ + end + + initial begin + #40000; + $finish; + end + + reg [0:35] data; + always @(posedge clk) begin + if(~a_waitrequest & a_write) + a_write <= 0; + if(~a_waitrequest & a_read) begin + a_read <= 0; + data <= a_readdata; + end + end + +endmodule diff --git a/verilog/tb/tb_ptp.v b/verilog/tb/tb_ptp.v new file mode 100644 index 0000000..cef9726 --- /dev/null +++ b/verilog/tb/tb_ptp.v @@ -0,0 +1,177 @@ +`default_nettype none +`timescale 1ns/1ns +`define simulation + +module tb_ptp(); + + wire clk, reset; + clock clock(clk, reset); + + reg read = 0; + wire [31:0] readdata; + reg [31:0] data; + + reg iobus_iob_poweron = 1; + reg iobus_iob_reset = 0; + reg iobus_datao_clear = 0; + reg iobus_datao_set = 0; + reg iobus_cono_clear = 0; + reg iobus_cono_set = 0; + reg iobus_iob_fm_datai = 0; + reg iobus_iob_fm_status = 0; + reg [3:9] iobus_ios = 0; + reg [0:35] iobus_iob_in = 0; + wire [1:7] iobus_pi_req; + wire [0:35] iobus_iob_out; + + reg key_tape_feed = 0; + + wire data_rq; + + ptp ptp(.clk(clk), .reset(~reset), + + .iobus_iob_poweron(iobus_iob_poweron), + .iobus_iob_reset(iobus_iob_reset), + .iobus_datao_clear(iobus_datao_clear), + .iobus_datao_set(iobus_datao_set), + .iobus_cono_clear(iobus_cono_clear), + .iobus_cono_set(iobus_cono_set), + .iobus_iob_fm_datai(iobus_iob_fm_datai), + .iobus_iob_fm_status(iobus_iob_fm_status), + .iobus_ios(iobus_ios), + .iobus_iob_in(iobus_iob_in), + .iobus_pi_req(iobus_pi_req), + .iobus_iob_out(iobus_iob_out), + + .key_tape_feed(key_tape_feed), + + .s_read(read), + .s_readdata(readdata), + + .fe_data_rq(data_rq)); + + + initial begin + $dumpfile("dump.vcd"); + $dumpvars(); + + #100; + iobus_iob_reset <= 1; + #100; + iobus_iob_reset <= 0; + #100; + iobus_ios <= 7'b001_000_0; + + + #200; + key_tape_feed <= 1; + ptp.ptp_pia <= 1; + ptp.ptp_flag <= 0; +// ptp.ptp_busy <= 1; + ptp.ptp <= 'o123; + +/* + #200; + ptp.ptp_busy <= 0; + #2200; + ptp.ptp_busy <= 1; +*/ + end + + initial begin: foo + integer i; + + @(posedge data_rq); + for(i = 0; i < 20; i = i+1) begin + @(posedge clk); + end + read <= 1; + @(posedge clk); + data <= readdata; + read <= 0; + +/* + @(posedge (|iobus_pi_req)); + @(posedge clk); + @(posedge clk); + @(posedge clk); + @(posedge clk); + @(posedge clk); + @(posedge clk); + @(posedge clk); + iobus_datao_clear <= 1; + @(posedge clk); + @(posedge clk); + @(posedge clk); + iobus_datao_clear <= 0; + iobus_datao_set <= 1; + iobus_iob_in <= 'o321; + @(posedge clk); + @(posedge clk); + @(posedge clk); + iobus_datao_set <= 0; +*/ + + @(posedge data_rq); + for(i = 0; i < 200; i = i+1) begin + @(posedge clk); + end + read <= 1; + @(posedge clk); + data <= readdata; + read <= 0; + +/* + @(posedge data_rq); + for(i = 0; i < 20; i = i+1) begin + @(posedge clk); + end + write <= 1; + writedata <= 'o255; + @(posedge clk); + write <= 0; + + @(posedge data_rq); + for(i = 0; i < 20; i = i+1) begin + @(posedge clk); + end + write <= 1; + writedata <= 'o244; + @(posedge clk); + write <= 0; + + @(posedge data_rq); + for(i = 0; i < 20; i = i+1) begin + @(posedge clk); + end + write <= 1; + writedata <= 'o233; + @(posedge clk); + write <= 0; + + @(posedge data_rq); + for(i = 0; i < 20; i = i+1) begin + @(posedge clk); + end + write <= 1; + writedata <= 'o222; + @(posedge clk); + write <= 0; + + + @(posedge (|iobus_pi_req)); + iobus_iob_fm_datai <= 1; + #400; + iobus_iob_fm_datai <= 0; + + key_stop <= 1; + #20; + key_stop <= 0; +*/ + end + + initial begin + #50000; + $finish; + end +endmodule diff --git a/verilog/tb/tb_ptr.v b/verilog/tb/tb_ptr.v new file mode 100644 index 0000000..b4c80f2 --- /dev/null +++ b/verilog/tb/tb_ptr.v @@ -0,0 +1,154 @@ +`default_nettype none +`timescale 1ns/1ns +`define simulation + +module tb_ptr(); + + wire clk, reset; + clock clock(clk, reset); + + reg write = 0; + reg [31:0] writedata = 0; + + reg iobus_iob_poweron = 1; + reg iobus_iob_reset = 0; + reg iobus_datao_clear = 0; + reg iobus_datao_set = 0; + reg iobus_cono_clear = 0; + reg iobus_cono_set = 0; + reg iobus_iob_fm_datai = 0; + reg iobus_iob_fm_status = 0; + reg [3:9] iobus_ios = 0; + reg [0:35] iobus_iob_in = 0; + wire [1:7] iobus_pi_req; + wire [0:35] iobus_iob_out; + + reg key_start = 0; + reg key_stop = 0; + reg key_tape_feed = 0; + + wire data_rq; + + ptr ptr(.clk(clk), .reset(~reset), + + .iobus_iob_poweron(iobus_iob_poweron), + .iobus_iob_reset(iobus_iob_reset), + .iobus_datao_clear(iobus_datao_clear), + .iobus_datao_set(iobus_datao_set), + .iobus_cono_clear(iobus_cono_clear), + .iobus_cono_set(iobus_cono_set), + .iobus_iob_fm_datai(iobus_iob_fm_datai), + .iobus_iob_fm_status(iobus_iob_fm_status), + .iobus_ios(iobus_ios), + .iobus_iob_in(iobus_iob_in), + .iobus_pi_req(iobus_pi_req), + .iobus_iob_out(iobus_iob_out), + + .key_start(key_start), + .key_stop(key_stop), + .key_tape_feed(key_tape_feed), + + .s_write(write), + .s_writedata(writedata), + + .fe_data_rq(data_rq)); + + + initial begin + $dumpfile("dump.vcd"); + $dumpvars(); + + #100; + iobus_iob_reset <= 1; + #100; + iobus_iob_reset <= 0; + #100; + iobus_ios <= 7'b001_000_1; + + + key_start <= 1; + #20; + key_start <= 0; + #200; +// key_tape_feed <= 1; + ptr.ptr_pia <= 1; + ptr.ptr_flag <= 0; + ptr.ptr_busy <= 1; + ptr.ptr <= 1; + end + + initial begin: foo + integer i; + + @(posedge data_rq); + for(i = 0; i < 20; i = i+1) begin + @(posedge clk); + end + write <= 1; + writedata <= 'o277; + @(posedge clk); + write <= 0; + +/* + @(posedge data_rq); + for(i = 0; i < 20; i = i+1) begin + @(posedge clk); + end + write <= 1; + writedata <= 'o266; + @(posedge clk); + write <= 0; + + @(posedge data_rq); + for(i = 0; i < 20; i = i+1) begin + @(posedge clk); + end + write <= 1; + writedata <= 'o255; + @(posedge clk); + write <= 0; + + @(posedge data_rq); + for(i = 0; i < 20; i = i+1) begin + @(posedge clk); + end + write <= 1; + writedata <= 'o244; + @(posedge clk); + write <= 0; + + @(posedge data_rq); + for(i = 0; i < 20; i = i+1) begin + @(posedge clk); + end + write <= 1; + writedata <= 'o233; + @(posedge clk); + write <= 0; + + @(posedge data_rq); + for(i = 0; i < 20; i = i+1) begin + @(posedge clk); + end + write <= 1; + writedata <= 'o222; + @(posedge clk); + write <= 0; + + + @(posedge (|iobus_pi_req)); + iobus_iob_fm_datai <= 1; + #400; + iobus_iob_fm_datai <= 0; + + key_stop <= 1; + #20; + key_stop <= 0; +*/ + end + + initial begin + #40000; + $finish; + end +endmodule diff --git a/verilog/test.gtkw b/verilog/test.gtkw deleted file mode 100644 index 4902f96..0000000 --- a/verilog/test.gtkw +++ /dev/null @@ -1,721 +0,0 @@ -[*] -[*] GTKWave Analyzer v3.3.76 (w)1999-2016 BSI -[*] Sun Dec 11 15:59:05 2016 -[*] -[dumpfile] "/home/aap/src/pdp6/verilog/dump.vcd" -[dumpfile_mtime] "Sun Dec 11 15:55:54 2016" -[dumpfile_size] 256855 -[savefile] "/home/aap/src/pdp6/verilog/test.gtkw" -[timestart] 0 -[size] 1920 1080 -[pos] -1 -1 -*-11.555068 5260 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -[treeopen] test. -[treeopen] test.pdp6. -[sst_width] 337 -[signals_width] 486 -[sst_expanded] 1 -[sst_vpaned_height] 319 -@28 -test.clk -test.reset -@c00200 --sw -@28 -test.pdp6.apr0.sw_power -test.pdp6.apr0.sw_repeat -test.pdp6.apr0.sw_addr_stop -test.pdp6.apr0.sw_mem_disable -test.pdp6.apr0.sw_rim_maint -test.pdp6.apr0.sw_split_cyc -test.pdp6.apr0.sw_repeat_bypass -test.pdp6.apr0.sw_art3_maint -test.pdp6.apr0.sw_sct_maint -@1401200 --sw -@c00200 --keys -@28 -test.pdp6.key_start -test.pdp6.key_read_in -test.pdp6.key_mem_cont -test.pdp6.key_inst_cont -test.pdp6.key_mem_stop -test.pdp6.key_inst_stop -test.pdp6.key_exec -test.pdp6.key_io_reset -test.pdp6.key_dep -test.pdp6.key_dep_nxt -test.pdp6.key_ex -test.pdp6.key_ex_nxt -@1401200 --keys -@800200 --regs -@30 -test.pdp6.apr0.ma[18:35] -test.pdp6.apr0.pc[18:35] -test.pdp6.apr0.ir[0:17] -test.pdp6.apr0.mb[0:35] -test.pdp6.apr0.ar[0:35] -test.pdp6.apr0.mq[0:35] -@28 -test.pdp6.apr0.mq36 -@30 -test.pdp6.apr0.sc[0:8] -test.pdp6.apr0.fe[0:8] -test.pdp6.apr0.datasw[0:35] -test.pdp6.apr0.mas[18:35] -@1000200 --regs -@c00200 --EX -@28 -test.pdp6.apr0.ex_user -test.pdp6.apr0.ex_mode_sync -test.pdp6.apr0.ex_uuo_sync -test.pdp6.apr0.ex_pi_sync -test.pdp6.apr0.ex_ill_op -test.pdp6.apr0.ex_inh_rel -@1401200 --EX -@c00200 --KEY -@28 -test.pdp6.apr0.run -test.pdp6.apr0.key_rim_sbr -test.pdp6.apr0.key_rdwr -test.pdp6.apr0.mr_pwr_clr -test.pdp6.apr0.mr_start -test.pdp6.apr0.mr_clr -test.pdp6.apr0.key_dep_st -test.pdp6.apr0.key_ex_st -test.pdp6.apr0.key_ex_sync -test.pdp6.apr0.key_dep_sync -@200 -- -@28 -test.pdp6.apr0.key_ma_clr -test.pdp6.apr0.key_ma_fm_masw1 -test.pdp6.apr0.key_ma_inc -test.pdp6.apr0.key_ar_clr -test.pdp6.apr0.key_ar_fm_datasw1 -test.pdp6.apr0.key_rd -test.pdp6.apr0.key_wr -test.pdp6.apr0.kt0 -test.pdp6.apr0.kt0a -test.pdp6.apr0.kt1 -test.pdp6.apr0.kt2 -test.pdp6.apr0.kt3 -test.pdp6.apr0.kt4 -test.pdp6.apr0.key_go -test.pdp6.apr0.key_rd -test.pdp6.apr0.key_wr -test.pdp6.apr0.key_rdwr_ret -@1401200 --KEY -@c00200 --MC -@28 -test.pdp6.apr0.mc_rd_rq_pulse -test.pdp6.apr0.mc_rdwr_rq_pulse -test.pdp6.apr0.mc_rdwr_rs_pulse -test.pdp6.apr0.mc_wr_rq_pulse -test.pdp6.apr0.mc_rq_pulse -test.pdp6.apr0.mc_mb_clr -test.pdp6.apr0.mc_rq_set -test.pdp6.apr0.mc_addr_ack -test.pdp6.apr0.mai_rd_rs -test.pdp6.apr0.mc_wr_rs -test.pdp6.apr0.mc_rs_t0 -test.pdp6.apr0.mc_rs_t1 -test.pdp6.apr0.mc_illeg_address -test.pdp6.apr0.mc_membus_fm_mb1 -@200 -- -@28 -test.pdp6.apr0.ex_clr -test.pdp6.apr0.ex_set -test.pdp6.apr0.rlr[18:25] -@30 -test.pdp6.apr0.rla[18:25] -@28 -test.pdp6.apr0.pr[18:25] -test.pdp6.apr0.pr18_ok -@200 -- -@28 -test.pdp6.apr0.mc_rd -test.pdp6.apr0.mc_wr -test.pdp6.apr0.mc_rq -test.pdp6.apr0.mc_stop -test.pdp6.apr0.mc_stop_sync -test.pdp6.apr0.mc_split_cyc_sync -test.pdp6.apr0.mc_mb_membus_enable -@1401200 --MC -@c00200 --I A -@28 -test.pdp6.apr0.it0 -test.pdp6.apr0.if1a -test.pdp6.apr0.it1 -test.pdp6.apr0.it1a -test.pdp6.apr0.at0 -test.pdp6.apr0.af0 -test.pdp6.apr0.at1 -test.pdp6.apr0.at2 -test.pdp6.apr0.at3 -test.pdp6.apr0.af3 -test.pdp6.apr0.at3a -test.pdp6.apr0.af3a -test.pdp6.apr0.at4 -test.pdp6.apr0.at5 -@1401200 --I A -@c00200 --F -@28 -test.pdp6.apr0.f_ac_inh -test.pdp6.apr0.f_c_e -test.pdp6.apr0.f_c_e_pse -test.pdp6.apr0.f_c_c_aclt -test.pdp6.apr0.f_c_c_acrt -test.pdp6.apr0.f_ac_2 -test.pdp6.apr0.f_ac_2_etc -@200 -- -@28 -test.pdp6.apr0.ft0 -test.pdp6.apr0.ft1 -test.pdp6.apr0.f1a -test.pdp6.apr0.ft1a -test.pdp6.apr0.ft3 -test.pdp6.apr0.ft4 -test.pdp6.apr0.f4a -test.pdp6.apr0.ft4a -test.pdp6.apr0.ft5 -test.pdp6.apr0.ft6 -test.pdp6.apr0.f6a -test.pdp6.apr0.ft6a -test.pdp6.apr0.ft7 -@1401200 --F -@c00200 --E -@28 -test.pdp6.apr0.et0a -test.pdp6.apr0.et0 -test.pdp6.apr0.et1 -test.pdp6.apr0.et3 -test.pdp6.apr0.et4_inh -test.pdp6.apr0.et4 -test.pdp6.apr0.et5_inh -test.pdp6.apr0.et5 -test.pdp6.apr0.et6 -test.pdp6.apr0.et7 -test.pdp6.apr0.et8 -test.pdp6.apr0.et9 -test.pdp6.apr0.et10 -@1401200 --E -@c00200 --S -@28 -test.pdp6.apr0.s_ac_0 -test.pdp6.apr0.s_ac_2 -test.pdp6.apr0.s_ac_inh -test.pdp6.apr0.s_ac_inh_if_ac_0 -test.pdp6.apr0.st1 -test.pdp6.apr0.st2 -test.pdp6.apr0.sf3 -test.pdp6.apr0.st3 -test.pdp6.apr0.st3a -test.pdp6.apr0.st5 -test.pdp6.apr0.st5a -test.pdp6.apr0.st6 -test.pdp6.apr0.sf7 -test.pdp6.apr0.st7 -@1401200 --S -@c00200 --iobus -@28 -test.pdp6.apr0.iobus_iob_poweron -test.pdp6.apr0.iobus_iob_reset -@30 -test.pdp6.apr0.iobus_pi_req[1:7] -test.pdp6.apr0.iobus_ios[3:9] -@28 -test.pdp6.apr0.iobus_cono_clear -test.pdp6.apr0.iobus_cono_set -test.pdp6.apr0.iobus_datao_clear -test.pdp6.apr0.iobus_datao_set -test.pdp6.apr0.iobus_iob_fm_datai -test.pdp6.apr0.iobus_iob_fm_status -@30 -test.pdp6.apr0.iobus_iob_out[0:35] -test.pdp6.apr0.iobus_iob_in[0:35] -@1401200 --iobus -@c00200 --membus -@28 -test.pdp6.apr0.membus_rq_cyc -test.pdp6.apr0.membus_rd_rq -test.pdp6.apr0.membus_wr_rq -test.pdp6.apr0.membus_wr_rs -@30 -test.pdp6.apr0.membus_sel[18:21] -test.pdp6.apr0.membus_ma[21:35] -test.pdp6.apr0.membus_fmc_select -test.pdp6.apr0.membus_mb_out[0:35] -test.pdp6.apr0.membus_rd_rs -test.pdp6.apr0.membus_addr_ack -test.pdp6.apr0.membus_mb_in[0:35] -test.pdp6.apr0.mc_non_exist_mem -test.pdp6.apr0.mc_non_exist_mem_rst -test.pdp6.apr0.mc_non_exist_rd -@1401200 --membus -@c00200 --mem0 -@28 -test.pdp6.mem0.sw_single_step -test.pdp6.mem0.sw_restart -test.pdp6.mem0.cmc_key_restart -@200 -- -@28 -test.pdp6.mem0.cmc_await_rq -test.pdp6.mem0.cmc_rd -test.pdp6.mem0.cmc_inhibit -test.pdp6.mem0.cmc_wr -test.pdp6.mem0.cyc_rq_p0 -test.pdp6.mem0.cyc_rq_p1 -test.pdp6.mem0.cyc_rq_p2 -test.pdp6.mem0.cyc_rq_p3 -test.pdp6.mem0.cmc_p0_act -test.pdp6.mem0.cmc_p1_act -test.pdp6.mem0.cmc_p2_act -test.pdp6.mem0.cmc_p3_act -@30 -test.pdp6.mem0.cmb[0:35] -@28 -test.pdp6.apr0.membus_mb_pulse -@200 -- -@30 -test.pdp6.mem0.ma[21:35] -test.pdp6.mem0.cma[22:35] -@28 -test.pdp6.mem0.cma_rd_rq -test.pdp6.mem0.cma_wr_rq -test.pdp6.mem0.cmc_pse_sync -test.pdp6.mem0.cmc_proc_rs -test.pdp6.mem0.cmc_proc_rs_P -@200 -- -@28 -test.pdp6.mem0.cmc_pwr_clr -test.pdp6.mem0.cmc_pwr_start -test.pdp6.mem0.cmc_state_clr -test.pdp6.mem0.cmc_cmb_clr -test.pdp6.mem0.cmc_strb_sa -test.pdp6.mem0.cmc_rd_rs -test.pdp6.mem0.cmc_t0 -test.pdp6.mem0.cmc_t1 -test.pdp6.mem0.cmc_t2 -test.pdp6.mem0.cmc_t4 -test.pdp6.mem0.cmc_t5 -test.pdp6.mem0.cmc_t6 -test.pdp6.mem0.cmc_t7 -test.pdp6.mem0.cmc_t8 -test.pdp6.mem0.cmc_t9 -test.pdp6.mem0.cmc_t9a -test.pdp6.mem0.cmc_t10 -test.pdp6.mem0.cmc_t11 -test.pdp6.mem0.cmc_t12 -@30 -test.pdp6.mem0.sa[0:35] -@1401200 --mem0 -@c00200 --fmem0 -@28 -test.pdp6.fmem0.fma_rd_rq -test.pdp6.fmem0.fma_wr_rq -@200 -- -@28 -test.pdp6.fmem0.fmct0 -test.pdp6.fmem0.fmct1 -test.pdp6.fmem0.fmct3 -test.pdp6.fmem0.fmct4 -test.pdp6.fmem0.fmct5 -@1401200 --fmem0 -@28 -test.pdp6.apr0.at1_inh -test.pdp6.apr0.ia_NOT_int -@c00200 --PI -@30 -test.pdp6.apr0.maN_set[30:35] -@28 -test.pdp6.apr0.pi_rq -test.pdp6.apr0.pi_cyc -test.pdp6.apr0.pi_sync -test.pdp6.apr0.pir_stb -test.pdp6.apr0.pi_req[1:7] -test.pdp6.apr0.pih[1:7] -test.pdp6.apr0.pir[1:7] -test.pdp6.apr0.pio[1:7] -test.pdp6.apr0.pi_select -@30 -test.pdp6.apr0.pi_iob[0:35] -@28 -test.pdp6.apr0.iob_pi_req[1:7] -@1401200 --PI -@c00200 --IOT -@28 -test.pdp6.apr0.iot_go -test.pdp6.apr0.iot_go_P -@200 -- -@28 -test.pdp6.apr0.iot_t0 -test.pdp6.apr0.iot_f0a -test.pdp6.apr0.iot_t0a -test.pdp6.apr0.iot_init_setup -test.pdp6.apr0.iot_t2 -test.pdp6.apr0.iot_final_setup -test.pdp6.apr0.iot_drive -test.pdp6.apr0.iot_t3a -test.pdp6.apr0.iot_reset -test.pdp6.apr0.iot_t4 -test.pdp6.apr0.iot_t3 -test.pdp6.apr0.iot_restart -@200 -- -@28 -test.pdp6.apr0.iot_blki -test.pdp6.apr0.iot_datai -test.pdp6.apr0.iot_blko -test.pdp6.apr0.iot_datao -test.pdp6.apr0.iot_coni -test.pdp6.apr0.iot_cono -test.pdp6.apr0.iot_consz -test.pdp6.apr0.iot_conso -@1401200 --IOT -@c00200 --misc -@28 -test.pdp6.apr0.ar_com_cont -test.pdp6.apr0.ar_add -test.pdp6.apr0.ar_as_t0 -test.pdp6.apr0.ar_as_t1 -test.pdp6.apr0.ar_as_t2 -test.pdp6.apr0.ar_cry_comp -test.pdp6.apr0.ar_t3 -test.pdp6.apr0.cfac_ar_add -@200 -- -@28 -test.pdp6.apr0.pc_inc -test.pdp6.apr0.ar_pc_chg_flag -test.pdp6.apr0.pc_inc_enable -test.pdp6.apr0.pc_inc_et9 -test.pdp6.apr0.pc_inc_inh_et0 -test.pdp6.apr0.pc_set_OR_pc_inc -test.pdp6.apr0.pc_set_enable -@1401200 --misc -@c00201 --cpa -@28 -test.pdp6.apr0.cpa -test.pdp6.apr0.cpa_cono_set -test.pdp6.apr0.cpa_status -@200 -- -@28 -test.pdp6.apr0.cpa_iot_user -test.pdp6.apr0.cpa_illeg_op -test.pdp6.apr0.cpa_non_exist_mem -test.pdp6.apr0.cpa_clock_enable -test.pdp6.apr0.cpa_clock_flag -test.pdp6.apr0.cpa_clock_flag_set -test.pdp6.apr0.cpa_pc_chg_enable -test.pdp6.apr0.cpa_pdl_ov -test.pdp6.apr0.cpa_arov_enable -test.pdp6.apr0.cpa_pia[33:35] -@30 -test.pdp6.apr0.cpa_iob[0:35] -@200 -- -@28 -test.pdp6.apr0.iob_pi_req[1:7] -test.pdp6.apr0.iobus_pi_req[1:7] -test.pdp6.apr0.cpa_req[1:7] -@1401201 --cpa -@c00200 --shift -@28 -test.pdp6.apr0.sht0 -test.pdp6.apr0.sht1 -test.pdp6.apr0.shf1 -test.pdp6.apr0.sht1a -@200 -- -@28 -test.pdp6.apr0.sct0 -test.pdp6.apr0.sct1 -test.pdp6.apr0.sct2 -@200 -- -@28 -test.pdp6.apr0.sat0 -test.pdp6.apr0.sat1 -test.pdp6.apr0.sat2 -test.pdp6.apr0.sat21 -test.pdp6.apr0.sat3 -@1401200 --shift -@c00200 --BLT -@28 -test.pdp6.apr0.blt_last -test.pdp6.apr0.blt_done -test.pdp6.apr0.blt_t0 -test.pdp6.apr0.blt_f0a -test.pdp6.apr0.blt_t0a -test.pdp6.apr0.blt_t1 -test.pdp6.apr0.blt_t2 -test.pdp6.apr0.blt_t3 -test.pdp6.apr0.blt_f3a -test.pdp6.apr0.blt_t3a -test.pdp6.apr0.blt_t4 -test.pdp6.apr0.blt_t5 -test.pdp6.apr0.blt_f5a -test.pdp6.apr0.blt_t5a -test.pdp6.apr0.blt_t6 -@1401200 --BLT -@c00200 --CH -@28 -test.pdp6.apr0.ch_inc_op -test.pdp6.apr0.ch_NOT_inc_op -test.pdp6.apr0.ch_load -test.pdp6.apr0.ch_dep -test.pdp6.apr0.cht1 -test.pdp6.apr0.chf1 -test.pdp6.apr0.cht2 -test.pdp6.apr0.chf2 -test.pdp6.apr0.cht3 -test.pdp6.apr0.cht3a -test.pdp6.apr0.cht4 -test.pdp6.apr0.chf3 -test.pdp6.apr0.cht4a -test.pdp6.apr0.cht5 -test.pdp6.apr0.cht6 -test.pdp6.apr0.cht7 -test.pdp6.apr0.cht8 -test.pdp6.apr0.chf6 -test.pdp6.apr0.cht8a -test.pdp6.apr0.cht8b -test.pdp6.apr0.cht9 -test.pdp6.apr0.chf7 -test.pdp6.apr0.chf4 -test.pdp6.apr0.chf5 -@1401200 --CH -@c00200 --LC -@28 -test.pdp6.apr0.lct0 -test.pdp6.apr0.lcf1 -test.pdp6.apr0.lct0a -@1401200 --LC -@c00200 --DC -@28 -test.pdp6.apr0.dct0 -test.pdp6.apr0.dcf1 -test.pdp6.apr0.dct0a -test.pdp6.apr0.dct0b -test.pdp6.apr0.dct1 -test.pdp6.apr0.dct2 -test.pdp6.apr0.dct3 -@1401200 --DC -@c00200 --MP -@28 -test.pdp6.apr0.mpf2 -test.pdp6.apr0.mpt0 -test.pdp6.apr0.mpf1 -test.pdp6.apr0.mpt0a -test.pdp6.apr0.mpt1 -test.pdp6.apr0.mpt2 -@1401200 --MP -@c00200 --MS -@28 -test.pdp6.apr0.mst1 -test.pdp6.apr0.mst2 -test.pdp6.apr0.mst3 -test.pdp6.apr0.mst4 -test.pdp6.apr0.msf1 -test.pdp6.apr0.mst3a -test.pdp6.apr0.mst5 -test.pdp6.apr0.mst6 -@1401200 --MS -@c00200 --DS -@28 -test.pdp6.apr0.ds_div_t0 -test.pdp6.apr0.dst0 -test.pdp6.apr0.dsf1 -test.pdp6.apr0.dst0a -test.pdp6.apr0.dst1 -test.pdp6.apr0.dst2 -test.pdp6.apr0.dst3 -test.pdp6.apr0.dst4 -test.pdp6.apr0.dst5 -test.pdp6.apr0.dsf2 -test.pdp6.apr0.dst5a -test.pdp6.apr0.dst6 -test.pdp6.apr0.dst7 -test.pdp6.apr0.dst8 -test.pdp6.apr0.dst9 -test.pdp6.apr0.dsf3 -test.pdp6.apr0.dst10 -test.pdp6.apr0.dst10a -test.pdp6.apr0.dst10b -test.pdp6.apr0.dst11 -test.pdp6.apr0.dst12 -test.pdp6.apr0.dsf4 -test.pdp6.apr0.dst11a -test.pdp6.apr0.dst13 -test.pdp6.apr0.dst14a -test.pdp6.apr0.dst14b -test.pdp6.apr0.dst14 -test.pdp6.apr0.dst15 -test.pdp6.apr0.dst16 -test.pdp6.apr0.dst17 -test.pdp6.apr0.dst17a -test.pdp6.apr0.dst18 -test.pdp6.apr0.dst19 -test.pdp6.apr0.dst19a -test.pdp6.apr0.dst19b -test.pdp6.apr0.dst20 -test.pdp6.apr0.dst21 -test.pdp6.apr0.dst21a -@200 -- -@28 -test.pdp6.apr0.dsf5 -test.pdp6.apr0.dsf6 -test.pdp6.apr0.dsf7 -test.pdp6.apr0.dsf7_xor_mq0 -test.pdp6.apr0.dsf8 -test.pdp6.apr0.dsf9 -@1401200 --DS -@c00200 --FM -@28 -test.pdp6.apr0.fmt0 -test.pdp6.apr0.fmf1 -test.pdp6.apr0.fmt0a -test.pdp6.apr0.fmf2 -test.pdp6.apr0.fmt0b -@1401200 --FM -@c00200 --FD -@28 -test.pdp6.apr0.fdt0 -test.pdp6.apr0.fdf1 -test.pdp6.apr0.fdt0a -test.pdp6.apr0.fdf2 -test.pdp6.apr0.fdt0b -test.pdp6.apr0.fdt1 -@1401200 --FD -@c00200 --FP -@28 -test.pdp6.apr0.fpt0 -test.pdp6.apr0.fpt01 -test.pdp6.apr0.fpt1 -test.pdp6.apr0.fpf1 -test.pdp6.apr0.fpt1a -test.pdp6.apr0.fpt1aa -test.pdp6.apr0.fpf2 -test.pdp6.apr0.fpt1b -test.pdp6.apr0.fpt2 -test.pdp6.apr0.fpt3 -test.pdp6.apr0.fpt4 -@200 -- -@28 -test.pdp6.apr0.fp_ar0_xor_fmf1 -test.pdp6.apr0.fp_ar0_xor_mb0_xor_fmf1 -test.pdp6.apr0.fp_mb0_eq_fmf1 -@1401200 --FP -@c00200 --NR -@28 -test.pdp6.apr0.ar_eq_fp_half -test.pdp6.apr0.nr_ar9_eq_ar0 -test.pdp6.apr0.nr_round -test.pdp6.apr0.nrt05 -test.pdp6.apr0.nrt0 -test.pdp6.apr0.nrt01 -test.pdp6.apr0.nrt1 -test.pdp6.apr0.nrt2 -test.pdp6.apr0.nrt3 -test.pdp6.apr0.nrt31 -test.pdp6.apr0.nrt4 -test.pdp6.apr0.nrt5 -test.pdp6.apr0.nrt5a -test.pdp6.apr0.nrt6 -@1401200 --NR -@c00200 --FA -@28 -test.pdp6.apr0.fat0 -test.pdp6.apr0.fat1 -test.pdp6.apr0.faf1 -test.pdp6.apr0.fat1b -test.pdp6.apr0.faf2 -test.pdp6.apr0.fat1a -test.pdp6.apr0.fat2 -test.pdp6.apr0.fat3 -test.pdp6.apr0.fat4 -test.pdp6.apr0.fat5 -test.pdp6.apr0.faf3 -test.pdp6.apr0.fat5a -test.pdp6.apr0.fat6 -test.pdp6.apr0.fat7 -test.pdp6.apr0.fat8 -test.pdp6.apr0.fat8a -test.pdp6.apr0.fat9 -test.pdp6.apr0.faf4 -test.pdp6.apr0.fat10 -@1401200 --FA -[pattern_trace] 1 -[pattern_trace] 0 diff --git a/verilog/test.v b/verilog/test.v deleted file mode 100644 index 6e049b0..0000000 --- a/verilog/test.v +++ /dev/null @@ -1,171 +0,0 @@ -`timescale 1ns/1ns -`define simulation - -module clock(output reg clk); - initial - clk = 0; - always - #5 clk = ~clk; -endmodule - -//`define TESTKEY pdp6.key_inst_stop -//`define TESTKEY pdp6.key_read_in -`define TESTKEY pdp6.key_start -//`define TESTKEY pdp6.key_exec -//`define TESTKEY pdp6.key_ex -//`define TESTKEY pdp6.key_dep -//`define TESTKEY pdp6.key_mem_cont - -module test; - wire clk; - reg reset; - reg stop; - - clock clock0(clk); - pdp6 pdp6(.clk(clk), .reset(reset)); - - initial begin - stop = 0; -// #110000 stop = 1; - #20000 stop = 1; - end - always @(pdp6.apr0.st7) - if(pdp6.apr0.st7) - stop = 1; - - // dump memory on exit - always @(stop) - if(stop) begin: fin - integer i; - #4000; - for(i = 0; i < 'o20; i = i + 1) - $display("%o %o %o", i, pdp6.mem0.core[i], pdp6.fmem0.ff[i]); - for(i = 'o1000; i < 'o1010; i = i + 1) - $display("%o %o", i, pdp6.mem0.core[i]); - $finish; - end - - initial begin - #100 `TESTKEY = 1; - #1000 `TESTKEY = 0; - -// #3000 pdp6.key_dep = 1; -// #1000 pdp6.key_dep = 0; - -// #3000 pdp6.key_inst_stop = 1; -// #1000 pdp6.key_inst_stop = 0; - end - - initial begin - #400; -// pdp6.apr0.cpa_pia = 5; - pdp6.apr0.pio = 7'b1111100; - pdp6.apr0.pir = 7'b0000000; - pdp6.apr0.pih = 7'b0000100; - #10; - pdp6.apr0.pi_active = 1; - end -// assign pdp6.apr0.iobus_pi_req = 7'b0010000; - assign pdp6.apr0.iobus_pi_req = 0; - -/* - initial begin - #300; - pdp6.apr0.cpa_iot_user <= 1; - #20; - pdp6.apr0.cpa_illeg_op <= 1; - #20; - pdp6.apr0.cpa_non_exist_mem <= 1; - #20; - pdp6.apr0.cpa_clock_enable <= 1; - #20; - pdp6.apr0.cpa_clock_flag <= 1; - #20; - pdp6.apr0.cpa_pc_chg_enable <= 1; - #20; - pdp6.apr0.cpa_pdl_ov <= 1; - #20; - pdp6.apr0.cpa_arov_enable <= 1; - #20; - pdp6.apr0.cpa_pia <= 7; - end -*/ - -/* initial begin - #100; - pdp6.mem0_sw_single_step = 1; - #6000; - pdp6.mem0_sw_restart = 1; - end*/ - - initial begin - $dumpfile("dump.vcd"); - $dumpvars(); - - reset = 0; - - pdp6.key_start = 0; - pdp6.key_read_in = 0; - pdp6.key_mem_cont = 0; - pdp6.key_inst_cont = 0; - pdp6.key_mem_stop = 0; - pdp6.key_inst_stop = 0; - pdp6.key_exec = 0; - pdp6.key_io_reset = 0; - pdp6.key_dep = 0; - pdp6.key_dep_nxt = 0; - pdp6.key_ex = 0; - pdp6.key_ex_nxt = 0; - - pdp6.sw_power = 0; - pdp6.sw_addr_stop = 0; - pdp6.sw_mem_disable = 0; - pdp6.sw_repeat = 0; - pdp6.sw_power = 0; - pdp6.datasw = 0; - pdp6.mas = 0; - - pdp6.sw_rim_maint = 0; - pdp6.sw_repeat_bypass = 0; - pdp6.sw_art3_maint = 0; - pdp6.sw_sct_maint = 0; - pdp6.sw_split_cyc = 0; - - pdp6.mem0_sw_single_step = 0; - pdp6.mem0_sw_restart = 0; - end - -/* - initial begin - #80 pdp6.apr0.pr = 8'o003; - pdp6.apr0.rlr = 8'o002; - //pdp6.apr0.ex_user = 1; - end -*/ - - initial begin: meminit - integer i; - #1 reset = 1; - #20 reset = 0; - - pdp6.datasw = 36'o111777222666; - pdp6.mas = 18'o000000; - - for(i = 0; i < 'o40000; i = i + 1) - pdp6.mem0.core[i] = 0; - for(i = 0; i < 'o20; i = i + 1) - pdp6.fmem0.ff[i] = 0; - - //`include "test1.inc" - //`include "test2.inc" - `include "test_fp.inc" - end - - wire [0:35] mem0scope = pdp6.mem0.core['o1000]; - wire [0:35] fmem0scope = pdp6.fmem0.ff[2]; - - initial begin - #25 pdp6.sw_power = 1; - end - -endmodule diff --git a/verilog/test1.inc b/verilog/test1.inc deleted file mode 100644 index 260efbb..0000000 --- a/verilog/test1.inc +++ /dev/null @@ -1,50 +0,0 @@ - pdp6.fmem0.ff['o0] = 36'o000000_010001; - pdp6.fmem0.ff['o1] = 36'o000000_010222; - pdp6.fmem0.ff['o2] = 36'o700000_200006; - pdp6.fmem0.ff['o3] = 36'o500000_000004; - pdp6.fmem0.ff['o4] = 36'o000000_010304; - pdp6.fmem0.ff['o5] = 36'o377777_777777; - pdp6.fmem0.ff['o6] = 36'o444000_222000; - pdp6.fmem0.ff['o7] = 36'o777776_000010; // BLK ptr - pdp6.fmem0.ff['o10] = 36'o000002_001000; // BLT ptr - pdp6.fmem0.ff['o11] = 36'o440600_001000; // char ptr - pdp6.fmem0.ff['o12] = 36'o300600_001000; // char ptr - pdp6.fmem0.ff['o13] = 36'o000000_005555; // char - pdp6.fmem0.ff['o14] = 36'o010700_001017; - pdp6.fmem0.ff['o17] = 36'o777000_001000; // PDL ptr -// pdp6.fmem0.ff['o17] = 36'o777000_777777; // PDL ptr - - pdp6.mem0.core['o20] = 36'o200_064_000104; // MOVE 1,@104(4) FAC_INH - pdp6.mem0.core['o21] = 36'o202_064_000104; // MOVEM 1,@104(4) - pdp6.mem0.core['o22] = 36'o245_100_000003; // ROTC 2,3 - pdp6.mem0.core['o23] = 36'o700200_675550; // CONO APR,675550 - pdp6.mem0.core['o24] = 36'o700200_102227; // CONO APR,102227 - pdp6.mem0.core['o25] = 36'o700240_000005; // CONI APR,5 - pdp6.mem0.core['o26] = 36'o700140_000006; // DATAO APR,6 - pdp6.mem0.core['o27] = 36'o700040_000005; // DATAI APR,5 - pdp6.mem0.core['o30] = 36'o700000_000007; // BLKI APR,7 - - pdp6.mem0.core['o40] = 36'o700640_000005; // CONI APR,5 - pdp6.mem0.core['o41] = 36'o260740_000020; // PUSHJ 17,20 - pdp6.mem0.core['o41] = 36'o250040_000000; // AOS 1, - pdp6.mem0.core['o42] = 36'o270000_000001; // ADD 0,1 - pdp6.mem0.core['o43] = 36'o274000_000001; // SUB 0,1 - - pdp6.mem0.core['o54] = 36'o245_100_000003; // ROTC 2,3 - pdp6.mem0.core['o55] = 36'o245_100_777775; // ROTC 2,-3 - pdp6.mem0.core['o56] = 36'o244_100_000001; // ASHC 2,1 - - pdp6.mem0.core['o60] = 36'o251_400_001001; // BLT 10,1007 - pdp6.mem0.core['o64] = 36'o133_000_000011; // IBP 11 - pdp6.mem0.core['o65] = 36'o135_000_000012; // LBP 0,12 - pdp6.mem0.core['o66] = 36'o134_000_000012; // ILBP 0,12 - pdp6.mem0.core['o67] = 36'o137_540_000012; // DBP 13,12 - pdp6.mem0.core['o70] = 36'o134_000_000014; // ILBP 0,14 - - pdp6.mem0.core['o100] = 36'o221_000_000123; // IMULI 0,123 - - pdp6.mem0.core['o110] = 36'o231_200_000123; // IDIVI 4,123 - pdp6.mem0.core['o111] = 36'o231_340_000123; // IDIVI 7,123 - - pdp6.mem0.core['o1000] = 36'o50_45_54_54_57_00; - pdp6.mem0.core['o10410] = 36'o000_000_000333; diff --git a/verilog/test2.inc b/verilog/test2.inc deleted file mode 100644 index e755816..0000000 --- a/verilog/test2.inc +++ /dev/null @@ -1,21 +0,0 @@ -pdp6.fmem0.ff['o0] = 36'o000000_010001; -pdp6.fmem0.ff['o1] = 36'o777777_767777; - -pdp6.fmem0.ff['o2] = 36'o000000_010001; -pdp6.fmem0.ff['o3] = 36'o001200_034000; - -pdp6.fmem0.ff['o4] = 36'o777777_767776; -pdp6.fmem0.ff['o5] = 36'o776577_744000; - -pdp6.fmem0.ff['o6] = 36'o777777_767776; -pdp6.fmem0.ff['o7] = 36'o000000_000000; - -pdp6.mem0.core['o100] = 36'o221_000_000123; // IMULI 0,123 - -pdp6.mem0.core['o110] = 36'o231_000_000123; // IDIVI 0,123 -pdp6.mem0.core['o111] = 36'o231_040_000123; // IDIVI 1,123 -pdp6.mem0.core['o112] = 36'o235_100_000123; // DIVI 2,123 -pdp6.mem0.core['o113] = 36'o235_200_000123; // DIVI 4,123 -pdp6.mem0.core['o114] = 36'o235_300_000123; // DIVI 6,123 - -pdp6.mas = 18'o000110; diff --git a/verilog/test_dec.v b/verilog/test_dec.v deleted file mode 100644 index 9d863af..0000000 --- a/verilog/test_dec.v +++ /dev/null @@ -1,25 +0,0 @@ -`timescale 1ns/1ns - -module test; - reg reset; - - pdp6 pdp6(.clk(1'b0), .reset(reset)); - - initial begin - $dumpfile("inst.vcd"); - $dumpvars(); -// $monitor("ir=%o ir_uuo_a=%b ir_fpch=%b ir_2xx=%b ir_accp_V_memac=%b ir_boole=%b ir_hwt=%b ir_acbm=%b ir_iot_a=%b", pdp6.apr0.ir, pdp6.apr0.ir_uuo_a, pdp6.apr0.ir_fpch, pdp6.apr0.ir_2xx, pdp6.apr0.ir_accp_OR_memac, pdp6.apr0.ir_boole, pdp6.apr0.ir_hwt, pdp6.apr0.ir_acbm, pdp6.apr0.ir_iot_a); -// $monitor("ir_%o ir_130=%o ir_131=%b ir_fsc=%b ir_cao=%b ir_ldci=%b ir_ldc=%b ir_dpci=%b ir_dpc=%b", pdp6.apr0.ir_130, pdp6.apr0.ir, pdp6.apr0.ir_131, pdp6.apr0.ir_fsc, pdp6.apr0.ir_cao, pdp6.apr0.ir_ldci, pdp6.apr0.ir_ldc, pdp6.apr0.ir_dpci, pdp6.apr0.ir_dpc); - end - - initial begin: inst - integer i; - pdp6.apr0.ar = 0; - pdp6.apr0.ir = 0; - for(i = 0; i < 'o700; i = i + 1) - #10 pdp6.apr0.ir[0:8] = i; - for(i = 'o700000; i <= 'o700340; i = i + 'o000040) - #10 pdp6.apr0.ir = i; - #10; - end -endmodule diff --git a/verilog/test_fp.inc b/verilog/test_fp.inc deleted file mode 100644 index 3485d1e..0000000 --- a/verilog/test_fp.inc +++ /dev/null @@ -1,16 +0,0 @@ -pdp6.fmem0.ff['o0] = 36'o201_400000000; // 1.0 -pdp6.fmem0.ff['o1] = 36'o202_400000000; // 2.0 -pdp6.fmem0.ff['o2] = 36'o200_754213603; -pdp6.fmem0.ff['o3] = 36'o202_561251001; - -pdp6.mem0.core['o100] = 36'o132_000_000004; // FSC 0,4 -pdp6.mem0.core['o101] = 36'o132_000_777776; // FSC 0,-2 - -pdp6.mem0.core['o110] = 36'o160_100_000003; // FMP 2,3 - -pdp6.mem0.core['o120] = 36'o170_100_000003; // FDV 2,3 - -pdp6.mem0.core['o130] = 36'o140_100_000003; // FAD 2,3 -pdp6.mem0.core['o131] = 36'o150_100_000003; // FSB 2,3 - -pdp6.mas = 18'o000131; diff --git a/verilog/testcore161.c b/verilog/testcore161.c new file mode 100644 index 0000000..7da7316 --- /dev/null +++ b/verilog/testcore161.c @@ -0,0 +1,334 @@ +module core161c( + input wire clk, + input wire reset, + input wire power, + input wire sw_single_step, + input wire sw_restart, + + input wire membus_wr_rs_p0, + input wire membus_rq_cyc_p0, + input wire membus_rd_rq_p0, + input wire membus_wr_rq_p0, + input wire [21:35] membus_ma_p0, + input wire [18:21] membus_sel_p0, + input wire membus_fmc_select_p0, + input wire [0:35] membus_mb_in_p0, + output wire membus_addr_ack_p0, + output wire membus_rd_rs_p0, + output wire [0:35] membus_mb_out_p0, + + input wire membus_wr_rs_p1, + input wire membus_rq_cyc_p1, + input wire membus_rd_rq_p1, + input wire membus_wr_rq_p1, + input wire [21:35] membus_ma_p1, + input wire [18:21] membus_sel_p1, + input wire membus_fmc_select_p1, + input wire [0:35] membus_mb_in_p1, + output wire membus_addr_ack_p1, + output wire membus_rd_rs_p1, + output wire [0:35] membus_mb_out_p1, + + input wire membus_wr_rs_p2, + input wire membus_rq_cyc_p2, + input wire membus_rd_rq_p2, + input wire membus_wr_rq_p2, + input wire [21:35] membus_ma_p2, + input wire [18:21] membus_sel_p2, + input wire membus_fmc_select_p2, + input wire [0:35] membus_mb_in_p2, + output wire membus_addr_ack_p2, + output wire membus_rd_rs_p2, + output wire [0:35] membus_mb_out_p2, + + input wire membus_wr_rs_p3, + input wire membus_rq_cyc_p3, + input wire membus_rd_rq_p3, + input wire membus_wr_rq_p3, + input wire [21:35] membus_ma_p3, + input wire [18:21] membus_sel_p3, + input wire membus_fmc_select_p3, + input wire [0:35] membus_mb_in_p3, + output wire membus_addr_ack_p3, + output wire membus_rd_rs_p3, + output wire [0:35] membus_mb_out_p3 +); + + /* Jumpers */ + parameter memsel_p0 = 4'b0; + parameter memsel_p1 = 4'b0; + parameter memsel_p2 = 4'b0; + parameter memsel_p3 = 4'b0; + + + reg [22:35] cma; + reg cma_rd_rq; + reg cma_wr_rq; + + reg [0:35] cmb; + + reg cmc_p0_act, cmc_p1_act, cmc_p2_act, cmc_p3_act; + reg cmc_last_proc; + reg cmc_rd; + reg cmc_inhibit; // not really used + reg cmc_wr; + reg cmc_await_rq = 0; + reg cmc_proc_rs = 0; + reg cmc_pse_sync; + reg cmc_stop; + + wire cyc_rq_p0 = memsel_p0 == membus_sel_p0 & + ~membus_fmc_select_p0 & membus_rq_cyc_p0; + wire cyc_rq_p1 = memsel_p1 == membus_sel_p1 & + ~membus_fmc_select_p1 & membus_rq_cyc_p1; + wire cyc_rq_p2 = memsel_p2 == membus_sel_p2 & + ~membus_fmc_select_p2 & membus_rq_cyc_p2; + wire cyc_rq_p3 = memsel_p3 == membus_sel_p3 & + ~membus_fmc_select_p3 & membus_rq_cyc_p3; + wire cmpc_p0_rq = cyc_rq_p0 & cmc_await_rq; + wire cmpc_p1_rq = cyc_rq_p1 & cmc_await_rq; + wire cmpc_p2_rq = cyc_rq_p2 & cmc_await_rq; + wire cmpc_p3_rq = cyc_rq_p3 & cmc_await_rq; + + wire wr_rs = cmc_p0_act ? membus_wr_rs_p0 : + cmc_p1_act ? membus_wr_rs_p1 : + cmc_p2_act ? membus_wr_rs_p2 : + cmc_p3_act ? membus_wr_rs_p3 : 1'b0; + wire rd_rq = cmc_p0_act ? membus_rd_rq_p0 : + cmc_p1_act ? membus_rd_rq_p1 : + cmc_p2_act ? membus_rd_rq_p2 : + cmc_p3_act ? membus_rd_rq_p3 : 1'b0; + wire wr_rq = cmc_p0_act ? membus_wr_rq_p0 : + cmc_p1_act ? membus_wr_rq_p1 : + cmc_p2_act ? membus_wr_rq_p2 : + cmc_p3_act ? membus_wr_rq_p3 : 1'b0; + wire [21:35] ma = cmc_p0_act ? membus_ma_p0 : + cmc_p1_act ? membus_ma_p1 : + cmc_p2_act ? membus_ma_p2 : + cmc_p3_act ? membus_ma_p3 : 15'b0; + wire [0:35] mb_in = cmc_p0_act ? membus_mb_in_p0 : + cmc_p1_act ? membus_mb_in_p1 : + cmc_p2_act ? membus_mb_in_p2 : + cmc_p3_act ? membus_mb_in_p3 : 36'b0; + assign membus_addr_ack_p0 = cmc_addr_ack & cmc_p0_act; + assign membus_rd_rs_p0 = cmc_rd_rs & cmc_p0_act; + assign membus_mb_out_p0 = cmc_p0_act ? mb_out : 36'b0; + assign membus_addr_ack_p1 = cmc_addr_ack & cmc_p1_act; + assign membus_rd_rs_p1 = cmc_rd_rs & cmc_p1_act; + assign membus_mb_out_p1 = cmc_p1_act ? mb_out : 36'b0; + assign membus_addr_ack_p2 = cmc_addr_ack & cmc_p2_act; + assign membus_rd_rs_p2 = cmc_rd_rs & cmc_p2_act; + assign membus_mb_out_p2 = cmc_p2_act ? mb_out : 36'b0; + assign membus_addr_ack_p3 = cmc_addr_ack & cmc_p3_act; + assign membus_rd_rs_p3 = cmc_rd_rs & cmc_p3_act; + assign membus_mb_out_p3 = cmc_p3_act ? mb_out : 36'b0; + + wire cmc_addr_ack; + wire cmc_rd_rs; + wire [0:35] mb_out = mb_pulse_out ? sa : 36'b0; + wire cmpc_rs_strb; + + wire cmc_pwr_clr; + wire cmc_pwr_start; + wire cmc_key_restart; + wire cmc_state_clr; + wire cmc_cmb_clr; + wire cmc_strb_sa; + wire cmc_proc_rs_P; + wire mb_pulse_out; + wire mb_pulse_in; + wire cmc_wr_rs; + wire cmc_t0; + wire cmc_t1; + wire cmc_t2; + wire cmc_t4; + wire cmc_t5; + wire cmc_t6; + wire cmc_t7; + wire cmc_t8; + wire cmc_t9; + wire cmc_t9a; + wire cmc_t10; + wire cmc_t11; + wire cmc_t12; + + // power-on timing is totally wrong + + pg cmc_pg0(.clk(clk), .reset(reset), .in(power), .p(cmc_pwr_clr)); + pg cmc_pg1(.clk(clk), .reset(reset), + .in(sw_restart & cmc_stop), .p(cmc_key_restart)); + pg cmc_pg2(.clk(clk), .reset(reset), + .in(cmpc_p0_rq | cmpc_p1_rq | cmpc_p2_rq | cmpc_p3_rq), + .p(cmc_t0)); + pg cmc_pg3(.clk(clk), .reset(reset), .in(| mb_in), .p(mb_pulse_in)); + pg cmc_pg4(.clk(clk), .reset(reset), .in(wr_rs), .p(cmpc_rs_strb)); + pg cmc_pg5(.clk(clk), .reset(reset), .in(cmc_proc_rs), .p(cmc_proc_rs_P)); + pg cmc_pg6(.clk(clk), .reset(reset), .in(cmc_pse_sync & cmc_proc_rs), .p(cmc_wr_rs)); + + + pa cmc_pa0(.clk(clk), .reset(reset), .in(cmc_pwr_clr | cmc_t9a_D), .p(cmc_t12)); + pa cmc_pa1(.clk(clk), .reset(reset), .in(cmc_pwr_clr_D), .p(cmc_pwr_start)); + pa cmc_pa2(.clk(clk), .reset(reset), + .in(cmc_t9a & ~cmc_stop | cmc_pwr_start | cmc_key_restart), + .p(cmc_t10)); + pa cmc_pa3(.clk(clk), .reset(reset), .in(cmc_t10_D), .p(cmc_t11)); + pa cmc_pa4(.clk(clk), .reset(reset), + .in(cmc_t10 | ~cma_wr_rq & cmc_strb_sa_D1 | cmc_proc_rs_P), + .p(cmc_state_clr)); + pa cmc_pa5(.clk(clk), .reset(reset), + .in(cmc_t0 | cmc_strb_sa_D2 & cma_wr_rq), + .p(cmc_cmb_clr)); + pa cmc_pa6(.clk(clk), .reset(reset), .in(cmc_t0_D), .p(cmc_t1)); + pa cmc_pa7(.clk(clk), .reset(reset), .in(cmc_t1_D), .p(cmc_t2)); + pa cmc_pa8(.clk(clk), .reset(reset), .in(cmc_t2_D0), .p(cmc_t4)); + pa cmc_pa9(.clk(clk), .reset(reset), .in(cmc_t4_D), .p(cmc_t5)); + pa cmc_pa10(.clk(clk), .reset(reset), + .in(cmc_t5 & ~cma_wr_rq | cmc_wr_rs), + .p(cmc_t6)); + pa cmc_pa11(.clk(clk), .reset(reset), .in(cmc_t6_D), .p(cmc_t7)); + pa cmc_pa12(.clk(clk), .reset(reset), .in(cmc_t7_D), .p(cmc_t8)); + pa cmc_pa13(.clk(clk), .reset(reset), .in(cmc_t8_D), .p(cmc_t9)); + pa cmc_pa14(.clk(clk), .reset(reset), .in(cmc_t9_D), .p(cmc_t9a)); + pa cmc_pa15(.clk(clk), .reset(reset), + .in(cmc_t2_D1 & cma_rd_rq), + .p(cmc_strb_sa)); + + // not on schematics + bd cmc_bd0(.clk(clk), .reset(reset), .in(cmc_t1), .p(cmc_addr_ack)); + bd cmc_bd1(.clk(clk), .reset(reset), .in(cmc_strb_sa_D0), .p(cmc_rd_rs)); + bd2 cmc_bd2(.clk(clk), .reset(reset), .in(cmc_strb_sa), .p(mb_pulse_out)); + + wire cmc_pwr_clr_D; + wire cmc_t0_D, cmc_t1_D, cmc_t2_D0, cmc_t2_D1, cmc_t4_D; + wire cmc_t6_D, cmc_t7_D, cmc_t8_D, cmc_t9_D, cmc_t9a_D, cmc_t10_D; + wire cmc_strb_sa_D0, cmc_strb_sa_D1, cmc_strb_sa_D2; + dly100ns cmc_dly0(.clk(clk), .reset(reset), .in(cmc_pwr_clr), .p(cmc_pwr_clr_D)); + dly100ns cmc_dly1(.clk(clk), .reset(reset), .in(cmc_t10), .p(cmc_t10_D)); + dly200ns cmc_dly2(.clk(clk), .reset(reset), .in(cmc_t0), .p(cmc_t0_D)); + dly1us cmc_dly3(.clk(clk), .reset(reset), .in(cmc_t1), .p(cmc_t1_D)); + dly1us cmc_dly4(.clk(clk), .reset(reset), .in(cmc_t2), .p(cmc_t2_D0)); + dly200ns cmc_dly5(.clk(clk), .reset(reset), .in(cmc_t4), .p(cmc_t4_D)); + dly200ns cmc_dly6(.clk(clk), .reset(reset), .in(cmc_t6), .p(cmc_t6_D)); + dly200ns cmc_dly7(.clk(clk), .reset(reset), .in(cmc_t7), .p(cmc_t7_D)); + dly1us cmc_dly8(.clk(clk), .reset(reset), .in(cmc_t8), .p(cmc_t8_D)); + dly400ns cmc_dly9(.clk(clk), .reset(reset), .in(cmc_t9), .p(cmc_t9_D)); + dly200ns cmc_dly10(.clk(clk), .reset(reset), .in(cmc_t9a), .p(cmc_t9a_D)); + dly800ns cmc_dly11(.clk(clk), .reset(reset), .in(cmc_t2), .p(cmc_t2_D1)); + dly100ns cmc_dly12(.clk(clk), .reset(reset), + .in(cmc_strb_sa), .p(cmc_strb_sa_D0)); + dly200ns cmc_dly13(.clk(clk), .reset(reset), + .in(cmc_strb_sa), .p(cmc_strb_sa_D1)); + dly250ns cmc_dly14(.clk(clk), .reset(reset), + .in(cmc_strb_sa), .p(cmc_strb_sa_D2)); + +// wire [0:35] sa = core[cma]; // "sense amplifiers" + + reg [0:35] sa; // "sense amplifiers" + reg [0:35] core[0:'o40000-1]; + wire [13:0] core_addr = cma[22:35]; + reg core_rd, core_wr; + + always @(posedge clk or posedge reset) begin + if(reset) begin + cmc_await_rq <= 0; + cmc_last_proc <= 0; + cmc_proc_rs <= 0; + + core_rd <= 0; + core_wr <= 0; + sa <= 0; + end else begin + if(core_rd) begin + sa <= core[core_addr]; + core_rd <= 0; + end else if(core_wr) begin + core[core_addr] <= cmb; + core_wr <= 0; + end + + if(cmc_state_clr) begin + cmc_p0_act <= 0; + cmc_p1_act <= 0; + cmc_p2_act <= 0; + cmc_p3_act <= 0; + end + if(cmc_cmb_clr) + cmb <= 0; + if(cmc_strb_sa) + cmb <= cmb | sa; + if(mb_pulse_in) + cmb <= cmb | mb_in; + if(cmpc_rs_strb) + cmc_proc_rs <= 1; + if(cmc_t0) begin + cmc_await_rq <= 0; + cmc_proc_rs <= 0; + cmc_pse_sync <= 0; + cmc_stop <= 0; + cma <= 0; + cma_rd_rq <= 0; + cma_wr_rq <= 0; + + // this happens between t0 and t1 */ + if(cmpc_p0_rq) + cmc_p0_act <= 1; + else if(cmpc_p1_rq) + cmc_p1_act <= 1; + else if(cmpc_p2_rq) begin + if(~cmpc_p3_rq | cmc_last_proc) + cmc_p2_act <= 1; + end else if(cmpc_p3_rq) begin + if(~cmpc_p2_rq | ~cmc_last_proc) + cmc_p3_act <= 1; + end + end + if(cmc_t1) begin // this seems to be missing from the schematics + cma <= cma | ma[22:35]; + if(rd_rq) + cma_rd_rq <= 1; + if(wr_rq) + cma_wr_rq <= 1; + end + if(cmc_t2) begin + cmc_rd <= 1; + if(cmc_p2_act) + cmc_last_proc <= 0; + if(cmc_p3_act) + cmc_last_proc <= 1; + + core_rd <= 1; + sa <= 0; +/// sa <= core[cma[22:35]]; + end +/// if(cmc_t4) +/// /* As a hack zero core here */ +/// core[cma[22:35]] <= 0; + if(cmc_t5) begin + cmc_rd <= 0; + cmc_pse_sync <= 1; + end + if(cmc_t7) begin + cmc_inhibit <= 1; + if(sw_single_step) + cmc_stop <= 1; + end + if(cmc_t8) begin + cmc_wr <= 1; + end + if(cmc_t9 & cmc_wr) + /* again a hack. core is written some time after t8. + * (cmc_wr is always set here) */ + // core[cma[22:35]] <= core[cma[22:35]] | cmb; +/// core[cma[22:35]] <= cmb; + core_wr <= 1; + if(cmc_t11) + cmc_await_rq <= 1; + if(cmc_t12) begin + cmc_rd <= 0; + cmc_inhibit <= 0; + cmc_wr <= 0; + end + end + end + +endmodule diff --git a/verilog/testfmem.v b/verilog/testfmem.v new file mode 100755 index 0000000..d86d5c1 --- /dev/null +++ b/verilog/testfmem.v @@ -0,0 +1,33 @@ +module testfmem( + // input + i_clk, i_reset_n, + i_address, i_write, i_read, i_writedata, + // output + o_readdata, o_waitrequest +); + input wire i_clk; + input wire i_reset_n; + input wire [17:0] i_address; + input wire i_write; + input wire i_read; + input wire [35:0] i_writedata; + output wire [35:0] o_readdata; + output wire o_waitrequest; + + reg [35:0] mem[0:'o20-1]; + wire [3:0] addr = i_address[3:0]; + wire [35:0] memword = mem[addr]; + + always @(posedge i_clk or negedge i_reset_n) begin + if(~i_reset_n) begin + end else begin + if(i_write) begin + mem[addr] <= i_writedata; + end + end + end + + assign o_readdata = i_read ? memword : 0; + assign o_waitrequest = 0; +endmodule + diff --git a/verilog/testmem16k.v b/verilog/testmem16k.v new file mode 100755 index 0000000..2aa6751 --- /dev/null +++ b/verilog/testmem16k.v @@ -0,0 +1,45 @@ +module testmem16k( + // input + i_clk, i_reset_n, + i_address, i_write, i_read, i_writedata, + // output + o_readdata, o_waitrequest +); + input wire i_clk; + input wire i_reset_n; + input wire [17:0] i_address; + input wire i_write; + input wire i_read; + input wire [35:0] i_writedata; + output wire [35:0] o_readdata; + output wire o_waitrequest; + + reg [35:0] mem[0:'o40000-1]; + wire addrok = i_address[17:14] == 0; + wire [13:0] addr = i_address[13:0]; + wire [35:0] memword = addrok ? mem[addr] : 0; + + wire write_edge, read_edge; + reg [3:0] dly; + wire ready = dly == 0; + + edgedet e0(i_clk, i_reset_n, i_write, write_edge); + edgedet e1(i_clk, i_reset_n, i_read, read_edge); + + always @(posedge i_clk or negedge i_reset_n) begin + if(~i_reset_n) begin + dly <= 4; + end else begin + if(i_write & ready & addrok) begin + mem[addr] <= i_writedata; + end + if(~(i_write | i_read)) + dly <= 4; + else if(dly) + dly <= dly - 1; + end + end + + assign o_readdata = i_read ? memword : 0; + assign o_waitrequest = ~ready; +endmodule diff --git a/verilog/quartus/uart.v b/verilog/tty.v similarity index 94% rename from verilog/quartus/uart.v rename to verilog/tty.v index 875ef12..54250cb 100644 --- a/verilog/quartus/uart.v +++ b/verilog/tty.v @@ -1,3 +1,159 @@ +module tty( + input wire clk, + input wire reset, + + /* IO bus */ + input wire iobus_iob_poweron, + input wire iobus_iob_reset, + input wire iobus_datao_clear, + input wire iobus_datao_set, + input wire iobus_cono_clear, + input wire iobus_cono_set, + input wire iobus_iob_fm_datai, + input wire iobus_iob_fm_status, + input wire [3:9] iobus_ios, + input wire [0:35] iobus_iob_in, + output wire [1:7] iobus_pi_req, + output wire [0:35] iobus_iob_out, + + /* UART pins */ + input wire rx, + output wire tx, + + /* Panel */ + output wire [7:0] tti_ind, + output wire [6:0] status_ind +); + wire clk2; + clk14khz clock2(.inclk(clk), + .outclk(clk2)); + + wire tti_clock, tto_clock; + clk16div ttidiv(.clk(clk), + .inclk(clk2), + .outclk(tti_clock)); + clk4div ttodiv(.clk(clk), + .inclk(tti_clock), + .outclk(tto_clock)); + + wire tty_sel = iobus_ios == 7'b001_010_0; + + wire tty_data_clr; + wire tty_data_set; + wire tty_ic_clr; + wire tty_ic_set; + wire tty_reset; + wire tty_datai = tty_sel & iobus_iob_fm_datai; + wire tty_status = tty_sel & iobus_iob_fm_status; + pg tty_pg0(.clk(clk), .reset(reset), + .in(tty_sel & iobus_datao_clear), + .p(tty_data_clr)); + pg tty_pg1(.clk(clk), .reset(reset), + .in(tty_sel & iobus_datao_set), + .p(tty_data_set)); + pg tty_pg2(.clk(clk), .reset(reset), + .in(tty_sel & iobus_cono_clear | iobus_iob_reset), + .p(tty_ic_clr)); + pg tty_pg3(.clk(clk), .reset(reset), + .in(tty_sel & iobus_cono_set), + .p(tty_ic_set)); + pg tty_pg4(.clk(clk), .reset(reset), + .in(iobus_iob_reset), + .p(tty_reset)); + + assign iobus_iob_out = + tty_datai ? { 28'b0, tti_ind } : + tty_status ? { 29'b0, tti_busy, tti_flag, tto_busy, tto_flag, tty_pia } : + 36'b0; + + wire [0:7] tty_req = { tti_flag | tto_flag, 7'b0 } >> tty_pia; + assign iobus_pi_req = tty_req[1:7]; + + reg [33:35] tty_pia = 0; + reg tti_busy = 0; + reg tti_flag = 0; + reg tto_busy = 0; + reg tto_flag = 0; + wire tto_done; + reg tto_done0; + wire tti_done; + reg tti_done0; + wire tti_active; + reg tti_active0; + + assign status_ind = { tti_busy, tti_flag, tto_busy, tto_flag, tty_pia }; + + always @(posedge clk) begin + tti_done0 <= tti_done; + tto_done0 <= tto_done; + tti_active0 <= tti_active; + + if(tty_ic_clr) + tty_pia <= 0; + if(tty_reset) begin + tto_busy <= 0; + tto_flag <= 0; + tti_busy <= 0; + tti_flag <= 0; + end + if(tty_ic_set) begin + tty_pia <= iobus_iob_in[33:35]; + if(iobus_iob_in[25]) + tti_busy <= 0; + if(iobus_iob_in[26]) + tti_flag <= 0; + if(iobus_iob_in[27]) + tto_busy <= 0; + if(iobus_iob_in[28]) + tto_flag <= 0; + if(iobus_iob_in[29]) + tti_busy <= 1; + if(iobus_iob_in[30]) + tti_flag <= 1; + if(iobus_iob_in[31]) + tto_busy <= 1; + if(iobus_iob_in[32]) + tto_flag <= 1; + end + + if(tty_data_clr) begin + tto_flag <= 0; + tto_busy <= 1; + end + if(~tto_done0 & tto_done) begin + tto_flag <= 1; + tto_busy <= 0; + end + + if(tty_datai) + tti_flag <= 0; + if(~tti_active0 & tti_active) + tti_busy <= 1; + if(~tti_done0 & tti_done) begin + tti_flag <= 1; + tti_busy <= 0; + end + end + + wire [8:1] iob; + + tti tti0(.clk(clk), + .tti_clock(tti_clock), + .rx(rx), + .iob(iob), + .tti_active(tti_active), + .tti_done(tti_done), + .tti(tti_ind)); + tto tto0(.clk(clk), + .tto_clock(tto_clock), + .iob(iobus_iob_in[28:35]), + .tty_data_clr(tty_data_clr), + .tty_data_set(tty_data_set), + .tx(tx), + .tto_done(tto_done)); + +endmodule + module tto(input wire clk, input wire tto_clock, input wire [8:1] iob, @@ -108,157 +264,6 @@ module tti(input wire clk, end endmodule -module tty( - input wire clk, - input wire rx, - output wire tx, - - output wire [7:0] tti_ind, - output wire [6:0] status_ind, - - input wire iobus_iob_poweron, - input wire iobus_iob_reset, - input wire iobus_datao_clear, - input wire iobus_datao_set, - input wire iobus_cono_clear, - input wire iobus_cono_set, - input wire iobus_iob_fm_datai, - input wire iobus_iob_fm_status, - input wire [3:9] iobus_ios, - input wire [0:35] iobus_iob_in, - output wire [1:7] iobus_pi_req, - output wire [0:35] iobus_iob_out -); - wire clk2; - clk14khz clock2(.inclk(clk), - .outclk(clk2)); - - wire tti_clock, tto_clock; - clk16div ttidiv(.clk(clk), - .inclk(clk2), - .outclk(tti_clock)); - clk4div ttodiv(.clk(clk), - .inclk(tti_clock), - .outclk(tto_clock)); - - wire tty_sel = iobus_ios == 7'b001_010_0; - - wire tty_data_clr; - wire tty_data_set; - wire tty_ic_clr; - wire tty_ic_set; - wire tty_reset; - wire tty_datai = tty_sel & iobus_iob_fm_datai; - wire tty_status = tty_sel & iobus_iob_fm_status; - pg tty_pg0(.clk(clk), .reset(0), - .in(tty_sel & iobus_datao_clear), - .p(tty_data_clr)); - pg tty_pg1(.clk(clk), .reset(0), - .in(tty_sel & iobus_datao_set), - .p(tty_data_set)); - pg tty_pg2(.clk(clk), .reset(0), - .in(tty_sel & iobus_cono_clear), - .p(tty_ic_clr)); - pg tty_pg3(.clk(clk), .reset(0), - .in(tty_sel & iobus_cono_set), - .p(tty_ic_set)); - pg tty_pg4(.clk(clk), .reset(0), - .in(iobus_iob_reset), - .p(tty_reset)); - - assign iobus_iob_out = - tty_datai ? { 28'b0, tti_ind } : - tty_status ? { 29'b0, tti_busy, tti_flag, tto_busy, tto_flag, tty_pia } : - 36'b0; - - wire [0:7] tty_req = { tti_flag | tto_flag, 7'b0 } >> tty_pia; - assign iobus_pi_req = tty_req[1:7]; - - reg [33:35] tty_pia = 0; - reg tti_busy = 0; - reg tti_flag = 0; - reg tto_busy = 0; - reg tto_flag = 0; - wire tto_done; - reg tto_done0; - wire tti_done; - reg tti_done0; - wire tti_active; - reg tti_active0; - - assign status_ind = { tti_busy, tti_flag, tto_busy, tto_flag, tty_pia }; - - always @(posedge clk) begin - tti_done0 <= tti_done; - tto_done0 <= tto_done; - tti_active0 <= tti_active; - - if(tty_ic_clr | tty_reset) - tty_pia <= 0; - if(tty_reset) begin - tto_busy <= 0; - tto_flag <= 0; - tti_busy <= 0; - tti_flag <= 0; - end - if(tty_ic_set) begin - tty_pia <= iobus_iob_in[33:35]; - if(iobus_iob_in[25]) - tti_busy <= 0; - if(iobus_iob_in[26]) - tti_flag <= 0; - if(iobus_iob_in[27]) - tto_busy <= 0; - if(iobus_iob_in[28]) - tto_flag <= 0; - if(iobus_iob_in[29]) - tti_busy <= 1; - if(iobus_iob_in[30]) - tti_flag <= 1; - if(iobus_iob_in[31]) - tto_busy <= 1; - if(iobus_iob_in[32]) - tto_flag <= 1; - end - - if(tty_data_clr) begin - tto_flag <= 0; - tto_busy <= 1; - end - if(~tto_done0 & tto_done) begin - tto_flag <= 1; - tto_busy <= 0; - end - - if(tty_datai) - tti_flag <= 0; - if(~tti_active0 & tti_active) - tti_busy <= 1; - if(~tti_done0 & tti_done) begin - tti_flag <= 1; - tti_busy <= 0; - end - end - - wire [8:1] iob; - - tti tti0(.clk(clk), - .tti_clock(tti_clock), - .rx(rx), - .iob(iob), - .tti_active(tti_active), - .tti_done(tti_done), - .tti(tti_ind)); - tto tto0(.clk(clk), - .tto_clock(tto_clock), - .iob(iobus_iob_in[28:35]), - .tty_data_clr(tty_data_clr), - .tty_data_set(tty_data_set), - .tx(tx), - .tto_done(tto_done)); - -endmodule - module clk14khz(input wire inclk, output wire outclk); reg [11:0] cnt = 0;