From d8edd19b0deeaeb559e65f6f5a1d8fc2ca8cf6aa Mon Sep 17 00:00:00 2001 From: aap Date: Sat, 10 Dec 2016 19:18:16 +0100 Subject: [PATCH] implemented mul and div subroutines --- verilog/Makefile | 2 +- verilog/apr.v | 364 ++++++++++++++++++++++++++++++++++++++------- verilog/core161c.v | 4 +- verilog/test.gtkw | 96 ++++++++++-- verilog/test.v | 49 +----- verilog/test1.inc | 50 +++++++ verilog/test2.inc | 21 +++ 7 files changed, 472 insertions(+), 114 deletions(-) create mode 100644 verilog/test1.inc create mode 100644 verilog/test2.inc diff --git a/verilog/Makefile b/verilog/Makefile index 3951002..41624a7 100644 --- a/verilog/Makefile +++ b/verilog/Makefile @@ -1,4 +1,4 @@ -test: test.v pdp6.v apr.v core161c.v fast162.v modules.v +test: test.v pdp6.v apr.v core161c.v fast162.v modules.v test1.inc test2.inc iverilog -o test test.v pdp6.v apr.v core161c.v fast162.v modules.v test_dec: test_dec.v pdp6.v apr.v core161c.v fast162.v modules.v diff --git a/verilog/apr.v b/verilog/apr.v index 40bf77a..d1d0eb5 100644 --- a/verilog/apr.v +++ b/verilog/apr.v @@ -1087,7 +1087,7 @@ module apr( wire ar_clr = dst2 | fat6 | et0a & ar_clr_et0 | et1 & ar_clr_et1 | - mst1_D; + mst1_D0; wire ar_clr_et0 = boole_0 | boole_3 | boole_14 | boole_17; wire ar_clr_et1 = hwt_ar_clr | iot_status | iot_datai; wire ar_com = ar_incdec_t0 | ar_negate_t0 | @@ -1211,11 +1211,6 @@ module apr( .in(ar_cry_comp), .p(ar_cry_comp_D)); - wire mst1_D; - dly50ns ar_dly7(.clk(clk), .reset(reset), - .in(mst1), - .p(mst1_D)); - wire [0:35] ar_mb_cry = mb & ~ar; wire [0:35] ar_cry_in = ar_cry_initiate ? { mb[1:35]&~ar[1:35], 1'b0 } : ar35_cry_in & ar17_cry_in ? 36'o000001000001 : @@ -1910,16 +1905,45 @@ module apr( reg mpf2; wire mp_clr = mr_clr; - wire mpt0 = 0; - wire mpt0a = 0; - wire mpt1 = 0; - wire mpt2 = 0; + wire mpt0; + wire mpt0a; + wire mpt1; + wire mpt2; + + pa mp_pa0(.clk(clk), .reset(reset), + .in(et0 & ir_mul), + .p(mpt0)); + pa mp_pa1(.clk(clk), .reset(reset), + .in(mst6 & mpf1), + .p(mpt0a)); + pa mp_pa2(.clk(clk), .reset(reset), + .in(mpt0a_D & ~ir[6]), + .p(mpt1)); + pa mp_pa3(.clk(clk), .reset(reset), + .in(mpt1_D), + .p(mpt2)); + + wire mpt0a_D, mpt1_D, mpt2_D; + dly200ns mp_dly0(.clk(clk), .reset(reset), + .in(mpt0a), + .p(mpt0a_D)); + dly100ns mp_dly1(.clk(clk), .reset(reset), + .in(mpt1), + .p(mpt1_D)); + dly100ns mp_dly2(.clk(clk), .reset(reset), + .in(mpt2), + .p(mpt2_D)); always @(posedge clk) begin if(mp_clr | mpt0a) mpf1 <= 0; + if(mpt0) + mpf1 <= 1; + if(mp_clr) mpf2 <= 0; + if(mpt0 & ar[0] & mb[0]) + mpf2 <= 1; end /* @@ -2022,19 +2046,58 @@ module apr( * MS */ reg msf1; - wire ms_mult = 0; + wire ms_mult = mpf1 | fmf2; - wire mst1 = 0; - wire mst2 = 0; - wire mst3 = 0; - wire mst3a = 0; - wire mst4 = 0; - wire mst5 = 0; - wire mst6 = 0; + wire mst1; + wire mst2; + wire mst3; + wire mst3a; + wire mst4; + wire mst5; + wire mst6; + + pa ms_pa0(.clk(clk), .reset(reset), + .in(mpt0 | fmt0a), + .p(mst1)); + pa ms_pa1(.clk(clk), .reset(reset), + .in(((mst1_D1 | mst2_D) & mq35_eq_mq36 | mst3a) & ~sc_eq_777), + .p(mst2)); + pa ms_pa2(.clk(clk), .reset(reset), + .in((mst1_D1 | mst2_D) & ~mq[35] & mq36), + .p(mst3)); + pa ms_pa3(.clk(clk), .reset(reset), + .in((mst1_D1 | mst2_D) & mq[35] & ~mq36), + .p(mst4)); + pa ms_pa4(.clk(clk), .reset(reset), + .in(ar_t3 & msf1), + .p(mst3a)); + pa ms_pa5(.clk(clk), .reset(reset), + .in((mst2_D & mq35_eq_mq36 | mst3a) & sc_eq_777), + .p(mst5)); + pa ms_pa6(.clk(clk), .reset(reset), + .in(mst5_D), + .p(mst6)); + + wire mst1_D0, mst1_D1; + wire mst2_D, mst5_D; + dly50ns ms_dly0(.clk(clk), .reset(reset), + .in(mst1), + .p(mst1_D0)); + dly200ns ms_dly1(.clk(clk), .reset(reset), + .in(mst1), + .p(mst1_D1)); + dly150ns ms_dly2(.clk(clk), .reset(reset), + .in(mst2), + .p(mst2_D)); + dly100ns ms_dly3(.clk(clk), .reset(reset), + .in(mst5), + .p(mst5_D)); always @(posedge clk) begin if(mp_clr | mst3a) msf1 <= 0; + if(mst3 | mst4) + msf1 <= 1; end /* @@ -2049,69 +2112,253 @@ module apr( reg dsf7; reg dsf8; reg dsf9; - wire ds_div = 0; - wire ds_divi = 0; + wire ds_div = ir_div & ir[6]; + wire ds_divi = ir_div & ~ir[6]; + wire dsf7_xor_mq0 = dsf7 ^ mq[0]; + wire ds_clr; - wire dsf7_xor_mq0 = 0; + wire dst0; + wire dst0a; + wire dst1; + wire dst2; + wire dst3; + wire dst4; + wire dst5; + wire dst5a; + wire dst6; + wire dst7; + wire dst8; + wire dst9; + wire dst10; + wire dst10a; + wire dst10b; + wire dst11; + wire dst11a; + wire dst12; + wire dst13; + wire dst14a; + wire dst14b; + wire dst14; + wire dst15; + wire dst16; + wire dst17; + wire dst17a; + wire dst18; + wire dst19; + wire dst19a; + wire dst19b; + wire dst20; + wire dst21; + wire dst21a; - wire dst0 = 0; - wire dst0a = 0; - wire dst1 = 0; - wire dst2 = 0; - wire dst3 = 0; - wire dst4 = 0; - wire dst5 = 0; - wire dst5a = 0; - wire dst6 = 0; - wire dst7 = 0; - wire dst8 = 0; - wire dst9 = 0; - wire dst10 = 0; - wire dst10a = 0; - wire dst10b = 0; - wire dst11 = 0; - wire dst11a = 0; - wire dst12 = 0; - wire dst13 = 0; - wire dst14 = 0; - wire dst14a = 0; - wire dst14b = 0; - wire dst15 = 0; - wire dst16 = 0; - wire dst17 = 0; - wire dst17a = 0; - wire dst18 = 0; - wire dst19 = 0; - wire dst19a = 0; - wire dst20 = 0; - wire dst21 = 0; - wire dst21a = 0; - - wire ds_div_t0 = 0; + wire ds_div_t0; pa ds_pa0(.clk(clk), .reset(reset), .in(mr_clr), .p(ds_clr)); + pa ds_pa1(.clk(clk), .reset(reset), + .in(et0 & ir_div), + .p(ds_div_t0)); + pa ds_pa2(.clk(clk), .reset(reset), + .in((et0 & ds_divi | fdt0a) & ar[0]), + .p(dst0)); + pa ds_pa3(.clk(clk), .reset(reset), + .in(ar_t3 & dsf1), + .p(dst0a)); + pa ds_pa4(.clk(clk), .reset(reset), + .in((et0 & ~ar[0] | dst0a) & ds_divi), + .p(dst1)); + pa ds_pa5(.clk(clk), .reset(reset), + .in(dst1_D), + .p(dst2)); + pa ds_pa6(.clk(clk), .reset(reset), + .in(et0 & ar[0] & ds_div), + .p(dst3)); + pa ds_pa7(.clk(clk), .reset(reset), + .in(dst3_D), + .p(dst4)); + pa ds_pa8(.clk(clk), .reset(reset), + .in(dst4_D), + .p(dst5)); + pa ds_pa9(.clk(clk), .reset(reset), + .in(ar_t3 & dsf2), + .p(dst5a)); + pa ds_pa10(.clk(clk), .reset(reset), + .in(dst5a_D & ~ar_eq_0), + .p(dst6)); + pa ds_pa11(.clk(clk), .reset(reset), + .in(dst6_D), + .p(dst7)); + pa ds_pa12(.clk(clk), .reset(reset), + .in(dst5a_D & ar_eq_0), + .p(dst8)); + pa ds_pa13(.clk(clk), .reset(reset), + .in(dst8_D), + .p(dst9)); + pa ds_pa14(.clk(clk), .reset(reset), + .in(ar_t3 & dsf3 | + fdt0a & ~ar[0] | + dst0a & ~ds_divi | + et0 & ds_div & ~ar[0] | + dst2 | dst7), + .p(dst10)); + pa ds_pa15(.clk(clk), .reset(reset), + .in(dst10_D & ir_fdv), + .p(dst10a)); + pa ds_pa16(.clk(clk), .reset(reset), + .in(dst10_D & ir_div), + .p(dst10b)); + pa ds_pa17(.clk(clk), .reset(reset), + .in((dst10a_D | dst10b_D) & mb[0]), + .p(dst11)); + pa ds_pa18(.clk(clk), .reset(reset), + .in((dst10a_D | dst10b_D) & ~mb[0]), + .p(dst12)); + pa ds_pa19(.clk(clk), .reset(reset), + .in(ar_t3 & dsf4), + .p(dst11a)); + pa ds_pa20(.clk(clk), .reset(reset), + .in(dst11a & ~ar[0]), + .p(dst13)); + pa ds_pa21(.clk(clk), .reset(reset), + .in(ar_t3 & dsf5 | + dst11a & ar[0]), + .p(dst14a)); + pa ds_pa22(.clk(clk), .reset(reset), + .in(dst14a), + .p(dst14b)); + pa ds_pa23(.clk(clk), .reset(reset), + .in(dst14b_D & ~sc_eq_777 & mq35_xor_mb0), + .p(dst14)); + pa ds_pa24(.clk(clk), .reset(reset), + .in(dst14b_D & ~sc_eq_777 & ~mq35_xor_mb0), + .p(dst15)); + pa ds_pa25(.clk(clk), .reset(reset), + .in(dst14b_D & sc_eq_777), + .p(dst16)); + pa ds_pa26(.clk(clk), .reset(reset), + .in(dst16_D & ar[0] & ~mb[0]), + .p(dst17)); + pa ds_pa27(.clk(clk), .reset(reset), + .in(dst16_D & ar[0] & mb[0]), + .p(dst18)); + pa ds_pa28(.clk(clk), .reset(reset), + .in(dst16_D & ~ar[0] | + ar_t3 & dsf6), + .p(dst17a)); + pa ds_pa29(.clk(clk), .reset(reset), + .in(dst17a & dsf7), + .p(dst19)); + pa ds_pa30(.clk(clk), .reset(reset), + .in(dst17a & ~dsf7 | + ar_t3 & dsf8), + .p(dst19a)); + pa ds_pa31(.clk(clk), .reset(reset), + .in(dst19_D), + .p(dst19b)); + pa ds_pa32(.clk(clk), .reset(reset), + .in(dst19a_D), + .p(dst20)); + pa ds_pa33(.clk(clk), .reset(reset), + .in(dst20_D & dsf7_xor_mq0), + .p(dst21)); + pa ds_pa34(.clk(clk), .reset(reset), + .in(dst20_D & ~dsf7_xor_mq0 | + ar_t3 & dsf9), + .p(dst21a)); + + + wire dst1_D, dst3_D, dst4_D, dst5a_D, dst6_D, dst8_D; + wire dst10_D, dst10a_D, dst10b_D, dst14b_D, dst16_D; + wire dst19_D, dst19a_D, dst20_D; + dly150ns ds_dly0(.clk(clk), .reset(reset), + .in(dst1), + .p(dst1_D)); + dly100ns ds_dly1(.clk(clk), .reset(reset), + .in(dst3), + .p(dst3_D)); + dly100ns ds_dly2(.clk(clk), .reset(reset), + .in(dst4), + .p(dst4_D)); + dly100ns ds_dly3(.clk(clk), .reset(reset), + .in(dst5a), + .p(dst5a_D)); + dly100ns ds_dly4(.clk(clk), .reset(reset), + .in(dst6), + .p(dst6_D)); + dly100ns ds_dly5(.clk(clk), .reset(reset), + .in(dst8), + .p(dst8_D)); + dly100ns ds_dly6(.clk(clk), .reset(reset), + .in(dst10), + .p(dst10_D)); + dly200ns ds_dly7(.clk(clk), .reset(reset), + .in(dst10a), + .p(dst10a_D)); + dly200ns ds_dly8(.clk(clk), .reset(reset), + .in(dst10b), + .p(dst10b_D)); + dly100ns ds_dly9(.clk(clk), .reset(reset), + .in(dst14b), + .p(dst14b_D)); + dly100ns ds_dly10(.clk(clk), .reset(reset), + .in(dst16), + .p(dst16_D)); + dly50ns ds_dly11(.clk(clk), .reset(reset), + .in(dst19), + .p(dst19_D)); + dly100ns ds_dly12(.clk(clk), .reset(reset), + .in(dst19a), + .p(dst19a_D)); + dly100ns ds_dly13(.clk(clk), .reset(reset), + .in(dst20), + .p(dst20_D)); always @(posedge clk) begin if(ds_clr | dst0a) dsf1 <= 0; + if(dst0) + dsf1 <= 1; + if(ds_clr | dst5a) dsf2 <= 0; + if(dst5) + dsf2 <= 1; + if(ds_clr | dst10) dsf3 <= 0; + if(dst9) + dsf3 <= 1; + if(ds_clr | dst11a) dsf4 <= 0; + if(dst11 | dst12) + dsf4 <= 1; + if(ds_clr | dst14a) dsf5 <= 0; + if(dst14 | dst15) + dsf5 <= 1; + if(ds_clr | dst17a) dsf6 <= 0; + if(dst17 | dst18) + dsf6 <= 1; + if(mr_clr) dsf7 <= 0; + if(dst0 | dst3) + dsf7 <= 1; + if(ds_clr | dst19a) dsf8 <= 0; + if(dst19b) + dsf8 <= 1; + if(ds_clr | dst21a) dsf9 <= 0; + if(dst21) + dsf9 <= 1; end /* @@ -2134,7 +2381,12 @@ module apr( wire nrt4 = 0; wire nrt5 = 0; wire nrt5a = 0; - wire nrt6 = 0; + wire nrt6; + + pa nr_pa0(.clk(clk), .reset(reset), + .in(mpt0a & ir[6] | + mpt2_D), // TODO + .p(nrt6)); always @(posedge clk) begin if(mp_clr | nrt5a) diff --git a/verilog/core161c.v b/verilog/core161c.v index c2f5f54..414adf0 100644 --- a/verilog/core161c.v +++ b/verilog/core161c.v @@ -316,7 +316,7 @@ module core161c( `ifdef simulation if(cmc_t4) /* As a hack zero core here */ - core[cma[32:35]] <= 0; + core[cma[22:35]] <= 0; `endif if(cmc_t5) begin cmc_rd <= 0; @@ -337,7 +337,7 @@ module core161c( if(cmc_t9 & cmc_wr) /* again a hack. core is written some time after t8. * (cmc_wr is always set here) */ - core[cma[32:35]] <= core[cma[32:35]] | cmb; + core[cma[22:35]] <= core[cma[22:35]] | cmb; `endif if(cmc_t11) cmc_await_rq <= 1; diff --git a/verilog/test.gtkw b/verilog/test.gtkw index 2423ed2..6f379df 100644 --- a/verilog/test.gtkw +++ b/verilog/test.gtkw @@ -1,20 +1,19 @@ [*] [*] GTKWave Analyzer v3.3.76 (w)1999-2016 BSI -[*] Thu Nov 24 15:13:00 2016 +[*] Sat Dec 10 18:05:06 2016 [*] [dumpfile] "/home/aap/src/pdp6/verilog/dump.vcd" -[dumpfile_mtime] "Thu Nov 24 15:10:54 2016" -[dumpfile_size] 251956 +[dumpfile_mtime] "Sat Dec 10 17:52:00 2016" +[dumpfile_size] 335826 [savefile] "/home/aap/src/pdp6/verilog/test.gtkw" -[timestart] 0 +[timestart] 4810 [size] 1920 1080 [pos] -1 -1 -*-11.555068 8970 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +*-11.555068 17575 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 [treeopen] test. [treeopen] test.pdp6. -[treeopen] test.pdp6.fmem0. [sst_width] 337 -[signals_width] 442 +[signals_width] 486 [sst_expanded] 1 [sst_vpaned_height] 319 @28 @@ -60,6 +59,9 @@ test.pdp6.apr0.ir[0:17] test.pdp6.apr0.mb[0:35] test.pdp6.apr0.ar[0:35] test.pdp6.apr0.mq[0:35] +@28 +test.pdp6.apr0.mq36 +@30 test.pdp6.apr0.sc[0:8] test.pdp6.apr0.fe[0:8] test.pdp6.apr0.datasw[0:35] @@ -304,7 +306,6 @@ test.pdp6.apr0.membus_mb_pulse @200 - @30 -test.pdp6.mem0.corescope[0:35] test.pdp6.mem0.ma[21:35] test.pdp6.mem0.cma[22:35] @28 @@ -335,6 +336,8 @@ test.pdp6.mem0.cmc_t9a test.pdp6.mem0.cmc_t10 test.pdp6.mem0.cmc_t11 test.pdp6.mem0.cmc_t12 +@30 +test.pdp6.mem0.sa[0:35] @1401200 -mem0 @c00200 @@ -354,7 +357,6 @@ test.pdp6.fmem0.fmct5 -fmem0 @28 test.pdp6.apr0.at1_inh -@29 test.pdp6.apr0.ia_NOT_int @c00200 -PI @@ -552,5 +554,81 @@ test.pdp6.apr0.dct2 test.pdp6.apr0.dct3 @1401200 -DC +@c00200 +-MP +@28 +test.pdp6.apr0.mpf2 +test.pdp6.apr0.mpt0 +test.pdp6.apr0.mpf1 +test.pdp6.apr0.mpt0a +test.pdp6.apr0.mpt1 +test.pdp6.apr0.mpt2 +@1401200 +-MP +@c00200 +-MS +@28 +test.pdp6.apr0.mst1 +test.pdp6.apr0.mst2 +test.pdp6.apr0.mst3 +test.pdp6.apr0.mst4 +test.pdp6.apr0.msf1 +test.pdp6.apr0.mst3a +test.pdp6.apr0.mst5 +test.pdp6.apr0.mst6 +@1401200 +-MS +@c00201 +-DS +@28 +test.pdp6.apr0.ds_div_t0 +test.pdp6.apr0.dst0 +test.pdp6.apr0.dsf1 +test.pdp6.apr0.dst0a +test.pdp6.apr0.dst1 +test.pdp6.apr0.dst2 +test.pdp6.apr0.dst3 +test.pdp6.apr0.dst4 +test.pdp6.apr0.dst5 +test.pdp6.apr0.dsf2 +test.pdp6.apr0.dst5a +test.pdp6.apr0.dst6 +test.pdp6.apr0.dst7 +test.pdp6.apr0.dst8 +test.pdp6.apr0.dst9 +test.pdp6.apr0.dsf3 +test.pdp6.apr0.dst10 +test.pdp6.apr0.dst10a +test.pdp6.apr0.dst10b +test.pdp6.apr0.dst11 +test.pdp6.apr0.dst12 +test.pdp6.apr0.dsf4 +test.pdp6.apr0.dst11a +test.pdp6.apr0.dst13 +test.pdp6.apr0.dst14a +test.pdp6.apr0.dst14b +test.pdp6.apr0.dst14 +test.pdp6.apr0.dst15 +test.pdp6.apr0.dst16 +test.pdp6.apr0.dst17 +test.pdp6.apr0.dst17a +test.pdp6.apr0.dst18 +test.pdp6.apr0.dst19 +test.pdp6.apr0.dst19a +test.pdp6.apr0.dst19b +test.pdp6.apr0.dst20 +test.pdp6.apr0.dst21 +test.pdp6.apr0.dst21a +@200 +- +@28 +test.pdp6.apr0.dsf5 +test.pdp6.apr0.dsf6 +test.pdp6.apr0.dsf7 +test.pdp6.apr0.dsf7_xor_mq0 +test.pdp6.apr0.dsf8 +test.pdp6.apr0.dsf9 +@1401201 +-DS [pattern_trace] 1 [pattern_trace] 0 diff --git a/verilog/test.v b/verilog/test.v index ec48a3a..4fb6ef2 100644 --- a/verilog/test.v +++ b/verilog/test.v @@ -149,58 +149,15 @@ module test; #20 reset = 0; pdp6.datasw = 36'o111777222666; - pdp6.mas = 18'o000070; + pdp6.mas = 18'o000000; for(i = 0; i < 'o40000; i = i + 1) pdp6.mem0.core[i] = 0; for(i = 0; i < 'o20; i = i + 1) pdp6.fmem0.ff[i] = 0; - pdp6.fmem0.ff['o0] = 36'o000000_010000; - pdp6.fmem0.ff['o1] = 36'o000000_010222; - pdp6.fmem0.ff['o2] = 36'o700000_200006; - pdp6.fmem0.ff['o3] = 36'o500000_000004; - pdp6.fmem0.ff['o4] = 36'o000000_010304; - pdp6.fmem0.ff['o5] = 36'o377777_777777; - pdp6.fmem0.ff['o6] = 36'o444000_222000; - pdp6.fmem0.ff['o7] = 36'o777776_000010; // BLK ptr - pdp6.fmem0.ff['o10] = 36'o000002_001000; // BLT ptr - pdp6.fmem0.ff['o11] = 36'o440600_001000; // char ptr - pdp6.fmem0.ff['o12] = 36'o300600_001000; // char ptr - pdp6.fmem0.ff['o13] = 36'o000000_005555; // char - pdp6.fmem0.ff['o14] = 36'o010700_001017; - pdp6.fmem0.ff['o17] = 36'o777000_001000; // PDL ptr -// pdp6.fmem0.ff['o17] = 36'o777000_777777; // PDL ptr - - pdp6.mem0.core['o20] = 36'o200_064_000104; // MOVE 1,@104(4) FAC_INH - pdp6.mem0.core['o21] = 36'o202_064_000104; // MOVEM 1,@104(4) - pdp6.mem0.core['o22] = 36'o245_100_000003; // ROTC 2,3 - pdp6.mem0.core['o23] = 36'o700200_675550; // CONO APR,675550 - pdp6.mem0.core['o24] = 36'o700200_102227; // CONO APR,102227 - pdp6.mem0.core['o25] = 36'o700240_000005; // CONI APR,5 - pdp6.mem0.core['o26] = 36'o700140_000006; // DATAO APR,6 - pdp6.mem0.core['o27] = 36'o700040_000005; // DATAI APR,5 - pdp6.mem0.core['o30] = 36'o700000_000007; // BLKI APR,7 - - pdp6.mem0.core['o40] = 36'o700640_000005; // CONI APR,5 - pdp6.mem0.core['o41] = 36'o260740_000020; // PUSHJ 17,20 - pdp6.mem0.core['o41] = 36'o250040_000000; // AOS 1, - pdp6.mem0.core['o42] = 36'o270000_000001; // ADD 0,1 - pdp6.mem0.core['o43] = 36'o274000_000001; // SUB 0,1 - - pdp6.mem0.core['o54] = 36'o245_100_000003; // ROTC 2,3 - pdp6.mem0.core['o55] = 36'o245_100_777775; // ROTC 2,-3 - pdp6.mem0.core['o56] = 36'o244_100_000001; // ASHC 2,1 - - pdp6.mem0.core['o60] = 36'o251_400_001001; // BLT 10,1007 - pdp6.mem0.core['o64] = 36'o133_000_000011; // IBP 11 - pdp6.mem0.core['o65] = 36'o135_000_000012; // LBP 0,12 - pdp6.mem0.core['o66] = 36'o134_000_000012; // ILBP 0,12 - pdp6.mem0.core['o67] = 36'o137_540_000012; // DBP 13,12 - pdp6.mem0.core['o70] = 36'o134_000_000014; // ILBP 0,14 - - pdp6.mem0.core['o1000] = 36'o50_45_54_54_57_00; - pdp6.mem0.core['o10410] = 36'o000_000_000333; + //`include "test1.inc" + `include "test2.inc" end wire [0:35] mem0scope = pdp6.mem0.core['o1000]; diff --git a/verilog/test1.inc b/verilog/test1.inc new file mode 100644 index 0000000..260efbb --- /dev/null +++ b/verilog/test1.inc @@ -0,0 +1,50 @@ + pdp6.fmem0.ff['o0] = 36'o000000_010001; + pdp6.fmem0.ff['o1] = 36'o000000_010222; + pdp6.fmem0.ff['o2] = 36'o700000_200006; + pdp6.fmem0.ff['o3] = 36'o500000_000004; + pdp6.fmem0.ff['o4] = 36'o000000_010304; + pdp6.fmem0.ff['o5] = 36'o377777_777777; + pdp6.fmem0.ff['o6] = 36'o444000_222000; + pdp6.fmem0.ff['o7] = 36'o777776_000010; // BLK ptr + pdp6.fmem0.ff['o10] = 36'o000002_001000; // BLT ptr + pdp6.fmem0.ff['o11] = 36'o440600_001000; // char ptr + pdp6.fmem0.ff['o12] = 36'o300600_001000; // char ptr + pdp6.fmem0.ff['o13] = 36'o000000_005555; // char + pdp6.fmem0.ff['o14] = 36'o010700_001017; + pdp6.fmem0.ff['o17] = 36'o777000_001000; // PDL ptr +// pdp6.fmem0.ff['o17] = 36'o777000_777777; // PDL ptr + + pdp6.mem0.core['o20] = 36'o200_064_000104; // MOVE 1,@104(4) FAC_INH + pdp6.mem0.core['o21] = 36'o202_064_000104; // MOVEM 1,@104(4) + pdp6.mem0.core['o22] = 36'o245_100_000003; // ROTC 2,3 + pdp6.mem0.core['o23] = 36'o700200_675550; // CONO APR,675550 + pdp6.mem0.core['o24] = 36'o700200_102227; // CONO APR,102227 + pdp6.mem0.core['o25] = 36'o700240_000005; // CONI APR,5 + pdp6.mem0.core['o26] = 36'o700140_000006; // DATAO APR,6 + pdp6.mem0.core['o27] = 36'o700040_000005; // DATAI APR,5 + pdp6.mem0.core['o30] = 36'o700000_000007; // BLKI APR,7 + + pdp6.mem0.core['o40] = 36'o700640_000005; // CONI APR,5 + pdp6.mem0.core['o41] = 36'o260740_000020; // PUSHJ 17,20 + pdp6.mem0.core['o41] = 36'o250040_000000; // AOS 1, + pdp6.mem0.core['o42] = 36'o270000_000001; // ADD 0,1 + pdp6.mem0.core['o43] = 36'o274000_000001; // SUB 0,1 + + pdp6.mem0.core['o54] = 36'o245_100_000003; // ROTC 2,3 + pdp6.mem0.core['o55] = 36'o245_100_777775; // ROTC 2,-3 + pdp6.mem0.core['o56] = 36'o244_100_000001; // ASHC 2,1 + + pdp6.mem0.core['o60] = 36'o251_400_001001; // BLT 10,1007 + pdp6.mem0.core['o64] = 36'o133_000_000011; // IBP 11 + pdp6.mem0.core['o65] = 36'o135_000_000012; // LBP 0,12 + pdp6.mem0.core['o66] = 36'o134_000_000012; // ILBP 0,12 + pdp6.mem0.core['o67] = 36'o137_540_000012; // DBP 13,12 + pdp6.mem0.core['o70] = 36'o134_000_000014; // ILBP 0,14 + + pdp6.mem0.core['o100] = 36'o221_000_000123; // IMULI 0,123 + + pdp6.mem0.core['o110] = 36'o231_200_000123; // IDIVI 4,123 + pdp6.mem0.core['o111] = 36'o231_340_000123; // IDIVI 7,123 + + pdp6.mem0.core['o1000] = 36'o50_45_54_54_57_00; + pdp6.mem0.core['o10410] = 36'o000_000_000333; diff --git a/verilog/test2.inc b/verilog/test2.inc new file mode 100644 index 0000000..e755816 --- /dev/null +++ b/verilog/test2.inc @@ -0,0 +1,21 @@ +pdp6.fmem0.ff['o0] = 36'o000000_010001; +pdp6.fmem0.ff['o1] = 36'o777777_767777; + +pdp6.fmem0.ff['o2] = 36'o000000_010001; +pdp6.fmem0.ff['o3] = 36'o001200_034000; + +pdp6.fmem0.ff['o4] = 36'o777777_767776; +pdp6.fmem0.ff['o5] = 36'o776577_744000; + +pdp6.fmem0.ff['o6] = 36'o777777_767776; +pdp6.fmem0.ff['o7] = 36'o000000_000000; + +pdp6.mem0.core['o100] = 36'o221_000_000123; // IMULI 0,123 + +pdp6.mem0.core['o110] = 36'o231_000_000123; // IDIVI 0,123 +pdp6.mem0.core['o111] = 36'o231_040_000123; // IDIVI 1,123 +pdp6.mem0.core['o112] = 36'o235_100_000123; // DIVI 2,123 +pdp6.mem0.core['o113] = 36'o235_200_000123; // DIVI 4,123 +pdp6.mem0.core['o114] = 36'o235_300_000123; // DIVI 6,123 + +pdp6.mas = 18'o000110;