From db93c803c81853397b921c57a1e3b8e532ec5d1c Mon Sep 17 00:00:00 2001 From: aap Date: Mon, 21 Nov 2016 11:39:40 +0100 Subject: [PATCH] work on IOT, AR, SH and SC --- art/elements.svg | 8 +- art/lamp_on.png | Bin 512 -> 510 bytes verilog/apr.v | 443 ++++++++++++++++++++++++++++++++++++++-------- verilog/modules.v | 84 +++++++++ verilog/test.gtkw | 102 +++++++++-- verilog/test.v | 91 +++++++--- 6 files changed, 618 insertions(+), 110 deletions(-) diff --git a/art/elements.svg b/art/elements.svg index e9af030..27e15b0 100644 --- a/art/elements.svg +++ b/art/elements.svg @@ -29,7 +29,7 @@ inkscape:pageopacity="0.0" inkscape:pageshadow="2" inkscape:zoom="2.2066156" - inkscape:cx="406.39064" + inkscape:cx="314.62114" inkscape:cy="326.91335" inkscape:document-units="mm" inkscape:current-layer="layer7" @@ -37,8 +37,8 @@ units="mm" inkscape:window-width="1920" inkscape:window-height="1080" - inkscape:window-x="0" - inkscape:window-y="0" + inkscape:window-x="32" + inkscape:window-y="18" inkscape:window-maximized="0" inkscape:snap-global="true" showguides="false" @@ -231,7 +231,7 @@ cy="92.126007" cx="139.42914" id="circle4665" - style="fill:#ffd700;fill-opacity:1;stroke:#000000;stroke-width:1.35701132;stroke-linecap:butt;stroke-linejoin:round;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1" /> + style="fill:#ffbf00;fill-opacity:1;stroke:#000000;stroke-width:1.35701132;stroke-linecap:butt;stroke-linejoin:round;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1" /> 0|$rbI1VT%9B- zoTOY_{3$tzv&-V@E_2XO=B7=`!AvaEuo;^JsqN=r`%y(BmB~sAV7N~g{pj-&aR0@Vt4=)sl3vpV`9+$ zapi0p>Y=o@f=NIr0m{_aNBS`2GN(1%i$SBNTLP48u(j4vAQxb*r$DErLjnjOigMk2 z6pN6Q0C!Q`UVk62asi%mUP2GJB|tdNj>E~NT)>)>t7x2E_+3R_Dps%+-< zZ5}rdnSY3LlnEdb!xOkg{ro~ho0&qzw^>LeVR?hFV~f?(04wSJA0ty)MyFB7oV6Z< z#Y8c{iJvF$1(&`XW`uX)Q`!efYSWo%apCCaVDjT;Fi zS5kK2#!JbC=Gx8T4`5d=l@yoSq{hh0Ch{`lK_Rsr7q-WQ?YZ-I_JQD zONvv=2IPqM1CN>jauID6GE-I)74^1@+4?-M# zA0ZE7-o~xDmf6@$Qq-8L7#<&FVx*Tm>6gYN37RZqq@_@Ic*^~qf(t+wsV7&-jP`YY z9yy-+yU4AU83U44Kz=SALp|sdg`*niMxU2Oy9y{OpxI(1RV%=1BDJKD78M|c5khE< zgAgDj!Ybe<$bYtbpEs=l*FLXTH*Bkbzys@!RnD{mmYn$RpV)w}YYgio-ZRr_ZZMJ- zFTCvJVQrI{pu$cpfI9`3|B|fd7YvPNGIYA{!B7b7%LE)NEP9Svh|d3bGNr||R+ces zHKI2g$OhQ+qPPz@JMuAk6<{lNeWK4)9`SzQDPC*;rxg!zb$1(xbz^n_0000> 35; - {cry0, ar} <= ar + { ar_mb_cry[1:35], 1'b0 }; + if(ar_cry_in) begin + cry1 <= (ar[1:35] + ar_cry_in[1:35]) + 36'o0 >> 35; + {cry0, ar} <= ar + ar_cry_in; end if(arlt_com) ar[0:17] <= ~ar[0:17]; if(arrt_com) - ar[0:17] <= ~ar[0:17]; + ar[18:35] <= ~ar[18:35]; if(arlt_fm_mb_xor) ar[0:17] <= ar[0:17] ^ mb[0:17]; if(arrt_fm_mb_xor) @@ -1199,9 +1235,19 @@ module apr( ar[0:17] <= ar[0:17] | iob[0:17]; if(arrt_fm_iob1) ar[18:35] <= ar[18:35] | iob[18:35]; + if(ar1_8_clr) + ar[1:8] <= 0; + if(ar1_8_set) + ar[1:8] <= 8'o377; + if(ar_fm_sc1_8J) + ar[1:8] <= sc; + if(ar0_5_fm_sc3_8J) + ar[0:5] <= sc[3:8]; if(mr_clr | ar_t3) ar_com_cont <= 0; + if(ar_as_t0 | ar_incdec_t0) + ar_com_cont <= 1; if(ar_flag_clr) begin ar_pc_chg_flag <= 0; ar_ov_flag <= 0; @@ -1327,20 +1373,31 @@ module apr( wire fe_fm_mb0_5_1 = 0; reg [0:8] sc; - wire sc_clr = 0; - wire sc_inc = 0; - wire sc_com = 0; + wire sc_clr = mr_clr | cht4 | cht8a | + fat5a | fpt3 | mst5 | dst20 | + cht6 & ch_inc_op; + wire sc_inc = fpt2 | fat2 | sht0 | fst1 | nrt0 | + sct1 | mst2 | dst14a | nrt2; + wire sc_com = cht8b | cht5 | fat3 | nrt1 | lct0 | dct0 | + et1 & ir_fsc & ~ar[0] | + fpt1 & fp_ar0_xor_fmf1 | + fat0 & ~ar0_xor_mb0 | + fpt1a & ~fp_ar0_xor_mb0_xor_fmf1 | + sht1 & mb[18] | + fpt1b & fp_mb0_eq_fmf1 | + fat7 & mb[0] | + nrt3 & (~ar[0] | nr_round); wire sc_pad = 0; wire sc_cry = 0; wire sc_fm_fe1 = 0; - wire sc_fm_mb18_28_35_0 = 0; + wire sc_fm_mb18_28_35_0 = et0a & (fsc | shift_op); wire sc_mb0_5_0_enable = 0; wire sc_mb6_11_1_enable = 0; wire sc_ar0_8_1_enable = 0; wire sc_mb0_8_1_enable = 0; - // TODO: figure out what's going on here... - wire sc_eq_777 = 0; - wire sc0_2_eq_7 = 0; + // TODO: what the hell is sc8b? + wire sc_eq_777 = sc == 9'o777; + wire sc0_2_eq_7 = sc[0:2] == 3'o7; wire sat0 = 0; wire sat1 = 0; @@ -1348,9 +1405,51 @@ module apr( wire sat21 = 0; wire sat3 = 0; - wire sct0 = 0; - wire sct1 = 0; - wire sct2 = 0; + wire sct0; + wire sct1; + wire sct2; + + pa sc_pa0(.clk(clk), .reset(reset), + .in(lct0 | dct0 | sht1 | fat5 | + cht8b & ~ir_cao), + .p(sct0)); + pa sc_pa1(.clk(clk), .reset(reset), + .in((sct0_D | sct1_D) & ~sc_eq_777), + .p(sct1)); + pa sc_pa2(.clk(clk), .reset(reset), + .in((sct0_D | sct1_D) & sc_eq_777), + .p(sct2)); + + wire sct0_D, sct1_D; + dly200ns sc_dly0(.clk(clk), .reset(reset), + .in(sct0), + .p(sct0_D)); + // should be 75ns + dly70ns sc_dly1(.clk(clk), .reset(reset), + .in(sct1), + .p(sct1_D)); + + always @(posedge clk) begin + if(fe_clr) + fe <= 0; + if(fe_fm_sc1) + fe <= fe | sc; + if(fe_fm_mb0_5_1) + fe <= fe | { 3'b0, mb[0:5]}; + + if(sc_clr) + sc <= 0; + if(sc_inc) + sc <= sc + 1; + if(sc_com) + sc <= ~sc; + // TODO: sc_pad, sc_cry + if(sc_fm_fe1) + sc <= sc | fe; + if(sc_fm_mb18_28_35_0) + sc <= sc | ~{ mb[18], mb[28:35] }; + // TODO: single bits + end /* * CFAC @@ -1363,10 +1462,14 @@ module apr( wire cfac_mb_ar_swap = 0; wire cfac_ar_com = 0; wire cfac_overflow = 0; - wire cfac_ar_sh_lt = 0; - wire cfac_mq_sh_lt = 0; - wire cfac_ar_sh_rt = 0; - wire cfac_mq_sh_rt = 0; + wire cfac_ar_sh_lt = dst14a | nrt2 | + sct1 & (dcf1 | shift_op & ~mb[18]); + wire cfac_mq_sh_lt = dst14a | nrt2 | dst10b | + sct1 & (dcf1 | chf4 | shift_op & ~mb[18]); + wire cfac_ar_sh_rt = nrt0 | mst2 | dst16 | dst10a | fdt1 | + sct1 & (faf3 | lcf1 | shift_op & mb[18]); + wire cfac_mq_sh_rt = nrt0 | mst2 | mst5 | fdt1 | + sct1 & (faf3 | shift_op & mb[18]); /* * BLT @@ -1462,9 +1565,31 @@ module apr( ir_rot | ir_rotc; wire sh_ac_2 = ir_ashc | ir_lshc | ir_rotc; - wire sht0 = 0; - wire sht1 = 0; - wire sht1a = 0; + wire sht0; + wire sht1; + wire sht1a; + + pa sh_p0(.clk(clk), .reset(reset), + .in(et1 & shift_op & mb[18]), + .p(sht0)); + pa sh_p1(.clk(clk), .reset(reset), + .in(et3_D & shift_op), + .p(sht1)); + pa sh_p2(.clk(clk), .reset(reset), + .in(sct2 & shf1), + .p(sht1a)); + + wire et3_D; + dly100ns sh_dly(.clk(clk), .reset(reset), + .in(et3), + .p(et3_D)); + + always @(posedge clk) begin + if(mp_clr | sht1a) + shf1 <= 0; + if(sht1) + shf1 <= 1; + end /* * MP @@ -1477,6 +1602,11 @@ module apr( wire mpt1 = 0; wire mpt2 = 0; + always @(posedge clk) begin + if(mp_clr | mpt0a) + mpf1 <= 0; + end + /* * FA */ @@ -1501,6 +1631,17 @@ module apr( wire fat9 = 0; wire fat10 = 0; + always @(posedge clk) begin + if(mp_clr | fat1b | fat10) + faf1 <= 0; + if(mp_clr | fat1a) + faf2 <= 0; + if(mp_clr | fat5a) + faf3 <= 0; + if(mp_clr | fat10) + faf4 <= 0; + end + /* * FM */ @@ -1511,6 +1652,13 @@ module apr( wire fmt0a = 0; wire fmt0b = 0; + always @(posedge clk) begin + if(mp_clr | fmt0a) + fmf1 <= 0; + if(mp_clr | fmt0b) + fmf2 <= 0; + end + /* * FD */ @@ -1522,6 +1670,13 @@ module apr( wire fdt0b = 0; wire fdt1 = 0; + always @(posedge clk) begin + if(mp_clr | fdt0a) + fdf1 <= 0; + if(mp_clr | fdt0b) + fdf2 <= 0; + end + /* * FP */ @@ -1541,6 +1696,13 @@ module apr( wire fpt3 = 0; wire fpt4 = 0; + always @(posedge clk) begin + if(mp_clr | fpt1a) + fpf1 <= 0; + if(mp_clr | fpt1b) + fpf2 <= 0; + end + /* * MS */ @@ -1555,6 +1717,11 @@ module apr( wire mst5 = 0; wire mst6 = 0; + always @(posedge clk) begin + if(mp_clr | mst3a) + msf1 <= 0; + end + /* * DS */ @@ -1579,6 +1746,7 @@ module apr( wire dst3 = 0; wire dst4 = 0; wire dst5 = 0; + wire dst5a = 0; wire dst6 = 0; wire dst7 = 0; wire dst8 = 0; @@ -1599,12 +1767,34 @@ module apr( wire dst17a = 0; wire dst18 = 0; wire dst19 = 0; + wire dst19a = 0; wire dst20 = 0; wire dst21 = 0; wire dst21a = 0; wire ds_div_t0 = 0; + always @(posedge clk) begin + if(ds_clr | dst0a) + dsf1 <= 0; + if(ds_clr | dst5a) + dsf2 <= 0; + if(ds_clr | dst10) + dsf3 <= 0; + if(ds_clr | dst11a) + dsf4 <= 0; + if(ds_clr | dst14a) + dsf5 <= 0; + if(ds_clr | dst17a) + dsf6 <= 0; + if(mr_clr) + dsf7 <= 0; + if(ds_clr | dst19a) + dsf8 <= 0; + if(ds_clr | dst21a) + dsf9 <= 0; + end + /* * NR */ @@ -1627,6 +1817,15 @@ module apr( wire nrt5a = 0; wire nrt6 = 0; + always @(posedge clk) begin + if(mp_clr | nrt5a) + nrf1 <= 0; + if(mp_clr) begin + nrf2 <= 0; + nrf3 <= 0; + end + end + /* * MA */ @@ -1710,6 +1909,10 @@ module apr( pr <= 0; rlr <= 0; end + if(ex_set) begin + pr <= pr | iob[0:7]; + rlr <= rlr | iob[18:25]; + end end /* @@ -1926,31 +2129,82 @@ module apr( wire iot_outgoing = iot_datao | iot_cono; wire iot_status = iot_coni | iot_consz | iot_conso; wire iot_datai_o = iot_datai | iot_datao; - wire iot_init_setup = 0; - wire iot_final_setup = 0; + wire iot_init_setup; + wire iot_restart; + wire iot_final_setup; + wire iot_reset; wire iot_t0 = 0; wire iot_t0a = 0; - wire iot_t2 = 0; - wire iot_t3 = 0; - wire iot_t3a = 0; - wire iot_t4 = 0; + wire iot_t2; + wire iot_t3; + wire iot_t3a; + wire iot_t4; + + wire iot_go_P; + pg iot_pg0(.clk(clk), .reset(reset), + .in(iot_go & ~iot_reset), + .p(iot_go_P)); + + assign iobus_iob_poweron = sw_power; + pa iot_pa0(.clk(clk), .reset(reset), + .in(mr_start | cpa_cono_set & iob[19]), + .p(iobus_iob_reset)); + pa iot_pa1(.clk(clk), .reset(reset), + .in(iot_t2 & iot_cono), + .p(iobus_cono_clear)); + pa iot_pa2(.clk(clk), .reset(reset), + .in(iot_t3 & iot_cono), + .p(iobus_cono_set)); + pa iot_pa3(.clk(clk), .reset(reset), + .in(iot_t2 & iot_datao), + .p(iobus_datao_clear)); + pa iot_pa4(.clk(clk), .reset(reset), + .in(iot_t3 & iot_datao), + .p(iobus_datao_set)); + assign iobus_iob_fm_datai = iot_datai & iot_drive; + assign iobus_iob_fm_status = iot_status & iot_drive; + wire iob_fm_ar1 = iot_outgoing & iot_drive; wire iot_t0a_D; dly200ns iot_dly0(.clk(clk), .reset(reset), .in(iot_t0a), .p(iot_t0a_D)); + ldly1us iot_dly1(.clk(clk), .reset(reset), + .in(iot_go_P), + .p(iot_t2), + .l(iot_init_setup)); + ldly1_5us iot_dly2(.clk(clk), .reset(reset), + .in(iot_t2), + .p(iot_t3a), + .l(iot_final_setup)); + ldly2us iot_dly3(.clk(clk), .reset(reset), + .in(iot_t3a), + .p(iot_t4), + .l(iot_reset)); + ldly1us iot_dly4(.clk(clk), .reset(reset), + .in(iot_t2), + .p(iot_t3), + .l(iot_restart)); + wire iot_drive = iot_init_setup | iot_final_setup | iot_t2; + + always @(posedge clk) begin + if(mr_clr | iot_t2) + iot_go <= 0; + if(et4 & ir_iot & ~iot_blk) + iot_go <= 1; + + if(mr_clr | iot_t0a) + iot_f0a <= 0; + if(iot_t0) + iot_f0a <= 1; + end /* IOB */ - assign iobus_iob_poweron = 0; - assign iobus_iob_reset = 0; - assign iobus_datao_clear = 0; - assign iobus_datao_set = 0; - assign iobus_cono_clear = 0; - assign iobus_cono_set = 0; - assign iobus_iob_fm_datai = 0; - assign iobus_iob_fm_status = 0; - assign iobus_iob_out = 0; + assign iobus_iob_out = iob_fm_ar1 ? ar : + cpa_status ? cpa_iob : + pi_status ? pi_iob : + 0; wire [0:35] iob = iobus_iob_in; /* @@ -2038,6 +2292,8 @@ module apr( wire pi_sync; wire pi_reset; + wire [0:35] pi_iob = { 28'b0, pi_active, pio }; + pa pi_pa0(.clk(clk), .reset(reset), .in(it0 | at0), .p(pi_sync)); @@ -2082,8 +2338,9 @@ module apr( reg cpa_arov_enable; reg [33:35] cpa_pia; wire cpa = iobus_ios == 0; - wire cpa_cono_set = 0; - wire cpa_status = 0; + wire cpa_cono_set = cpa & iobus_cono_set; + wire cpa_status = cpa & iobus_iob_fm_status; + wire cpa_clock_flag_set = 0; wire cpa_req_enable = cpa_illeg_op | cpa_non_exist_mem | cpa_pdl_ov | cpa_clock_enable & cpa_clock_flag | @@ -2094,6 +2351,13 @@ module apr( for(j = 1; j <= 7; j = j + 1) assign cpa_req[j] = cpa_req_enable & (cpa_pia == j); + wire [0:35] cpa_iob = { 18'b0, + 1'b0, cpa_pdl_ov, cpa_iot_user, ex_user, + cpa_illeg_op, cpa_non_exist_mem, 1'b0, cpa_clock_enable, + cpa_clock_flag, 1'b0, cpa_pc_chg_enable, ar_pc_chg_flag, + 1'b0, cpa_arov_enable, ar_ov_flag, + cpa_pia }; + always @(posedge clk) begin if(mr_start) begin cpa_iot_user <= 0; @@ -2106,6 +2370,47 @@ module apr( cpa_arov_enable <= 0; cpa_pia <= 0; end + + if(cpa_cono_set & iob[21]) + cpa_iot_user <= 0; + if(cpa_cono_set & iob[20]) + cpa_iot_user <= 1; + + if(cpa_cono_set & iob[22]) + cpa_illeg_op <= 0; + if(mc_illeg_address) + cpa_illeg_op <= 1; + + if(cpa_cono_set & iob[23]) + cpa_non_exist_mem <= 0; + if(mc_non_exist_mem) + cpa_non_exist_mem <= 1; + + if(cpa_cono_set & iob[24]) + cpa_clock_enable <= 0; + if(cpa_cono_set & iob[25]) + cpa_clock_enable <= 1; + if(cpa_cono_set & iob[26]) + cpa_clock_flag <= 0; + if(cpa_clock_flag_set) + cpa_clock_flag <= 1; + + if(cpa_cono_set & iob[27]) + cpa_pc_chg_enable <= 0; + if(cpa_cono_set & iob[28]) + cpa_pc_chg_enable <= 1; + if(cpa_cono_set & iob[18]) + cpa_pdl_ov <= 0; + if(et10 & mb_ar_swap_et10 & ar_cry0) + cpa_pdl_ov <= 1; + + if(cpa_cono_set & iob[30]) + cpa_arov_enable <= 0; + if(cpa_cono_set & iob[31]) + cpa_arov_enable <= 1; + + if(cpa_cono_set) + cpa_pia <= iob[33:35]; end endmodule diff --git a/verilog/modules.v b/verilog/modules.v index 5e7fb3c..29b89a7 100644 --- a/verilog/modules.v +++ b/verilog/modules.v @@ -83,6 +83,21 @@ module dly50ns(input clk, input reset, input in, output p); assign p = r == 7; endmodule +module dly70ns(input clk, input reset, input in, output p); + reg [3:0] r; + always @(posedge clk or posedge reset) begin + if(reset) + r <= 0; + else begin + if(r) + r <= r + 1; + if(in) + r <= 1; + end + end + assign p = r == 9; +endmodule + module dly100ns(input clk, input reset, input in, output p); reg [3:0] r; always @(posedge clk or posedge reset) begin @@ -188,6 +203,75 @@ module dly1us(input clk, input reset, input in, output p); assign p = r == 102; endmodule +module ldly1us(input clk, input reset, input in, output p, output l); + reg [6:0] r; + reg l; + always @(posedge clk or posedge reset) begin + if(reset) begin + l <= 0; + r <= 0; + end else begin + if(r) + r <= r + 1; + if(in) begin + l <= 1; + r <= 1; + end + if(r == 101) begin + l <= 0; + //r <= 0; + end + end + end + assign p = r == 102; +endmodule + +module ldly1_5us(input clk, input reset, input in, output p, output l); + reg [7:0] r; + reg l; + always @(posedge clk or posedge reset) begin + if(reset) begin + l <= 0; + r <= 0; + end else begin + if(r) + r <= r + 1; + if(in) begin + l <= 1; + r <= 1; + end + if(r == 151) begin + l <= 0; + //r <= 0; + end + end + end + assign p = r == 152; +endmodule + +module ldly2us(input clk, input reset, input in, output p, output l); + reg [7:0] r; + reg l; + always @(posedge clk or posedge reset) begin + if(reset) begin + l <= 0; + r <= 0; + end else begin + if(r) + r <= r + 1; + if(in) begin + l <= 1; + r <= 1; + end + if(r == 201) begin + l <= 0; + //r <= 0; + end + end + end + assign p = r == 202; +endmodule + module dly100us(input clk, input reset, input in, output p); reg [15:0] r; always @(posedge clk or posedge reset) begin diff --git a/verilog/test.gtkw b/verilog/test.gtkw index 282a3f7..c8c101b 100644 --- a/verilog/test.gtkw +++ b/verilog/test.gtkw @@ -1,15 +1,15 @@ [*] [*] GTKWave Analyzer v3.3.76 (w)1999-2016 BSI -[*] Wed Nov 16 16:03:38 2016 +[*] Sun Nov 20 23:19:44 2016 [*] [dumpfile] "/home/aap/src/pdp6/verilog/dump.vcd" -[dumpfile_mtime] "Wed Nov 16 16:02:55 2016" -[dumpfile_size] 275421 +[dumpfile_mtime] "Sun Nov 20 15:05:49 2016" +[dumpfile_size] 137687 [savefile] "/home/aap/src/pdp6/verilog/test.gtkw" -[timestart] 5380 +[timestart] 4220 [size] 1920 1080 [pos] -1 -1 -*-11.385187 13535 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +*-7.832355 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 [treeopen] test. [treeopen] test.pdp6. [treeopen] test.pdp6.mem0. @@ -129,11 +129,14 @@ test.pdp6.apr0.mc_illeg_address test.pdp6.apr0.mc_membus_fm_mb1 @200 - -@30 -test.pdp6.apr0.rlr[18:25] -test.pdp6.apr0.rla[18:25] -test.pdp6.apr0.pr[18:25] @28 +test.pdp6.apr0.ex_clr +test.pdp6.apr0.ex_set +test.pdp6.apr0.rlr[18:25] +@30 +test.pdp6.apr0.rla[18:25] +@28 +test.pdp6.apr0.pr[18:25] test.pdp6.apr0.pr18_ok @200 - @@ -147,7 +150,7 @@ test.pdp6.apr0.mc_split_cyc_sync test.pdp6.apr0.mc_mb_membus_enable @1401200 -MC -@c00201 +@c00200 -I A @28 test.pdp6.apr0.it0 @@ -164,7 +167,7 @@ test.pdp6.apr0.at3a test.pdp6.apr0.af3a test.pdp6.apr0.at4 test.pdp6.apr0.at5 -@1401201 +@1401200 -I A @c00200 -F @@ -191,7 +194,7 @@ test.pdp6.apr0.ft6a test.pdp6.apr0.ft7 @1401200 -F -@800200 +@c00200 -E @28 test.pdp6.apr0.et0a @@ -205,9 +208,9 @@ test.pdp6.apr0.et7 test.pdp6.apr0.et8 test.pdp6.apr0.et9 test.pdp6.apr0.et10 -@1000200 +@1401200 -E -@800200 +@c00200 -S @28 test.pdp6.apr0.s_ac_0 @@ -224,7 +227,7 @@ test.pdp6.apr0.st5a test.pdp6.apr0.st6 test.pdp6.apr0.sf7 test.pdp6.apr0.st7 -@1000200 +@1401200 -S @c00200 -iobus @@ -343,9 +346,48 @@ test.pdp6.apr0.pi_req[1:7] test.pdp6.apr0.pih[1:7] test.pdp6.apr0.pir[1:7] test.pdp6.apr0.pio[1:7] +test.pdp6.apr0.pi_select +@30 +test.pdp6.apr0.pi_iob[0:35] +@28 test.pdp6.apr0.iob_pi_req[1:7] @1401200 -PI +@c00200 +-IOT +@28 +test.pdp6.apr0.iot_go +test.pdp6.apr0.iot_go_P +@200 +- +@28 +test.pdp6.apr0.iot_t0 +test.pdp6.apr0.iot_f0a +test.pdp6.apr0.iot_t0a +test.pdp6.apr0.iot_init_setup +test.pdp6.apr0.iot_t2 +test.pdp6.apr0.iot_final_setup +test.pdp6.apr0.iot_drive +test.pdp6.apr0.iot_t3a +test.pdp6.apr0.iot_reset +test.pdp6.apr0.iot_t4 +test.pdp6.apr0.iot_t3 +test.pdp6.apr0.iot_restart +@200 +- +@28 +test.pdp6.apr0.iot_blki +test.pdp6.apr0.iot_datai +test.pdp6.apr0.iot_blko +test.pdp6.apr0.iot_datao +test.pdp6.apr0.iot_coni +test.pdp6.apr0.iot_cono +test.pdp6.apr0.iot_consz +test.pdp6.apr0.iot_conso +@1401200 +-IOT +@800200 +-misc @28 test.pdp6.apr0.ar_com_cont test.pdp6.apr0.ar_add @@ -365,5 +407,35 @@ test.pdp6.apr0.pc_inc_et9 test.pdp6.apr0.pc_inc_inh_et0 test.pdp6.apr0.pc_set_OR_pc_inc test.pdp6.apr0.pc_set_enable +@1000200 +-misc +@c00200 +-cpa +@28 +test.pdp6.apr0.cpa +test.pdp6.apr0.cpa_cono_set +test.pdp6.apr0.cpa_status +@200 +- +@28 +test.pdp6.apr0.cpa_iot_user +test.pdp6.apr0.cpa_illeg_op +test.pdp6.apr0.cpa_non_exist_mem +test.pdp6.apr0.cpa_clock_enable +test.pdp6.apr0.cpa_clock_flag +test.pdp6.apr0.cpa_pc_chg_enable +test.pdp6.apr0.cpa_pdl_ov +test.pdp6.apr0.cpa_arov_enable +test.pdp6.apr0.cpa_pia[33:35] +@30 +test.pdp6.apr0.cpa_iob[0:35] +@200 +- +@28 +test.pdp6.apr0.iob_pi_req[1:7] +test.pdp6.apr0.iobus_pi_req[1:7] +test.pdp6.apr0.cpa_req[1:7] +@1401200 +-cpa [pattern_trace] 1 [pattern_trace] 0 diff --git a/verilog/test.v b/verilog/test.v index fda35b5..02572a1 100644 --- a/verilog/test.v +++ b/verilog/test.v @@ -18,17 +18,31 @@ endmodule module test; wire clk; reg reset; + reg stop; clock clock0(clk); pdp6 pdp6(.clk(clk), .reset(reset)); initial begin -// #110000 $finish; - #20000 $finish; + stop = 0; +// #110000 stop = 1; + #20000 stop = 1; end always @(pdp6.apr0.st7) if(pdp6.apr0.st7) + stop = 1; + + // dump memory on exit + always @(stop) + if(stop) begin: fin + integer i; + for(i = 0; i < 'o50; i = i + 1) + if(i < 'o20) + $display("%o %o %o", i, pdp6.mem0.core[i], pdp6.fmem0.ff[i]); + else + $display("%o %o", i, pdp6.mem0.core[i]); $finish; + end initial begin #100 `TESTKEY = 1; @@ -43,15 +57,38 @@ module test; initial begin #400; - pdp6.apr0.cpa_pia = 5; -/* - pdp6.apr0.pio = 7'b1111111; +// pdp6.apr0.cpa_pia = 5; + pdp6.apr0.pio = 7'b1111100; + pdp6.apr0.pir = 7'b0000000; pdp6.apr0.pih = 7'b0000100; + #10; pdp6.apr0.pi_active = 1; -*/ end -// assign pdp6.apr0.iobus_pi_req = 0; - assign pdp6.apr0.iobus_pi_req = 7'b0010000; +// assign pdp6.apr0.iobus_pi_req = 7'b0010000; + assign pdp6.apr0.iobus_pi_req = 0; + +/* + initial begin + #300; + pdp6.apr0.cpa_iot_user <= 1; + #20; + pdp6.apr0.cpa_illeg_op <= 1; + #20; + pdp6.apr0.cpa_non_exist_mem <= 1; + #20; + pdp6.apr0.cpa_clock_enable <= 1; + #20; + pdp6.apr0.cpa_clock_flag <= 1; + #20; + pdp6.apr0.cpa_pc_chg_enable <= 1; + #20; + pdp6.apr0.cpa_pdl_ov <= 1; + #20; + pdp6.apr0.cpa_arov_enable <= 1; + #20; + pdp6.apr0.cpa_pia <= 7; + end +*/ /* initial begin #100; @@ -110,43 +147,53 @@ module test; end +/* initial begin #80 pdp6.apr0.pr = 8'o003; pdp6.apr0.rlr = 8'o002; //pdp6.apr0.ex_user = 1; end +*/ initial begin #1 reset = 1; #20 reset = 0; pdp6.datasw = 36'o111777222666; -// pdp6.mas = 18'o010100; -// pdp6.mas = 18'o000004; - pdp6.mas = 18'o000023; - //pdp6.mas = 18'o777777; + pdp6.mas = 18'o000034; pdp6.fmem0.ff['o0] = 36'o000000_010000; - pdp6.fmem0.ff['o1] = 36'o000000_000222; - pdp6.fmem0.ff['o2] = 36'o700000_000006; + pdp6.fmem0.ff['o1] = 36'o000000_010222; + pdp6.fmem0.ff['o2] = 36'o700000_200006; pdp6.fmem0.ff['o3] = 36'o500000_000004; pdp6.fmem0.ff['o4] = 36'o000000_010304; pdp6.fmem0.ff['o5] = 36'o377777_777777; - // MOVE 1,@104(4) FAC_INH - pdp6.mem0.core['o20] = 36'o200_064_000104; - // MOVEM 1,@104(4) - pdp6.mem0.core['o21] = 36'o202_064_000104; - // ROTC 2,3 - pdp6.mem0.core['o22] = 36'o245_100_000003; + pdp6.fmem0.ff['o6] = 36'o444000_222000; + pdp6.fmem0.ff['o17] = 36'o777000_001000; // PDL ptr +// pdp6.fmem0.ff['o17] = 36'o777000_777777; // PDL ptr + pdp6.mem0.core['o20] = 36'o200_064_000104; // MOVE 1,@104(4) FAC_INH + pdp6.mem0.core['o21] = 36'o202_064_000104; // MOVEM 1,@104(4) + pdp6.mem0.core['o22] = 36'o245_100_000003; // ROTC 2,3 + pdp6.mem0.core['o23] = 36'o700200_675550; // CONO APR,675550 + pdp6.mem0.core['o24] = 36'o700200_102227; // CONO APR,102227 + pdp6.mem0.core['o25] = 36'o700240_000005; // CONI APR,5 + pdp6.mem0.core['o26] = 36'o700140_000006; // DATAO APR,6 + pdp6.mem0.core['o27] = 36'o700040_000005; // DATAI APR,5 + pdp6.mem0.core['o30] = 36'o700640_000005; // CONI APR,5 + pdp6.mem0.core['o31] = 36'o260740_000020; // PUSHJ 17,20 + pdp6.mem0.core['o31] = 36'o250040_000000; // AOS 1, + pdp6.mem0.core['o32] = 36'o270000_000001; // ADD 0,1 + pdp6.mem0.core['o33] = 36'o274000_000001; // SUB 0,1 - pdp6.mem0.core['o23] = 36'o700200_000005; + pdp6.mem0.core['o34] = 36'o245_100_000003; // ROTC 2,3 + pdp6.mem0.core['o35] = 36'o245_100_777775; // ROTC 2,-3 + pdp6.mem0.core['o36] = 36'o244_100_000001; // ASHC 2,1 pdp6.mem0.core['o10410] = 36'o000_000_000333; end initial begin #25 pdp6.sw_power = 1; - #25 pdp6.sw_power = 0; end endmodule