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32 lines
447 B
Verilog
32 lines
447 B
Verilog
module clock(clk, reset);
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output reg clk;
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output reg reset;
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initial begin
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clk = 0;
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reset = 0;
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#50 reset = 1;
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end
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always
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// #5 clk = ~clk;
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#10 clk = ~clk;
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endmodule
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module edgedet(clk, reset, signal, p);
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input wire clk;
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input wire reset;
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input wire signal;
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output wire p;
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reg last;
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always @(posedge clk or negedge reset) begin
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if(~reset)
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last <= 0;
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else
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last <= signal;
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end
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assign p = signal & ~last;
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endmodule
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