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69 lines
1.6 KiB
Verilog
69 lines
1.6 KiB
Verilog
module membus_2_connect(
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// unused
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input wire clk,
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input wire reset,
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// Master
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input wire m_wr_rs,
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input wire m_rq_cyc,
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input wire m_rd_rq,
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input wire m_wr_rq,
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input wire [21:35] m_ma,
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input wire [18:21] m_sel,
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input wire m_fmc_select,
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input wire [0:35] m_mb_write,
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output wire m_addr_ack,
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output wire m_rd_rs,
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output wire [0:35] m_mb_read,
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// Slave 0
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output wire s0_wr_rs,
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output wire s0_rq_cyc,
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output wire s0_rd_rq,
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output wire s0_wr_rq,
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output wire [21:35] s0_ma,
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output wire [18:21] s0_sel,
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output wire s0_fmc_select,
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output wire [0:35] s0_mb_write,
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input wire s0_addr_ack,
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input wire s0_rd_rs,
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input wire [0:35] s0_mb_read,
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// Slave 1
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output wire s1_wr_rs,
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output wire s1_rq_cyc,
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output wire s1_rd_rq,
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output wire s1_wr_rq,
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output wire [21:35] s1_ma,
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output wire [18:21] s1_sel,
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output wire s1_fmc_select,
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output wire [0:35] s1_mb_write,
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input wire s1_addr_ack,
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input wire s1_rd_rs,
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input wire [0:35] s1_mb_read
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);
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wire [0:35] mb_out = m_mb_write | s0_mb_read | s1_mb_read;
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assign m_addr_ack = s0_addr_ack | s1_addr_ack;
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assign m_rd_rs = s0_rd_rs | s1_rd_rs;
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assign m_mb_read = mb_out;
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assign s0_wr_rs = m_wr_rs;
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assign s0_rq_cyc = m_rq_cyc;
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assign s0_rd_rq = m_rd_rq;
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assign s0_wr_rq = m_wr_rq;
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assign s0_ma = m_ma;
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assign s0_sel = m_sel;
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assign s0_fmc_select = m_fmc_select;
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assign s0_mb_write = mb_out;
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assign s1_wr_rs = m_wr_rs;
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assign s1_rq_cyc = m_rq_cyc;
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assign s1_rd_rq = m_rd_rq;
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assign s1_wr_rq = m_wr_rq;
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assign s1_ma = m_ma;
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assign s1_sel = m_sel;
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assign s1_fmc_select = m_fmc_select;
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assign s1_mb_write = mb_out;
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endmodule
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