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81 lines
1.6 KiB
Verilog
81 lines
1.6 KiB
Verilog
module memif(
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input wire clk,
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input wire reset,
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// Avalon Slave
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input wire [1:0] s_address,
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input wire s_write,
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input wire s_read,
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input wire [31:0] s_writedata,
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output reg [31:0] s_readdata,
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output wire s_waitrequest,
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// 36 bit Avalon Master
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output wire [17:0] m_address,
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output reg m_write,
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output reg m_read,
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output wire [35:0] m_writedata,
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input wire [35:0] m_readdata,
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input wire m_waitrequest
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);
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reg [17:0] addr;
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reg [35:0] word;
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assign m_address = addr;
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assign m_writedata = word;
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wire write_edge, read_edge;
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edgedet e0(clk, reset, s_write, write_edge);
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edgedet e1(clk, reset, s_read, read_edge);
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reg waiting;
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wire req = (write_edge|read_edge) & s_address == 2'h2;
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assign s_waitrequest = req | waiting;
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always @(posedge clk or negedge reset) begin
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if(~reset) begin
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m_write <= 0;
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m_read <= 0;
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waiting <= 0;
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addr <= 0;
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word <= 0;
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end else begin
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if(write_edge) begin
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case(s_address)
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2'h0: addr <= s_writedata[17:0];
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2'h1: word[17:0] <= s_writedata[17:0];
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2'h2: word[35:18] <= s_writedata[17:0];
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endcase
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end
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if(req) begin
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waiting <= 1;
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if(s_write)
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m_write <= 1;
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else if(s_read)
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m_read <= 1;
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end
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if(m_write & ~m_waitrequest) begin
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m_write <= 0;
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waiting <= 0;
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end
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if(m_read & ~m_waitrequest) begin
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m_read <= 0;
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waiting <= 0;
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word <= m_readdata;
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end
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end
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end
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always @(*) begin
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case(s_address)
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2'h1: s_readdata <= { 14'b0, word[17:0] };
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2'h2: s_readdata <= { 14'b0, word[35:18] };
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default: s_readdata <= 32'b0;
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endcase
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end
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endmodule
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