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30 lines
697 B
Verilog
Executable File
30 lines
697 B
Verilog
Executable File
module memory_256k(
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input wire clk,
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input wire reset,
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// 36 bit Slave
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input wire [17:0] s_address,
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input wire s_write,
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input wire s_read,
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input wire [35:0] s_writedata,
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output wire [35:0] s_readdata,
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output wire s_waitrequest,
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// 64 bit Avalon Master
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output wire [31:0] m_address,
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output wire m_write,
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output wire m_read,
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output wire [63:0] m_writedata,
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input wire [63:0] m_readdata,
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input wire m_waitrequest
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);
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parameter [31:0] base_addr = 32'h30000000;
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assign m_address = base_addr | { s_address, 3'b0 };
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assign m_write = s_write;
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assign m_read = s_read;
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assign m_writedata = s_writedata;
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assign s_readdata = m_readdata;
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assign s_waitrequest = m_waitrequest;
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endmodule
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