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31 lines
630 B
Verilog
Executable File
31 lines
630 B
Verilog
Executable File
module onchip_ram
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#(parameter DATA_WIDTH=36, parameter ADDR_WIDTH=14)
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(
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input [(DATA_WIDTH-1):0] data,
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input [(ADDR_WIDTH-1):0] addr,
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input we, clk,
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output [(DATA_WIDTH-1):0] q
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);
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// Declare the RAM variable
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reg [DATA_WIDTH-1:0] ram[2**ADDR_WIDTH-1:0];
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// Variable to hold the registered read address
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reg [ADDR_WIDTH-1:0] addr_reg;
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always @ (posedge clk)
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begin
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// Write
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if (we)
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ram[addr] <= data;
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addr_reg <= addr;
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end
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// Continuous assignment implies read returns NEW data.
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// This is the natural behavior of the TriMatrix memory
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// blocks in Single Port mode.
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assign q = ram[addr_reg];
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endmodule
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