mirror of
https://github.com/aap/pdp6.git
synced 2026-03-07 03:36:03 +00:00
393 lines
8.6 KiB
Verilog
393 lines
8.6 KiB
Verilog
/*
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0 CTL1_DN
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1 CTL1_UP
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2 CTL2_DN
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3 CTL2_UP
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4 MAINT_DN
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5 MAINT_UP
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6 DS LT
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7 DS RT
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10 MAS
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11 REPEAT
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12 IR
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13 MI LT
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14 MI RT
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15 PC
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16 MA
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17 PI
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20 MB LT
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21 MB RT
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22 AR LT
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23 AR RT
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24 MQ LT
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25 MQ RT
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26 FF1
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27 FF2
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30 FF3
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31 FF4
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32 MMU
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33 TTY
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34 PTP
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35 PTR
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36 PTR B LT
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37 PTR B RT
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40 IO STATUS
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*/
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module panel_6(
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input wire clk,
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input wire reset,
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// Avalon Slave
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input wire [5:0] s_address,
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input wire s_write,
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input wire s_read,
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input wire [31:0] s_writedata,
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output reg [31:0] s_readdata,
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output wire s_waitrequest,
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/*
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* APR
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*/
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// keys
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output reg key_start,
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output reg key_read_in,
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output reg key_mem_cont,
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output reg key_inst_cont,
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output reg key_mem_stop,
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output reg key_inst_stop,
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output reg key_exec,
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output reg key_io_reset,
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output reg key_dep,
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output reg key_dep_nxt,
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output reg key_ex,
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output reg key_ex_nxt,
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// switches
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output reg sw_addr_stop,
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output reg sw_mem_disable,
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output reg sw_repeat,
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output reg sw_power,
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output reg [0:35] datasw,
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output reg [18:35] mas,
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// maintenance switches
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output reg sw_rim_maint,
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output reg sw_repeat_bypass,
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output reg sw_art3_maint,
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output reg sw_sct_maint,
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output reg sw_split_cyc,
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// lights
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input wire power,
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input wire [0:17] ir,
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input wire [0:35] mi,
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input wire [0:35] ar,
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input wire [0:35] mb,
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input wire [0:35] mq,
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input wire [18:35] pc,
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input wire [18:35] ma,
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input wire run,
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input wire mc_stop,
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input wire pi_active,
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input wire [1:7] pih,
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input wire [1:7] pir,
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input wire [1:7] pio,
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input wire [18:25] pr,
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input wire [18:25] rlr,
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input wire [18:25] rla,
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input wire [0:7] ff0,
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input wire [0:7] ff1,
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input wire [0:7] ff2,
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input wire [0:7] ff3,
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input wire [0:7] ff4,
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input wire [0:7] ff5,
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input wire [0:7] ff6,
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input wire [0:7] ff7,
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input wire [0:7] ff8,
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input wire [0:7] ff9,
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input wire [0:7] ff10,
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input wire [0:7] ff11,
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input wire [0:7] ff12,
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input wire [0:7] ff13,
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/*
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* TTY
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*/
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input wire [7:0] tty_tti,
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input wire [6:0] tty_status,
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/*
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* PTR
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*/
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output reg ptr_key_start,
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output reg ptr_key_stop,
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output reg ptr_key_tape_feed,
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input wire [35:0] ptr,
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input wire [6:0] ptr_status, // also includes motor on
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/*
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* PTP
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*/
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output reg ptp_key_tape_feed,
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input wire [7:0] ptp,
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input wire [6:0] ptp_status, // also includes motor on
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/*
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* 340 display
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*/
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input wire [0:17] dis_br,
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input wire [0:6] dis_brm,
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input wire [0:9] dis_x,
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input wire [0:9] dis_y,
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input wire [1:4] dis_s,
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input wire [0:2] dis_i,
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input wire [0:2] dis_mode,
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input wire [0:1] dis_sz,
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input wire [0:8] dis_flags,
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input wire [0:4] dis_fe,
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input wire [31:0] dis_foo,
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/*
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* External panel
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*/
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input wire [3:0] switches,
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input wire [7:0] ext,
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output reg [7:0] leds
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);
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wire ext_sw_power = switches[0];
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wire [7:0] apr_status = { 5'b0, mc_stop, run, power };
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always @(*) begin
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case(switches[3:1])
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3'b000: leds <= apr_status;
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3'b001: leds <= tty_tti;
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3'b010: leds <= tty_status;
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3'b011: leds <= ptr;
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3'b100: leds <= ptr_status;
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// 3'b101: leds <= ptp;
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// 3'b110: leds <= ptp_status;
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3'b101: leds <= dis_fe;
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3'b111: leds <= ext;
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default: leds <= 0;
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endcase
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end
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always @(*) begin
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case(s_address)
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6'o00: s_readdata <=
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{ 20'b0,
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power, mc_stop, run, sw_addr_stop,
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key_exec, key_io_reset, key_mem_stop, key_inst_stop,
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key_mem_cont, key_inst_cont, key_read_in, key_start
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};
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6'o01: s_readdata <= 0;
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6'o02: s_readdata <=
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{ 22'b0,
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sw_mem_disable, sw_repeat,
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ptr_key_tape_feed, ptp_key_tape_feed,
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ptr_key_start, ptr_key_stop,
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key_ex_nxt, key_ex, key_dep_nxt, key_dep
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};
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6'o03: s_readdata <= 0;
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6'o04: s_readdata <=
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{ 26'b0,
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sw_split_cyc, sw_sct_maint,
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sw_art3_maint, sw_repeat_bypass, sw_rim_maint,
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1'b0 // spare?
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};
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6'o05: s_readdata <= 0;
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6'o06: s_readdata <= { 14'b0, datasw[0:17] };
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6'o07: s_readdata <= { 14'b0, datasw[18:35] };
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6'o10: s_readdata <= { 14'b0, mas };
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6'o11: s_readdata <= 0; // TODO: repeat
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6'o12: s_readdata <= { 14'b0, ir };
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6'o13: s_readdata <= { 14'b0, mi[0:17] };
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6'o14: s_readdata <= { 14'b0, mi[18:35] };
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6'o15: s_readdata <= { 14'b0, pc };
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6'o16: s_readdata <= { 14'b0, ma };
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6'o17: s_readdata <= { 10'b0, pih, pir, pio, pi_active };
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6'o20: s_readdata <= { 14'b0, mb[0:17] };
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6'o21: s_readdata <= { 14'b0, mb[18:35] };
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6'o22: s_readdata <= { 14'b0, ar[0:17] };
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6'o23: s_readdata <= { 14'b0, ar[18:35] };
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6'o24: s_readdata <= { 14'b0, mq[0:17] };
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6'o25: s_readdata <= { 14'b0, mq[18:35] };
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6'o26: s_readdata <= { ff0, ff1, ff2, ff3 };
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6'o27: s_readdata <= { ff4, ff5, ff6, ff7 };
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6'o30: s_readdata <= { ff8, ff9, ff10, ff11 };
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6'o31: s_readdata <= { ff12, ff13, 16'b0 };
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6'o32: s_readdata <= { 8'b0, rla, rlr, pr };
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6'o33: s_readdata <= { tty_tti, 2'b0, tty_status };
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6'o34: s_readdata <= { ptp, 2'b0, ptp_status };
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6'o35: s_readdata <= ptr_status;
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6'o36: s_readdata <= ptr[35:18];
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6'o37: s_readdata <= ptr[17:0];
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6'o40: s_readdata <= dis_br;
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6'o41: s_readdata <= { dis_brm, dis_y, dis_x };
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6'o42: s_readdata <= { dis_flags, dis_s, dis_i,
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dis_sz, dis_mode };
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6'o43: s_readdata <= dis_foo;
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default: s_readdata <= 0;
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endcase
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end
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assign s_waitrequest = 0;
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always @(posedge clk or negedge reset) begin
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if(~reset) begin
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// keys
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key_start <= 0;
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key_read_in <= 0;
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key_mem_cont <= 0;
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key_inst_cont <= 0;
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key_mem_stop <= 0;
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key_inst_stop <= 0;
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key_exec <= 0;
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key_io_reset <= 0;
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key_dep <= 0;
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key_dep_nxt <= 0;
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key_ex <= 0;
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key_ex_nxt <= 0;
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ptr_key_start <= 0;
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ptr_key_stop <= 0;
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ptr_key_tape_feed <= 0;
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ptp_key_tape_feed <= 0;
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// switches
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sw_addr_stop <= 0;
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sw_mem_disable <= 0;
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sw_repeat <= 0;
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/**/ sw_power <= 0;
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datasw <= 0;
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mas <= 0;
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// maintenance switches
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sw_rim_maint <= 0;
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sw_repeat_bypass <= 0;
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sw_art3_maint <= 0;
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sw_sct_maint <= 0;
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sw_split_cyc <= 0;
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end else begin
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sw_power <= ext_sw_power;
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if(s_write) case(s_address)
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6'o00: begin
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if(s_writedata[0])
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{ key_read_in, key_start } <= 2'b01;
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if(s_writedata[1])
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{ key_read_in, key_start } <= 2'b10;
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if(s_writedata[2])
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{ key_mem_cont, key_inst_cont } <= 2'b01;
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if(s_writedata[3])
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{ key_mem_cont, key_inst_cont } <= 2'b10;
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if(s_writedata[4])
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{ key_mem_stop, key_inst_stop } <= 2'b01;
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if(s_writedata[5])
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{ key_mem_stop, key_inst_stop } <= 2'b10;
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if(s_writedata[6])
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{ key_exec, key_io_reset } <= 2'b01;
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if(s_writedata[7])
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{ key_exec, key_io_reset } <= 2'b10;
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if(s_writedata[8])
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sw_addr_stop <= 1;
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end
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6'o01: begin
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if(s_writedata[0] | s_writedata[1])
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{ key_read_in, key_start } <= 2'b00;
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if(s_writedata[2] | s_writedata[3])
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{ key_mem_cont, key_inst_cont } <= 2'b00;
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if(s_writedata[4] | s_writedata[5])
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{ key_mem_stop, key_inst_stop } <= 2'b00;
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if(s_writedata[6] |s_writedata[7])
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{ key_exec, key_io_reset } <= 2'b00;
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if(s_writedata[8])
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sw_addr_stop <= 0;
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end
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6'o02: begin
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if(s_writedata[0])
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{ key_dep_nxt, key_dep } <= 2'b01;
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if(s_writedata[1])
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{ key_dep_nxt, key_dep } <= 2'b10;
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if(s_writedata[2])
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{ key_ex_nxt, key_ex } <= 2'b01;
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if(s_writedata[3])
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{ key_ex_nxt, key_ex } <= 2'b10;
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if(s_writedata[4])
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{ ptr_key_start, ptr_key_stop } <= 2'b01;
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if(s_writedata[5])
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{ ptr_key_start, ptr_key_stop } <= 2'b10;
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if(s_writedata[6])
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{ ptp_key_tape_feed, ptr_key_tape_feed } <= 2'b10;
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if(s_writedata[7])
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{ ptp_key_tape_feed, ptr_key_tape_feed } <= 2'b01;
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if(s_writedata[8])
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sw_repeat <= 1;
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if(s_writedata[9])
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sw_mem_disable <= 1;
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end
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6'o03: begin
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if(s_writedata[0] | s_writedata[1])
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{ key_dep_nxt, key_dep } <= 2'b00;
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if(s_writedata[2] | s_writedata[3])
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{ key_ex_nxt, key_ex } <= 2'b00;
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if(s_writedata[4] | s_writedata[5])
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{ ptr_key_start, ptr_key_stop } <= 2'b00;
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if(s_writedata[6] | s_writedata[7])
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{ ptp_key_tape_feed, ptr_key_tape_feed } <= 2'b00;
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if(s_writedata[8])
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sw_repeat <= 0;
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if(s_writedata[9])
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sw_mem_disable <= 0;
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end
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6'o04: begin
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if(s_writedata[1])
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sw_rim_maint <= 1;
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if(s_writedata[2])
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sw_repeat_bypass <= 1;
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if(s_writedata[3])
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sw_art3_maint <= 1;
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if(s_writedata[4])
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sw_sct_maint <= 1;
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if(s_writedata[5])
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sw_split_cyc <= 1;
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end
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6'o05: begin
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if(s_writedata[1])
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sw_rim_maint <= 0;
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if(s_writedata[2])
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sw_repeat_bypass <= 0;
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if(s_writedata[3])
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sw_art3_maint <= 0;
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if(s_writedata[4])
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sw_sct_maint <= 0;
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if(s_writedata[5])
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sw_split_cyc <= 0;
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end
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6'o06: datasw[0:17] <= s_writedata;
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6'o07: datasw[18:35] <= s_writedata;
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6'o10: mas <= s_writedata;
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// TODO: 11 REPEAT
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endcase
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end
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end
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endmodule
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