mirror of
https://github.com/aap/pdp6.git
synced 2026-02-08 01:11:56 +00:00
14 lines
184 B
Verilog
14 lines
184 B
Verilog
module fe_req(
|
|
// unused
|
|
input wire clk,
|
|
input wire reset,
|
|
|
|
// requests
|
|
input wire [31:0] req,
|
|
|
|
// Avalon slave
|
|
output wire [31:0] readdata
|
|
);
|
|
assign readdata = req;
|
|
endmodule
|