mirror of
https://github.com/aap/pdp6.git
synced 2026-05-04 23:25:26 +00:00
300 lines
6.5 KiB
Verilog
300 lines
6.5 KiB
Verilog
`default_nettype none
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`timescale 1ns/1ns
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`define simulation
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module tb_apr();
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wire clk, reset;
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clock clock(clk, reset);
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// membus
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wire membus_rq_cyc;
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wire membus_rd_rq;
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wire membus_wr_rq;
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wire [21:35] membus_ma;
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wire [18:21] membus_sel;
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wire membus_fmc_select;
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wire [0:35] membus_mb_write;
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wire membus_wr_rs;
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wire [0:35] membus_mb_read = membus_mb_write | membus_mb_read_0 | membus_mb_read_1;
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wire membus_addr_ack = membus_addr_ack_0 | membus_addr_ack_1;
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wire membus_rd_rs = membus_rd_rs_0 | membus_rd_rs_1;
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// iobus
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wire iobus_iob_poweron;
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wire iobus_iob_reset;
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wire iobus_datao_clear;
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wire iobus_datao_set;
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wire iobus_cono_clear;
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wire iobus_cono_set;
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wire iobus_iob_fm_datai;
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wire iobus_iob_fm_status;
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wire [3:9] iobus_ios;
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wire [0:35] iobus_iob_in;
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wire [1:7] iobus_pi_req = 0;
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wire [0:35] iobus_iob_out = 0;
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reg key_start = 0;
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reg key_read_in = 0;
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reg key_mem_cont = 0;
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reg key_inst_cont = 0;
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reg key_mem_stop = 0;
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reg key_inst_stop = 0;
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reg key_exec = 0;
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reg key_io_reset = 0;
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reg key_dep = 0;
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reg key_dep_nxt = 0;
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reg key_ex = 0;
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reg key_ex_nxt = 0;
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reg sw_addr_stop = 0;
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reg sw_mem_disable = 0;
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reg sw_repeat = 0;
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reg sw_power = 0;
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reg [0:35] datasw = 0;
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reg [18:35] mas = 0;
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reg sw_rim_maint = 0;
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reg sw_repeat_bypass = 0;
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reg sw_art3_maint = 0;
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reg sw_sct_maint = 0;
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reg sw_split_cyc = 0;
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apr apr(
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.clk(clk),
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.reset(~reset),
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.key_start(key_start),
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.key_read_in(key_read_in),
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.key_mem_cont(key_mem_cont),
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.key_inst_cont(key_inst_cont),
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.key_mem_stop(key_mem_stop),
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.key_inst_stop(key_inst_stop),
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.key_exec(key_exec),
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.key_io_reset(key_io_reset),
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.key_dep(key_dep),
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.key_dep_nxt(key_dep_nxt),
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.key_ex(key_ex),
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.key_ex_nxt(key_ex_nxt),
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.sw_addr_stop(sw_addr_stop),
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.sw_mem_disable(sw_mem_disable),
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.sw_repeat(sw_repeat),
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.sw_power(sw_power),
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.datasw(datasw),
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.mas(mas),
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.sw_rim_maint(sw_rim_maint),
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.sw_repeat_bypass(sw_repeat_bypass),
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.sw_art3_maint(sw_art3_maint),
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.sw_sct_maint(sw_sct_maint),
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.sw_split_cyc(sw_split_cyc),
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.membus_wr_rs(membus_wr_rs),
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.membus_rq_cyc(membus_rq_cyc),
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.membus_rd_rq(membus_rd_rq),
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.membus_wr_rq(membus_wr_rq),
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.membus_ma(membus_ma),
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.membus_sel(membus_sel),
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.membus_fmc_select(membus_fmc_select),
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.membus_mb_out(membus_mb_write),
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.membus_addr_ack(membus_addr_ack),
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.membus_rd_rs(membus_rd_rs),
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.membus_mb_in(membus_mb_read),
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.iobus_pi_req(iobus_pi_req),
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.iobus_iob_in(iobus_iob_in)
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);
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wire [17:0] av_address;
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wire av_write;
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wire av_read;
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wire [35:0] av_writedata;
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wire [35:0] av_readdata;
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wire av_waitrequest;
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memory_32k mem(
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.i_clk(clk),
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.i_reset_n(reset),
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.i_address(av_address),
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.i_write(av_write),
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.i_read(av_read),
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.i_writedata(av_writedata),
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.o_readdata(av_readdata),
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.o_waitrequest(av_waitrequest)
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);
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wire [0:35] membus_mb_read_0;
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wire membus_addr_ack_0;
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wire membus_rd_rs_0;
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core32k cmem(
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.clk(clk),
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.reset(~reset),
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.power(1'b1),
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.sw_single_step(1'b0),
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.sw_restart(1'b0),
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.membus_rq_cyc_p0(membus_rq_cyc),
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.membus_rd_rq_p0(membus_rd_rq),
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.membus_wr_rq_p0(membus_wr_rq),
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.membus_ma_p0(membus_ma),
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.membus_sel_p0(membus_sel),
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.membus_fmc_select_p0(membus_fmc_select),
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.membus_mb_in_p0(membus_mb_write),
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.membus_wr_rs_p0(membus_wr_rs),
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.membus_mb_out_p0(membus_mb_read_0),
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.membus_addr_ack_p0(membus_addr_ack_0),
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.membus_rd_rs_p0(membus_rd_rs_0),
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.membus_wr_rs_p1(1'b0),
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.membus_rq_cyc_p1(1'b0),
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.membus_rd_rq_p1(1'b0),
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.membus_wr_rq_p1(1'b0),
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.membus_ma_p1(15'b0),
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.membus_sel_p1(4'b0),
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.membus_fmc_select_p1(1'b0),
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.membus_mb_in_p1(36'b0),
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.membus_wr_rs_p2(1'b0),
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.membus_rq_cyc_p2(1'b0),
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.membus_rd_rq_p2(1'b0),
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.membus_wr_rq_p2(1'b0),
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.membus_ma_p2(15'b0),
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.membus_sel_p2(4'b0),
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.membus_fmc_select_p2(1'b0),
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.membus_mb_in_p2(36'b0),
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.membus_wr_rs_p3(1'b0),
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.membus_rq_cyc_p3(1'b0),
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.membus_rd_rq_p3(1'b0),
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.membus_wr_rq_p3(1'b0),
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.membus_ma_p3(15'b0),
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.membus_sel_p3(4'b0),
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.membus_fmc_select_p3(1'b0),
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.membus_mb_in_p3(36'b0),
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.m_address(av_address),
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.m_write(av_write),
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.m_read(av_read),
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.m_writedata(av_writedata),
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.m_readdata(av_readdata),
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.m_waitrequest(av_waitrequest)
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);
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wire [0:35] membus_mb_read_1;
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wire membus_addr_ack_1;
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wire membus_rd_rs_1;
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fast162 fmem(
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.clk(clk),
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.reset(~reset),
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.power(1'b1),
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.sw_single_step(1'b0),
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.sw_restart(1'b0),
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.membus_rq_cyc_p0(membus_rq_cyc),
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.membus_rd_rq_p0(membus_rd_rq),
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.membus_wr_rq_p0(membus_wr_rq),
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.membus_ma_p0(membus_ma),
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.membus_sel_p0(membus_sel),
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.membus_fmc_select_p0(membus_fmc_select),
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.membus_mb_in_p0(membus_mb_write),
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.membus_wr_rs_p0(membus_wr_rs),
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.membus_mb_out_p0(membus_mb_read_1),
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.membus_addr_ack_p0(membus_addr_ack_1),
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.membus_rd_rs_p0(membus_rd_rs_1),
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.membus_wr_rs_p1(1'b0),
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.membus_rq_cyc_p1(1'b0),
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.membus_rd_rq_p1(1'b0),
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.membus_wr_rq_p1(1'b0),
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.membus_ma_p1(15'b0),
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.membus_sel_p1(4'b0),
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.membus_fmc_select_p1(1'b0),
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.membus_mb_in_p1(36'b0),
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.membus_wr_rs_p2(1'b0),
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.membus_rq_cyc_p2(1'b0),
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.membus_rd_rq_p2(1'b0),
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.membus_wr_rq_p2(1'b0),
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.membus_ma_p2(15'b0),
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.membus_sel_p2(4'b0),
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.membus_fmc_select_p2(1'b0),
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.membus_mb_in_p2(36'b0),
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.membus_wr_rs_p3(1'b0),
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.membus_rq_cyc_p3(1'b0),
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.membus_rd_rq_p3(1'b0),
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.membus_wr_rq_p3(1'b0),
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.membus_ma_p3(15'b0),
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.membus_sel_p3(4'b0),
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.membus_fmc_select_p3(1'b0),
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.membus_mb_in_p3(36'b0)
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);
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initial begin: init
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integer i;
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$dumpfile("dump.vcd");
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$dumpvars();
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for(i = 0; i < 'o40000; i = i + 1)
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mem.ram.ram[i] <= 0;
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#10;
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mem.ram.ram['o42] <= 36'o334000_000000;
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mem.ram.ram['o43] <= 36'o000000_000000;
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mem.ram.ram['o44] <= 36'o334000_000000;
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mem.ram.ram['o45] <= 36'o000000_000000;
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mem.ram.ram['o46] <= 36'o334000_000000;
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mem.ram.ram['o47] <= 36'o000000_000000;
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mem.ram.ram['o50] <= 36'o334000_000000;
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mem.ram.ram['o51] <= 36'o000000_000000;
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mem.ram.ram['o52] <= 36'o334000_000000;
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mem.ram.ram['o53] <= 36'o000000_000000;
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mem.ram.ram['o100] <= 36'o202000001000;
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mem.ram.ram['o101] <= 36'o254200000000;
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mem.ram.ram['o1000] <= 36'o123321456654;
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fmem.ff[0] <= 36'o611042323251;
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fmem.ff[1] <= 36'o472340710317;
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fmem.ff[2] <= 36'o545777777776;
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mas <= 'o100;
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#200;
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sw_power <= 1;
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#200;
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// key_mem_stop <= 1;
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key_start <= 1;
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#1000;
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key_start <= 0;
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/*
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#500;
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key_mem_stop <= 0;
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key_inst_stop <= 1;
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#1000;
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key_inst_stop <= 0;
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#1000;
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key_inst_cont <= 1;
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#500;
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key_inst_cont <= 0;
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*/
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end
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initial begin
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#50000;
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$finish;
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end
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endmodule
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