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101 lines
2.1 KiB
Verilog
101 lines
2.1 KiB
Verilog
module fakeapr(
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input wire clk,
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input wire reset,
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// keys
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input wire key_start,
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input wire key_read_in,
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input wire key_mem_cont,
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input wire key_inst_cont,
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input wire key_mem_stop,
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input wire key_inst_stop,
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input wire key_exec,
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input wire key_io_reset,
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input wire key_dep,
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input wire key_dep_nxt,
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input wire key_ex,
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input wire key_ex_nxt,
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// switches
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input wire sw_addr_stop,
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input wire sw_mem_disable,
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input wire sw_repeat,
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input wire sw_power,
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input wire [0:35] datasw,
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input wire [18:35] mas,
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// maintenance switches
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input wire sw_rim_maint,
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input wire sw_repeat_bypass,
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input wire sw_art3_maint,
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input wire sw_sct_maint,
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input wire sw_split_cyc,
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// lights
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output wire power,
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output wire [0:17] ir,
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output wire [0:35] mi,
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output wire [0:35] ar,
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output wire [0:35] mb,
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output wire [0:35] mq,
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output wire [18:35] pc,
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output wire [18:35] ma,
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output wire run,
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output wire mc_stop,
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output wire pi_active,
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output wire [1:7] pih,
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output wire [1:7] pir,
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output wire [1:7] pio,
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output wire [18:25] pr,
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output wire [18:25] rlr,
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output wire [18:25] rla,
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output wire [0:7] ff0,
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output wire [0:7] ff1,
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output wire [0:7] ff2,
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output wire [0:7] ff3,
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output wire [0:7] ff4,
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output wire [0:7] ff5,
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output wire [0:7] ff6,
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output wire [0:7] ff7,
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output wire [0:7] ff8,
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output wire [0:7] ff9,
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output wire [0:7] ff10,
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output wire [0:7] ff11,
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output wire [0:7] ff12,
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output wire [0:7] ff13
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);
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assign power = sw_power;
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assign ir = 18'o111111;
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assign mi = 36'o222222333333;
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assign ar = 36'o444444555555;
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assign mb = 36'o666666777777;
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assign mq = 36'o101010202020;
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assign pc = 18'o303030;
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assign ma = 18'o404040;
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assign run = datasw[35];
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assign mc_stop = datasw[34];
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assign pi_active = 0;
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assign pih = 7'o123;
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assign pir = 7'o134;
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assign pio = 7'o145;
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assign pr = 8'o352;
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assign rlr = 8'o333;
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assign rla = 8'o222;
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assign ff0 = 8'o201;
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assign ff1 = 8'o202;
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assign ff2 = 8'o203;
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assign ff3 = 8'o204;
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assign ff4 = 8'o205;
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assign ff5 = 8'o206;
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assign ff6 = 8'o207;
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assign ff7 = 8'o210;
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assign ff8 = 8'o211;
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assign ff9 = 8'o212;
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assign ff10 = 8'o213;
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assign ff11 = 8'o214;
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assign ff12 = 8'o215;
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assign ff13 = 8'o216;
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endmodule
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