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234 lines
7.0 KiB
Verilog
234 lines
7.0 KiB
Verilog
module fast162(
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input wire clk,
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input wire reset,
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input wire power,
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input wire sw_single_step,
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input wire sw_restart,
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input wire membus_wr_rs_p0,
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input wire membus_rq_cyc_p0,
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input wire membus_rd_rq_p0,
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input wire membus_wr_rq_p0,
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input wire [21:35] membus_ma_p0,
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input wire [18:21] membus_sel_p0,
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input wire membus_fmc_select_p0,
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input wire [0:35] membus_mb_in_p0,
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output wire membus_addr_ack_p0,
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output wire membus_rd_rs_p0,
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output wire [0:35] membus_mb_out_p0,
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input wire membus_wr_rs_p1,
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input wire membus_rq_cyc_p1,
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input wire membus_rd_rq_p1,
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input wire membus_wr_rq_p1,
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input wire [21:35] membus_ma_p1,
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input wire [18:21] membus_sel_p1,
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input wire membus_fmc_select_p1,
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input wire [0:35] membus_mb_in_p1,
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output wire membus_addr_ack_p1,
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output wire membus_rd_rs_p1,
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output wire [0:35] membus_mb_out_p1,
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input wire membus_wr_rs_p2,
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input wire membus_rq_cyc_p2,
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input wire membus_rd_rq_p2,
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input wire membus_wr_rq_p2,
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input wire [21:35] membus_ma_p2,
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input wire [18:21] membus_sel_p2,
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input wire membus_fmc_select_p2,
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input wire [0:35] membus_mb_in_p2,
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output wire membus_addr_ack_p2,
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output wire membus_rd_rs_p2,
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output wire [0:35] membus_mb_out_p2,
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input wire membus_wr_rs_p3,
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input wire membus_rq_cyc_p3,
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input wire membus_rd_rq_p3,
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input wire membus_wr_rq_p3,
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input wire [21:35] membus_ma_p3,
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input wire [18:21] membus_sel_p3,
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input wire membus_fmc_select_p3,
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input wire [0:35] membus_mb_in_p3,
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output wire membus_addr_ack_p3,
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output wire membus_rd_rs_p3,
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output wire [0:35] membus_mb_out_p3
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);
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/* Jumpers */
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parameter memsel_p0 = 4'b0;
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parameter memsel_p1 = 4'b0;
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parameter memsel_p2 = 4'b0;
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parameter memsel_p3 = 4'b0;
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parameter fmc_p0_sel = 1'b1;
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parameter fmc_p1_sel = 1'b0;
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parameter fmc_p2_sel = 1'b0;
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parameter fmc_p3_sel = 1'b0;
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reg fmc_act;
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reg fmc_rd0;
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reg fmc_rs; // not used, what is this?
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reg fmc_stop;
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reg fmc_wr;
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wire [0:35] fm_out = (fma != 0 | fmc_rd0) ? ff[fma] : 0;
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reg [0:35] ff[0:16];
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wire wr_rs = fmc_p0_sel ? membus_wr_rs_p0 :
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fmc_p1_sel ? membus_wr_rs_p1 :
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fmc_p2_sel ? membus_wr_rs_p2 :
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fmc_p3_sel ? membus_wr_rs_p3 : 1'b0;
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wire fma_rd_rq = fmc_p0_sel ? membus_rd_rq_p0 :
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fmc_p1_sel ? membus_rd_rq_p1 :
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fmc_p2_sel ? membus_rd_rq_p2 :
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fmc_p3_sel ? membus_rd_rq_p3 : 1'b0;
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wire fma_wr_rq = fmc_p0_sel ? membus_wr_rq_p0 :
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fmc_p1_sel ? membus_wr_rq_p1 :
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fmc_p2_sel ? membus_wr_rq_p2 :
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fmc_p3_sel ? membus_wr_rq_p3 : 1'b0;
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wire [21:35] fma = fmc_p0_sel ? membus_ma_p0[32:35] :
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fmc_p1_sel ? membus_ma_p1[32:35] :
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fmc_p2_sel ? membus_ma_p2[32:35] :
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fmc_p3_sel ? membus_ma_p3[32:35] : 1'b0;
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wire [0:35] mb_in = fmc_p0_wr_sel ? membus_mb_in_p0 :
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fmc_p1_wr_sel ? membus_mb_in_p1 :
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fmc_p2_wr_sel ? membus_mb_in_p2 :
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fmc_p3_wr_sel ? membus_mb_in_p3 : 1'b0;
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assign membus_addr_ack_p0 = fmc_addr_ack & fmc_p0_sel;
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assign membus_rd_rs_p0 = fmc_rd_rs & fmc_p0_sel;
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assign membus_mb_out_p0 = fmc_p0_sel ? mb_out : 1'b0;
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assign membus_addr_ack_p1 = fmc_addr_ack & fmc_p1_sel;
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assign membus_rd_rs_p1 = fmc_rd_rs & fmc_p1_sel;
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assign membus_mb_out_p1 = fmc_p1_sel ? mb_out : 1'b0;
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assign membus_addr_ack_p2 = fmc_addr_ack & fmc_p2_sel;
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assign membus_rd_rs_p2 = fmc_rd_rs & fmc_p2_sel;
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assign membus_mb_out_p2 = fmc_p2_sel ? mb_out : 1'b0;
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assign membus_addr_ack_p3 = fmc_addr_ack & fmc_p3_sel;
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assign membus_rd_rs_p3 = fmc_rd_rs & fmc_p3_sel;
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assign membus_mb_out_p3 = fmc_p3_sel ? mb_out : 1'b0;
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wire fmc_addr_ack;
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wire fmc_rd_rs;
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wire [0:35] mb_out = fmc_rd_strb ? fm_out : 36'b0;
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wire fmc_p0_sel1 = fmc_p0_sel & ~fmc_stop;
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wire fmc_p1_sel1 = fmc_p1_sel & ~fmc_stop;
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wire fmc_p2_sel1 = fmc_p2_sel & ~fmc_stop;
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wire fmc_p3_sel1 = fmc_p3_sel & ~fmc_stop;
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wire fmc_p0_wr_sel = fmc_p0_sel & fmc_act & ~fma_rd_rq;
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wire fmc_p1_wr_sel = fmc_p1_sel & fmc_act & ~fma_rd_rq;
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wire fmc_p2_wr_sel = fmc_p2_sel & fmc_act & ~fma_rd_rq;
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wire fmc_p3_wr_sel = fmc_p3_sel & fmc_act & ~fma_rd_rq;
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wire fmpc_p0_rq = fmc_p0_sel1 & memsel_p0 == membus_sel_p0 &
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membus_fmc_select_p0 & membus_rq_cyc_p0;
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wire fmpc_p1_rq = fmc_p1_sel1 & memsel_p1 == membus_sel_p1 &
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membus_fmc_select_p1 & membus_rq_cyc_p1;
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wire fmpc_p2_rq = fmc_p2_sel1 & memsel_p2 == membus_sel_p2 &
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membus_fmc_select_p2 & membus_rq_cyc_p2;
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wire fmpc_p3_rq = fmc_p3_sel1 & memsel_p3 == membus_sel_p3 &
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membus_fmc_select_p3 & membus_rq_cyc_p3;
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wire fmc_pwr_on;
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wire fmc_restart;
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wire fmc_start;
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wire fmc_rd_strb;
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wire fmct0;
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wire fmct1;
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wire fmct3;
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wire fmct4;
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wire fmct5;
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wire fm_clr;
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wire fmc_wr_set;
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wire fmc_wr_rs;
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wire fma_rd_rq_P, fma_rd_rq_D, fmc_rd0_set;
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wire fmct1_D, fmct3_D;
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wire mb_pulse_in;
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pg fmc_pg0(.clk(clk), .reset(reset), .in(power), .p(fmc_pwr_on));
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pg fmc_pg1(.clk(clk), .reset(reset), .in(sw_restart & fmc_stop),
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.p(fmc_restart));
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pg fmc_pg2(.clk(clk), .reset(reset), .in(fmc_act), .p(fmct0));
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pg fmc_pg3(.clk(clk), .reset(reset), .in(fma_rd_rq), .p(fma_rd_rq_P));
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pg cmc_pg4(.clk(clk), .reset(reset), .in(| mb_in), .p(mb_pulse_in));
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pg cmc_pg5(.clk(clk), .reset(reset), .in(wr_rs), .p(fmc_wr_rs));
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pa fmc_pa0(.clk(clk), .reset(reset),
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.in(fmc_start | fmct4 & ~fmc_stop),
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.p(fmct5));
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pa fmc_pa1(.clk(clk), .reset(reset),
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.in(fmct0 & fma_rd_rq),
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.p(fmct1));
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pa fmc_pa2(.clk(clk), .reset(reset),
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.in(fma_rd_rq_D),
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.p(fmc_rd0_set));
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pa fmc_pa3(.clk(clk), .reset(reset),
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.in(fmct3),
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.p(fm_clr));
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pa fmc_pa4(.clk(clk), .reset(reset),
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.in(fmct3_D),
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.p(fmc_wr_set));
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pg fmc_pg5(.clk(clk), .reset(reset),
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.in(fmct0 & ~fma_rd_rq & fma_wr_rq |
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fmct1_D & fma_wr_rq),
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.p(fmct3));
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pa fmc_pa6(.clk(clk), .reset(reset),
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.in(fmct1_D & ~fma_wr_rq | fmc_wr_rs),
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.p(fmct4));
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dly200ns fmc_dly0(.clk(clk), .reset(reset),
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.in(fmc_restart | fmc_pwr_on),
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.p(fmc_start));
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dly50ns fmc_dly1(.clk(clk), .reset(reset),
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.in(fma_rd_rq_P),
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.p(fma_rd_rq_D));
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dly100ns fmc_dly3(.clk(clk), .reset(reset),
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.in(fmct1),
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.p(fmct1_D));
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dly50ns fmc_dly4(.clk(clk), .reset(reset),
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.in(fmct3),
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.p(fmct3_D));
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bd fmc_bd0(.clk(clk), .reset(reset), .in(fmct0), .p(fmc_addr_ack));
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bd fmc_bd1(.clk(clk), .reset(reset), .in(fmct1), .p(fmc_rd_rs));
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bd2 fmc_bd2(.clk(clk), .reset(reset), .in(fmct1), .p(fmc_rd_strb));
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`ifdef simulation
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always @(posedge reset) begin
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fmc_act <= 0;
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end
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`endif
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always @(posedge clk) begin
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if(fmc_restart | fmc_pwr_on) begin
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fmc_act <= 0;
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fmc_stop <= 1;
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end
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if(fmpc_p0_rq | fmpc_p1_rq | fmpc_p2_rq | fmpc_p3_rq)
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fmc_act <= 1;
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if(fmc_wr_rs)
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fmc_rs <= 1;
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if(~fma_rd_rq)
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fmc_rd0 <= 0;
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if(fmc_rd0_set)
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fmc_rd0 <= 1;
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if(fmc_wr_set)
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fmc_wr <= 1;
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if(fm_clr)
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ff[fma] <= 0;
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if(mb_pulse_in & fmc_wr)
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ff[fma] <= ff[fma] | mb_in;
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if(fmct0) begin
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fmc_rs <= 0;
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fmc_stop <= sw_single_step;
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end
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if(fmct4) begin
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fmc_act <= 0;
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fmc_rd0 <= 0;
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end
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if(fmct5) begin
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fmc_stop <= 0;
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fmc_wr <= 0;
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end
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end
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endmodule
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