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https://github.com/aap/pdp6.git
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155 lines
2.6 KiB
Verilog
155 lines
2.6 KiB
Verilog
`default_nettype none
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`timescale 1ns/1ns
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`define simulation
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module tb_ptr();
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wire clk, reset;
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clock clock(clk, reset);
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reg write = 0;
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reg [31:0] writedata = 0;
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reg iobus_iob_poweron = 1;
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reg iobus_iob_reset = 0;
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reg iobus_datao_clear = 0;
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reg iobus_datao_set = 0;
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reg iobus_cono_clear = 0;
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reg iobus_cono_set = 0;
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reg iobus_iob_fm_datai = 0;
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reg iobus_iob_fm_status = 0;
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reg [3:9] iobus_ios = 0;
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reg [0:35] iobus_iob_in = 0;
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wire [1:7] iobus_pi_req;
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wire [0:35] iobus_iob_out;
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reg key_start = 0;
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reg key_stop = 0;
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reg key_tape_feed = 0;
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wire data_rq;
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ptr ptr(.clk(clk), .reset(~reset),
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.iobus_iob_poweron(iobus_iob_poweron),
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.iobus_iob_reset(iobus_iob_reset),
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.iobus_datao_clear(iobus_datao_clear),
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.iobus_datao_set(iobus_datao_set),
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.iobus_cono_clear(iobus_cono_clear),
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.iobus_cono_set(iobus_cono_set),
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.iobus_iob_fm_datai(iobus_iob_fm_datai),
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.iobus_iob_fm_status(iobus_iob_fm_status),
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.iobus_ios(iobus_ios),
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.iobus_iob_in(iobus_iob_in),
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.iobus_pi_req(iobus_pi_req),
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.iobus_iob_out(iobus_iob_out),
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.key_start(key_start),
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.key_stop(key_stop),
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.key_tape_feed(key_tape_feed),
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.s_write(write),
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.s_writedata(writedata),
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.fe_data_rq(data_rq));
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initial begin
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$dumpfile("dump.vcd");
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$dumpvars();
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#100;
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iobus_iob_reset <= 1;
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#100;
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iobus_iob_reset <= 0;
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#100;
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iobus_ios <= 7'b001_000_1;
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key_start <= 1;
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#20;
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key_start <= 0;
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#200;
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// key_tape_feed <= 1;
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ptr.ptr_pia <= 1;
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ptr.ptr_flag <= 0;
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ptr.ptr_busy <= 1;
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ptr.ptr <= 1;
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end
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initial begin: foo
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integer i;
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@(posedge data_rq);
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for(i = 0; i < 20; i = i+1) begin
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@(posedge clk);
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end
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write <= 1;
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writedata <= 'o277;
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@(posedge clk);
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write <= 0;
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/*
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@(posedge data_rq);
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for(i = 0; i < 20; i = i+1) begin
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@(posedge clk);
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end
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write <= 1;
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writedata <= 'o266;
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@(posedge clk);
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write <= 0;
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@(posedge data_rq);
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for(i = 0; i < 20; i = i+1) begin
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@(posedge clk);
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end
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write <= 1;
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writedata <= 'o255;
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@(posedge clk);
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write <= 0;
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@(posedge data_rq);
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for(i = 0; i < 20; i = i+1) begin
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@(posedge clk);
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end
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write <= 1;
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writedata <= 'o244;
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@(posedge clk);
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write <= 0;
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@(posedge data_rq);
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for(i = 0; i < 20; i = i+1) begin
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@(posedge clk);
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end
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write <= 1;
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writedata <= 'o233;
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@(posedge clk);
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write <= 0;
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@(posedge data_rq);
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for(i = 0; i < 20; i = i+1) begin
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@(posedge clk);
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end
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write <= 1;
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writedata <= 'o222;
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@(posedge clk);
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write <= 0;
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@(posedge (|iobus_pi_req));
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iobus_iob_fm_datai <= 1;
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#400;
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iobus_iob_fm_datai <= 0;
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key_stop <= 1;
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#20;
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key_stop <= 0;
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*/
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end
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initial begin
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#40000;
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$finish;
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end
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endmodule
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