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33 lines
583 B
Verilog
33 lines
583 B
Verilog
module wcsl_av(
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input wire clk,
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input wire reset,
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/* Avalon slave */
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input wire s_write,
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input wire [1:0] s_address,
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input wire [31:0] s_writedata,
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/* Externals */
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output reg [0:17] ctl1,
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output reg [0:17] ctl2,
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output reg [0:17] ctl3,
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output reg [0:17] ctl4
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);
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always @(posedge clk) begin
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if(reset) begin
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ctl1 <= 0;
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ctl2 <= 0;
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ctl3 <= 0;
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ctl4 <= 0;
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end else begin
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if(s_write) case(s_address)
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2'b00: ctl1 <= s_writedata;
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2'b01: ctl2 <= s_writedata;
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2'b10: ctl3 <= s_writedata;
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2'b11: ctl4 <= s_writedata;
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endcase
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end
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end
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endmodule
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