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34 lines
675 B
Verilog
Executable File
34 lines
675 B
Verilog
Executable File
module testfmem(
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// input
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i_clk, i_reset_n,
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i_address, i_write, i_read, i_writedata,
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// output
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o_readdata, o_waitrequest
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);
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input wire i_clk;
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input wire i_reset_n;
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input wire [17:0] i_address;
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input wire i_write;
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input wire i_read;
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input wire [35:0] i_writedata;
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output wire [35:0] o_readdata;
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output wire o_waitrequest;
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reg [35:0] mem[0:'o20-1];
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wire [3:0] addr = i_address[3:0];
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wire [35:0] memword = mem[addr];
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always @(posedge i_clk or negedge i_reset_n) begin
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if(~i_reset_n) begin
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end else begin
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if(i_write) begin
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mem[addr] <= i_writedata;
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end
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end
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end
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assign o_readdata = i_read ? memword : 0;
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assign o_waitrequest = 0;
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endmodule
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