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https://github.com/aap/pdp6.git
synced 2026-05-01 05:58:35 +00:00
256 lines
7.2 KiB
Verilog
256 lines
7.2 KiB
Verilog
module coremem16k(
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input clk,
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input mc_wr_rs_p0,
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input mc_rq_cyc_p0,
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input mc_rd_rq_p0,
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input mc_wr_rq_p0,
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input [21:35] ma_p0,
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input [18:21] sel_p0,
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input fmc_select_p0,
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input [0:35] mb_in_p0,
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output cmc_addr_ack_p0,
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output cmc_rd_rs_p0,
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output [0:35] mb_out_p0,
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input mc_wr_rs_p1,
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input mc_rq_cyc_p1,
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input mc_rd_rq_p1,
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input mc_wr_rq_p1,
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input [21:35] ma_p1,
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input [18:21] sel_p1,
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input fmc_select_p1,
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input [0:35] mb_in_p1,
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output cmc_addr_ack_p1,
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output cmc_rd_rs_p1,
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output [0:35] mb_out_p1,
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input mc_wr_rs_p2,
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input mc_rq_cyc_p2,
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input mc_rd_rq_p2,
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input mc_wr_rq_p2,
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input [21:35] ma_p2,
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input [18:21] sel_p2,
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input fmc_select_p2,
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input [0:35] mb_in_p2,
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output cmc_addr_ack_p2,
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output cmc_rd_rs_p2,
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output [0:35] mb_out_p2,
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input mc_wr_rs_p3,
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input mc_rq_cyc_p3,
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input mc_rd_rq_p3,
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input mc_wr_rq_p3,
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input [21:35] ma_p3,
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input [18:21] sel_p3,
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input fmc_select_p3,
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input [0:35] mb_in_p3,
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output cmc_addr_ack_p3,
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output cmc_rd_rs_p3,
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output [0:35] mb_out_p3
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);
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wire [21:35] ma;
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wire [0:35] mb_out;
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wire [0:35] mb_in;
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wire cmc_power_start;
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reg power;
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reg single_step_sw;
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reg restart_sw;
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reg [0:3] memsel_p0;
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reg [0:3] memsel_p1;
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reg [0:3] memsel_p2;
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reg [0:3] memsel_p3;
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reg cmc_p0_act, cmc_p1_act, cmc_p2_act, cmc_p3_act;
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reg cmc_last_proc;
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reg cmc_aw_rq, cmc_proc_rs, cmc_pse_sync, cmc_stop;
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reg cmc_rd, cmc_wr, cmc_inhibit;
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reg [0:35] cmb;
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reg [22:35] cma;
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reg cma_rd_rq, cma_wr_rq;
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reg [0:36] core[0:040000];
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assign cyc_rq_p0 = memsel_p0 == sel_p0 & ~fmc_select_p0 & mc_rq_cyc_p0;
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assign cyc_rq_p1 = memsel_p1 == sel_p1 & ~fmc_select_p1 & mc_rq_cyc_p1;
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assign cyc_rq_p2 = memsel_p2 == sel_p2 & ~fmc_select_p2 & mc_rq_cyc_p2;
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assign cyc_rq_p3 = memsel_p3 == sel_p3 & ~fmc_select_p3 & mc_rq_cyc_p3;
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assign cmpc_p0_rq = cyc_rq_p0 & cmc_aw_rq;
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assign cmpc_p1_rq = cyc_rq_p1 & cmc_aw_rq;
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assign cmpc_p2_rq = cyc_rq_p2 & cmc_aw_rq;
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assign cmpc_p3_rq = cyc_rq_p3 & cmc_aw_rq;
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// simulate power on
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initial begin
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power = 0;
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cmc_aw_rq = 0;
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cmc_rd = 0;
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cmc_wr = 0;
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single_step_sw = 0;
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restart_sw = 0;
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cmc_proc_rs = 0;
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cmc_pse_sync = 0;
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cmc_last_proc = 0;
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#500;
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power = 1;
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end
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// there has to be a better way....
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// from proc to mem
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assign mc_wr_rs = cmc_p0_act ? mc_wr_rs_p0 :
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cmc_p1_act ? mc_wr_rs_p1 :
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cmc_p2_act ? mc_wr_rs_p2 :
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cmc_p3_act ? mc_wr_rs_p3 : 0;
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assign mc_rq_cyc = cmc_p0_act ? mc_rq_cyc_p0 :
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cmc_p1_act ? mc_rq_cyc_p1 :
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cmc_p2_act ? mc_rq_cyc_p2 :
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cmc_p3_act ? mc_rq_cyc_p3 : 0;
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assign mc_rd_rq = cmc_p0_act ? mc_rd_rq_p0 :
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cmc_p1_act ? mc_rd_rq_p1 :
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cmc_p2_act ? mc_rd_rq_p2 :
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cmc_p3_act ? mc_rd_rq_p3 : 0;
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assign mc_wr_rq = cmc_p0_act ? mc_wr_rq_p0 :
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cmc_p1_act ? mc_wr_rq_p1 :
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cmc_p2_act ? mc_wr_rq_p2 :
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cmc_p3_act ? mc_wr_rq_p3 : 0;
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assign ma = cmc_p0_act ? ma_p0 :
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cmc_p1_act ? ma_p1 :
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cmc_p2_act ? ma_p2 :
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cmc_p3_act ? ma_p3 : 0;
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assign mb_in = cmc_p0_act ? mb_in_p0 :
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cmc_p1_act ? mb_in_p1 :
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cmc_p2_act ? mb_in_p2 :
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cmc_p3_act ? mb_in_p3 : 0;
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// from mem to proc
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assign cmc_addr_ack_p0 = cmc_addr_ack & cmc_p0_act;
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assign cmc_rd_rs_p0 = cmc_rd_rs & cmc_p0_act;
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assign mb_out_p0 = cmc_p0_act ? mb_out : 0;
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assign cmc_addr_ack_p1 = cmc_addr_ack & cmc_p1_act;
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assign cmc_rd_rs_p1 = cmc_rd_rs & cmc_p1_act;
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assign mb_out_p1 = cmc_p1_act ? mb_out : 0;
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assign cmc_addr_ack_p2 = cmc_addr_ack & cmc_p2_act;
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assign cmc_rd_rs_p2 = cmc_rd_rs & cmc_p2_act;
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assign mb_out_p2 = cmc_p2_act ? mb_out : 0;
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assign cmc_addr_ack_p3 = cmc_addr_ack & cmc_p3_act;
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assign cmc_rd_rs_p3 = cmc_rd_rs & cmc_p3_act;
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assign mb_out_p3 = cmc_p3_act ? mb_out : 0;
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syncpulse synccmc0(.clk(clk), .in(cmc_aw_rq & mc_rq_cyc), .out(cmc_t0));
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syncpulse synccmc2(.clk(clk), .in(mc_wr_rs), .out(mc_wr_rs_S));
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dly200ns cmcdly1(.clk(clk), .in(cmc_t0), .out(cmc_t1));
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assign cmc_addr_ack = cmc_t1;
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dly1000ns cmcdly2(.clk(clk), .in(cmc_t1), .out(cmc_t2));
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dly1000ns cmcdly3(.clk(clk), .in(cmc_t2), .out(cmc_t4));
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dly200ns cmcdly4(.clk(clk), .in(cmc_t4), .out(cmc_t5));
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assign cmc_t6 = cmc_t5 & ~cma_wr_rq | cmc_tmp4;
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dly200ns cmcdly9(.clk(clk), .in(cmc_t6), .out(cmc_t7));
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dly200ns cmcdly10(.clk(clk), .in(cmc_t7), .out(cmc_t8));
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dly1000ns cmcdly11(.clk(clk), .in(cmc_t8), .out(cmc_t9));
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dly400ns cmcdly12(.clk(clk), .in(cmc_t9), .out(cmc_t9a));
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assign cmc_t10 = cmc_t9a & ~cmc_stop | cmc_pwr_start;
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dly100ns cmcdly13(.clk(clk), .in(cmc_t10), .out(cmc_t11));
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dly200ns cmcdly14(.clk(clk), .in(cmc_t9a), .out(cmc_t12));
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dly800ns cmcdly5(.clk(clk), .in(cmc_t2), .out(cmc_tmp1));
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assign cmc_strb_sa = cmc_tmp1 & cma_rd_rq;
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dly100ns cmcdly6(.clk(clk), .in(cmc_strb_sa), .out(cmc_rd_rs));
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dly250ns cmcdly7(.clk(clk), .in(cmc_strb_sa), .out(cmc_tmp2));
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dly200ns cmcdly8(.clk(clk), .in(cmc_strb_sa), .out(cmc_tmp3));
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assign cmc_cmb_clr = cmc_t0 | cmc_tmp2 & cma_wr_rq;
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assign cmc_state_clr = cmc_tmp3 & ~cma_wr_rq | cmc_t10 | cmc_proc_rs1;
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syncpulse synccmc1(.clk(clk), .in(| mb_in), .out(mb_pulse));
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syncpulse synccmc3(.clk(clk), .in(cmc_proc_rs & cmc_pse_sync), .out(cmc_tmp4));
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syncpulse synccmc4(.clk(clk), .in(cmc_proc_rs), .out(cmc_proc_rs1));
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syncpulse synccmc5(.clk(clk), .in(power), .out(cmc_pwr_start));
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// generate a longer pulse so processor has time to read
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pa100ns cmcpa0(.clk(clk), .in(cmc_strb_sa), .out(cmc_strb_sa_b));
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assign mb_out = cmc_strb_sa_b ? core[cma] : 0;
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wire [0:35] corescope;
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assign corescope = core[cma];
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always @(posedge clk) begin
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if(cmc_power_start)
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cmc_aw_rq <= 1;
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if(cmc_aw_rq) begin
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if(cmpc_p0_rq)
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cmc_p0_act <= 1;
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else if(cmpc_p1_rq)
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cmc_p1_act <= 1;
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else if(cmpc_p2_rq) begin
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if(~cmpc_p3_rq | cmc_last_proc)
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cmc_p2_act <= 1;
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end else if(cmpc_p3_rq) begin
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if(~cmpc_p2_rq | ~cmc_last_proc)
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cmc_p3_act <= 1;
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end
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end
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if(cmc_state_clr) begin
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cmc_p0_act <= 0;
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cmc_p1_act <= 0;
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cmc_p2_act <= 0;
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cmc_p3_act <= 0;
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end
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if(cmc_t0) begin
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cmc_aw_rq <= 0;
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cmc_proc_rs <= 0;
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cmc_pse_sync <= 0;
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cmc_stop <= 0;
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cma <= 0;
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cma_rd_rq <= 0;
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cma_wr_rq <= 0;
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end
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if(cmc_t1) begin
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cma <= cma | ma_p0[22:35];
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if(mc_rd_rq)
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cma_rd_rq <= 1;
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if(mc_wr_rq)
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cma_wr_rq <= 1;
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end
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if(cmc_t2) begin
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cmc_rd <= 1;
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if(cmc_p2_act)
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cmc_last_proc <= 0;
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if(cmc_p3_act)
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cmc_last_proc <= 1;
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end
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if(cmc_t5) begin
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// this is hack, normally core should be cleared
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// roughly at the time of cmc_strb_sa, which is
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// however does not happen on a write
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core[cma] <= 0;
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cmc_rd <= 0;
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cmc_pse_sync <= 1;
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end
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if(cmc_t7)
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cmc_inhibit <= 1; // totally useless
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if(cmc_t8)
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cmc_wr <= 1;
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if(cmc_t9 & cmc_wr)
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// again a hack, core is written some time after T8
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// ...and we know cmc_wr is set then anway.
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core[cma] <= core[cma] | cmb;
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if(cmc_t11)
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cmc_aw_rq <= 1;
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if(cmc_t12) begin
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cmc_rd <= 0;
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cmc_wr <= 0;
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cmc_inhibit <= 0;
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end
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if(mc_wr_rs_S)
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cmc_proc_rs <= 1;
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if(cmc_strb_sa) begin
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cmb <= mb_out;
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end
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if(cmc_cmb_clr)
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cmb <= 0;
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if(mb_pulse)
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cmb <= cmb | mb_in;
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end
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endmodule
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