Merge pull request #36 from antonblanchard/update-chisel

Update chisel

README.md

@@ -54,7 +54,7 @@ The `hello_world` example should run everywhere, so start with it.
 Edit `src/main/scala/Core.scala` and set memory to 16 kB (`16*1024`):
 
 ```scala
-chisel3.Driver.execute(Array[String](), () => new Core(64, 16*1024, "insns.hex", 0x0))
+  (new ChiselStage).emitVerilog(new Core(64, 16*1024, "insns.hex", 0x0))
 ```
 
 Then link in the hello_world image:

build.sc

@@ -19,17 +19,21 @@ trait HasXsource211 extends ScalaModule {
 
 trait HasChisel3 extends ScalaModule {
   override def ivyDeps = Agg(
-    ivy"edu.berkeley.cs::chisel3:3.2.5"
- )
+    ivy"edu.berkeley.cs::chisel3:3.4.+"
+  )
+  // These lines are needed to use snapshot version of Chisel.
+  def repositories = super.repositories ++ Seq(
+    MavenRepository("https://oss.sonatype.org/content/repositories/snapshots")
+  )
 }
 
 trait HasChiselTests extends CrossSbtModule  {
   object test extends Tests {
     override def ivyDeps = Agg(
       ivy"org.scalatest::scalatest:3.0.4",
-      ivy"edu.berkeley.cs::chisel-iotesters:1.2+",
-      ivy"edu.berkeley.cs::chiseltest:0.2-SNAPSHOT"
+      ivy"edu.berkeley.cs::chiseltest:0.3.0"
     )
+    // These lines are needed to use snapshot version of Chisel.
     def repositories = super.repositories ++ Seq(
       MavenRepository("https://oss.sonatype.org/content/repositories/snapshots")
     )

src/main/scala/Adder.scala

@@ -1,4 +1,5 @@
 import chisel3._
+import chisel3.stage.ChiselStage
 
 class Adder(n: Int) extends Module {
   val io = IO(new Bundle {
@@ -33,5 +34,5 @@ class Adder(n: Int) extends Module {
 }
 
 object AdderObj extends App {
-  chisel3.Driver.execute(Array[String](), () => new Adder(64))
+  (new ChiselStage).emitVerilog(new Adder(64))
 }

src/main/scala/Control.scala

@@ -1,5 +1,6 @@
 import chisel3._
 import chisel3.util.{ListLookup}
+import chisel3.stage.ChiselStage
 
 object Control {
   val Y = true.B
@@ -324,5 +325,5 @@ class Control(val n: Int) extends Module {
 }
 
 object ControlObj extends App {
-  chisel3.Driver.execute(Array[String](), () => new Control(64))
+  (new ChiselStage).emitVerilog(new Control(64))
 }

src/main/scala/Core.scala

@@ -1,5 +1,6 @@
 import chisel3._
 import chisel3.util._
+import chisel3.stage.ChiselStage
 
 import Control._
 import Helpers._
@@ -444,5 +445,5 @@ class Core(bits: Int, memSize: Int, memFileName: String, resetAddr: Int) extends
 }
 
 object CoreObj extends App {
-  chisel3.Driver.execute(Array[String](), () => new Core(64, 384*1024, "insns.hex", 0x0))
+  (new ChiselStage).emitVerilog(new Core(64, 384*1024, "insns.hex", 0x0))
 }

src/main/scala/CountZeroes.scala

@@ -1,5 +1,6 @@
 import chisel3._
 import chisel3.util.{log2Ceil, MuxCase, Reverse}
+import chisel3.stage.ChiselStage
 
 /** Module for counting leading zeroes in a [[UInt]]
   * @param n the width of the [[UInt]]
@@ -59,7 +60,7 @@ class CountZeroes(bits: Int) extends Module {
 }
 
 object CountZeroesObj extends App {
-  chisel3.Driver.execute(Array[String](), () => new CountZeroes(64))
+  (new ChiselStage).emitVerilog(new CountZeroes(64))
 }
 
 /** Utilities for counting zeroes */

src/main/scala/LoadStore.scala

@@ -1,5 +1,6 @@
 import chisel3._
 import chisel3.util._
+import chisel3.stage.ChiselStage
 
 import Control._
 import Helpers._
@@ -205,5 +206,5 @@ class LoadStoreWrapper(val bits: Int, val size: Int, filename: String) extends M
 }
 
 object LoadStoreObj extends App {
-  chisel3.Driver.execute(Array[String](), () => new LoadStoreWrapper(64, 128*1024, "test.hex"))
+  (new ChiselStage).emitVerilog(new LoadStoreWrapper(64, 128*1024, "test.hex"))
 }

src/main/scala/LoadStoreByteReverse.scala

@@ -1,5 +1,6 @@
 import chisel3._
 import chisel3.util.{MuxLookup}
+import chisel3.stage.ChiselStage
 
 import Control._
 import Helpers._
@@ -26,7 +27,7 @@ class LoadStoreByteReverse(bits: Int) extends Module {
 }
 
 object LoadStoreByteReverseObj extends App {
-  chisel3.Driver.execute(Array[String](), () => new LoadStoreByteReverse(64))
+  (new ChiselStage).emitVerilog(new LoadStoreByteReverse(64))
 }
 
 object LoadStoreByteReverse {

src/main/scala/Logical.scala

@@ -1,5 +1,6 @@
 import chisel3._
 import chisel3.util.{MuxCase, MuxLookup}
+import chisel3.stage.ChiselStage
 
 import Control._
 import Helpers._
@@ -32,5 +33,5 @@ class Logical(bits: Int) extends Module {
 }
 
 object LogicalObj extends App {
-  chisel3.Driver.execute(Array[String](), () => new Logical(64))
+  (new ChiselStage).emitVerilog(new Logical(64))
 }

src/main/scala/MemoryBlackBox.scala

@@ -1,5 +1,6 @@
 import chisel3._
 import chisel3.util.{log2Ceil,HasBlackBoxInline}
+import chisel3.stage.ChiselStage
 
 class MemoryBlackBox(val bits: Int, val words: Int, val filename: String) extends BlackBox with HasBlackBoxInline {
   val io = IO(new Bundle() {
@@ -88,5 +89,5 @@ class MemoryBlackBoxWrapper(val bits: Int, val words: Int, val filename: String)
 }
 
 object MemoryBlackBoxObj extends App {
-  chisel3.Driver.execute(Array[String](), () => new MemoryBlackBoxWrapper(64, 1024, "test.hex"))
+  (new ChiselStage).emitVerilog(new MemoryBlackBoxWrapper(64, 1024, "test.hex"))
 }

src/main/scala/Nia.scala

@@ -1,5 +1,6 @@
 import chisel3._
 import chisel3.util.Decoupled
+import chisel3.stage.ChiselStage
 
 class Nia(val bits: Int, val resetAddr: Int) extends Module {
   val io = IO(new Bundle {
@@ -24,5 +25,5 @@ class Nia(val bits: Int, val resetAddr: Int) extends Module {
 }
 
 object NiaObj extends App {
-  chisel3.Driver.execute(Array[String](), () => new Nia(32, 0x100))
+  (new ChiselStage).emitVerilog(new Nia(32, 0x100))
 }

src/main/scala/PopulationCount.scala

@@ -1,5 +1,6 @@
 import chisel3._
 import chisel3.util.{PopCount, MuxLookup}
+import chisel3.stage.ChiselStage
 
 import Control._
 import Helpers._
@@ -49,5 +50,5 @@ class PopulationCount(bits: Int) extends Module {
 }
 
 object PopulationCountObj extends App {
-  chisel3.Driver.execute(Array[String](), () => new PopulationCount(64))
+  (new ChiselStage).emitVerilog(new PopulationCount(64))
 }

src/main/scala/RegisterFile.scala

@@ -1,5 +1,6 @@
 import chisel3._
 import chisel3.util.{log2Ceil, Valid}
+import chisel3.stage.ChiselStage
 
 object RegisterFile {
   sealed trait PortDirection
@@ -36,5 +37,5 @@ class RegisterFile(numRegs: Int, bits: Int, numReadPorts: Int, numWritePorts: In
 }
 
 object RegisterFileObj extends App {
-  chisel3.Driver.execute(Array[String](), () => new RegisterFile(32, 64, 3, 1, true))
+  (new ChiselStage).emitVerilog(new RegisterFile(32, 64, 3, 1, true))
 }

src/main/scala/Rotator.scala

@@ -1,5 +1,6 @@
 import chisel3._
 import chisel3.util.log2Ceil
+import chisel3.stage.ChiselStage
 
 import InstructionHelpers._
 
@@ -111,5 +112,5 @@ class Rotator(bits: Int) extends Module {
 }
 
 object RotatorObj extends App {
-  chisel3.Driver.execute(Array[String](), () => new Rotator(64))
+  (new ChiselStage).emitVerilog(new Rotator(64))
 }

src/main/scala/SimpleDivider.scala

@@ -1,5 +1,6 @@
 import chisel3._
 import chisel3.util.{Valid, Decoupled, log2Ceil}
+import chisel3.stage.ChiselStage
 
 class DividerInput(val bits: Int) extends Bundle {
   val dividend = UInt(bits.W)
@@ -106,5 +107,5 @@ class SimpleDivider(val bits: Int) extends Module {
 }
 
 object SimpleDividerObj extends App {
-  chisel3.Driver.execute(Array[String](), () => new SimpleDivider(64))
+  (new ChiselStage).emitVerilog(new SimpleDivider(64))
 }

src/main/scala/SimpleMultiplier.scala

@@ -1,5 +1,6 @@
 import chisel3._
 import chisel3.util.{Valid, Decoupled, log2Ceil}
+import chisel3.stage.ChiselStage
 
 import Helpers._
 
@@ -92,5 +93,5 @@ class SimpleMultiplier(val bits: Int) extends Module {
 }
 
 object SimpleMultiplierObj extends App {
-  chisel3.Driver.execute(Array[String](), () => new SimpleMultiplier(64))
+  (new ChiselStage).emitVerilog(new SimpleMultiplier(64))
 }

src/main/scala/Uart.scala

@@ -1,5 +1,6 @@
 import chisel3._
 import chisel3.util._
+import chisel3.stage.ChiselStage
 
 /*
  * A simple TTL serial module. Idle is high. Start bits are low, stop bits
@@ -198,5 +199,5 @@ class Uart(val fifoLength: Int, val rxOverclock: Int) extends Module {
 }
 
 object UartObj extends App {
-  chisel3.Driver.execute(Array[String](), () => new Uart(64, 16))
+  (new ChiselStage).emitVerilog(new Uart(64, 16))
 }