From 43e1e73ce869a4e10e78afd0214db417f4fc55fc Mon Sep 17 00:00:00 2001 From: Anton Blanchard Date: Sun, 2 Feb 2020 09:44:04 +1100 Subject: [PATCH] Rename PLL Now we have multiple PLLs it makes no sense to call it pll_ecp5_evn. Signed-off-by: Anton Blanchard --- pll/pll_ehxplll.v | 2 +- pll/pll_mmcme2.v | 2 +- toplevel.v | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/pll/pll_ehxplll.v b/pll/pll_ehxplll.v index bc032ba..c8fe212 100644 --- a/pll/pll_ehxplll.v +++ b/pll/pll_ehxplll.v @@ -1,4 +1,4 @@ -module pll_ecp5_evn(input clki, output clko, output lock); +module pll(input clki, output clko, output lock); (* ICP_CURRENT="12" *) (* LPF_RESISTOR="8" *) (* MFG_ENABLE_FILTEROPAMP="1" *) (* MFG_GMCREF_SEL="2" *) EHXPLLL #( .PLLRST_ENA("DISABLED"), diff --git a/pll/pll_mmcme2.v b/pll/pll_mmcme2.v index ee4fc65..90014bf 100644 --- a/pll/pll_mmcme2.v +++ b/pll/pll_mmcme2.v @@ -1,4 +1,4 @@ -module pll_ecp5_evn(input clki, output clko, output lock); +module pll(input clki, output clko, output lock); wire clkfb; diff --git a/toplevel.v b/toplevel.v index 9f0977d..a9412fb 100644 --- a/toplevel.v +++ b/toplevel.v @@ -14,7 +14,7 @@ wire clock_out; reg reset_out; wire lock; -pll_ecp5_evn pll( +pll chiselwatt_pll( .clki(clock), .clko(clock_out), .lock(lock)